Fix xarch instruction size estimates#129877
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Correct xarch size accounting for VEX/K encodings and add an opt-in debug check. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
Make the emit-size check exact by default and cover the remaining xarch estimator gaps. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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Pull request overview
This PR updates the xarch emitter’s instruction-size estimation logic to more accurately account for encoding details (prefixes/opcode forms) and adds a DEBUG-only sanity check to assert when the emitted size differs from the estimated size.
Changes:
- Add a new DEBUG-only JIT config switch to enable/disable an emit-size mismatch assertion.
- Refine xarch size estimation in multiple paths (VEX/EVEX prefix accounting, certain opcode forms, K-reg moves, etc.).
- Add a DEBUG-only emit-time verification in
emitOutputInstrto compare estimated vs. actual encoded byte count (with skips for known intentionally-variable cases).
Reviewed changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated 1 comment.
| File | Description |
|---|---|
| src/coreclr/jit/jitconfigvalues.h | Adds JitAssertOnEmitSizeMismatch debug config switch. |
| src/coreclr/jit/emitxarch.cpp | Adjusts instruction size estimation for various xarch encodings and adds DEBUG-only emit-size mismatch checking. |
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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/azp run runtime-coreclr jitstress-isas-avx512, runtime-coreclr jitstress-isas-x86 |
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Azure Pipelines successfully started running 2 pipeline(s). |
This was referenced Jun 26, 2026
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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/azp run runtime-coreclr jitstress-isas-avx512, runtime-coreclr jitstress-isas-x86 |
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Azure Pipelines successfully started running 2 pipeline(s). |
| // RyuJIT where possible | ||
| CONFIG_INTEGER(JitAssertOnMaxRAPasses, "JitAssertOnMaxRAPasses", 0) | ||
| CONFIG_INTEGER(JitBreakEmitOutputInstr, "JitBreakEmitOutputInstr", -1) | ||
| // Assert if the xarch encoder emits a different number of bytes than its estimator predicted; set to 0 to disable. |
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| // Labels and align pseudo-instructions can intentionally shrink after initial size estimation. | ||
| const IS_INFO insFmtInfo = emitGetSchedInfo(insFmt); | ||
| #if !FEATURE_FIXED_OUT_ARGS | ||
| const bool skipStackSizeCheck = ((insFmtInfo & (IS_SF_RD | IS_SF_RW | IS_SF_WR)) != 0); | ||
| #else | ||
| const bool skipStackSizeCheck = false; | ||
| #endif | ||
| const bool skipSizeCheck = (id->idIns() == INS_align) || (insFmt == IF_LABEL) || (insFmt == IF_RWR_LABEL) || | ||
| (insFmt == IF_SWR_LABEL) || skipStackSizeCheck; | ||
| const UNATIVE_OFFSET actualCodeSize = static_cast<UNATIVE_OFFSET>(dst - *dp); | ||
| if (!skipSizeCheck && (id->idCodeSize() != actualCodeSize)) |
Use the actual opcode prefix state when adjusting K-instruction size estimates so EVEX stress and VEX output stay consistent. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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/azp run runtime-coreclr jitstress-isas-avx512, runtime-coreclr jitstress-isas-x86 |
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Azure Pipelines successfully started running 2 pipeline(s). |
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Summary
Validation
build.cmd -subset clr.jit -c Checkedbuild.cmd -subset clr.jit -arch x86 -c CheckedNote
This PR description was generated by GitHub Copilot.