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feat(igc): enable multi-queue tx/rx#693

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ytakano merged 3 commits into
tier4:mainfrom
ytakano:igc_multi_queue
Jun 8, 2026
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feat(igc): enable multi-queue tx/rx#693
ytakano merged 3 commits into
tier4:mainfrom
ytakano:igc_multi_queue

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@ytakano ytakano commented Jun 1, 2026

Description

This PR adds multi-queue TX/RX support to the IGC driver. It is the fifth step in the incremental IGC bring-up stack; PR4 (#691) must be merged before this one.

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How was this PR tested?

  • make x86_64 RELEASE=1 — build passes
  • make check_x86_64 — unit tests pass
  • Real-machine validation

Notes for reviewers

  • igc_txeof ignores _que_id because the DD-bit reclaim implementation (adopted in PR4's review) does not need the hardware head register. The parameter is present only for call-site uniformity and future extensibility.
  • Queue count is capped at 4 to match the I225's RSS queue limit. The actual count will be 1 on systems where num_cpu() returns 1 or where few MSI-X vectors are available, so single-queue regression risk is low.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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Pull request overview

This PR extends the Intel IGC (I225/I226) driver to support multiple TX/RX queues, aligning the driver with the kernel networking stack’s multi-queue model and MSI-X queue interrupt layout.

Changes:

  • Added a per-queue service routine and updated the interrupt/tick paths to service RX and TX reclaim per queue.
  • Removed single-queue constraints in TX/RX paths and updated TX reclaim (igc_txeof) call sites to be queue-aware.
  • Introduced queue-count selection based on available MSI-X vectors and CPU count (capped to 4), and enabled MSI-X masks for all queue vectors plus the event/link vector.

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Comment thread awkernel_drivers/src/pcie/intel/igc.rs Outdated
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
@ytakano ytakano marked this pull request as ready for review June 1, 2026 09:44
@ytakano ytakano requested a review from atsushi421 June 1, 2026 09:44
Comment thread awkernel_drivers/src/pcie/intel/igc.rs
Comment thread awkernel_drivers/src/pcie/intel/igc.rs
Comment thread awkernel_drivers/src/pcie/intel/igc.rs Outdated
Comment thread awkernel_drivers/src/pcie/intel/igc.rs
Comment thread awkernel_drivers/src/pcie/intel/igc.rs
Comment thread awkernel_drivers/src/pcie/intel/igc.rs
- intr: accumulate errors from service_queue/link handlers instead of
  using `?` so EIMS/IMS re-arm writes always execute and the interrupt
  line is never left permanently masked
- igc_send, igc_rx_recv: guard against out-of-range que_id with an
  early Err(Param) return to prevent index-out-of-bounds panic
- can_send: remove igc_txeof call; descriptor reclaim is the ISR's
  responsibility and calling it here contends with the ISR TX lock path
- igc_select_num_queues: add doc comment explaining the three
  constraints (MSI-X vectors, CPU count, hard cap of 4) and the
  rationale for power-of-two rounding for even RETA distribution
- igc_txeof: add comment explaining why _que_id is unused

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@atsushi421 atsushi421 self-requested a review June 8, 2026 08:53
@ytakano ytakano merged commit 91b9a16 into tier4:main Jun 8, 2026
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3 participants