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[feature] Add Im2colRTL data mover and unit test#301

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[feature] Add Im2colRTL data mover and unit test#301
zsjiang99 wants to merge 2 commits into
tancheng:masterfrom
zsjiang99:feature/im2col-rtl

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Single-channel scalar 32-bit im2col engine that streams an HxW image from one memory port and writes the (kHkW)x(HoutWout) lowered matrix to a second port. Unit test verifies three configurations (4x4/2x2/s1, 4x4/2x2/s2, 5x5/3x3/s1) against a software golden in both pure-PyMTL3 simulation and full --test-verilog translation.

Single-channel scalar 32-bit im2col engine that streams an HxW image
from one memory port and writes the (kH*kW)x(Hout*Wout) lowered
matrix to a second port. Unit test verifies three configurations
(4x4/2x2/s1, 4x4/2x2/s2, 5x5/3x3/s1) against a software golden in
both pure-PyMTL3 simulation and full --test-verilog translation.
@zsjiang99 zsjiang99 force-pushed the feature/im2col-rtl branch from 6618844 to e8f74cf Compare June 20, 2026 03:56
@zsjiang99 zsjiang99 changed the title [feature] Add stand-alone Im2colRTL data mover and unit test [feature] Add Im2colRTL data mover and unit test Jun 20, 2026
@zsjiang99 zsjiang99 requested a review from tancheng June 20, 2026 15:25
@tancheng tancheng requested review from ShangkunLi and yyan7223 June 21, 2026 06:36

@tancheng tancheng left a comment

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Can we have a new module to connect this Im2col to the systolic array, so that we can verify e2e functionality from image towards matmul?

@zsjiang99

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Yes, just saw this message. I will do it on this weekend.

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