GitHub - sagrig/vrv: Virtual RISC-V CPU implementation.

Virtual RISC-V implementation by Sahak Grigoryan for educational purposes.

Name		Name	Last commit message	Last commit date
Latest commit History 42 Commits
cmn		cmn
ext		ext
test		test
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
btree.c		btree.c
btree.h		btree.h
core.c		core.c
core.h		core.h
csr.c		csr.c
csr.h		csr.h
gid.c		gid.c
gid.h		gid.h
ins.c		ins.c
ins.h		ins.h
main.c		main.c
makefile		makefile

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