inst64: Drive on-the-fly transpose; add the snitch integration harness

[DanielKellerM]

Summary

Drives on-the-fly transpose through the inst64 (Snitch) frontend and adds a standalone Snitch integration harness.

inst64's backend (rw_axi_rw_init_rw_obi) is multi-write and therefore cannot host the #112 single-AXI-write transpose engine. Instead, the transpose is executed by address generation: idma_transpose_midend (new AddrGenTranspose mode) emits an element-granular NumDim=3 swapped-stride ND program (out_T[c][r] = in[r][c]) and clears opt.compute, so the backend runs a plain strided copy — no engine, no tile buffer. OBI/TCDM is random-access, so this is the natural (and only needed) mechanism for inst64; the #112 FF engine remains the full-throughput path for AXI↔AXI transpose on rw_axi.

What's here

• Frontend (idma_inst64_top): decode the transpose DMCPY into opt.compute, splice idma_transpose_midend ahead of idma_nd_midend, and reject malformed requests (no hardware / reserved mode / zero dim / unaligned dst).
• Address-gen (idma_transpose_midend, AddrGenTranspose): swapped-stride transpose with an optional BankSkew that pads the dst row pitch by one bus-word when the column stride would hammer a single TCDM bank — makes the per-column word stride odd, so writes round-robin across all banks on any power-of-2-bank L1, at ≤1 word/row cost.
• Harness (systems/snitch): standalone BFM driving the accelerator port plus AXI and native-OBI sim memories.

Testing

The self-checking harness TB sweeps a geometry list in one elaboration (int8/fp16/fp32, square/rectangular/odd) over the real OBI/TCDM port:

• OBI→OBI — transpose a tile within L1/TCDM
• AXI→OBI — load an external matrix into TCDM transposed
• back-to-back (consecutive cases), cross-transfer compute-leak (a plain copy after transposes must not inherit opt.compute), and malformed-request reject
• both BankSkew off (contiguous N×M) and on (padded N×M′, padding stays sentinel)

A standalone copy harness (tb_idma_inst64_copy) also passes. All changes live in src/ — no codegen/templatization.

Notes

• Address-gen is element-granular (M·N transactions): ideal on random-access OBI/TCDM, slower than a burst on AXI. The FF engine (Add on-the-fly compute support with a transpose engine #112) stays the full-throughput path for AXI↔AXI on rw_axi.
• Rebased on current devel; the earlier transpose-engine commits are dropped (they landed via Add on-the-fly compute support with a transpose engine #112).

[Copilot]

Pull request overview

This PR wires the on-the-fly transpose feature end-to-end for the Snitch inst64 frontend and adds a standalone Snitch integration harness, while also extending the backend generation flow to optionally include compute support in selected variants.

Changes:

• Add a typed per-transfer opt.compute capability (transpose op + params) and route it through legalizer/backend/transport to a write-seam compute dispatcher and transpose engine.
• Extend the inst64 frontend to decode transpose requests from spare DMCPY argb bits, expand transpose geometry via a new idma_transpose_midend, and reject malformed transpose requests.
• Add new SV/DPI-C testbenches (engine-level + ND/back-to-back) and a Snitch inst64 integration harness + Makefile flow (snitch_transpose_sweep), plus docs and Bender target support (split_rtl).

Reviewed changes

Copilot reviewed 36 out of 37 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
util/mario/util.py	Add parsing for --compute-ids configuration strings (ops + fd/hd).
util/mario/transport_layer.py	Pass compute enable/op info into transport-layer templating context.
util/mario/legalizer.py	Pass compute enable flag into legalizer templating context.
util/mario/backend.py	Enforce “single AXI write port” constraint for compute-enabled variants and pass ops into backend templating context.
util/gen_idma.py	Add --compute-ids CLI and propagate compute config into generators.
test/tb_idma_transpose_nd.sv	Multi-tile end-to-end transpose test via ND midend → compute backend → AXI sim mem.
test/tb_idma_transpose_b2b.sv	End-to-end back-to-back transpose regression to distinct destinations.
test/tb_idma_otf_transpose.sv	Standalone transpose engine SV testbench using DPI-C golden model.
test/midend/tb_idma_transpose_midend.sv	Unit test for transpose geometry expansion midend.
test/midend/tb_idma_nd_midend_b2b.sv	Back-to-back ND midend base-address reload regression under backpressure.
test/idma_transpose_dpi.c	DPI-C golden model for element-granular transpose verification.
test/idma_test.sv	Extend request-driving task to optionally program transpose compute options.
systems/snitch/test/tb_idma_inst64_transpose.sv	Snitch inst64 end-to-end transpose integration test (incl. rejects + no-leak).
systems/snitch/test/tb_idma_inst64_copy.sv	Snitch inst64 plain-copy regression.
systems/snitch/test/idma_inst64_tb_pkg.sv	Package/types/constants for the standalone Snitch harness.
systems/snitch/test/idma_inst64_drv_if.sv	Accelerator-bus BFM tasks, including DMCPY-encoded transpose launch helpers.
systems/snitch/test/idma_inst64_base.sv	Base harness instantiating idma_inst64_top + AXI sim memories.
systems/snitch/README.md	Document Snitch harness purpose, build flow, and transpose contract.
systems/snitch/Makefile	Standalone build + sim/sweep targets for the Snitch harness.
systems/snitch/.gitignore	Ignore build products for the Snitch harness flow.
src/midend/idma_transpose_midend.sv	New combinational transpose geometry expander (NumDim=4) for ND midend.
src/midend/idma_nd_midend.sv	Add non-synth assertion enforcing stride width == address width.
src/include/idma/typedef.svh	Extend options_t with typed compute options field.
src/idma_pkg.sv	Define compute op enum, transpose params, compute options, and feature enable struct.
src/frontend/inst64/idma_inst64_top.sv	Add ComputeEnable param, decode/validate transpose from DMCPY, splice transpose midend, widen strides to addr width, add backend capability cross-check.
src/db/idma_tilelink.yml	Forward compute options into write datapath request struct where needed.
src/db/idma_axi.yml	Forward compute options; extend AXI write template to accept strobe mask + beat-done pulse.
src/backend/tpl/idma_transport_layer.sv.tpl	Add write-seam compute integration (dispatcher + mask/beat-done plumbing).
src/backend/tpl/idma_legalizer.sv.tpl	Force decouple on compute transfers; propagate compute options into mutable transfer opts and write datapath req.
src/backend/tpl/idma_backend.sv.tpl	Add compute-enabled variant metadata (ComputeEnable), enforce NO_ERROR_HANDLING, increase meta FIFO depth for compute latency, propagate compute options into write datapath req.
src/backend/idma_otf_transpose.sv	New transpose engine (tile ping-pong) producing per-byte strobe mask.
src/backend/idma_otf_compute.sv	New write-seam compute dispatcher (currently transpose only).
src/backend/idma_axi_write.sv	Add external strobe mask input and a strobe-independent “beat accepted” pulse output.
jobs/backend_rw_axi/transpose_none.txt	Add job artifact/marker for transpose-none configuration (empty in this diff).
idma.mk	Add compute-enabled variant list (IDMA_VIDMA_IDS), propagate to generator, add simulation targets for transpose regressions, include split_rtl in vsim script target set.
doc/transpose-engine-routing-plan.md	Detailed routing/signaling plan and rationale for transpose integration.
Bender.yml	Add compute RTL, new midend, Snitch harness sources, transpose tests, and introduce split_rtl generated-file selection.

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[DanielKellerM]

Superseded by #141.