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Support critical-word-first cache line loads

enhancement

Status: Open.

#4 In joewing/memsim;

· joewing opened on Sep 9, 2013

Correct VHDL model for high-associativity caches

bug

Status: Open.

#3 In joewing/memsim;

· joewing opened on Aug 28, 2013

Pipelined memory accesses

enhancement

Status: Open.

#2 In joewing/memsim;

· joewing opened on Aug 14, 2013

Stream buffer memory component

enhancement

Status: Open.

#1 In joewing/memsim;

· joewing opened on Aug 14, 2013