Add Feature: golden-reference pipeline for FPGA/ASIC synthesis: online learning, quantization, arithmetic, export, verification, and RTL-matched PRNG

[ajyds]

Overview
This PR adds 6 new modules that transform torchhd from a pure prototyping
library into a golden-reference pipeline for RTL (FPGA/ASIC) synthesis.
Every operation can now be validated bit-accurately against what the
hardware ALU produces in Vivado/Quartus.

New Modules

torchhd.online
Streaming/online learning without batching.

• HebbianAccumulator — running outer-product weight matrix with
  exponential moving average (lr < 1 forgets stale data).
• StreamingCentroid — OnlineHD-style test-then-train centroid classifier,
  one sample per step() call.

torchhd.quantize
Fixed-point quantization and hardware memory export.

• to_fixed_point / from_fixed_point — Q<M.N> signed/unsigned.
• quantize_bipolar — bipolar {−1, +1} and ternary {−1, 0, +1}.
• block_float_quantize — shared exponent per block.
• pack_bits / unpack_bits — dense bit-packing for BRAM storage.
• export_verilog, export_c_header, export_binary — writeout formats.

torchhd.arith
Bit-accurate fixed-point ALU matching RTL behavior.

• q_bundle, q_bind, q_permute, q_dot, q_cos_similarity,
  q_majority — all with configurable saturation (clamp/wrap) and
  accumulator width.

torchhd.export
Basis/codebook extraction from embeddings + memory init file generation.

• extract_basis, extract_codebook, extract_projection_matrix
• export_coe (Xilinx blk_mem_gen), export_mif (Altera/Intel),
  export_hex ($readmemh), export_bram_init (depth×width image).

torchhd.verif
Golden trace capture → SystemVerilog testbench generation.

• GoldenTrace records encode/step/forward events cycle-by-cycle.
• write_sv_stimulus emits an initial block replaying all inputs
  at correct clock offsets.
• write_sv_checker emits a parallel always block with assert
  statements comparing RTL outputs to golden expected values.

torchhd.prng
Deterministic PRNGs matching RTL implementations.

• LFSR — Galois (one-to-many), 8/10/12/16/24/32-bit, with
  pre-verified maximal-length polynomials.
• XORShift32 / XORShift64 — Marsaglia xorshift.
• export_lfsr_verilog — emits a synthesizable Verilog module
  bit-identical to the Python instance.

End-to-End Workflow

1. Train with StreamingCentroid (or existing Centroid)
2. Quantize weights with to_fixed_point
3. Validate arithmetic with q_bundle/q_dot against RTL ALU spec
4. Export weights via export_coe or export_bram_init
5. Generate testbench with GoldenTrace.write_sv_stimulus + checker
6. Match PRNG seeds with LFSR → export_lfsr_verilog for identical
   hypervector generation in Python and Vivado sim

All modules are backwards-compatible; no existing APIs are modified.