Map Cortex-A320 to A510 kernel selection path#10173
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Bring in pytorch/cpuinfo commit 3681f0c which adds the Cortex-A320 (MIDR part 0xD8F) entry to the MIDR decode table. This makes cpuinfo_uarch_cortex_a320 available for use in src/configs/hardware-config.c. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The Cortex-A320 is an ARMv9.2-A efficiency core in the same family as the A510/A520. Map it to xnn_uarch_cortex_a510 (the closest existing entry; A520 is not exposed in xnn_uarch) so XNNPACK selects the optimised GEMM and depthwise convolution kernels tuned for this class of core rather than falling back to the generic path. The mapping can be revisited once silicon is available for benchmarking. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
dsharlet
approved these changes
Jun 3, 2026
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Follow-up to #10060 (Zephyr platform support).
Bumps the cpuinfo dependency to include the Cortex-A320 MIDR decode
(pytorch/cpuinfo#384, merged) and adds a one-line mapping in
cpuinfo_to_xnn_uarch()so XNNPACK selects the optimised kernelpath on Cortex-A320 cores.
The A320 is an ARMv9.2-A efficiency core in the same family as
the A510/A520. We map it to
xnn_uarch_cortex_a510since A520 isnot exposed in
xnn_uarcheither, and A510 is the closest existingentry; the mapping can be revisited once silicon is available for
benchmarking.