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reginfo: add Hi3519DV500/Hi3516DV500 pinmux dump; audit cv6xx table#177

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feat/dv500-reginfo
Jun 27, 2026
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reginfo: add Hi3519DV500/Hi3516DV500 pinmux dump; audit cv6xx table#177
widgetii merged 1 commit into
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feat/dv500-reginfo

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What

reginfo decodes the pinmux (IOCFG) registers and prints the active function per pin (--script emits devmem lines). DV500 was already detected (HISI_OT) but regs_by_chip() routed it to the cv6xx CV610regs table — so on a 3519/3516DV500 it decoded cv6xx pins at cv6xx addresses, which are wrong (different IOCFG bases, different pins).

Changes

  • New DV500regs[] — Hi3519DV500 / Hi3516DV500 (V5, aarch64). Three IOCFG controllers:
    • IOCFG0 0x10260000, IOCFG2 0x179F0000, IOCFG3 0x0EFF0000 (IOCFG2/3 differ from cv6xx).
    • 90 mux registers; per-mux-index function lists derived from the vendor SDK pin_mux.c (every function the SDK selects across its modes; mux values the SDK never uses left "reserved"). All addresses verified in-range and de-duplicated.
  • Dispatch fixregs_by_chip() case HISI_OT now returns DV500regs for 3519DV500/3516DV500, CV610regs otherwise (cv6xx unchanged).
  • cv6xx audit — cross-checked CV610regs against the cv6xx SDK pin_mux.c and added 19 registers it configures that were missing: the VI data bus (io2 0x300x78) and UART2 (io1 0x10/0x14).

Testing

  • Builds clean (cmake .. && make).
  • Static checks: all 90 DV500 addresses fall within the three IOCFG bases, no duplicate addresses in either table, pointer-array counts match definition counts (DV500 90, CV610 71), dispatch returns the correct table per chip.
  • On-target decode (e.g. SENSOR0_CLK @ IOCFG2+0x44, I2C0_SCL @ IOCFG0+0x70) follows directly from the SDK pin_mux.c mux indices.

🤖 Generated with Claude Code

@widgetii widgetii force-pushed the feat/dv500-reginfo branch 3 times, most recently from e8b7d45 to 9424ce7 Compare June 27, 2026 08:02
…v6xx

DV500 (V5, aarch64) has three IOCFG controllers at IOCFG0 0x10260000,
IOCFG2 0x179F0000, IOCFG3 0x0EFF0000 (IOCFG2/3 differ from cv6xx), plus the
AON pad-mux in the PMC at 0x11120000. It is already detected as HISI_OT but
regs_by_chip() routed it to CV610regs, so reginfo decoded cv6xx pins at
cv6xx addresses. Add a dedicated DV500regs[] and dispatch 3519/3516DV500
to it.

Function lists are built from the vendor SDK pin_mux.c (every function the
SDK selects across its modes, indexed by mux value) and cross-checked /
extended with the vendor U-Boot register-init spreadsheets (the per-board
.xlsm "pinout"/"normal" sheets). For DV500 the xlsm filled the index-0 GPIO
and index-1 names pin_mux.c never configures (GPIO2_6/2_7, MDCLK0/MDIO0,
the GPIO13/14 alternates on the MIPI_RX1 pads), added five U-Boot-only pins
(PWM0/1/2, USB_PWREN, USB_OVRCUR), and provided the PMC AON GPIO9 pads
(0x11120204-0x1112021C). Mux values nothing selects are left "reserved".
All addresses verified in-range, de-duplicated, and every pin_mux.c-
configured register is covered.

Also audit CV610regs (cv6xx): against the SDK pin_mux.c, add 19 registers
the SDK configures that were missing (the VI data bus io2 0x30-0x78 and
UART2 io1 0x10/0x14); and against the vendor cv6xx U-Boot .xlsm, add five
more the kernel never touches: SFC_CSN1 (io0 0x24), USB_OVRCUR/USB_PWREN
(io0 0x58/0x5C) and the Ethernet link LEDs (io1 0x18/0x1C).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@widgetii widgetii force-pushed the feat/dv500-reginfo branch from 9424ce7 to 40ccb65 Compare June 27, 2026 08:19
@widgetii widgetii merged commit a12cf00 into master Jun 27, 2026
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@widgetii widgetii deleted the feat/dv500-reginfo branch June 27, 2026 08:22
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