From 4044122886aeccf0c0bc3e9dc75bd3d34897ed0b Mon Sep 17 00:00:00 2001 From: Sneha Voona Date: Fri, 10 Apr 2026 11:56:01 +0530 Subject: [PATCH 01/10] scripts: add support for ACP_7_X platform Add ACP_7_X platform support to xtensa-build-zephyr.py build script. Signed-off-by: Sneha Voona Co-authored-by: DineshKumar Kalva --- scripts/xtensa-build-zephyr.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py index 36c0a25aabb5..2fa446d22a2a 100755 --- a/scripts/xtensa-build-zephyr.py +++ b/scripts/xtensa-build-zephyr.py @@ -117,6 +117,12 @@ class PlatformConfig: "ACP_7_0_HiFi5_NNE_PROD", RIMAGE_KEY = "key param ignored by acp_7_0" ), + "acp_7_x" : PlatformConfig( + "amd", "acp_7_x_adsp/acp_7_x", + f"RI-2022.9{xtensa_tools_version_postfix}", + "ACP73x_HiFi5_NNE_PROD", + RIMAGE_KEY = "key param ignored by acp_7_x" + ), # MediaTek platforms # (move to platform_configs_all on next Zephyr SDK release after 0.17.0) "mt8195" : PlatformConfig( @@ -1324,7 +1330,7 @@ def gzip_compress(fname, gzdst=None): RI_INFO_UNSUPPORTED = [] RI_INFO_UNSUPPORTED += ['imx8', 'imx8x', 'imx8m', 'imx8m_cm7', 'imx8ulp', 'imx95'] -RI_INFO_UNSUPPORTED += ['rn', 'acp_6_0', 'acp_7_0'] +RI_INFO_UNSUPPORTED += ['rn', 'acp_6_0', 'acp_7_0', 'acp_7_x'] RI_INFO_UNSUPPORTED += ['mt8186', 'mt8188', 'mt8195', 'mt8196', 'mt8365'] RI_INFO_UNSUPPORTED += ['qemu_xtensa', 'qemu_xtensa_mmu'] From df18acd44c826a2ee7fb0d36b5b1107606eec55c Mon Sep 17 00:00:00 2001 From: Sneha Voona Date: Fri, 10 Apr 2026 11:56:01 +0530 Subject: [PATCH 02/10] src: arch: xtensa: configs: add ACP_7_X defconfig Add the Xtensa HiFi5 defconfig for the AMD ACP 7.X audio DSP. Signed-off-by: Sneha Voona Co-authored-by: DineshKumar Kalva --- src/arch/xtensa/configs/acp_7_x_defconfig | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/arch/xtensa/configs/acp_7_x_defconfig diff --git a/src/arch/xtensa/configs/acp_7_x_defconfig b/src/arch/xtensa/configs/acp_7_x_defconfig new file mode 100644 index 000000000000..9a24d5517df4 --- /dev/null +++ b/src/arch/xtensa/configs/acp_7_x_defconfig @@ -0,0 +1,32 @@ +CONFIG_ACP_7_X=y +CONFIG_RIMAGE_SIGNING_SCHEMA="acp_7_3" +CONFIG_TRACE_CHANNEL=7 +CONFIG_WRAP_ACTUAL_POSITION=y +CONFIG_CORE_COUNT=1 +CONFIG_FORMAT_CONVERT_HIFI3=n +CONFIG_LP_SRAM=n +CONFIG_HAVE_AGENT=n +CONFIG_COMP_VOLUME=n +CONFIG_COMP_SRC=n +CONFIG_COMP_FIR=n +CONFIG_COMP_IIR=n +CONFIG_COMP_DCBLOCK=n +CONFIG_COMP_CROSSOVER=n +CONFIG_COMP_DRC=n +CONFIG_COMP_MULTIBAND_DRC=n +CONFIG_COMP_TONE=n +CONFIG_COMP_SWITCH=n +CONFIG_COMP_KPB=n +CONFIG_MAXIM_DSM=n +CONFIG_COMP_ASRC=n +CONFIG_COMP_IGO_NR=n +CONFIG_COMP_COPIER=n +CONFIG_COMP_RTNR=n +CONFIG_COMP_ARIA=n +CONFIG_COMP_BASEFW_IPC4=n +CONFIG_COMP_UP_DOWN_MIXER=n +CONFIG_COMP_TDFB=n +CONFIG_COMP_MUX=n +CONFIG_COMP_SEL=n +CONFIG_COMP_MIXER=n +CONFIG_PROBE=n From 59ade47b31af23c02803b1d2fce68933bf143d1d Mon Sep 17 00:00:00 2001 From: Sneha Voona Date: Fri, 10 Apr 2026 11:56:01 +0530 Subject: [PATCH 03/10] tools: topology: add ACP_7_X topology support for native Zephyr Add the SoundWire topology M4 source file for AMD ACP 7.X (sof-acp_7_x_sdw.m4). The topology defines the SoundWire pipeline for native Zephyr, covering playback and capture paths for the SoundWire SW0 instance on ACP 7.X hardware. Signed-off-by: Sneha Voona --- tools/topology/topology1/CMakeLists.txt | 1 + tools/topology/topology1/sof-acp_7_x_sdw.m4 | 132 ++++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 tools/topology/topology1/sof-acp_7_x_sdw.m4 diff --git a/tools/topology/topology1/CMakeLists.txt b/tools/topology/topology1/CMakeLists.txt index c6ae06d0be04..05d912bb9ec3 100644 --- a/tools/topology/topology1/CMakeLists.txt +++ b/tools/topology/topology1/CMakeLists.txt @@ -122,6 +122,7 @@ set(TPLGS "sof-acp_6_3_sdw\;sof-acp_6_3-rt711-l0-rt1316-l0-rt714-l1" "sof-acp_7_0\;sof-acp_7_0" "sof-acp_7_0_sdw\;sof-acp_7_0-rt722-l0" + "sof-acp_7_x_sdw\;sof-acp_7_x-rt721-l0" ) # This empty 'production/' source subdirectory exists only to create the diff --git a/tools/topology/topology1/sof-acp_7_x_sdw.m4 b/tools/topology/topology1/sof-acp_7_x_sdw.m4 new file mode 100644 index 000000000000..5574b6cbb155 --- /dev/null +++ b/tools/topology/topology1/sof-acp_7_x_sdw.m4 @@ -0,0 +1,132 @@ +#Required Topology for rt721 with ACP DMIC Card for ACP_7_X +# +# PCM Description DAI LINK DAI BE +# 0 HS Playback 0 SDW0-PIN0-PLAYBACK-SimpleJack AUDIO_TX +# 1 HS Capture 1 SDW0-PIN11-CAPTURE-SimpleJack AUDIO_RX +# 2 Speaker playback 2 SDW0-PIN4-PLAYBACK-SmartAmp BT_TX +# 4 SDW DMIC 4 SDW0-PIN15-CAPTURE-SmartMic HS_RX + +# +# Define the pipelines +# +# PCM0 ----> buffer ----> AUDIO_TX +# PCM1 <---- buffer <---- AUDIO_RX +# PCM2 ----> buffer ----> BT_TX +# PCM4 <---- buffer <---- HS_RX + +# Include topology builder +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') +include(`acp-sdw.m4') +include(`acp-dmic.m4') + +# Include TLV library +include(`common/tlv.m4') + +# Include Token library +include(`sof/tokens.m4') + +# Include ACP DSP configuration +include(`platform/amd/acp.m4') + +DEBUG_START + +define(DI_SDW0_ACP_SW_AUDIO_0_TX, 0 ) +define(DI_SDW0_ACP_SW_AUDIO_4_TX, 4 ) +define(DI_SDW0_ACP_SW_AUDIO_0_RX, 11) +define(DI_SDW0_ACP_SW_AUDIO_5_RX, 16) + +define(DAI_BE_SDW0_ACP_SW_AUDIO_4_TX, SDW0-PIN4-PLAYBACK-SmartAmp) +define(DAI_BE_SDW0_ACP_SW_AUDIO_0_TX, SDW0-PIN0-PLAYBACK-SimpleJack) + +define(DAI_BE_SDW0_ACP_SW_AUDIO_0_RX, SDW0-PIN11-CAPTURE-SimpleJack) +define(DAI_BE_SDW0_ACP_SW_AUDIO_5_RX, SDW0-PIN16-CAPTURE-SmartMic) + +#pipeline: name of the predefined pipeline +#pipe id: pipeline ID. This should be a unique ID identifying the pipeline +#pcm: PCM ID. This will be used to bind to the correct front end DAI link + +dnl PIPELINE_PCM_ADD(pipeline, +dnl pipe id, pcm, max channels, format, +dnl period, priority, core, +dnl pcm_min_rate, pcm_max_rate, pipeline_rate) + +dnl DAI_ADD(pipeline, +dnl pipe id, dai type, dai_index, dai_be, +dnl buffer, periods, format, +dnl deadline, priority, core, time_domain) + +dnl DAI_CONFIG(type, dai_index, link_id, name, acphs_config/acpdmic_config) +dnl ACPHS_CONFIG(format, mclk, bclk, fsync, tdm, acphs_config_data) +dnl ACP_CLOCK(clock, freq, codec_provider, polarity) +dnl ACPHS_CONFIG_DATA(type, idx, valid bits, mclk_id) +dnl mclk_id is optional + +#/**********************************************************************************/ +# PCM 0, HS Playback, DAI link id 0, Dai index 0(Audio_Tx), BE SW0-PIN0-PLAYBACK +PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, + 0, 0, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +DAI_ADD(sof/pipe-dai-playback.m4, 0, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_TX, DAI_BE_SDW0_ACP_SW_AUDIO_0_TX, +PIPELINE_SOURCE_0, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_TX, 0, DAI_BE_SDW0_ACP_SW_AUDIO_0_TX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_TX, 48000, 2))) +PCM_PLAYBACK_ADD(ACP-SW0-PIN0-Playback-HS, 0, PIPELINE_PCM_0) + +#/**********************************************************************************/ +#PCM 2, Speaker Playback, PIPE line 2, DAI link id 2, Dai index 4(DI_SDW0_ACP_SW_AUDIO_4_TX), DAI BE SDW0-PIN4-PLAYBACK-SmartAmp +PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, + 2, 2, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# playback DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-playback.m4, 2, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_4_TX, DAI_BE_SDW0_ACP_SW_AUDIO_4_TX, + PIPELINE_SOURCE_2, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_4_TX, 2, DAI_BE_SDW0_ACP_SW_AUDIO_4_TX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_4_TX, 48000, 2))) + +PCM_PLAYBACK_ADD(ACP-SW0-PIN4-Playback-SPK, 2, PIPELINE_PCM_2) +#/**********************************************************************************/ + +#/**********************************************************************************/ +#PCM 1, HS Capture, DAI link id 1, Dai index 11(DI_SDW0_ACP_SW_AUDIO_0_RX), BE DAI_BE_SDW0_ACP_SW_AUDIO_0_RX +# Capture pipeline 1 on PCM 1 using max 2 channels of s16le. +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 1, 1, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# Capture DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-capture.m4, 1, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_RX, DAI_BE_SDW0_ACP_SW_AUDIO_0_RX, + PIPELINE_SINK_1, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_RX, 1, DAI_BE_SDW0_ACP_SW_AUDIO_0_RX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_RX, 48000, 2))) + +PCM_CAPTURE_ADD(ACP-SW0-PIN11-Capture-HS, 1, PIPELINE_PCM_1) +#/**********************************************************************************/ +#/**********************************************************************************/ +#PCM 4, SDW Capture, DAI link id 4, Dai index 16(DI_SDW0_ACP_SW_AUDIO_5_RX), BE SDW0-PIN16-CAPTURE-SmartMic +# Capture pipeline 1 on PCM 1 using max 2 channels of s16le. +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 4, 4, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# Capture DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-capture.m4, 4, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_5_RX, DAI_BE_SDW0_ACP_SW_AUDIO_5_RX, + PIPELINE_SINK_4, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_5_RX, 4, DAI_BE_SDW0_ACP_SW_AUDIO_5_RX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_5_RX, 48000, 2))) + +PCM_CAPTURE_ADD(ACP-SW0-PIN16-CAPTURE-DMIC, 4, PIPELINE_PCM_4) +#/**********************************************************************************/ + +DEBUG_END \ No newline at end of file From d4aac277ab729412da1a49aa0afb54a4f42b12d7 Mon Sep 17 00:00:00 2001 From: Sneha Voona Date: Fri, 10 Apr 2026 11:56:01 +0530 Subject: [PATCH 04/10] rimage: config: add acp_7_x toml file to support acp_7_x build Add the rimage toml configuration file for AMD ACP 7.X to enable signing and packaging of the sof-acp_7_x.ri firmware binary. The file specifies the adsp name and memory layout required by rimage to produce a correctly formatted image for the ACP 7.X audio DSP. Signed-off-by: Sneha Voona Co-authored-by: DineshKumar Kalva --- tools/rimage/config/acp_7_x.toml | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 tools/rimage/config/acp_7_x.toml diff --git a/tools/rimage/config/acp_7_x.toml b/tools/rimage/config/acp_7_x.toml new file mode 100644 index 000000000000..7787bb3c6e1c --- /dev/null +++ b/tools/rimage/config/acp_7_x.toml @@ -0,0 +1,20 @@ +version = [1, 0] # use simple file write + +[adsp] +name = "acp_7_x" + +[[adsp.mem_zone]] +type = "IRAM" +base = "0x7F000000" +size = "0x20000" +host_offset = "0x0" +[[adsp.mem_zone]] +type = "DRAM" +base = "0xE0000000" +size = "0x20000" +host_offset = "0x0" +[[adsp.mem_zone]] +type = "SRAM" +base = "0x6000C000" +size = "0x274000" +host_offset = "0x0" \ No newline at end of file From c90bc6f88ee5105e0e95227370ab0176f1fe44b6 Mon Sep 17 00:00:00 2001 From: Sneha Voona Date: Fri, 10 Apr 2026 11:56:01 +0530 Subject: [PATCH 05/10] amd: acp_7_x: add build support for ACP_7_X Add CMakeLists.txt files to integrate the ACP 7.X platform and driver sources into the SOF CMake build system. This covers the platform-level build (platform.c, lib/clk.c) and the driver-level build (ipc.c) under src/drivers/amd/acp_7_x/, enabling the ACP_7_X platform to be compiled when CONFIG_ACP_7_X is selected. Signed-off-by: Sneha Voona Co-authored-by: DineshKumar Kalva --- src/drivers/amd/CMakeLists.txt | 6 +++++- src/platform/Kconfig | 14 ++++++++++++++ src/platform/amd/CMakeLists.txt | 6 +++++- 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/src/drivers/amd/CMakeLists.txt b/src/drivers/amd/CMakeLists.txt index a6ece5e3a0ed..8b58af2b3017 100644 --- a/src/drivers/amd/CMakeLists.txt +++ b/src/drivers/amd/CMakeLists.txt @@ -1,9 +1,13 @@ # SPDX-License-Identifier: BSD-3-Clause -add_subdirectory(common) +if(CONFIG_RENOIR OR CONFIG_VANGOGH OR CONFIG_REMBRANDT OR CONFIG_ACP_6_3 OR CONFIG_ACP_7_0) + add_subdirectory(common) +endif() if(CONFIG_RENOIR) add_subdirectory(renoir) elseif(CONFIG_REMBRANDT OR CONFIG_ACP_6_3 OR CONFIG_ACP_7_0) add_subdirectory(rembrandt) elseif(CONFIG_VANGOGH) add_subdirectory(vangogh) +elseif(CONFIG_ACP_7_X) + add_subdirectory(acp_7_x) endif() diff --git a/src/platform/Kconfig b/src/platform/Kconfig index 2de2c5ed00da..1970c80cbd1b 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -251,6 +251,19 @@ config ACP_7_0 help Select if your target platform is acp_7_0-compatible +config ACP_7_X + bool "Build for ACP_7_X" + select XT_INTERRUPT_LEVEL_5 + select XT_INTERRUPT_LEVEL_3 + select XT_INTERRUPT_LEVEL_1 + select XT_INTERRUPT_LEVEL_4 + select XT_WAITI_DELAY + select XTENSA_EXCLUSIVE + select AMD + select AMD_BINARY_BUILD + help + Select if your target platform is acp_7_x-compatible + config MT8186 bool "Build for MTK MT8186 (XTOS)" select XT_INTERRUPT_LEVEL_1 @@ -544,6 +557,7 @@ config RIMAGE_SIGNING_SCHEMA default "vangogh" if VANGOGH default "acp_6_3" if ACP_6_3 default "acp_7_0" if ACP_7_0 + default "acp_7_x" if ACP_7_X default "mt8186" if MT8186 default "mt8188" if MT8188 default "mt8195" if MT8195 diff --git a/src/platform/amd/CMakeLists.txt b/src/platform/amd/CMakeLists.txt index 5b971f6e4b9e..9ae93911168d 100644 --- a/src/platform/amd/CMakeLists.txt +++ b/src/platform/amd/CMakeLists.txt @@ -1,5 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause -add_subdirectory(common) +if(CONFIG_RENOIR OR CONFIG_VANGOGH OR CONFIG_REMBRANDT OR CONFIG_ACP_6_3 OR CONFIG_ACP_7_0) + add_subdirectory(common) +endif() if(CONFIG_RENOIR) add_subdirectory(renoir) elseif(CONFIG_REMBRANDT) @@ -10,4 +12,6 @@ elseif(CONFIG_ACP_6_3) add_subdirectory(acp_6_3) elseif(CONFIG_ACP_7_0) add_subdirectory(acp_7_0) +elseif(CONFIG_ACP_7_X) + add_subdirectory(acp_7_x) endif() From 65a9d9fa4de7d0bfa1b2ab7a1964f29dabbab9bb Mon Sep 17 00:00:00 2001 From: Sneha Voona Date: Wed, 29 Apr 2026 12:44:33 +0530 Subject: [PATCH 06/10] platform: add ACP_7_X platform support for native Zephyr Add ACP_7_X platform support for native Zephyr drivers. Changes include: - Add platform-specific files for ACP_7_X native Zephyr support - Add ACP_7_X in zephyr/CMakeLists.txt with platform sources, include directories and PLATFORM variable - Add app/boards/acp_7_x_adsp.conf with ACP_7_X Kconfig options for native Zephyr drivers (DMA, DAI, interrupts) Signed-off-by: Sneha Voona Co-authored-by: DineshKumar Kalva --- app/boards/acp_7_x_adsp.conf | 52 ++ src/drivers/amd/acp_7_x/CMakeLists.txt | 5 + src/drivers/amd/acp_7_x/ipc.c | 280 +++++++ src/platform/amd/acp_7_x/CMakeLists.txt | 4 + .../include/arch/xtensa/config/core-isa.h | 757 ++++++++++++++++++ .../include/arch/xtensa/config/core-matmap.h | 106 +++ .../acp_7_x/include/arch/xtensa/config/defs.h | 38 + .../include/arch/xtensa/config/specreg.h | 109 +++ .../include/arch/xtensa/config/system.h | 262 ++++++ .../include/arch/xtensa/config/tie-asm.h | 382 +++++++++ .../acp_7_x/include/arch/xtensa/config/tie.h | 211 +++++ .../include/arch/xtensa/tie/xt_datacache.h | 103 +++ .../acp_7_x/include/platform/fw_scratch_mem.h | 119 +++ .../amd/acp_7_x/include/platform/lib/memory.h | 252 ++++++ .../amd/acp_7_x/include/platform/platform.h | 101 +++ .../acp_7_x/include/platform/platform_misc.h | 577 +++++++++++++ src/platform/amd/acp_7_x/lib/CMakeLists.txt | 5 + src/platform/amd/acp_7_x/lib/clk.c | 427 ++++++++++ src/platform/amd/acp_7_x/platform.c | 208 +++++ zephyr/CMakeLists.txt | 14 + 20 files changed, 4012 insertions(+) create mode 100644 app/boards/acp_7_x_adsp.conf create mode 100644 src/drivers/amd/acp_7_x/CMakeLists.txt create mode 100644 src/drivers/amd/acp_7_x/ipc.c create mode 100644 src/platform/amd/acp_7_x/CMakeLists.txt create mode 100644 src/platform/amd/acp_7_x/include/arch/xtensa/config/core-isa.h create mode 100644 src/platform/amd/acp_7_x/include/arch/xtensa/config/core-matmap.h create mode 100644 src/platform/amd/acp_7_x/include/arch/xtensa/config/defs.h create mode 100644 src/platform/amd/acp_7_x/include/arch/xtensa/config/specreg.h create mode 100644 src/platform/amd/acp_7_x/include/arch/xtensa/config/system.h create mode 100644 src/platform/amd/acp_7_x/include/arch/xtensa/config/tie-asm.h create mode 100644 src/platform/amd/acp_7_x/include/arch/xtensa/config/tie.h create mode 100755 src/platform/amd/acp_7_x/include/arch/xtensa/tie/xt_datacache.h create mode 100644 src/platform/amd/acp_7_x/include/platform/fw_scratch_mem.h create mode 100644 src/platform/amd/acp_7_x/include/platform/lib/memory.h create mode 100644 src/platform/amd/acp_7_x/include/platform/platform.h create mode 100644 src/platform/amd/acp_7_x/include/platform/platform_misc.h create mode 100644 src/platform/amd/acp_7_x/lib/CMakeLists.txt create mode 100644 src/platform/amd/acp_7_x/lib/clk.c create mode 100644 src/platform/amd/acp_7_x/platform.c diff --git a/app/boards/acp_7_x_adsp.conf b/app/boards/acp_7_x_adsp.conf new file mode 100644 index 000000000000..c8b2fab3e744 --- /dev/null +++ b/app/boards/acp_7_x_adsp.conf @@ -0,0 +1,52 @@ +CONFIG_ACP_7_X=y +CONFIG_HAVE_AGENT=n +CONFIG_DCACHE_LINE_SIZE_DETECT=n +CONFIG_DCACHE_LINE_SIZE=128 +CONFIG_DYNAMIC_INTERRUPTS=y +CONFIG_SHARED_INTERRUPTS=n +CONFIG_ZEPHYR_LOG=y +CONFIG_LOG_MODE_DEFERRED=n +CONFIG_LOG_MODE_MINIMAL=y +CONFIG_DMA=y +CONFIG_DMA_DOMAIN=n +CONFIG_ZEPHYR_NATIVE_DRIVERS=y +CONFIG_INTC_AMD_ACP=y +CONFIG_DMA_AMD_ACP_HOST=y +CONFIG_DMA_AMD_ACP_SDW=y +CONFIG_DAI_AMD_SDW=y +CONFIG_AMS=n +CONFIG_WRAP_ACTUAL_POSITION=y +CONFIG_TRACE=n +CONFIG_COMP_VOLUME=y +CONFIG_COMP_SRC=n +CONFIG_COMP_FIR=n +CONFIG_COMP_IIR=n +CONFIG_COMP_DCBLOCK=n +CONFIG_COMP_CROSSOVER=n +CONFIG_COMP_DRC=n +CONFIG_COMP_MULTIBAND_DRC=n +CONFIG_COMP_TONE=n +CONFIG_COMP_KPB=n +CONFIG_MAXIM_DSM=n +CONFIG_COMP_ASRC=n +CONFIG_COMP_IGO_NR=n +CONFIG_COMP_COPIER=n +CONFIG_COMP_RTNR=n +CONFIG_COMP_ARIA=n +CONFIG_COMP_BASEFW_IPC4=n +CONFIG_COMP_UP_DOWN_MIXER=n +CONFIG_COMP_TDFB=n +CONFIG_COMP_SEL=n +CONFIG_COMP_MIXER=n +CONFIG_ASRC_SUPPORT_CONVERSION_24000_TO_08000=n +CONFIG_ASRC_SUPPORT_CONVERSION_24000_TO_16000=n +CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_08000=n +CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_11025=n +CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_12000=n +CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_16000=n +CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_22050=n +CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_24000=n +CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_32000=n +CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_44100=n +CONFIG_CORE_COUNT=1 +CONFIG_FORMAT_CONVERT_HIFI3=n diff --git a/src/drivers/amd/acp_7_x/CMakeLists.txt b/src/drivers/amd/acp_7_x/CMakeLists.txt new file mode 100644 index 000000000000..5dd81656d1ea --- /dev/null +++ b/src/drivers/amd/acp_7_x/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_local_sources(sof + ipc.c +) diff --git a/src/drivers/amd/acp_7_x/ipc.c b/src/drivers/amd/acp_7_x/ipc.c new file mode 100644 index 000000000000..dcdb4e66807f --- /dev/null +++ b/src/drivers/amd/acp_7_x/ipc.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2026 AMD. All rights reserved. + * + * Author: Basavaraj Hiregoudar + * Sneha Voona + * DineshKumar Kalva + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +volatile acp_scratch_mem_config_t *pscratch_mem_cfg = + (volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + + SCRATCH_REG_OFFSET); + +SOF_DEFINE_REG_UUID(ipc_task_amd); +extern volatile acp_scratch_mem_config_t *pscratch_mem_cfg; +LOG_MODULE_REGISTER(ipc_handler_file, LOG_LEVEL_DBG); + +#define HOST_TO_DSP_INTR 1 +#define INTERRUPT_DISABLE 0 +#define IRQ_NUM_EXT_LEVEL3 3 +#define IRQ_EXT_IPC_LEVEL_3 3 + +/* This function triggers a host interrupt from ACP DSP */ +void acp_dsp_to_host_intr_trig(void) +{ + acp_sw_intr_trig_t sw_intr_trig; + /* Read the Software Interrupt controller register and update */ + sw_intr_trig = (acp_sw_intr_trig_t) io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG); + /* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */ + sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_ENABLE; + /* Write the Software Interrupt controller register */ + io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all); +} + +/* Clear the Acknowledge ( status) for the host to DSP interrupt */ +static void acp_ack_intr_from_host(void) +{ + /* acknowledge the host interrupt */ + acp_dsp_sw_intr_stat_t sw_intr_stat; + + sw_intr_stat.u32all = 0; + sw_intr_stat.bits.host_to_dsp0_intr1_stat = INTERRUPT_ENABLE; + io_reg_write((PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT), sw_intr_stat.u32all); +} + +inline uint32_t sof_ipc_host_status(void) +{ + return (pscratch_mem_cfg->acp_host_ack_write | pscratch_mem_cfg->acp_host_msg_write); +} + +inline uint32_t sof_ipc_host_msg_flag(void) +{ + return pscratch_mem_cfg->acp_host_msg_write; +} + +inline uint32_t sof_ipc_host_ack_flag(void) +{ + return pscratch_mem_cfg->acp_host_ack_write; +} + +inline uint32_t sof_ipc_dsp_status(void) +{ + return (pscratch_mem_cfg->acp_dsp_msg_write | pscratch_mem_cfg->acp_dsp_ack_write); +} + +inline void sof_ipc_host_ack_clear(void) +{ + pscratch_mem_cfg->acp_host_ack_write = 0; +} + +inline void sof_ipc_host_msg_clear(void) +{ + pscratch_mem_cfg->acp_host_msg_write = 0; +} + +inline void sof_ipc_dsp_ack_set(void) +{ + pscratch_mem_cfg->acp_dsp_ack_write = 1; +} + +inline void sof_ipc_dsp_msg_set(void) +{ + pscratch_mem_cfg->acp_dsp_msg_write = 1; +} + +enum task_state ipc_platform_do_cmd(struct ipc *ipc) +{ + struct ipc_cmd_hdr *hdr; + + hdr = mailbox_validate(); + ipc_cmd(hdr); + return SOF_TASK_STATE_COMPLETED; +} + +int platform_ipc_init(struct ipc *ipc) +{ + ipc_set_drvdata(ipc, NULL); + /* schedule */ + schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_amd_uuid), + &ipc_task_ops, ipc, 0, 0); + interrupt_disable(IRQ_EXT_IPC_LEVEL_3, 0); + interrupt_unregister(IRQ_EXT_IPC_LEVEL_3, ipc); + interrupt_register(IRQ_EXT_IPC_LEVEL_3, amd_irq_handler, ipc); + /* Enabling software interuppts */ + interrupt_enable(IRQ_EXT_IPC_LEVEL_3, ipc); + return 0; +} + +void amd_irq_handler(void *arg) +{ + struct ipc *ipc = arg; + uint32_t status; + uint32_t lock; + acp_dsp_sw_intr_stat_t swintrstat; + acp_sw_intr_trig_t swintrtrig; + + swintrstat = (acp_dsp_sw_intr_stat_t)io_reg_read(PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT); + status = swintrstat.u32all & HOST_TO_DSP_INTR; + if (status) { + /* Interrupt source */ + lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0); + /* Removed unbounded while(lock) loop - using bounded loop below instead */ + int timeout = 20000; + + while (lock && --timeout > 0) { + lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0); + } + if (timeout == 0) { + /* Give up, don't block forever */ + LOG_ERR("ACP semaphore timeout in IRQ handler"); + return; + } + /***************************************************** */ + /* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */ + swintrtrig = (acp_sw_intr_trig_t) + io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG); + swintrtrig.bits.trig_host_to_dsp0_intr1 = INTERRUPT_DISABLE; + swintrtrig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE; + io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), + swintrtrig.u32all); + + /* Clear the Host to DSP Status Register */ + acp_ack_intr_from_host(); + /********************************************* */ + + if (sof_ipc_host_status()) { + if (sof_ipc_host_ack_flag()) { + /* Clear the ACK from host */ + sof_ipc_host_ack_clear(); + } + /* Check if new message from host */ + if (sof_ipc_host_msg_flag()) { + /* Clear the msg bit from host*/ + sof_ipc_host_msg_clear(); + ipc_schedule_process(ipc); + } + } else { + tr_err(&ipc_tr, "IPC:interrupt without setting flags host status 0x%x", sof_ipc_host_status()); + io_reg_write((PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0), 0); + } + } +} + +void ipc_platform_complete_cmd(struct ipc *ipc) +{ + acp_sw_intr_trig_t sw_intr_trig; + + /* Set Dsp Ack for msg from host */ + sof_ipc_dsp_ack_set(); + /* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */ + sw_intr_trig = (acp_sw_intr_trig_t) + io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG); + sw_intr_trig.bits.trig_host_to_dsp0_intr1 = INTERRUPT_DISABLE; + sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE; + io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all); + /* now interrupt host to tell it we have sent a message */ + acp_dsp_to_host_intr_trig(); + /* Disable the trigger bit in ACP_DSP_SW_INTR_TRIG register */ + sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG); + sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE; + io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all); + io_reg_write((PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0), 0); + LOG_DBG("IPC cmd completed"); + if (ipc->pm_prepare_D3) { + while (1) { + wait_for_interrupt(0); + } + } +} + +int ipc_platform_send_msg(const struct ipc_msg *msg) +{ + int ret = 0; + acp_sw_intr_trig_t sw_intr_trig; + acp_dsp_sw_intr_stat_t sw_intr_stat; + uint32_t status; + uint32_t lock; + /* Check if host cleared the status for previous messages */ + sw_intr_stat = (acp_dsp_sw_intr_stat_t) + io_reg_read(PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT); + status = sw_intr_stat.bits.dsp0_to_host_intr_stat; + if (sof_ipc_dsp_status() || status) { + return -EBUSY; + } + lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0); + int timeout = 20000; + + while (lock && --timeout > 0) { + lock = io_reg_read(PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0); + } + if (timeout == 0) { + /* Give up, don't block forever */ + LOG_ERR("ACP semaphore timeout in IPC send"); + return -EBUSY; + } + + /* Write new message in the mailbox */ + mailbox_dspbox_write(0, msg->tx_data, msg->tx_size); + /* Need to set DSP message flag */ + sof_ipc_dsp_msg_set(); + /* Trigger host interrupt to notify new message from DSP */ + /* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */ + sw_intr_trig = (acp_sw_intr_trig_t) + io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG); + sw_intr_trig.bits.trig_host_to_dsp0_intr1 = INTERRUPT_DISABLE; + sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE; + io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all); + acp_dsp_to_host_intr_trig(); + /* Disable the trigger bit in ACP_DSP_SW_INTR_TRIG register */ + sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG); + sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE; + io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all); + io_reg_write((PU_REGISTER_BASE + ACP_AXI2DAGB_SEM_0), lock); + return ret; +} + +void ipc_platform_send_msg_direct(const struct ipc_msg *msg) +{ + acp_sw_intr_trig_t sw_intr_trig; + + /* Write message directly to mailbox - no status checks for emergency */ + mailbox_dspbox_write(0, msg->tx_data, msg->tx_size); + + /* Set DSP message flag */ + sof_ipc_dsp_msg_set(); + + /* Interrupt host immediately */ + acp_dsp_to_host_intr_trig(); + + /* Disable the trigger bit */ + sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG); + sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE; + io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all); +} diff --git a/src/platform/amd/acp_7_x/CMakeLists.txt b/src/platform/amd/acp_7_x/CMakeLists.txt new file mode 100644 index 000000000000..3108ac12f8db --- /dev/null +++ b/src/platform/amd/acp_7_x/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_subdirectory(lib) +add_local_sources(sof platform.c) diff --git a/src/platform/amd/acp_7_x/include/arch/xtensa/config/core-isa.h b/src/platform/amd/acp_7_x/include/arch/xtensa/config/core-isa.h new file mode 100644 index 000000000000..f1f02e8bc786 --- /dev/null +++ b/src/platform/amd/acp_7_x/include/arch/xtensa/config/core-isa.h @@ -0,0 +1,757 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Customer ID=20511; Build=0xb6494; Copyright (c) 1999-2024 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_CORE_CONFIGURATION_H_ +#define XTENSA_CORE_CONFIGURATION_H_ + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 16 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ +#define XCHAL_HAVE_LX 1 /* LX core */ +#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */ +#define XCHAL_HAVE_RNX 0 /* RNX core (starting RJ) */ + +#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion */ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5 1 /* HiFi5 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5_NN_MAC 1 /* HiFi5 Audio Engine NN-MAC option */ +#define XCHAL_HAVE_HIFI5_VFPU 1 /* HiFi5 Audio Engine Single-Precision VFPU option */ +#define XCHAL_HAVE_HIFI5_HP_VFPU 1 /* HiFi5 Audio Engine Half-Precision VFPU option */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 1 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 1 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI1 0 /* HiFi1 */ +#define XCHAL_HAVE_HIFI1_VFPU 0 /* HiFi1 VFPU option */ +#define XCHAL_HAVE_HIFI1_LOW_LATENCY_MAC_FMA 0 /* HiFi1 Low-latency MAC/FMA option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 1 /* user SP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */ +#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */ +#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */ +#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */ +#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */ + +#define XCHAL_HAVE_PDX 0 /* PDX-LX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */ +#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */ +#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */ +#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BALL 0 +#define XCHAL_HAVE_BALLAP 0 +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/ +#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/ +#define XCHAL_HAVE_CONNX_B_DP_VFPU 0 /* Double-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_DPX_VFPU 0 /* Double-precision Vector Floating-point option on FP Machine*/ +#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HP_VFPU 0 /* Half-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_LDPC 0 /* LDPC option on ConnX B10 & B20 */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6, Q7 or Q8 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_DP_VFPU 0 /* dp_vfpu option on Vision Q7/Q8 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */ +#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */ +#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +#define XCHAL_HAVE_XNNE 1 /* XNNE */ +#define XCHAL_XNNE_VERSION 2 /* XNNE version */ +#define XCHAL_XNNE_PADDR 0x20000000 /* Base address */ +#define XCHAL_XNNE_NUM_SBLKS 1 /* SBLK count */ +#define XCHAL_XNNE_MBLKS_PER_SBLK 4 /* MBLKs per SBLK */ +#define XCHAL_XNNE_IBUF_SIZE 0 /* IBuf size */ +#define XCHAL_XNNE_OBUF_SIZE 0 /* OBuf size */ +#define XCHAL_XNNE_CBUF_SIZE 0 /* CBuf size */ +#define XCHAL_XNNE_UBUF_SIZE 131072 /* UBuf size */ +#define XCHAL_XNNE_AXIM_DATA_WIDTH 128 /* Data Width */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 2 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 16 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 16 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_UNIFIED_LOADSTORE 0 + +#define XCHAL_SW_VERSION 1409000 /* sw version of this header */ +#define XCHAL_SW_VERSION_MAJOR 14000 /* major ver# of sw */ +#define XCHAL_SW_VERSION_MINOR 9 /* minor ver# of sw */ +#define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */ +#define XCHAL_SW_MINOR_VERSION 1409000 /* with zeroed micro */ +#define XCHAL_SW_MICRO_VERSION 1409000 + +#define XCHAL_CORE_ID "ACP7Xx_HiFi5_NNE_PROD" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x000B6494 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC0039286 /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x2A4B6494 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX7.1.9" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2810 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 9 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */ +#define XCHAL_HW_VERSION 281090 /* major*100+(major<2810 ? minor : minor*10+micro) */ +#define XCHAL_HW_REL_LX7 1 +#define XCHAL_HW_REL_LX7_1 1 +#define XCHAL_HW_REL_LX7_1_9 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2810 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 9 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 281090 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2810 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 9 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 281090 /* latest targeted hw */ + +/* Config is enabled for functional safety: */ +#define XCHAL_HAVE_FUNC_SAFETY 0 + +/* Config is enabled for secure operation: */ +#define XCHAL_HAVE_SECURE 0 + +#define XCHAL_HAVE_APB 0 + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 131072 /* I-cache size in bytes or 0 */ +#define XCHAL_ICACHE_SIZE_LOG2 17 +#define XCHAL_DCACHE_SIZE 131072 /* D-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE_LOG2 17 + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 cache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 2 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_CME_DOWNGRADES 0 +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 1 /* Dcache dynamic way support */ +#define XCHAL_HAVE_ICACHE_DYN_ENABLE 1 /* Icache enabled via MEMCTL */ +#define XCHAL_HAVE_DCACHE_DYN_ENABLE 1 /* Dcache enabled via MEMCTL */ + +#define XCHAL_L1SCACHE_SIZE 0 +#define XCHAL_L1SCACHE_SIZE_LOG2 0 +#define XCHAL_L1SCACHE_WAYS 1 +#define XCHAL_L1SCACHE_WAYS_LOG2 0 +#define XCHAL_L1SCACHE_ACCESS_SIZE 0 +#define XCHAL_L1SCACHE_BANKS 1 + +#define XCHAL_L1VCACHE_SIZE 0 + +#define XCHAL_HAVE_L2 0 /* NX L2 cache controller */ +#define XCHAL_HAVE_L2_CACHE 0 +#define XCHAL_NUM_CORES_IN_CLUSTER 0 + +/* PRID_ID macros are for internal use only ... subject to removal */ +#define PRID_ID_SHIFT 0 +#define PRID_ID_BITS 4 +#define PRID_ID_MASK 0x0000000F + +/* This one is a form of caching, though not architecturally visible: */ +#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 1 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 1 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 8 +#define XCHAL_DCACHE_SETWIDTH 8 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_ICACHE_WAYS_LOG2 2 +#define XCHAL_DCACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS_LOG2 2 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 +#define XCHAL_ICACHE_ECC_WIDTH 4 +#define XCHAL_DCACHE_ECC_WIDTH 1 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 16 +#define XCHAL_DCACHE_ACCESS_SIZE 16 + +#define XCHAL_DCACHE_BANKS 2 /* number of banks */ + +/* The number of Cache lines associated with a single cache tag */ +#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0 + +/* Number of encoded cache attr bits (see for decoded bits): */ + +/* Extended memory attributes supported. */ +#define XCHAL_HAVE_EXT_CA 0 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ +#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */ +#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x7F000000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x7F000000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 524288 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM0 1 +#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0xE0000000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0xE0000000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 2 /* number of banks */ +#define XCHAL_HAVE_DATARAM0 1 +#define XCHAL_DATARAM0_HAVE_IDMA 1 /* idma supported by this local memory */ + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + IDMA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_IDMA 0 +#define XCHAL_IDMA_NUM_CHANNELS 1 /* number of channels */ +#define XCHAL_IDMA_ADDR_WIDTH 32 /* address width in bits */ +#define XCHAL_IDMA_DATA_WIDTH 128 /* data width in bits */ +#define XCHAL_IDMA_DESC_SIZE 32 /* max descriptor size */ +#define XCHAL_IDMA_MAX_OUTSTANDING_REQ 64 /* max outstanding requests */ +#define XCHAL_IDMA_HAVE_REORDERBUF 0 /* has reorder buffer */ +#define XCHAL_IDMA_HAVE_TRANSPOSE 0 /* has transpose function */ +#define XCHAL_HAVE_IDMA_TRANSPOSE 0 /* Deprecated */ +#define XCHAL_IDMA_NUM_AXI2AXI_CHAN 0 /* how many channels support AXI-to-AXI transfers */ +#define XCHAL_IDMA_ID_PER_CHANNEL 0 + +#define XCHAL_IDMA_CH0_DONE_INTERRUPT 9 +#define XCHAL_IDMA_CH0_ERR_INTERRUPT 10 + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 13 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 7 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ + + +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x00001F43 +#define XCHAL_INTLEVEL2_MASK 0x00000004 +#define XCHAL_INTLEVEL3_MASK 0x00000008 +#define XCHAL_INTLEVEL4_MASK 0x00000010 +#define XCHAL_INTLEVEL5_MASK 0x00000020 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00000080 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00001F43 +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00001F47 +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00001F4F +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00001F5F +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00001F7F +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00001F7F +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00001FFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 2 +#define XCHAL_INT3_LEVEL 3 +#define XCHAL_INT4_LEVEL 4 +#define XCHAL_INT5_LEVEL 5 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 7 +#define XCHAL_INT8_LEVEL 1 +#define XCHAL_INT9_LEVEL 1 +#define XCHAL_INT10_LEVEL 1 +#define XCHAL_INT11_LEVEL 1 +#define XCHAL_INT12_LEVEL 1 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_WRITE_ERROR +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_IDMA_DONE +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_IDMA_ERR +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFFE000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00001938 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 +#define XCHAL_INTTYPE_MASK_NMI 0x00000080 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000002 +#define XCHAL_INTTYPE_MASK_TIMER 0x00000041 +#define XCHAL_INTTYPE_MASK_ETIE 0x00000000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000004 +#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000 +#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000 +#define XCHAL_INTTYPE_MASK_TRAX 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000200 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000400 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000 +#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_WWDT 0x00000000 +#define XCHAL_INTTYPE_MASK_FXLK 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 0 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 6 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 7 /* non-maskable interrupt */ +#define XCHAL_WRITE_ERROR_INTERRUPT 2 +#define XCHAL_IDMA_DONE_INTERRUPT 9 +#define XCHAL_IDMA_ERR_INTERRUPT 10 + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL2_NUM 2 +#define XCHAL_INTLEVEL3_NUM 3 +#define XCHAL_INTLEVEL4_NUM 4 +#define XCHAL_INTLEVEL5_NUM 5 +#define XCHAL_INTLEVEL7_NUM 7 +/* (There are many interrupts each at level(s) 1.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 3 /* (intlevel 3) */ +#define XCHAL_EXTINT1_NUM 4 /* (intlevel 4) */ +#define XCHAL_EXTINT2_NUM 5 /* (intlevel 5) */ +#define XCHAL_EXTINT3_NUM 7 /* (intlevel 7) */ +#define XCHAL_EXTINT4_NUM 8 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 11 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 12 /* (intlevel 1) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT3_EXTNUM 0 /* (intlevel 3) */ +#define XCHAL_INT4_EXTNUM 1 /* (intlevel 4) */ +#define XCHAL_INT5_EXTNUM 2 /* (intlevel 5) */ +#define XCHAL_INT7_EXTNUM 3 /* (intlevel 7) */ +#define XCHAL_INT8_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT11_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT12_EXTNUM 6 /* (intlevel 1) */ + +#define XCHAL_HAVE_ISB 0 /* No ISB */ +#define XCHAL_ISB_VADDR 0 /* N/A */ +#define XCHAL_HAVE_ITB 0 /* No ITB */ +#define XCHAL_ITB_VADDR 0 /* N/A */ + +#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */ +#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */ +#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (until T1050) + 2 == XEA2 (LX) + 3 == XEA3 (NX) + 0 == XEA5 (RNX) */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */ +#define XCHAL_HAVE_XEA5 0 /* Exception Architecture 5 */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */ +#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */ + +#define XCHAL_RESET_VECOFS 0x00000000 +#define XCHAL_RESET_VECTOR_VADDR 0x7F000000 +#define XCHAL_RESET_VECTOR_PADDR 0x7F000000 +#define XCHAL_USER_VECOFS 0x00000000 +#define XCHAL_USER_VECTOR_VADDR 0x7F000740 +#define XCHAL_USER_VECTOR_PADDR 0x7F000740 +#define XCHAL_KERNEL_VECOFS 0x00000000 +#define XCHAL_KERNEL_VECTOR_VADDR 0x7F000700 +#define XCHAL_KERNEL_VECTOR_PADDR 0x7F000700 +#define XCHAL_DOUBLEEXC_VECOFS 0x00000000 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x7F0007C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x7F0007C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x7F000400 +#define XCHAL_WINDOW_VECTORS_PADDR 0x7F000400 +#define XCHAL_INTLEVEL2_VECOFS 0x00000000 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x7F000580 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x7F000580 +#define XCHAL_INTLEVEL3_VECOFS 0x00000000 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x7F0005C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x7F0005C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000000 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x7F000600 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x7F000600 +#define XCHAL_INTLEVEL5_VECOFS 0x00000000 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x7F000640 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x7F000640 +#define XCHAL_INTLEVEL6_VECOFS 0x00000000 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x7F000680 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x7F000680 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x00000000 +#define XCHAL_NMI_VECTOR_VADDR 0x7F0006C0 +#define XCHAL_NMI_VECTOR_PADDR 0x7F0006C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 4096 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 0 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ +#define XCHAL_HAVE_MPU 1 +#define XCHAL_MPU_ENTRIES 32 +#define XCHAL_MPU_LOCK 0 + +#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_BACKGROUND_ENTRIES 2 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0xFF /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 12 +#define XCHAL_MPU_ALIGN 4096 + +/*----------------------------------------------------------------------- + CSR Parity +------------------------------------------------------------------------*/ +#define XCHAL_HAVE_CSR_PARITY 0 + + +/*---------------------------------------------------------------------- + FLEX-LOCK +------------------------------------------------------------------------*/ + +#define XCHAL_HAVE_FXLK 0 + +/*---------------------------------------------------------------------- + WWDT (Windowed Watchdog Timer) +------------------------------------------------------------------------*/ +#define XCHAL_HAVE_WWDT 0 +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* XTENSA_CORE_CONFIGURATION_H_ */ + diff --git a/src/platform/amd/acp_7_x/include/arch/xtensa/config/core-matmap.h b/src/platform/amd/acp_7_x/include/arch/xtensa/config/core-matmap.h new file mode 100644 index 000000000000..23dca086d8b8 --- /dev/null +++ b/src/platform/amd/acp_7_x/include/arch/xtensa/config/core-matmap.h @@ -0,0 +1,106 @@ +/* + * xtensa/config/core-matmap.h -- Memory access and translation mapping + * parameters (CHAL) of the Xtensa processor core configuration. + * + * If you are using Xtensa Tools, see (which includes + * this file) for more details. + * + * In the Xtensa processor products released to date, all parameters + * defined in this file are derivable (at least in theory) from + * information contained in the core-isa.h header file. + * In particular, the following core configuration parameters are relevant: + * XCHAL_HAVE_CACHEATTR + * XCHAL_HAVE_MIMIC_CACHEATTR + * XCHAL_HAVE_XLT_CACHEATTR + * XCHAL_HAVE_PTP_MMU + * XCHAL_ITLB_ARF_ENTRIES_LOG2 + * XCHAL_DTLB_ARF_ENTRIES_LOG2 + * XCHAL_DCACHE_IS_WRITEBACK + * XCHAL_ICACHE_SIZE (presence of I-cache) + * XCHAL_DCACHE_SIZE (presence of D-cache) + * XCHAL_HW_VERSION_MAJOR + * XCHAL_HW_VERSION_MINOR + */ + +/* Customer ID=20511; Build=0xb6494; Copyright (c) 1999-2024 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_CORE_MATMAP_H +#define XTENSA_CONFIG_CORE_MATMAP_H + + +/*---------------------------------------------------------------------- + CACHE (MEMORY ACCESS) ATTRIBUTES + ----------------------------------------------------------------------*/ +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ + +/* Mappings for legacy constants where appropriate */ + +#define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx) + +#define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC| XTHAL_AR_RWXrwx ) + +#define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx) + +#define XCHAL_CA_ILLEGAL (XTHAL_AR_NONE | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASSBUF (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE |\ + XTHAL_MEM_BUFFERABLE) +#define XCHAL_CA_BYPASS_RX (XTHAL_AR_RX | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS_R (XTHAL_AR_R | XTHAL_MEM_DEVICE) +#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 + +#define XCHAL_CA_R (XTHAL_AR_R) +#define XCHAL_CA_RX (XTHAL_AR_RX) +#define XCHAL_CA_RW (XTHAL_AR_RW) +#define XCHAL_CA_RWX (XTHAL_AR_RWX) + + +/* + * Contents of MPU background map. + * NOTE: caller must define the XCHAL_MPU_BGMAP() macro (not defined here + * but specified below) before expanding the XCHAL_MPU_BACKGROUND_MAP(s) macro. + * + * XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...) + * + * s = passed from XCHAL_MPU_BACKGROUND_MAP(s), eg. to select how to expand + * vaddr_start = first byte of region (always 0 for first entry) + * vaddr_end = last byte of region (always 0xFFFFFFFF for last entry) + * rights = access rights + * memtype = memory type + * x = reserved for future use (0 until then) + */ +/* parasoft-begin-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */ +#define XCHAL_MPU_BACKGROUND_MAP(s) \ + XCHAL_MPU_BGMAP(s, 0x00000000, 0x7fffffff, 7, 6, 0) \ + XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff, 7, 6, 0) \ +/* parasoft-end-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */ + + /* end */ + + + +#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ + diff --git a/src/platform/amd/acp_7_x/include/arch/xtensa/config/defs.h b/src/platform/amd/acp_7_x/include/arch/xtensa/config/defs.h new file mode 100644 index 000000000000..cbcb6b5c39de --- /dev/null +++ b/src/platform/amd/acp_7_x/include/arch/xtensa/config/defs.h @@ -0,0 +1,38 @@ +/* Definitions for Xtensa instructions, types, and protos. */ + +/* Customer ID=20511; Build=0xb6494; Copyright (c) 2003-2004 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* NOTE: This file exists only for backward compatibility with T1050 + and earlier Xtensa releases. It includes only a subset of the + available header files. */ + +#ifndef _XTENSA_BASE_HEADER +#define _XTENSA_BASE_HEADER + +#ifdef __XTENSA__ + +#include +#include +#include + +#endif /* __XTENSA__ */ +#endif /* !_XTENSA_BASE_HEADER */ diff --git a/src/platform/amd/acp_7_x/include/arch/xtensa/config/specreg.h b/src/platform/amd/acp_7_x/include/arch/xtensa/config/specreg.h new file mode 100644 index 000000000000..81a0a6780016 --- /dev/null +++ b/src/platform/amd/acp_7_x/include/arch/xtensa/config/specreg.h @@ -0,0 +1,109 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* $Id: //depot/rel/Homewood/ib.9/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ + +/* Customer ID=20511; Build=0xb6494; Copyright (c) 1998-2002 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_SPECREG_H +#define XTENSA_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include + + +/* Special registers: */ +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define BR 4 +#define PREFCTL 40 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define MPUENB 90 +#define ERACCESS 95 +#define IBREAKENABLE 96 +#define MEMCTL 97 +#define CACHEADRDIS 98 +#define DDR 104 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define EPC_5 181 +#define EPC_6 182 +#define EPC_7 183 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EPS_5 197 +#define EPS_6 198 +#define EPS_7 199 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define EXCSAVE_5 213 +#define EXCSAVE_6 214 +#define EXCSAVE_7 215 +#define CPENABLE 224 +#define INTERRUPT 226 +#define INTENABLE 228 +#define PS 230 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define CCOMPARE_1 241 +#define MISC_REG_0 244 +#define MISC_REG_1 245 + + +/* Special cases (bases of special register series): */ +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define INTREAD 226 +#define INTSET 226 +#define INTCLEAR 227 + +#endif /* XTENSA_SPECREG_H */ + diff --git a/src/platform/amd/acp_7_x/include/arch/xtensa/config/system.h b/src/platform/amd/acp_7_x/include/arch/xtensa/config/system.h new file mode 100644 index 000000000000..5a03eebf7b85 --- /dev/null +++ b/src/platform/amd/acp_7_x/include/arch/xtensa/config/system.h @@ -0,0 +1,262 @@ +/* + * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration + * + * NOTE: The location and contents of this file are highly subject to change. + * + * Source for configuration-independent binaries (which link in a + * configuration-specific HAL library) must NEVER include this file. + * The HAL itself has historically included this file in some instances, + * but this is not appropriate either, because the HAL is meant to be + * core-specific but system independent. + */ + +/* Customer ID=20511; Build=0xb6494; Copyright (c) 2000-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_SYSTEM_H +#define XTENSA_CONFIG_SYSTEM_H + + +/*---------------------------------------------------------------------- + CONFIGURED SOFTWARE OPTIONS + ----------------------------------------------------------------------*/ + +#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */ +/* The above maps to one of the following constants: */ +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + +#define XSHAL_CLIB XTHAL_CLIB_XCLIB /* (sw-only option, selected C library) */ +/* The above maps to one of the following constants: */ +#define XTHAL_CLIB_NEWLIB 0 +#define XTHAL_CLIB_UCLIBC 1 +#define XTHAL_CLIB_XCLIB 2 + +#define XSHAL_USE_FLOATING_POINT 1 + +#define XSHAL_FLOATING_POINT_ABI 1 + +/* SW workarounds enabled for HW errata: */ + +/*---------------------------------------------------------------------- + DEVICE ADDRESSES + ----------------------------------------------------------------------*/ + +/* + * Strange place to find these, but the configuration GUI + * allows moving these around to account for various core + * configurations. Specific boards (and their BSP software) + * will have specific meanings for these components. + */ + +/* I/O Block areas: */ +#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 + +#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 + +/* System ROM: */ +#define XSHAL_ROM_VADDR 0x50000000 +#define XSHAL_ROM_PADDR 0x50000000 +#define XSHAL_ROM_SIZE 0x00020000 +/* Largest available area (free of vectors): */ +#define XSHAL_ROM_AVAIL_VADDR 0x50000000 +#define XSHAL_ROM_AVAIL_VSIZE 0x00020000 + +/* System RAM: */ +#define XSHAL_RAM_VADDR 0x60000000 +#define XSHAL_RAM_PADDR 0x60000000 +#define XSHAL_RAM_VSIZE 0x1F000000 +#define XSHAL_RAM_PSIZE 0x1F000000 +#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE +/* Largest available area (free of vectors): */ +#define XSHAL_RAM_AVAIL_VADDR 0x60000000 +#define XSHAL_RAM_AVAIL_VSIZE 0x1F000000 + +/* + * Shadow system RAM (same device as system RAM, at different address). + * (Emulation boards need this for the SONIC Ethernet driver + * when data caches are configured for writeback mode.) + * NOTE: on full MMU configs, this points to the BYPASS virtual address + * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual + * addresses are viewed through the BYPASS static map rather than + * the CACHED static map. + */ +#define XSHAL_RAM_BYPASS_VADDR 0x20000000 +#define XSHAL_RAM_BYPASS_PADDR 0x20000000 +#define XSHAL_RAM_BYPASS_PSIZE 0x1F000000 + +/* Alternate system RAM (different device than system RAM): */ + +/* Some available location in which to place devices in a simulation (eg. XTMP): */ +#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 +#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 +#define XSHAL_SIMIO_PADDR 0xC0000000 +#define XSHAL_SIMIO_SIZE 0x20000000 + + +/*---------------------------------------------------------------------- + * For use by reference testbench exit and diagnostic routines. + */ +#define XSHAL_MAGIC_EXIT 0xc61b3000 +#define XSHAL_STL_INFO_LOCATION 0xbffffffc + +/*---------------------------------------------------------------------- + * DEVICE-ADDRESS DEPENDENT... + * + * Values written to CACHEATTR special register (or its equivalent) + * to enable and disable caches in various modes. + *----------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------- + BACKWARD COMPATIBILITY ... + ----------------------------------------------------------------------*/ + +/* + * NOTE: the following two macros are DEPRECATED. Use the latter + * board-specific macros instead, which are specially tuned for the + * particular target environments' memory maps. + */ +#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ +#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ + +/*---------------------------------------------------------------------- + GENERIC + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains a system (PIF) RAM, + * system (PIF) ROM, local memory, or XLMI. */ + +/* These set any unused 512MB region to cache-BYPASS attribute: */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x42224422 /* enable caches in write-back mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x12221122 /* enable caches in write-allocate mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x12221122 /* enable caches in write-through mode */ +#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ +#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set any unused 512MB region to ILLEGAL attribute: */ +#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0x4FFF44FF /* enable caches in write-back mode */ +#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0x1FFF11FF /* enable caches in write-allocate mode */ +#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0x1FFF11FF /* enable caches in write-through mode */ +#define XSHAL_STRICT_CACHEATTR_BYPASS 0x2FFF22FF /* disable caches in bypass mode */ +#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch + * NULL-pointer dereference bugs; all other unused 512MB regions are set + * to cache-BYPASS attribute: */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x4222442F /* enable caches in write-back mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x1222112F /* enable caches in write-allocate mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x1222112F /* enable caches in write-through mode */ +#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */ +#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/*---------------------------------------------------------------------- + ISS (Instruction Set Simulator) SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For now, ISS defaults to the TRAPNULL settings: */ +#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK +#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC +#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU +#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS +#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK + +#define XSHAL_ISS_PIPE_REGIONS 0 +#define XSHAL_ISS_SDRAM_REGIONS 0 + + +/*---------------------------------------------------------------------- + XT2000 BOARD SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains any system RAM, + * system ROM, local memory, XLMI, or other XT2000 board device or memory. + * Regions containing devices are forced to cache-BYPASS mode regardless + * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ + +/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ +#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x4FF2442F /* enable caches in write-back mode */ +#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x1FF2112F /* enable caches in write-allocate mode */ +#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x1FF2112F /* enable caches in write-through mode */ +#define XSHAL_XT2000_CACHEATTR_BYPASS 0x2FF2222F /* disable caches in bypass mode */ +#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ +#define XSHAL_XT2000_SDRAM_REGIONS 0x00000044 /* BusInt SDRAM regions */ + + +/*---------------------------------------------------------------------- + VECTOR INFO AND SIZES + ----------------------------------------------------------------------*/ + +#define XSHAL_VECTORS_PACKED 0 /* UNUSED */ +#define XSHAL_STATIC_VECTOR_SELECT 0 +#define XSHAL_RESET_VECTOR_VADDR 0x7F000000 +#define XSHAL_RESET_VECTOR_PADDR 0x7F000000 + +/* + * Sizes allocated to vectors by the system (memory map) configuration. + * These sizes are constrained by core configuration (eg. one vector's + * code cannot overflow into another vector) but are dependent on the + * system or board (or LSP) memory map configuration. + * + * Whether or not each vector happens to be in a system ROM is also + * a system configuration matter, sometimes useful, included here also: + */ +#define XSHAL_RESET_VECTOR_SIZE 0x00000300 +#define XSHAL_RESET_VECTOR_ISROM 0 +#define XSHAL_USER_VECTOR_SIZE 0x00000038 +#define XSHAL_USER_VECTOR_ISROM 0 +#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038 +#define XSHAL_KERNEL_VECTOR_ISROM 0 +#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040 +#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 +#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 +#define XSHAL_WINDOW_VECTORS_ISROM 0 +#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL2_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL3_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL4_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL5_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL6_VECTOR_ISROM 0 +#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE +#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM +#define XSHAL_NMI_VECTOR_SIZE 0x00000038 +#define XSHAL_NMI_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE + +#endif /*XTENSA_CONFIG_SYSTEM_H*/ + diff --git a/src/platform/amd/acp_7_x/include/arch/xtensa/config/tie-asm.h b/src/platform/amd/acp_7_x/include/arch/xtensa/config/tie-asm.h new file mode 100644 index 000000000000..18935b08cc73 --- /dev/null +++ b/src/platform/amd/acp_7_x/include/arch/xtensa/config/tie-asm.h @@ -0,0 +1,382 @@ +/* + * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file contains assembly-language definitions (assembly + macros, etc.) for this specific Xtensa processor's TIE extensions + and options. It is customized to this Xtensa processor configuration. + + Customer ID=20511; Build=0xb6494; Copyright (c) 1999-2024 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_TIE_ASM_H +#define _XTENSA_CORE_TIE_ASM_H + +#include + +/* Selection parameter values for save-area save/restore macros: */ +/* Option vs. TIE: */ +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ +/* Whether used automatically by compiler: */ +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ +/* ABI handling across function calls: */ +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ +/* Misc */ +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ +#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ + | ((ccuse) & XTHAL_SAS_ANYCC) \ + | ((abi) & XTHAL_SAS_ANYABI) ) + + + /* + * Macro to store all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to store. Defaults to next available space + * (or 0 if is 0). + * select Select what category(ies) of registers to store, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in , space for + * the corresponding registers is skipped without doing any load. + */ + .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Optional global registers used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.threadptr \at1 // threadptr option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + // Optional caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr.br \at1 // boolean option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.xnne_rerr \at1 // ureg 0 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + .endm // xchal_ncp_load + + +#define XCHAL_NCP_NUM_ATMPS 1 + + /* + * Macro to store the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 16 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_store. + */ +#define xchal_cp_AudioEngineLX_store xchal_cp1_store + .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 0, 16, 16 + ae_s64.i aed0, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_s64.i aed1, \ptr, .Lxchal_ofs_+0 + ae_s64.i aed2, \ptr, .Lxchal_ofs_+8 + ae_s64.i aed3, \ptr, .Lxchal_ofs_+16 + ae_s64.i aed4, \ptr, .Lxchal_ofs_+24 + ae_s64.i aed5, \ptr, .Lxchal_ofs_+32 + ae_s64.i aed6, \ptr, .Lxchal_ofs_+40 + ae_s64.i aed7, \ptr, .Lxchal_ofs_+48 + ae_s64.i aed8, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_s64.i aed9, \ptr, .Lxchal_ofs_+0 + ae_s64.i aed10, \ptr, .Lxchal_ofs_+8 + ae_s64.i aed11, \ptr, .Lxchal_ofs_+16 + ae_s64.i aed12, \ptr, .Lxchal_ofs_+24 + ae_s64.i aed13, \ptr, .Lxchal_ofs_+32 + ae_s64.i aed14, \ptr, .Lxchal_ofs_+40 + ae_s64.i aed15, \ptr, .Lxchal_ofs_+48 + ae_s64.i aed16, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_s64.i aed17, \ptr, .Lxchal_ofs_+0 + ae_s64.i aed18, \ptr, .Lxchal_ofs_+8 + ae_s64.i aed19, \ptr, .Lxchal_ofs_+16 + ae_s64.i aed20, \ptr, .Lxchal_ofs_+24 + ae_s64.i aed21, \ptr, .Lxchal_ofs_+32 + ae_s64.i aed22, \ptr, .Lxchal_ofs_+40 + ae_s64.i aed23, \ptr, .Lxchal_ofs_+48 + ae_s64.i aed24, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_s64.i aed25, \ptr, .Lxchal_ofs_+0 + ae_s64.i aed26, \ptr, .Lxchal_ofs_+8 + ae_s64.i aed27, \ptr, .Lxchal_ofs_+16 + ae_s64.i aed28, \ptr, .Lxchal_ofs_+24 + ae_s64.i aed29, \ptr, .Lxchal_ofs_+32 + ae_s64.i aed30, \ptr, .Lxchal_ofs_+40 + ae_s64.i aed31, \ptr, .Lxchal_ofs_+48 + ae_movae \at1, aep0 + s8i \at1, \ptr, .Lxchal_ofs_+56 + ae_movae \at1, aep1 + s8i \at1, \ptr, .Lxchal_ofs_+57 + ae_movae \at1, aep2 + s8i \at1, \ptr, .Lxchal_ofs_+58 + ae_movae \at1, aep3 + s8i \at1, \ptr, .Lxchal_ofs_+59 + addi \ptr, \ptr, 64 + ae_salign128.i u0, \ptr, .Lxchal_ofs_+0 + ae_salign128.i u1, \ptr, .Lxchal_ofs_+16 + ae_salign128.i u2, \ptr, .Lxchal_ofs_+32 + ae_salign128.i u3, \ptr, .Lxchal_ofs_+48 + addi \ptr, \ptr, -320 + ae_movdrzbvc aed0 // ureg AE_ZBIASV8C + ae_s64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 + ae_movvfcrfsr aed0 // ureg FCR_FSR + ae_s64.i aed0, \ptr, .Lxchal_ofs_+8 + 0 + rur.ae_ovf_sar \at1 // ureg 240 + s32i \at1, \ptr, .Lxchal_ofs_+16 + rur.ae_bithead \at1 // ureg 241 + s32i \at1, \ptr, .Lxchal_ofs_+20 + rur.ae_ts_fts_bu_bp \at1 // ureg 242 + s32i \at1, \ptr, .Lxchal_ofs_+24 + rur.ae_cw_sd_no \at1 // ureg 243 + s32i \at1, \ptr, .Lxchal_ofs_+28 + rur.ae_cbegin0 \at1 // ureg 246 + s32i \at1, \ptr, .Lxchal_ofs_+32 + rur.ae_cend0 \at1 // ureg 247 + s32i \at1, \ptr, .Lxchal_ofs_+36 + rur.ae_cbegin1 \at1 // ureg 248 + s32i \at1, \ptr, .Lxchal_ofs_+40 + rur.ae_cend1 \at1 // ureg 249 + s32i \at1, \ptr, .Lxchal_ofs_+44 + rur.ae_cbegin2 \at1 // ureg 250 + s32i \at1, \ptr, .Lxchal_ofs_+48 + rur.ae_cend2 \at1 // ureg 251 + s32i \at1, \ptr, .Lxchal_ofs_+52 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 384 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 0, 16, 16 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 384 + .endif + .endm // xchal_cp1_store + + /* + * Macro to load the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 16 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_load. + */ +#define xchal_cp_AudioEngineLX_load xchal_cp1_load + .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 0, 16, 16 + ae_l64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 // ureg AE_ZBIASV8C + ae_movzbvcdr aed0 + ae_l64.i aed0, \ptr, .Lxchal_ofs_+8 + 0 // ureg FCR_FSR + ae_movfcrfsrv aed0 + l32i \at1, \ptr, .Lxchal_ofs_+16 + wur.ae_ovf_sar \at1 // ureg 240 + l32i \at1, \ptr, .Lxchal_ofs_+20 + wur.ae_bithead \at1 // ureg 241 + l32i \at1, \ptr, .Lxchal_ofs_+24 + wur.ae_ts_fts_bu_bp \at1 // ureg 242 + l32i \at1, \ptr, .Lxchal_ofs_+28 + wur.ae_cw_sd_no \at1 // ureg 243 + l32i \at1, \ptr, .Lxchal_ofs_+32 + wur.ae_cbegin0 \at1 // ureg 246 + l32i \at1, \ptr, .Lxchal_ofs_+36 + wur.ae_cend0 \at1 // ureg 247 + l32i \at1, \ptr, .Lxchal_ofs_+40 + wur.ae_cbegin1 \at1 // ureg 248 + l32i \at1, \ptr, .Lxchal_ofs_+44 + wur.ae_cend1 \at1 // ureg 249 + l32i \at1, \ptr, .Lxchal_ofs_+48 + wur.ae_cbegin2 \at1 // ureg 250 + l32i \at1, \ptr, .Lxchal_ofs_+52 + wur.ae_cend2 \at1 // ureg 251 + ae_l64.i aed0, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_l64.i aed1, \ptr, .Lxchal_ofs_+0 + ae_l64.i aed2, \ptr, .Lxchal_ofs_+8 + ae_l64.i aed3, \ptr, .Lxchal_ofs_+16 + ae_l64.i aed4, \ptr, .Lxchal_ofs_+24 + ae_l64.i aed5, \ptr, .Lxchal_ofs_+32 + ae_l64.i aed6, \ptr, .Lxchal_ofs_+40 + ae_l64.i aed7, \ptr, .Lxchal_ofs_+48 + ae_l64.i aed8, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_l64.i aed9, \ptr, .Lxchal_ofs_+0 + ae_l64.i aed10, \ptr, .Lxchal_ofs_+8 + ae_l64.i aed11, \ptr, .Lxchal_ofs_+16 + ae_l64.i aed12, \ptr, .Lxchal_ofs_+24 + ae_l64.i aed13, \ptr, .Lxchal_ofs_+32 + ae_l64.i aed14, \ptr, .Lxchal_ofs_+40 + ae_l64.i aed15, \ptr, .Lxchal_ofs_+48 + ae_l64.i aed16, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_l64.i aed17, \ptr, .Lxchal_ofs_+0 + ae_l64.i aed18, \ptr, .Lxchal_ofs_+8 + ae_l64.i aed19, \ptr, .Lxchal_ofs_+16 + ae_l64.i aed20, \ptr, .Lxchal_ofs_+24 + ae_l64.i aed21, \ptr, .Lxchal_ofs_+32 + ae_l64.i aed22, \ptr, .Lxchal_ofs_+40 + ae_l64.i aed23, \ptr, .Lxchal_ofs_+48 + ae_l64.i aed24, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_l64.i aed25, \ptr, .Lxchal_ofs_+0 + ae_l64.i aed26, \ptr, .Lxchal_ofs_+8 + ae_l64.i aed27, \ptr, .Lxchal_ofs_+16 + ae_l64.i aed28, \ptr, .Lxchal_ofs_+24 + ae_l64.i aed29, \ptr, .Lxchal_ofs_+32 + ae_l64.i aed30, \ptr, .Lxchal_ofs_+40 + ae_l64.i aed31, \ptr, .Lxchal_ofs_+48 + addi \ptr, \ptr, 56 + l8ui \at1, \ptr, .Lxchal_ofs_+0 + ae_movea aep0, \at1 + l8ui \at1, \ptr, .Lxchal_ofs_+1 + ae_movea aep1, \at1 + l8ui \at1, \ptr, .Lxchal_ofs_+2 + ae_movea aep2, \at1 + l8ui \at1, \ptr, .Lxchal_ofs_+3 + ae_movea aep3, \at1 + addi \ptr, \ptr, 8 + ae_lalign128.i u0, \ptr, .Lxchal_ofs_+0 + ae_lalign128.i u1, \ptr, .Lxchal_ofs_+16 + ae_lalign128.i u2, \ptr, .Lxchal_ofs_+32 + ae_lalign128.i u3, \ptr, .Lxchal_ofs_+48 + .set .Lxchal_pofs_, .Lxchal_pofs_ + 320 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 64 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 0, 16, 16 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 384 + .endif + .endm // xchal_cp1_load + +#define XCHAL_CP1_NUM_ATMPS 1 +#define XCHAL_SA_NUM_ATMPS 1 + + /* Empty macros for unconfigured coprocessors: */ + .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + +#endif /*_XTENSA_CORE_TIE_ASM_H*/ + diff --git a/src/platform/amd/acp_7_x/include/arch/xtensa/config/tie.h b/src/platform/amd/acp_7_x/include/arch/xtensa/config/tie.h new file mode 100644 index 000000000000..3faa4ccfa7a1 --- /dev/null +++ b/src/platform/amd/acp_7_x/include/arch/xtensa/config/tie.h @@ -0,0 +1,211 @@ +/* + * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file describes this specific Xtensa processor's TIE extensions + that extend basic Xtensa core functionality. It is customized to this + Xtensa processor configuration. + + Customer ID=20511; Build=0xb6494; Copyright (c) 1999-2024 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_CORE_TIE_H +#define XTENSA_CORE_TIE_H + +/* parasoft-begin-suppress ALL "This file not MISRA checked." */ + +#define XCHAL_CP_NUM 1 /* number of coprocessors */ +#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ +#define XCHAL_CP1_NAME "AudioEngineLX" +#define XCHAL_CP1_IDENT AudioEngineLX +#define XCHAL_CP1_SA_SIZE 384 /* size of state save area */ +#define XCHAL_CP1_SA_ALIGN 16 /* min alignment of save area */ +#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ +#define XCHAL_CP0_SA_SIZE 0 +#define XCHAL_CP0_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 +#define XCHAL_CP7_SA_SIZE 0 +#define XCHAL_CP7_SA_ALIGN 1 + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE 12 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE 400 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see ) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 3 +#define XCHAL_NCP_SA_LIST(s) \ + XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, xnne_rerr, 4, 4, 4,0x0300, ur,0 , 1,0,0,0) + +#define XCHAL_CP0_SA_NUM 0 +#define XCHAL_CP0_SA_LIST(s) /* empty */ + +#define XCHAL_CP1_SA_NUM 52 +#define XCHAL_CP1_SA_LIST(s) \ + XCHAL_SA_REG(s,0,0,1,0, ae_zbiasv8c,16, 8, 8,0x1029, ur,-1 , 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, fcr_fsr, 8, 8, 8,0x102A, ur,-1 , 7,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 4, 4, 4,0x03F0, ur,240, 15,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cw_sd_no, 4, 4, 4,0x03F3, ur,243, 29,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cbegin1, 4, 4, 4,0x03F8, ur,248, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cend1, 4, 4, 4,0x03F9, ur,249, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cbegin2, 4, 4, 4,0x03FA, ur,250, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_cend2, 4, 4, 4,0x03FB, ur,251, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed0, 8, 8, 8,0x1000, aed,0 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed1, 8, 8, 8,0x1001, aed,1 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed2, 8, 8, 8,0x1002, aed,2 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed3, 8, 8, 8,0x1003, aed,3 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed4, 8, 8, 8,0x1004, aed,4 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed5, 8, 8, 8,0x1005, aed,5 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed6, 8, 8, 8,0x1006, aed,6 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed7, 8, 8, 8,0x1007, aed,7 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed8, 8, 8, 8,0x1008, aed,8 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed9, 8, 8, 8,0x1009, aed,9 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed10, 8, 8, 8,0x100A, aed,10 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed11, 8, 8, 8,0x100B, aed,11 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed12, 8, 8, 8,0x100C, aed,12 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed13, 8, 8, 8,0x100D, aed,13 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed14, 8, 8, 8,0x100E, aed,14 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed15, 8, 8, 8,0x100F, aed,15 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed16, 8, 8, 8,0x1010, aed,16 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed17, 8, 8, 8,0x1011, aed,17 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed18, 8, 8, 8,0x1012, aed,18 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed19, 8, 8, 8,0x1013, aed,19 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed20, 8, 8, 8,0x1014, aed,20 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed21, 8, 8, 8,0x1015, aed,21 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed22, 8, 8, 8,0x1016, aed,22 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed23, 8, 8, 8,0x1017, aed,23 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed24, 8, 8, 8,0x1018, aed,24 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed25, 8, 8, 8,0x1019, aed,25 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed26, 8, 8, 8,0x101A, aed,26 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed27, 8, 8, 8,0x101B, aed,27 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed28, 8, 8, 8,0x101C, aed,28 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed29, 8, 8, 8,0x101D, aed,29 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed30, 8, 8, 8,0x101E, aed,30 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aed31, 8, 8, 8,0x101F, aed,31 , 64,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep0, 1, 1, 1,0x1024, aep,0 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep1, 1, 1, 1,0x1025, aep,1 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep2, 1, 1, 1,0x1026, aep,2 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep3, 1, 1, 1,0x1027, aep,3 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, u0,16,16,16,0x1020, u,0 ,128,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, u1,16,16,16,0x1021, u,1 ,128,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, u2,16,16,16,0x1022, u,2 ,128,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, u3,16,16,16,0x1023, u,3 ,128,0,0,0) + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +/* (not available, must use XCHAL_BYTE0_FORMAT_LENGTHS for this processor) */ +/* Byte length of instruction from its first byte, per FLIX. */ +#define XCHAL_BYTE0_FORMAT_LENGTHS \ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,16, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,6,8 + +/* parasoft-end-suppress ALL "This file not MISRA checked." */ + +#endif /* XTENSA_CORE_TIE_H */ + diff --git a/src/platform/amd/acp_7_x/include/arch/xtensa/tie/xt_datacache.h b/src/platform/amd/acp_7_x/include/arch/xtensa/tie/xt_datacache.h new file mode 100755 index 000000000000..a84835c4b5f7 --- /dev/null +++ b/src/platform/amd/acp_7_x/include/arch/xtensa/tie/xt_datacache.h @@ -0,0 +1,103 @@ +// Customer ID=20511; Build=0xb6494; Copyright (c) 2017-2019 Cadence Design Systems, Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +/* Definitions for the xt_datacache TIE package */ + +/* Do not modify. This is automatically generated.*/ + +/* parasoft-begin-suppress ALL "This file not MISRA checked." */ + +#ifndef _XTENSA_xt_datacache_HEADER +#define _XTENSA_xt_datacache_HEADER + +#ifdef __XTENSA__ +#ifdef __XCC__ + +#ifndef _ASMLANGUAGE +#ifndef _NOCLANGUAGE +#ifndef __ASSEMBLER__ + +#include + +/* + * The following prototypes describe intrinsic functions + * corresponding to TIE instructions. Some TIE instructions + * may produce multiple results (designated as "out" operands + * in the iclass section) or may have operands used as both + * inputs and outputs (designated as "inout"). However, the C + * and C++ languages do not provide syntax that can express + * the in/out/inout constraints of TIE intrinsics. + * Nevertheless, the compiler understands these constraints + * and will check that the intrinsic functions are used + * correctly. To improve the readability of these prototypes, + * the "out" and "inout" parameters are marked accordingly + * with comments. + */ + +extern void _TIE_xt_datacache_DHI(const int * s, immediate i); +extern void _TIE_xt_datacache_DHU(const int * s, immediate i); +extern void _TIE_xt_datacache_DHWB(const int * s, immediate i); +extern void _TIE_xt_datacache_DHWBI(const int * s, immediate i); +extern void _TIE_xt_datacache_DII(const int * s, immediate i); +extern void _TIE_xt_datacache_DIU(const int * s, immediate i); +extern void _TIE_xt_datacache_DIWB(const int * s, immediate i); +extern void _TIE_xt_datacache_DIWBI(const int * s, immediate i); +extern void _TIE_xt_datacache_DIWBUI_P(const int * s /*inout*/); +extern void _TIE_xt_datacache_DPFL(const int * s, immediate i); +extern void _TIE_xt_datacache_DPFR(const int * s, immediate i); +extern void _TIE_xt_datacache_DPFRO(const int * s, immediate i); +extern void _TIE_xt_datacache_DPFW(const int * s, immediate i); +extern void _TIE_xt_datacache_DPFWO(const int * s, immediate i); +extern int _TIE_xt_datacache_LDCT(const int * s); +extern int _TIE_xt_datacache_LDCW(const int * s); +extern void _TIE_xt_datacache_SDCT(int t, int * s); +extern void _TIE_xt_datacache_SDCW(int t, int * s); + +#endif /*__ASSEMBLER__*/ +#endif /*_NOCLANGUAGE*/ +#endif /*_ASMLANGUAGE*/ + +#define XT_DHI _TIE_xt_datacache_DHI +#define XT_DHU _TIE_xt_datacache_DHU +#define XT_DHWB _TIE_xt_datacache_DHWB +#define XT_DHWBI _TIE_xt_datacache_DHWBI +#define XT_DII _TIE_xt_datacache_DII +#define XT_DIU _TIE_xt_datacache_DIU +#define XT_DIWB _TIE_xt_datacache_DIWB +#define XT_DIWBI _TIE_xt_datacache_DIWBI +#define XT_DIWBUI_P _TIE_xt_datacache_DIWBUI_P +#define XT_DPFL _TIE_xt_datacache_DPFL +#define XT_DPFR _TIE_xt_datacache_DPFR +#define XT_DPFRO _TIE_xt_datacache_DPFRO +#define XT_DPFW _TIE_xt_datacache_DPFW +#define XT_DPFWO _TIE_xt_datacache_DPFWO +#define XT_LDCT _TIE_xt_datacache_LDCT +#define XT_LDCW _TIE_xt_datacache_LDCW +#define XT_SDCT _TIE_xt_datacache_SDCT +#define XT_SDCW _TIE_xt_datacache_SDCW + +#endif /* __XCC__ */ + +#endif /* __XTENSA__ */ + +#endif /* !_XTENSA_xt_datacache_HEADER */ + +/* parasoft-end-suppress ALL "This file not MISRA checked." */ diff --git a/src/platform/amd/acp_7_x/include/platform/fw_scratch_mem.h b/src/platform/amd/acp_7_x/include/platform/fw_scratch_mem.h new file mode 100644 index 000000000000..8c7eec522e65 --- /dev/null +++ b/src/platform/amd/acp_7_x/include/platform/fw_scratch_mem.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2026 AMD. All rights reserved. + * + * Author: Sneha Voona + * DineshKumar Kalva + */ +#ifndef __EXT_SCRATCH_MEM_H__ +#define __EXT_SCRATCH_MEM_H__ + +#include + +/* MAX number of DMA descriptors */ +#define MAX_NUM_DMA_DESC_DSCR 64 +#define SCRATCH_REG_OFFSET 0x1250000 +#define ACP_SRAM 0x03800000 + +typedef struct acp_atu_grp_pte { + uint32_t low_part; + uint32_t high_part; +} __attribute__((packed, aligned(4))) acp_atu_grp_pte_t; + +typedef union acp_cfg_dma_trns_cnt { + struct{ + uint32_t trns_cnt : 19; + uint32_t reserved : 12; + uint32_t ioc : 1; + } bits; + unsigned int u32all; +} __attribute__((packed, aligned(4))) acp_cfg_dma_trns_cnt_t; + +typedef struct acp_config_dma_descriptor { + uint32_t src_addr; + uint32_t dest_addr; + acp_cfg_dma_trns_cnt_t trns_cnt; + uint32_t reserved; +} __attribute__((packed, aligned(4))) acp_cfg_dma_descriptor_t; + +typedef struct acp_config_dma_misc { + uint32_t channelstatus; + uint32_t channel; + uint32_t flag; +} __attribute__((packed, aligned(4))) acp_cfg_dma_misc_t; + +typedef struct acp_scratch_memory_config { + /* ACP out box buffer */ + uint8_t acp_outbox_buffer[MAILBOX_DSPBOX_SIZE]; + + /* ACP in box buffer */ + uint8_t acp_inbox_buffer[MAILBOX_HOSTBOX_SIZE]; + + /* ACP debug box buffer */ + uint8_t acp_debug_buffer[MAILBOX_DEBUG_SIZE]; + + /* ACP exception box buffer */ + uint8_t acp_except_buffer[MAILBOX_EXCEPTION_SIZE]; + + /* ACP stream buffer */ + uint8_t acp_stream_buffer[MAILBOX_STREAM_SIZE]; + + /* ACP trace buffer */ + uint8_t acp_trace_buffer[MAILBOX_TRACE_SIZE]; + + /* Host msg write flag */ + uint32_t acp_host_msg_write; + + /* Host ack flag */ + uint32_t acp_host_ack_write; + + /* Dsp msg write flag */ + uint32_t acp_dsp_msg_write; + + /* Dsp ack flag */ + uint32_t acp_dsp_ack_write; + + /* ACP pte1 table */ + acp_atu_grp_pte_t acp_atugrp1_pte[16]; + + /* ACP pte2 table */ + acp_atu_grp_pte_t acp_atugrp2_pte[16]; + + /* ACP pte3 table */ + acp_atu_grp_pte_t acp_atugrp3_pte[16]; + + /* ACP pte4 table */ + acp_atu_grp_pte_t acp_atugrp4_pte[16]; + + /* ACP pte5 table */ + acp_atu_grp_pte_t acp_atugrp5_pte[16]; + + /* ACP pte6 table */ + acp_atu_grp_pte_t acp_atugrp6_pte[16]; + + /* ACP pte7 table */ + acp_atu_grp_pte_t acp_atugrp7_pte[16]; + + /* ACP pte8 table */ + acp_atu_grp_pte_t acp_atugrp8_pte[16]; + + /* ACP DMA Descriptor */ + acp_cfg_dma_descriptor_t acp_cfg_dma_descriptor[MAX_NUM_DMA_DESC_DSCR]; + + /* Stream physical offset */ + uint32_t phy_offset[8]; + + /* Stream system memory size */ + uint32_t syst_buff_size[8]; + + /* Fifo buffers are not part of scratch memory on ACP_7_X */ + /* Added fifo members to align with Driver structure */ + /* ACP transmit fifo buffer */ + uint8_t acp_transmit_fifo_buffer[256] __attribute__((aligned(128))); + + /* ACP receive fifo buffer */ + uint8_t acp_receive_fifo_buffer[256] __attribute__((aligned(128))); + uint32_t reserve[]; +} __attribute__((packed, aligned(4))) acp_scratch_mem_config_t; + +#endif /* __EXT_SCRATCH_MEM_H__ */ diff --git a/src/platform/amd/acp_7_x/include/platform/lib/memory.h b/src/platform/amd/acp_7_x/include/platform/lib/memory.h new file mode 100644 index 000000000000..dd407a18e086 --- /dev/null +++ b/src/platform/amd/acp_7_x/include/platform/lib/memory.h @@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2026 AMD. All rights reserved. + * + * Author: Sneha Voona + * DineshKumar Kalva + */ + +#ifdef __SOF_LIB_MEMORY_H__ + +#ifndef __PLATFORM_LIB_MEMORY_H__ +#define __PLATFORM_LIB_MEMORY_H__ + +#include + +/* data cache line alignment */ +#define PLATFORM_DCACHE_ALIGN 128 + +#define PU_REGISTER_BASE (0x9FD00000 - 0x01240000) + +/* physical DSP addresses */ +#define IRAM_BASE 0x7F000000 +#define IRAM_SIZE 0x20000 + +#define DRAM0_BASE 0xE0000000 +#define DRAM0_SIZE 0x10000 +#define SRAM0_BASE 0x9FF00000 + +#define DRAM1_BASE 0xE0010000 +#define DRAM1_SIZE 0x10000 +#define SRAM1_BASE 0x6000C000 +#define SRAM1_SIZE 0x274000 + +#define DMA0_BASE PU_REGISTER_BASE +#define DMA0_SIZE 0x4 + +/* DAI DMA register base address */ +#define DAI_BASE_I2S_TDM (PU_REGISTER_BASE + ACP_I2S_TDM_RX_RINGBUFADDR) +#define DAI_BASE_SW (PU_REGISTER_BASE + ACP_SW0_RX_DMA0_RINGBUFADDR) +#define DAI_BASE_PDM (PU_REGISTER_BASE + ACP_WOV_RX_RINGBUFADDR) +#define DAI_BASE_PDM1 (DAI_BASE_PDM + ACP_PDM_2_RX_RINGBUFADDR_96K) +#define DAI_SIZE 0x4 + +#define I2S_TDM_TX_FIFO_OFFST (ACP_I2S_TDM_TX_FIFOADDR - ACP_I2S_TDM_RX_RINGBUFADDR) +#define I2S_TDM_RX_FIFO_OFFST (ACP_I2S_TDM_RX_FIFOADDR - ACP_I2S_TDM_RX_RINGBUFADDR) + +/* SW0 FIFO */ +#define SW0_AUDIO0_TX_FIFO_OFFST (ACP_SW0_TX_DMA0_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO0_RX_FIFO_OFFST (ACP_SW0_RX_DMA0_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO1_TX_FIFO_OFFST (ACP_SW0_TX_DMA1_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO1_RX_FIFO_OFFST (ACP_SW0_RX_DMA1_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO2_TX_FIFO_OFFST (ACP_SW0_TX_DMA2_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO2_RX_FIFO_OFFST (ACP_SW0_RX_DMA2_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO3_TX_FIFO_OFFST (ACP_SW0_TX_DMA3_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO3_RX_FIFO_OFFST (ACP_SW0_RX_DMA3_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO4_TX_FIFO_OFFST (ACP_SW0_TX_DMA4_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO4_RX_FIFO_OFFST (ACP_SW0_RX_DMA4_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO5_TX_FIFO_OFFST (ACP_SW0_TX_DMA5_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO5_RX_FIFO_OFFST (ACP_SW0_RX_DMA5_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO6_TX_FIFO_OFFST (ACP_SW0_TX_DMA6_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO6_RX_FIFO_OFFST (ACP_SW0_RX_DMA6_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO7_TX_FIFO_OFFST (ACP_SW0_TX_DMA7_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW0_AUDIO7_RX_FIFO_OFFST (ACP_SW0_RX_DMA7_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) + +/* SW1 FIFO */ +#define SW1_AUDIO0_TX_FIFO_OFFST (ACP_SW1_TX_DMA0_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO0_RX_FIFO_OFFST (ACP_SW1_RX_DMA0_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO1_TX_FIFO_OFFST (ACP_SW1_TX_DMA1_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO1_RX_FIFO_OFFST (ACP_SW1_RX_DMA1_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO2_TX_FIFO_OFFST (ACP_SW1_TX_DMA2_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO2_RX_FIFO_OFFST (ACP_SW1_RX_DMA2_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO3_TX_FIFO_OFFST (ACP_SW1_TX_DMA3_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO3_RX_FIFO_OFFST (ACP_SW1_RX_DMA3_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO4_TX_FIFO_OFFST (ACP_SW1_TX_DMA4_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO4_RX_FIFO_OFFST (ACP_SW1_RX_DMA4_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO5_TX_FIFO_OFFST (ACP_SW1_TX_DMA5_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO5_RX_FIFO_OFFST (ACP_SW1_RX_DMA5_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO6_TX_FIFO_OFFST (ACP_SW1_TX_DMA6_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO6_RX_FIFO_OFFST (ACP_SW1_RX_DMA6_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO7_TX_FIFO_OFFST (ACP_SW1_TX_DMA7_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW1_AUDIO7_RX_FIFO_OFFST (ACP_SW1_RX_DMA7_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) + +/* SW2 FIFO */ +#define SW2_AUDIO0_TX_FIFO_OFFST (ACP_SW2_TX_DMA0_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO0_RX_FIFO_OFFST (ACP_SW2_RX_DMA0_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO1_TX_FIFO_OFFST (ACP_SW2_TX_DMA1_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO1_RX_FIFO_OFFST (ACP_SW2_RX_DMA1_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO2_TX_FIFO_OFFST (ACP_SW2_TX_DMA2_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO2_RX_FIFO_OFFST (ACP_SW2_RX_DMA2_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO3_TX_FIFO_OFFST (ACP_SW2_TX_DMA3_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO3_RX_FIFO_OFFST (ACP_SW2_RX_DMA3_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO4_TX_FIFO_OFFST (ACP_SW2_TX_DMA4_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO4_RX_FIFO_OFFST (ACP_SW2_RX_DMA4_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO5_TX_FIFO_OFFST (ACP_SW2_TX_DMA5_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO5_RX_FIFO_OFFST (ACP_SW2_RX_DMA5_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO6_TX_FIFO_OFFST (ACP_SW2_TX_DMA6_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO6_RX_FIFO_OFFST (ACP_SW2_RX_DMA6_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO7_TX_FIFO_OFFST (ACP_SW2_TX_DMA7_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW2_AUDIO7_RX_FIFO_OFFST (ACP_SW2_RX_DMA7_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) + +/* SW3 FIFO */ +#define SW3_AUDIO0_TX_FIFO_OFFST (ACP_SW3_TX_DMA0_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO0_RX_FIFO_OFFST (ACP_SW3_RX_DMA0_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO1_TX_FIFO_OFFST (ACP_SW3_TX_DMA1_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO1_RX_FIFO_OFFST (ACP_SW3_RX_DMA1_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO2_TX_FIFO_OFFST (ACP_SW3_TX_DMA2_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO2_RX_FIFO_OFFST (ACP_SW3_RX_DMA2_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO3_TX_FIFO_OFFST (ACP_SW3_TX_DMA3_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO3_RX_FIFO_OFFST (ACP_SW3_RX_DMA3_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO4_TX_FIFO_OFFST (ACP_SW3_TX_DMA4_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO4_RX_FIFO_OFFST (ACP_SW3_RX_DMA4_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO5_TX_FIFO_OFFST (ACP_SW3_TX_DMA5_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO5_RX_FIFO_OFFST (ACP_SW3_RX_DMA5_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO6_TX_FIFO_OFFST (ACP_SW3_TX_DMA6_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO6_RX_FIFO_OFFST (ACP_SW3_RX_DMA6_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO7_TX_FIFO_OFFST (ACP_SW3_TX_DMA7_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) +#define SW3_AUDIO7_RX_FIFO_OFFST (ACP_SW3_RX_DMA7_FIFOADDR - ACP_SW0_RX_DMA0_RINGBUFADDR) + +#define UUID_ENTRY_ELF_BASE 0x1FFFA000 +#define UUID_ENTRY_ELF_SIZE 0x6000 + +/* Log buffer base need to be updated properly, these are used in linker scripts */ +#define LOG_ENTRY_ELF_BASE 0x20000000 +#define LOG_ENTRY_ELF_SIZE 0x2000000 + +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE 0x2000000 + +/* Stack configuration */ +#define SOF_STACK_SIZE (0x1000) +#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE +#define SOF_STACK_END (DRAM1_BASE + DRAM1_SIZE - SOF_STACK_SIZE) +#define SOF_STACK_BASE (SOF_STACK_END + SOF_STACK_SIZE) + +/* Mailbox configuration */ +#define SRAM_OUTBOX_BASE SRAM0_BASE +#define SRAM_OUTBOX_SIZE 0x400 +#define SRAM_OUTBOX_OFFSET 0 + +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x400 +#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE + +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_DEBUG_SIZE 0x400 +#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE) + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x400 +#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE) + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x400 +#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE) + +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#define SRAM_TRACE_SIZE 0x400 +#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE) +#define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \ + + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \ + + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE) + +/* Heap section sizes for module pool */ +#define HEAP_RT_COUNT8 0 +#define HEAP_RT_COUNT16 192 +#define HEAP_RT_COUNT32 192 +#define HEAP_RT_COUNT64 128 +#define HEAP_RT_COUNT128 240 +#define HEAP_RT_COUNT256 128 +#define HEAP_RT_COUNT512 16 +#define HEAP_RT_COUNT1024 73 +#define HEAP_RT_COUNT2048 48 + +/* Heap section sizes for system runtime heap */ +#define HEAP_SYS_RT_COUNT64 720 +#define HEAP_SYS_RT_COUNT512 240 +#define HEAP_SYS_RT_COUNT1024 91 + +#define SIZE_OF_MEMORY_FOR_DATA_SECTION 0x60000 + +/* Heap configuration */ +#define HEAP_SYSTEM_BASE (SRAM1_BASE + SIZE_OF_MEMORY_FOR_DATA_SECTION) +#define HEAP_SYSTEM_SIZE 0x40000 +#define HEAP_SYSTEM_0_BASE HEAP_SYSTEM_BASE +#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE) +#define HEAP_SYS_RUNTIME_SIZE (HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \ + HEAP_SYS_RT_COUNT1024 * 1024) + +#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE) +#define HEAP_RUNTIME_SIZE \ + (HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \ + HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \ + HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \ + HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024 + \ + HEAP_RT_COUNT2048 * 2048) + +#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE) +#define HEAP_BUFFER_SIZE (0x60000) +#define HEAP_BUFFER_BLOCK_SIZE 0x180 +#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE) + +#define PLATFORM_HEAP_SYSTEM 1 +#define PLATFORM_HEAP_SYSTEM_RUNTIME 1 +#define PLATFORM_HEAP_RUNTIME 1 +#define PLATFORM_HEAP_BUFFER 1 + +/* Vector and literal sizes - not in core-isa.h */ +#define SOF_MEM_VECT_LIT_SIZE 0x7 +#define SOF_MEM_VECT_TEXT_SIZE 0x37 +#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE) + +#define SOF_MEM_RESET_TEXT_SIZE 0x400 +#define SOF_MEM_RESET_LIT_SIZE 0x8 +#define SOF_MEM_VECBASE_LIT_SIZE 0x178 +#define SOF_MEM_WIN_TEXT_SIZE 0x178 + +#define SOF_MEM_RO_SIZE 0x8 + +#define uncache_to_cache(address) address +#define cache_to_uncache(address) address +#define is_uncached(address) 0 + +#define HEAP_BUF_ALIGNMENT PLATFORM_DCACHE_ALIGN + +/* brief EDF task's default stack size in bytes */ +#define PLATFORM_TASK_DEFAULT_STACK_SIZE 3072 + +#if !defined(__ASSEMBLER__) && !defined(LINKER) +struct sof; + +#define SHARED_DATA +void platform_init_memmap(struct sof *sof); + +static inline void *platform_shared_get(void *ptr, int bytes) +{ + return ptr; +} + +static inline void *platform_rfree_prepare(void *ptr) +{ + return ptr; +} +#endif +#define host_to_local(addr) (addr) +#define local_to_host(addr) (addr) + +#endif /* __PLATFORM_LIB_MEMORY_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/memory.h" +#endif /* __SOF_LIB_MEMORY_H__ */ diff --git a/src/platform/amd/acp_7_x/include/platform/platform.h b/src/platform/amd/acp_7_x/include/platform/platform.h new file mode 100644 index 000000000000..2a6b0147446d --- /dev/null +++ b/src/platform/amd/acp_7_x/include/platform/platform.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2026 AMD. All rights reserved. + * + * Author: Sneha Voona + * DineshKumar Kalva + */ + +#ifdef __SOF_PLATFORM_H__ + +#ifndef __PLATFORM_PLATFORM_H__ +#define __PLATFORM_PLATFORM_H__ + +#if !defined(__ASSEMBLER__) && !defined(LINKER) + +#include +#include +#include +#include +#include +#include +#include + +struct ll_schedule_domain; +struct timer; +#define INTERRUPT_ENABLE 1 +#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0) + +/* IPC Interrupt */ +#define PLATFORM_IPC_INTERRUPT IRQ_EXT_IPC_LEVEL_3 +#define PLATFORM_IPC_INTERRUPT_NAME NULL + +/* Host page size */ +#define HOST_PAGE_SIZE 65536 + +/* pipeline IRQ */ +#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE0 +#define PLATFORM_SCHEDULE_IRQ_NAME NULL + +/* Platform stream capabilities */ +#define PLATFORM_MAX_CHANNELS 8 +#define PLATFORM_MAX_STREAMS 5 + +/* local buffer size of DMA tracing */ +#define DMA_TRACE_LOCAL_SIZE 8192 + +/* trace bytes flushed during panic */ +#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2) + +/* the interval of DMA trace copying */ +#define DMA_TRACE_PERIOD 500 /* 1000 / 50000 */ + +/* + * the interval of reschedule DMA trace copying in special case like half + * fullness of local DMA trace buffer + */ +#define DMA_TRACE_RESCHEDULE_TIME 100 + +/* DSP default delay in cycles */ +#define PLATFORM_DEFAULT_DELAY 12 + +/* default dma trace channel */ +#define DMA_TRACE_CHANNEL 7 + +/* debug offset */ +#define ACP_SOF_FW_STATUS 0 + +/* Platform defined panic code */ +static inline void platform_panic(uint32_t p) +{ + acp_sw_intr_trig_t sw_intr_trig; + volatile acp_scratch_mem_config_t *pscratch_mem_cfg = + (volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET); + + pscratch_mem_cfg->acp_dsp_msg_write = p; + mailbox_sw_reg_write(ACP_SOF_FW_STATUS, p); + /* Read the Software Interrupt controller register and update */ + sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG); + /* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */ + sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_ENABLE; + /* Write the Software Interrupt trigger register */ + io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all); +} + +/* + * brief Platform specific CPU entering idle. + * May be power-optimized using platform specific capabilities. + * @param level Interrupt level. + */ +void platform_wait_for_interrupt(int level); + +extern intptr_t _module_init_start; +extern intptr_t _module_init_end; +#endif + +#endif /* __PLATFORM_PLATFORM_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/platform.h" +#endif /* __SOF_PLATFORM_H__ */ diff --git a/src/platform/amd/acp_7_x/include/platform/platform_misc.h b/src/platform/amd/acp_7_x/include/platform/platform_misc.h new file mode 100644 index 000000000000..949f3622374f --- /dev/null +++ b/src/platform/amd/acp_7_x/include/platform/platform_misc.h @@ -0,0 +1,577 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2026 AMD. All rights reserved. + * + * Author: Sneha Voona + */ + +#include + +#define PU_REGISTER_BASE (0x9FD00000 - 0x01240000) +#define PU_SCRATCH_REG_BASE (0x9FF00000 - 0x01250000) +#define ACP_FUTURE_REG_ACLK_0 0x12418E0 /* don't use - reserved for driver gsync */ +#define ACP_FUTURE_REG_ACLK_1 0x12418E4 +#define ACP_FUTURE_REG_ACLK_2 0x12418E8 +#define ACP_FUTURE_REG_ACLK_3 0x12418EC +#define ACP_FUTURE_REG_ACLK_4 0x12418F0 +#define ACP_SW_INTR_TRIG 0x1241890 +#define ACP_DSP0_INTR_CNTL 0x1241800 +#define ACP_DSP0_INTR_STAT 0x1241818 +#define ACP_DSP_SW_INTR_CNTL 0x1241860 +#define ACP_DSP_SW_INTR_STAT 0x1241864 +#define ACP_AXI2DAGB_SEM_0 0x12418F4 +#define ACP_SRBM_CLIENT_BASE_ADDR 0x1241BF0 +#define ACP_SRBM_CLIENT_RDDATA 0x1241BF4 +#define ACP_SRBM_CYCLE_STS 0x1241BF8 +#define ACP_SRBM_CLIENT_CONFIG 0x1241BFC + +/* Registers from SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6 block ACP_7X */ +#define ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_REFCLK_BRDS 0x6D204 +#define ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_NON_AI_CTRL0_BRDS 0x6D214 +#define ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL6_1_BRDS 0x6D21C +#define ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL7_BRDS 0x6D220 +#define ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL9_BRDS 0x6D20C + +/* Registers from CLK6 block */ +#define mmCLK6_PLL0_DFS0_CNTL 0x6D014 +#define mmCLK6_PLL0_DFS0_STATUS 0x6D018 +#define mmCLK6_PLL0_DFS1_CNTL 0x6D01C +#define mmCLK6_PLL0_DFS1_STATUS 0x6D020 +#define mmCLK6_CLK0_BYPASS_CNTL 0x6D06C +#define mmCLK6_CLK1_BYPASS_CNTL 0x6D08C +#define mmCLK6_CLK_TICK_CNT_CONFIG_REG 0x6D188 +#define mmCLK6_CLK0_CURRENT_CNT 0x6D190 +#define mmCLK6_CLK1_CURRENT_CNT 0x6D194 + +/* CLK6 register aliases without mm prefix for clock management code */ +#define CLK6_PLL0_DFS0_CNTL mmCLK6_PLL0_DFS0_CNTL +#define CLK6_PLL0_DFS1_CNTL mmCLK6_PLL0_DFS1_CNTL +#define CLK6_PLL0_DFS1_STATUS mmCLK6_PLL0_DFS1_STATUS +#define CLK0_CURRENT_CNT mmCLK6_CLK0_CURRENT_CNT +#define CLK1_CURRENT_CNT mmCLK6_CLK1_CURRENT_CNT +#define CLK_TICK_CNT_CONFIG_REG mmCLK6_CLK_TICK_CNT_CONFIG_REG + +/* SYSTEMPLL2P0 register aliases without ACP_7X prefix */ +#define SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_NON_AI_CTRL0_BRDS ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_NON_AI_CTRL0_BRDS +#define SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_REFCLK_BRDS ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_REFCLK_BRDS +#define SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL6_1_BRDS ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL6_1_BRDS +#define SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL7_BRDS ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL7_BRDS +#define SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL9_BRDS ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL9_BRDS + +#define mmMP1_C2PMSG_37 0x3B10994 +#define mmMP1_C2PMSG_38 0x3B10998 +#define mmMP1_C2PMSG_39 0x3B1099C +#define ACPSMC_MSG_PllPowerState 0x3 /* Toggle PLL power state ON/OFF */ +#define ACP_AUDIOPLL_POWER_OFF_REQ 0x0 /* ACP Power Down Request Value */ +#define ACP_AUDIOPLL_POWER_ON_REQ 0x1 /* ACP Power Up Request Value */ +#define ACP_AUDIOPLL_POWER_OFF_REQ_WITH_WOV_EN 0x2 /* ACP Power Down Request Value */ +#define ACP_AUDIOPLL_POWER_ON_REQ_WITH_WOV_EN 0x3 /* ACP Power Up Request Value */ +#define ACP_AUDIO_CLK_SEL 0x1241038 +#define ACP_PDM_CORE_CLK_SEL 0x124103C + +typedef union acp_srbm_cycle_sts { + struct { + unsigned int srbm_clients_sts :1; + unsigned int:7; + } bits; + unsigned int u32all; +} acp_srbm_cycle_sts_t; + +typedef union acp_clkmux_sel { + struct { + unsigned int acp_clkmux_sel:3; + unsigned int:13; + unsigned int acp_clkmux_div_value:16; + } bits; + unsigned int u32all; +} acp_clkmux_sel_t; + +typedef union clk7_clk1_dfs_cntl_u { + struct { + unsigned int CLK1_DIVIDER:7; + unsigned int:25; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_clk1_dfs_cntl_u_t; +typedef union clk7_clk1_dfs_status_u { + struct { + unsigned int : 16; + unsigned int CLK1_DFS_DIV_REQ_IDLE :1; + unsigned int : 2; + unsigned int RO_CLK1_DFS_STATE_IDLE :1; + unsigned int CLK1_CURRENT_DFS_DID :7; + unsigned int : 5; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_clk1_dfs_status_u_t; + +typedef union clk7_clk1_bypass_cntl_u { + struct { + unsigned int CLK1_BYPASS_SEL:3; + unsigned int:13; + unsigned int CLK1_BYPASS_DIV:4; + unsigned int:12; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_clk1_bypass_cntl_u_t; + +typedef union clk7_clk_fsm_status_u { + struct { + unsigned int AUTOLAUCH_FSM_FULL_SPEED_IDLE:1; + unsigned int:3; + unsigned int AUTOLAUCH_FSM_BYPASS_IDLE:1; + unsigned int:3; + unsigned int RO_FSM_PLL_STATUS_STARTED:1; + unsigned int:3; + unsigned int RO_FSM_PLL_STATUS_STOPPED:1; + unsigned int:3; + unsigned int RO_EARLY_FSM_DONE:1; + unsigned int:3; + unsigned int RO_DFS_GAP_ACTIVE:1; + unsigned int:3; + unsigned int RO_DID_FSM_IDLE:1; + unsigned int:7; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_clk_fsm_status_t; + +typedef union clk7_clk_pll_req_u { + struct { + unsigned int fbmult_int:9; + unsigned int:3; + unsigned int pllspinediv:4; + unsigned int fbmult_frac:16; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_clk_pll_req_u_t; + +typedef union clk7_clk_pll_refclk_startup { + struct { + unsigned int main_pll_ref_clk_rate_startup:8; + unsigned int main_pll_cfg_4_startup :8; + unsigned int main_pll_ref_clk_div_startup:2; + unsigned int main_pll_cfg_3_startup :10; + unsigned int:1; + unsigned int main_pll_refclk_src_mux0_startup:1; + unsigned int main_pll_refclk_src_mux1_startup:1; + unsigned int:1; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_clk_pll_refclk_startup_t; +typedef union clk7_spll_field_2 { + struct{ + unsigned int:3; + unsigned int spll_fbdiv_mask_en :1; + unsigned int spll_fracn_en :1; + unsigned int spll_freq_jump_en :1; + unsigned int:25; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_spll_field_2_t; + +typedef union clk7_clk_dfsbypass_cntl { + struct { + unsigned int enter_dfs_bypass_0 :1; + unsigned int enter_dfs_bypass_1 :1; + unsigned int:14; + unsigned int exit_dfs_bypass_0 :1; + unsigned int exit_dfs_bypass_1 :1; + unsigned int:14; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_clk_dfsbypass_cntl_t; + +typedef union clk7_clk_pll_pwr_req { + struct { + unsigned int PLL_AUTO_START_REQ :1; + unsigned int:3; + unsigned int PLL_AUTO_STOP_REQ :1; + unsigned int:3; + unsigned int PLL_AUTO_STOP_NOCLK_REQ :1; + unsigned int:3; + unsigned int PLL_AUTO_STOP_REFBYPCLK_REQ:1; + unsigned int:3; + unsigned int PLL_FORCE_RESET_HIGH :1; + unsigned int:15; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_clk_pll_pwr_req_t; + +typedef union clk7_spll_fuse_1 { + struct { + unsigned int:8; + unsigned int spll_gp_coarse_exp :4; + unsigned int spll_gp_coarse_mant :4; + unsigned int:4; + unsigned int spll_gi_coarse_exp :4; + unsigned int:1; + unsigned int spll_gi_coarse_mant :2; + unsigned int:5; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_spll_fuse_1_t; + +typedef union clk7_spll_fuse_2 { + struct { + unsigned int spll_tdc_resolution :8; + unsigned int spll_freq_offset_exp :4; + unsigned int spll_freq_offset_mant :5; + unsigned int:15; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_spll_fuse_2_t; + +typedef union clk7_spll_field_9 { + struct { + unsigned int:16; + unsigned int spll_dpll_cfg_3 :10; + unsigned int spll_fll_mode :1; + unsigned int:5; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_spll_field_9_t; + +typedef union clk7_spll_field_6nm { + struct { + unsigned int spll_dpll_cfg_4 :8; + unsigned int spll_reg_tim_exp :3; + unsigned int spll_reg_tim_mant :1; + unsigned int spll_ref_tim_exp :3; + unsigned int spll_ref_tim_mant :1; + unsigned int spll_vco_pre_div :2; + unsigned int:14; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_spll_field_6nm_t; + +typedef union clk7_spll_field_7 { + struct { + unsigned int:7; + unsigned int spll_pllout_sel :1; + unsigned int spll_pllout_req :1; + unsigned int spll_pllout_state :2; + unsigned int spll_postdiv_ovrd :4; + unsigned int spll_postdiv_pllout_ovrd :4; + unsigned int spll_postdiv_sync_enable :1; + unsigned int:1; + unsigned int spll_pwr_state :2; + unsigned int:1; + unsigned int spll_refclk_rate :8; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_spll_field_7_t; + +typedef union clk7_spll_field_4 { + struct { + unsigned int spll_fcw0_frac_ovrd :16; + unsigned int pll_out_sel :1; + unsigned int:3; + unsigned int pll_pwr_dn_state :2; + unsigned int:2; + unsigned int spll_refclk_div :2; + unsigned int:6; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_spll_field_4_t; + +typedef union clk7_spll_field_5nm_bus_ctrl { + struct { + unsigned int bus_spll_async_mode :1; + unsigned int bus_spll_apb_mode :1; + unsigned int bus_spll_addr :8; + unsigned int bus_spll_byte_en :4; + unsigned int bus_spll_rdtr :1; + unsigned int bus_spll_resetb :1; + unsigned int bus_spll_sel :1; + unsigned int bus_spll_wrtr :1; + unsigned int:14; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_spll_field_5nm_bus_ctrl_t; + +typedef union clk7_spll_field_5nm_bus_wdata { + struct { + unsigned int bus_spll_wr_data; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_spll_field_5nm_bus_wdata_t; + +typedef union clk7_rootrefclk_mux_1 { + struct { + unsigned int ROOTREFCLK_MUX_1 :1; + unsigned int reserved :31; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_rootrefclk_mux_1_t; + +typedef union clk7_spll_field_5nm_bus_status { + struct { + unsigned int spll_bus_error :1; + unsigned int spll_bus_rd_valid :1; + unsigned int spll_bus_wr_ack :1; + unsigned int:29; + } bitfields, bits; + uint32_t u32all; + int32_t i32all; + float f32all; +} clk7_spll_field_5nm_bus_status_t; + +typedef union clk_tick_cnt_config_reg { + struct { + uint32_t TIMER_THRESHOLD:24; + uint32_t TIMER_ENABLE:1; + uint32_t HISTORY_ENABLE:1; + uint32_t HISTORY_SP_RESET:1; + uint32_t HISTORY_CLK_SEL:5; + } bitfields, bits; + uint32_t u32All; + int32_t i32All; + float f32All; +} clk_tick_cnt_config_reg_t; +typedef union SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_NON_AI_CTRL0_BRDS_u { + struct { + uint32_t vco_pre_div:2; + uint32_t dac_ibiastrim:4; + uint32_t:26; + } bitfields, bits; + uint32_t u32All; + int32_t i32All; + float f32All; +} SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_NON_AI_CTRL0_BRDS_u_t; + +typedef union SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_REFCLK_BRDS_u { + struct { + uint32_t refclk_rate:8; + uint32_t refclk_div: 6; + uint32_t:1; + uint32_t cml_sel:1; + uint32_t:16; + + } bitfields, bits; + uint32_t u32All; + int32_t i32All; + float f32All; +} SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_REFCLK_BRDS_u_t; + +typedef union SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL6_1_BRDS_u { + struct { + uint32_t fcw_int:9; + uint32_t:23; + } bitfields, bits; + uint32_t u32All; + int32_t i32All; + float f32All; +} SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL6_1_BRDS_u_t; + +typedef union SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL7_BRDS_u { + struct { + uint32_t fcw_frac:16; + uint32_t:16; + } bitfields, bits; + uint32_t u32All; + int32_t i32All; + float f32All; +} SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL7_BRDS_u_t; + +typedef union SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL9_BRDS_u { + struct { + uint32_t fcw0_frac_lsb:8; + uint32_t fcw1_frac_lsb:8; + uint32_t:16; + } bitfields, bits; + uint32_t u32All; + int32_t i32All; + float f32All; +} SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL9_BRDS_u_t; + +typedef union clk6_pll_dfs_cntl_u { + struct { + uint32_t PLL0_DFS0_DIVIDER:7; + uint32_t PLL0_DFS0_DDCA:2; + uint32_t:3; + uint32_t PLL0_DFS0_ADCA:4; + uint32_t PLL0_DFS0_AllowZeroDID :1; + uint32_t PLL0_DFS0_EnableCLKOffInBypass:1; + uint32_t PLL0_DFS0_EnableVCO48OffInBypass :1; + uint32_t:1; + uint32_t PLL0_DFS0_DiDtWait:3; + uint32_t:1; + uint32_t PLL0_DFS0_DiDtFloor : 2; + uint32_t:2; + uint32_t PLL0_DFS0_SlamDid:1; + uint32_t PLL0_DFS0_FastRamp :1; + uint32_t:2; + } bitfields, bits; + uint32_t u32All; + int32_t i32All; + float f32All; +} clk6_pll_dfs_cntl_u_t; + +typedef union clk_dfs_status_u { + struct { + uint32_t PLL0_DFS0_CURRENT_DFS_DID:7; + uint32_t:1; + uint32_t PLL0_DFS0_AUTOLAUCH_FSM_FULL_SPEED_IDLE:1; + uint32_t PLL0_DFS0_AUTOLAUCH_FSM_BYPASS_IDLE: 1; + uint32_t:6; + uint32_t PLL0_DFS0_DFS_STATE_IDLE:1; + uint32_t PLL0_DFS0_DID_FSM_IDLE:1; + uint32_t PLL0_DFS0_DFS_DIV_REQ_IDLE: 1; + uint32_t:13; + } bitfields, bits; + uint32_t u32All; + int32_t i32All; + float f32All; +} clk_dfs_status_u_t; + +typedef union clk6_clk_bypass_cntl_u { + struct { + uint32_t CLK_BYPASS_SEL:3; + uint32_t CLK_BYPASS_DIV:4; + uint32_t CLK_PMUX_SGMode:8; + uint32_t CLK_BYPASS_SEL_STARTUP:3; + uint32_t:1; + uint32_t CLK_BYPASS_DIV_STARTUP:4; + uint32_t:8; + } bitfields, bits; + uint32_t u32All; + int32_t i32All; + float f32All; +} clk6_bypass_cntl_u_t; + +typedef union acp_dsp_sw_intr_stat { + struct { + unsigned int host_to_dsp0_intr1_stat:1; + unsigned int host_to_dsp0_intr2_stat:1; + unsigned int dsp0_to_host_intr_stat:1; + unsigned int host_to_dsp0_intr3_stat:1; + unsigned int:28; + } bits; + unsigned int u32all; +} acp_dsp_sw_intr_stat_t; + +typedef union acp_sw_intr_trig { + struct { + unsigned int trig_host_to_dsp0_intr1:1; + unsigned int:1; + unsigned int trig_dsp0_to_host_intr:1; + unsigned int:29; + } bits; + unsigned int u32all; +} acp_sw_intr_trig_t; + +typedef void (*dma_callback_t)(const struct device *dev, void *user_data, + uint32_t channel, int status); + +#define ACP_DMA_CHAN_COUNT 64 +struct acp_dma_ptr_data { + /* base address of dma buffer */ + uint32_t base; + /* size of dma buffer */ + uint32_t size; + /* write pointer of dma buffer */ + uint32_t wr_ptr; + /* read pointer of dma buffer */ + uint32_t rd_ptr; + /* read size of dma buffer */ + uint32_t rd_size; + /* write size of dma buffer */ + uint32_t wr_size; + /* system memory size defined for the stream */ + uint32_t sys_buff_size; + /* virtual system memory offset for system memory buffer */ + uint32_t phy_off; + /* probe_channel id */ + uint32_t probe_channel; +}; + +enum acp_dma_state { + ACP_DMA_READY, + ACP_DMA_PREPARED, + ACP_DMA_SUSPENDED, + ACP_DMA_ACTIVE, +}; + +struct acp_dma_chan_data { + uint32_t direction; + enum acp_dma_state state; + struct acp_dma_ptr_data ptr_data; /* pointer data */ + dma_callback_t dma_tfrcallback; + void *priv_data; /* unused */ +}; + + +#define SDW_INSTANCES 4 +struct sdw_pin_data { + uint32_t pin_num; + uint32_t pin_dir; + uint32_t dma_channel; + uint32_t dma_channel1; + uint32_t index[SDW_INSTANCES]; + uint32_t instance; + uint32_t instance1; +}; + +struct tdm_context { + uint64_t prev_pos; + uint32_t buff_size; + uint32_t tdm_instance; + uint32_t pin_dir; + uint32_t dma_channel; + uint32_t index; + uint32_t frame_fmt; +}; + +struct dmic_context { + uint64_t prev_pos; + uint32_t dmic_instance; + uint32_t pin_dir; + uint32_t dma_channel; + uint32_t index; +}; + +struct acp_dma_dev_data { + struct dma_context dma_ctx; + struct acp_dma_chan_data chan_data[ACP_DMA_CHAN_COUNT]; + + ATOMIC_DEFINE(atomic, ACP_DMA_CHAN_COUNT); + struct dma_config *dma_config; + void *dai_index_ptr; +}; + diff --git a/src/platform/amd/acp_7_x/lib/CMakeLists.txt b/src/platform/amd/acp_7_x/lib/CMakeLists.txt new file mode 100644 index 000000000000..147d9d9bea93 --- /dev/null +++ b/src/platform/amd/acp_7_x/lib/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_local_sources(sof + clk.c +) diff --git a/src/platform/amd/acp_7_x/lib/clk.c b/src/platform/amd/acp_7_x/lib/clk.c new file mode 100644 index 000000000000..00aa89be48b2 --- /dev/null +++ b/src/platform/amd/acp_7_x/lib/clk.c @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2026 AMD. All rights reserved. + * + * Author: Sneha Voona + * Basavaraj Hiregoudar + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +SOF_DEFINE_REG_UUID(acp_clk); +LOG_MODULE_REGISTER(acp_clk, CONFIG_SOF_LOG_LEVEL); +DECLARE_TR_CTX(acp_clk_tr, SOF_UUID(acp_clk_uuid), LOG_LEVEL_INFO); + +/* Frequency tables */ +const struct freq_table platform_cpu_freq[] = { + {600000000, 600000 }, +}; + +STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, + invalid_number_of_cpu_frequencies); + +/* Type definitions */ +typedef enum { + PLL_MODE_100MHZ_NORMAL, + PLL_MODE_48MHZ_NORMAL, + PLL_MODE_32KHZ_LPPM, + PLL_MODE_48MHZ_LPPM, + PLL_MODE_100MHZ_LPPM +} PLL_MODE; + +/* Enumeration for the Clock Types */ +typedef enum _acp_clock_type_ { + acp_aclk_clock, + acp_sclk_clock, + acp_clock_type_max, + acp_clock_type_force = 0xFF +} acp_clock_type_t; + +/* Static variables */ +static SHARED_DATA struct clock_info platform_clocks_info[NUM_CLOCKS]; + +/* Function prototypes */ +void audio_pll_power_off(void); +void audio_pll_power_on(void); +void clk_dfs_bypassexit(void); +void audio_pll_mode_switch(uint32_t mode, uint32_t fcw_int, uint32_t fcw_frac, + uint32_t fcw_denom, uint32_t pllspinediv); +void clk7_init_vco(void); +void acp_7_x_reg_wait(void); +void acp_7_x_get_boot_ref_clock(float *boot_ref_clk); +uint32_t acp_clk_update_dfs_did(uint32_t did, uint32_t clk_type); +void acp_cpl_aclk_dfs_did_update(bool poll, uint32_t timeout_cnt, uint8_t did); +void acp_cpl_audioclk_dfs_did_update(bool poll, uint32_t timeout_cnt, uint8_t did); +void acp_cpl_aclk_poll_dfs_div_req_idle(uint32_t timeout_cnt); +void acp_cpl_audioclk_poll_dfs_div_req_idle(uint32_t timeout_cnt); +void change_clock_notify(uint32_t clock_freq); +int acp_get_current_clk(acp_clock_type_t clk_type, + float *clk_value); + +/* Static function prototypes */ +static int acp_reg_read_via_smn(uint32_t reg_offset, uint32_t size); +static void acp_reg_write_via_smn(uint32_t reg_offset, uint32_t reg_value, uint32_t size); + +static int acp_reg_read_via_smn(uint32_t reg_offset, + uint32_t size) +{ + uint32_t reg_value; + uint32_t delay_cnt = 10000; + uint32_t smn_client_base_addr = (reg_offset >> 10); + uint32_t region_start_addr = (smn_client_base_addr << 10); + uint32_t apertureid = ((reg_offset >> 20) & 0xFFF); + acp_srbm_cycle_sts_t acp_srbm_cycle_sts; + + io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_CONFIG), apertureid); + io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_BASE_ADDR), smn_client_base_addr); + reg_value = (uint32_t)io_reg_read(PU_REGISTER_BASE + + (ACP_MASTER_REG_ACCESS_ADDRESS + reg_offset - region_start_addr + ACP_FIRST_REG_OFFSET)); + if (reg_value) { + reg_value = 0; + } + acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE + + ACP_SRBM_CYCLE_STS); + while (delay_cnt > 0) { + if (!acp_srbm_cycle_sts.bits.srbm_clients_sts) { + return (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_SRBM_CLIENT_RDDATA); + } + acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE + + ACP_SRBM_CYCLE_STS); + delay_cnt--; + } + return -1; +} + +static void acp_reg_write_via_smn(uint32_t reg_offset, + uint32_t value, uint32_t size) +{ + uint32_t delay_cnt = 10000; + uint32_t smn_client_base_addr = (reg_offset >> 10); + uint32_t region_start_addr = (smn_client_base_addr << 10); + uint32_t apertureid = ((reg_offset >> 20) & 0xFFF); + acp_srbm_cycle_sts_t acp_srbm_cycle_sts; + + io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_CONFIG), apertureid); + io_reg_write((PU_REGISTER_BASE + ACP_SRBM_CLIENT_BASE_ADDR), smn_client_base_addr); + io_reg_write((PU_REGISTER_BASE + (ACP_MASTER_REG_ACCESS_ADDRESS + + reg_offset - region_start_addr + + ACP_FIRST_REG_OFFSET)), value); + acp_srbm_cycle_sts = + (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE + ACP_SRBM_CYCLE_STS); + while (delay_cnt > 0) { + acp_srbm_cycle_sts = (acp_srbm_cycle_sts_t)io_reg_read(PU_REGISTER_BASE + + ACP_SRBM_CYCLE_STS); + if (!acp_srbm_cycle_sts.bits.srbm_clients_sts) { + return; + } + delay_cnt--; + } +} + +void platform_clock_init(struct sof *sof) +{ + int i; + + sof->clocks = platform_clocks_info; + for (i = 0; i < CONFIG_CORE_COUNT; i++) { + sof->clocks[i] = (struct clock_info) { + .freqs_num = NUM_CPU_FREQ, + .freqs = platform_cpu_freq, + .default_freq_idx = CPU_DEFAULT_IDX, + .current_freq_idx = CPU_DEFAULT_IDX, + .notification_id = NOTIFIER_ID_CPU_FREQ, + .notification_mask = NOTIFIER_TARGET_CORE_MASK(i), + .set_freq = NULL, + }; + } + /* acp_reg_write_via_smn(CLK6_PLL0_DFS0_CNTL, 0x19, sizeof(int)); */ +} +void acp_cpl_audioclk_poll_dfs_div_req_idle(uint32_t timeout_cnt) +{ + uint32_t timeout = 0; + clk_dfs_status_u_t clk_dfs_status; + + do { + clk_dfs_status.u32All = acp_reg_read_via_smn( + mmCLK6_PLL0_DFS0_STATUS, sizeof(uint32_t)); + timeout++; + } while ((clk_dfs_status.bitfields.PLL0_DFS0_DFS_DIV_REQ_IDLE == 0) & + (timeout < timeout_cnt)); + +} + +uint32_t mp1_mailbox_send(uint32_t _reg_id, uint32_t _value) +{ + uint32_t ready = 0; + uint32_t wait_cnt = 0; + + while (wait_cnt < 0x1000) { + ready = acp_reg_read_via_smn(mmMP1_C2PMSG_38, sizeof(ready)); + if (ready != 0) { + break; + } + wait_cnt++; + } + if (ready == 0) { + return 0; + } + /* Clear the response register */ + acp_reg_write_via_smn(mmMP1_C2PMSG_38, 0, sizeof(uint32_t)); + /* Write the argument (value) to the argument register */ + acp_reg_write_via_smn(mmMP1_C2PMSG_39, _value, sizeof(uint32_t)); + /* Write the message ID to the message register */ + acp_reg_write_via_smn(mmMP1_C2PMSG_37, _reg_id, sizeof(uint32_t)); + /* Poll until response is non-zero */ + uint32_t resp = 0; + /* TODO: Enable this code after bringup is complete. This is commented to avoid hang */ + int count = 0; + + do { + resp = acp_reg_read_via_smn(mmMP1_C2PMSG_38, sizeof(uint32_t)); + count++; + if (count >= 100) { + break; + } + } while (resp == 0); + /* Optionally, read back the argument register if needed (not used here) */ + + return resp; +} + +void acp_clk_d0_sequence(uint32_t clock_freq) +{ + /* Send message to PMFW to power on Audio PLL */ + mp1_mailbox_send(ACPSMC_MSG_PllPowerState, ACP_AUDIOPLL_POWER_ON_REQ); + + change_clock_notify(clock_freq); + + /* Audio PLL DFS Output for AUDIOCLK */ + acp_reg_write_via_smn(mmCLK6_CLK0_BYPASS_CNTL, 0, sizeof(uint32_t)); + /* Audio PLL DFS Output for ACLK */ + acp_reg_write_via_smn(mmCLK6_CLK1_BYPASS_CNTL, 0, sizeof(uint32_t)); + +} + +void acp_clk_d3_sequence(void) +{ + clk6_bypass_cntl_u_t bypass_cntl; + + bypass_cntl.u32All = 0; + bypass_cntl.bitfields.CLK_BYPASS_SEL = 4; + + /* SET AUDIOCLK TO LPPLL 196.608MHz */ + acp_reg_write_via_smn(mmCLK6_CLK0_BYPASS_CNTL, bypass_cntl.u32All, sizeof(uint32_t)); + + bypass_cntl.u32All = 0; + bypass_cntl.bitfields.CLK_BYPASS_SEL = 2; + + /* SET ACLK TO LPPLL 393MHz */ + acp_reg_write_via_smn(mmCLK6_CLK1_BYPASS_CNTL, bypass_cntl.u32All, sizeof(uint32_t)); + /* mp1_mailbox_send(ACPSMC_MSG_PllPowerState, ACP_AUDIOPLL_POWER_OFF_REQ); */ + + /* Send message to PMFW to power off Audio PLL */ + mp1_mailbox_send(ACPSMC_MSG_PllPowerState, ACP_AUDIOPLL_POWER_OFF_REQ_WITH_WOV_EN); +} + +void change_clock_notify(uint32_t clock_freq) +{ + uint32_t final_did = 4; /* Default DID value */ + float did = 0.0f; + float fraction_val = 0.0f; + uint32_t int_did_val = 0; + float boot_ref_clk = 0.0f; + acp_clock_type_t clock_type = acp_aclk_clock; + + acp_7_x_get_boot_ref_clock(&boot_ref_clk); + + tr_info(&acp_clk_tr, "acp_change_clock_notify clock_freq : %d clock_type : %d", clock_freq, clock_type); + + fraction_val = (float)(clock_freq / (float)1000000.0f); /*converting Hz to Mhz*/ + clock_freq = (clock_freq / 1000000); /*converting Hz to Mhz*/ + + did = (float)(boot_ref_clk/(float)fraction_val); + if (did > 62.0f) { + final_did = 0x7F; + } else { + /* Fractional part of the divider value. Based on fractional + * value increment the did value. + */ + /* Refer DID value sheet for reference. */ + /* Extracting the fractional value from float divider value */ + fraction_val = did - (uint8_t)(did); + + /* Extracting only integer part of the divider */ + did = did - fraction_val; + if (did <= 16.00f) { + did = (did * 4.0f); + } else if ((did > 16.0f) && (did <= 32.0f)) { + did = ((did - 16.0f) * 2.0f + 64.0f); + } else if ((did > 32.0f) && (did <= 62.0f)) { + did = ((did - 32.0f) + 96.0f); + } + + /* Following logic is to ensure the fractional divider value is + * only limited to 2 decimal places, in order to ensure correct + * calculation of DID value + */ + int_did_val = (uint32_t)(fraction_val * 100.0f); + fraction_val = (float)(int_did_val / 100.0f); + + if (fraction_val == 0.0f) { + final_did = (uint8_t)(did); + } else if (fraction_val <= 0.25f) { + final_did = (uint8_t)(did)+1; + } else if ((fraction_val > 0.25f) && (fraction_val <= 0.5f)) { + final_did = (uint8_t)(did)+2; + } else if ((fraction_val > 0.5f) && (fraction_val <= 0.75f)) { + final_did = (uint8_t)(did)+3; + } else if ((fraction_val > 0.75f)) { + final_did = (uint8_t)(did)+4; + } + } + + acp_clk_update_dfs_did((uint32_t)final_did, clock_type); + +} +void acp_change_clock_notify(uint32_t clock_freq) +{ + if (clock_freq) { + /* d0 sequence */ + acp_clk_d0_sequence(clock_freq); + } else { + /* d3 sequence */ + acp_clk_d3_sequence(); + } + +} + +uint32_t acp_clk_update_dfs_did(uint32_t did, uint32_t clk_type) +{ + uint32_t updated_clk = 0; + + if (clk_type == acp_aclk_clock) { + acp_cpl_aclk_dfs_did_update(true, 10, did); + } else if (clk_type == acp_sclk_clock) { + acp_cpl_audioclk_dfs_did_update(true, 10, did); + } + + acp_get_current_clk(acp_aclk_clock, (float *)&updated_clk); + return updated_clk; + +} +void acp_cpl_aclk_dfs_did_update(bool poll, uint32_t timeout_cnt, uint8_t did) +{ /* CLK instance #6, clock slice #1 */ + clk6_pll_dfs_cntl_u_t clk6_pll0_dfs1_cntl; + + clk6_pll0_dfs1_cntl.u32All = acp_reg_read_via_smn(CLK6_PLL0_DFS1_CNTL, sizeof(int)); + clk6_pll0_dfs1_cntl.bitfields.PLL0_DFS0_DIVIDER = did; + acp_reg_write_via_smn(CLK6_PLL0_DFS1_CNTL, clk6_pll0_dfs1_cntl.u32All, sizeof(int)); + if (poll) { + acp_cpl_aclk_poll_dfs_div_req_idle(10); + } +} +void acp_cpl_audioclk_dfs_did_update(bool poll, uint32_t timeout_cnt, uint8_t did) +{ /* CLK instance #6, clock slice #0 */ + clk6_pll_dfs_cntl_u_t clk6_pll0_dfs0_cntl; + + clk6_pll0_dfs0_cntl.u32All = acp_reg_read_via_smn(CLK6_PLL0_DFS0_CNTL, sizeof(uint32_t)); + clk6_pll0_dfs0_cntl.bitfields.PLL0_DFS0_DIVIDER = did; + acp_reg_write_via_smn(CLK6_PLL0_DFS0_CNTL, clk6_pll0_dfs0_cntl.u32All, sizeof(uint32_t)); + /* polling DID change done */ + if (poll) { + acp_cpl_audioclk_poll_dfs_div_req_idle(timeout_cnt); + } +} + +void acp_cpl_aclk_poll_dfs_div_req_idle(uint32_t timeout_cnt) +{ + uint32_t timeout = 0; + clk_dfs_status_u_t clk6_pll0_dfs1_status; + + do { + clk6_pll0_dfs1_status.u32All = acp_reg_read_via_smn( + CLK6_PLL0_DFS1_STATUS, sizeof(uint32_t)); + timeout++; + } while ((clk6_pll0_dfs1_status.bitfields.PLL0_DFS0_DFS_DIV_REQ_IDLE == 0) && + (timeout < timeout_cnt)); +} + +void acp_7_x_get_boot_ref_clock(float *_boot_ref_clk) +{ + volatile SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_NON_AI_CTRL0_BRDS_u_t non_ai_ctrl0; + volatile SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_REFCLK_BRDS_u_t clk_pll_refclk; + volatile SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL6_1_BRDS_u_t ai_freq_ctrl6_1_brds; + volatile SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL7_BRDS_u_t ai_freq_ctrl7_brds; + volatile SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL9_BRDS_u_t ai_freq_ctrl9_brds; + + non_ai_ctrl0.u32All = acp_reg_read_via_smn( + SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_NON_AI_CTRL0_BRDS, sizeof(uint32_t)); + clk_pll_refclk.u32All = acp_reg_read_via_smn( + SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_REFCLK_BRDS, sizeof(uint32_t)); + ai_freq_ctrl6_1_brds.u32All = acp_reg_read_via_smn( + SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL6_1_BRDS, sizeof(uint32_t)); + ai_freq_ctrl7_brds.u32All = acp_reg_read_via_smn( + SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL7_BRDS, sizeof(uint32_t)); + ai_freq_ctrl9_brds.u32All = acp_reg_read_via_smn( + SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_AI_FREQ_CTRL9_BRDS, sizeof(uint32_t)); + + *_boot_ref_clk = 0.0f; + /* 16777216 = 2^24 */ + *_boot_ref_clk = + (((float)(ai_freq_ctrl6_1_brds.bitfields.fcw_int) + + ((float)(ai_freq_ctrl7_brds.bitfields.fcw_frac << 8 | + ai_freq_ctrl9_brds.bitfields.fcw0_frac_lsb) / + (16777216.0f))) * + (clk_pll_refclk.bitfields.refclk_rate / 2) * + (1 << non_ai_ctrl0.bitfields.vco_pre_div)); +} + +int acp_get_current_clk(acp_clock_type_t clk_type, float *clk_value) +{ + uint32_t temp_clk_value = 0; + clk_tick_cnt_config_reg_t clk_tick_config; + + clk_tick_config.u32All = acp_reg_read_via_smn(CLK_TICK_CNT_CONFIG_REG, sizeof(uint32_t)); + + /* Get current output clock based on CLK TYPE */ + if (acp_sclk_clock == clk_type) { + temp_clk_value = acp_reg_read_via_smn(CLK0_CURRENT_CNT, sizeof(uint32_t)); + } else if (acp_aclk_clock == clk_type) { + temp_clk_value = acp_reg_read_via_smn(CLK1_CURRENT_CNT, sizeof(uint32_t)); + } else { + return -EINVAL; /* Invalid parameter */ + } + + *clk_value = temp_clk_value / (clk_tick_config.bitfields.TIMER_THRESHOLD / 48.0f); + return 0; /* Success */ +} diff --git a/src/platform/amd/acp_7_x/platform.c b/src/platform/amd/acp_7_x/platform.c new file mode 100644 index 000000000000..33f49bcced36 --- /dev/null +++ b/src/platform/amd/acp_7_x/platform.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2026 AMD. All rights reserved. + * + * Author: Sneha Voona + * DineshKumar Kalva + * Basavaraj Hiregoudar + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(platform_file, CONFIG_SOF_LOG_LEVEL); + +#define INTERRUPT_DISABLE 0 +extern void acp_dsp_to_host_intr_trig(void); +struct sof; +static const struct sof_ipc_fw_ready ready + __attribute__((section(".fw_ready"))) = { + .hdr = { + .cmd = SOF_IPC_FW_READY, + .size = sizeof(struct sof_ipc_fw_ready), + }, + /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */ + .version = { + .hdr.size = sizeof(struct sof_ipc_fw_version), + .micro = SOF_MICRO, + .minor = SOF_MINOR, + .major = SOF_MAJOR, +#if BLD_COUNTERS + .build = SOF_BUILD, /* See version-build-counter.cmake */ + .date = __DATE__, + .time = __TIME__, +#else + .build = -1, + .date = "dtermin.\0", + .time = "fwready.\0", +#endif + .tag = SOF_TAG, + .abi_version = SOF_ABI_VERSION, + }, + .flags = DEBUG_SET_FW_READY_FLAGS, +}; + +#define NUM_ACP_WINDOWS 6 + +const struct ext_man_windows xsram_window +#ifdef CONFIG_AMD_BINARY_BUILD + __aligned(EXT_MAN_ALIGN) __unused = { +#else + __aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = { +#endif + .hdr = { + .type = EXT_MAN_ELEM_WINDOW, + .elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN), + }, + .window = { + .ext_hdr = { + .hdr.cmd = SOF_IPC_FW_READY, + .hdr.size = sizeof(struct sof_ipc_window), + .type = SOF_IPC_EXT_WINDOW, + }, + .num_windows = NUM_ACP_WINDOWS, + .window = { + { + .type = SOF_IPC_REGION_UPBOX, + .id = 0, + .flags = 0, + .size = MAILBOX_DSPBOX_SIZE, + .offset = MAILBOX_DSPBOX_OFFSET, + }, + { + .type = SOF_IPC_REGION_DOWNBOX, + .id = 0, + .flags = 0, + .size = MAILBOX_HOSTBOX_SIZE, + .offset = MAILBOX_HOSTBOX_OFFSET, + }, + { + .type = SOF_IPC_REGION_DEBUG, + .id = 0, + .flags = 0, + .size = MAILBOX_DEBUG_SIZE, + .offset = MAILBOX_DEBUG_OFFSET, + }, + { + .type = SOF_IPC_REGION_TRACE, + .id = 0, + .flags = 0, + .size = MAILBOX_TRACE_SIZE, + .offset = MAILBOX_TRACE_OFFSET, + }, + { + .type = SOF_IPC_REGION_STREAM, + .id = 0, + .flags = 0, + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, + { + .type = SOF_IPC_REGION_EXCEPTION, + .id = 0, + .flags = 0, + .size = MAILBOX_EXCEPTION_SIZE, + .offset = MAILBOX_EXCEPTION_OFFSET, + }, + }, + }, +}; + +int platform_init(struct sof *sof) +{ + int ret; + + /* to view system memory */ + platform_interrupt_init(); + platform_clock_init(sof); + scheduler_init_edf(); + /* init low latency domains and schedulers */ + /* CONFIG_SYSTICK_PERIOD set as PLATFORM_DEFAULT_CLOCK */ + sof->platform_timer_domain = zephyr_domain_init(PLATFORM_DEFAULT_CLOCK); + zephyr_ll_scheduler_init(sof->platform_timer_domain); + + /*CONFIG_SYSTICK_PERIOD hardcoded as 200000*/ + sa_init(sof, 200000); + clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ); + /* init DMA */ + ret = dmac_init(sof); + if (ret < 0) { + return -ENODEV; + } + + /* initialize the host IPC mechanisms */ + ipc_init(sof); + /* initialize the DAI mechanisms */ + ret = dai_init(sof); + if (ret < 0) { + return -ENODEV; + } + + /* show heap status */ + heap_trace_all(1); + return 0; +} + +int platform_boot_complete(uint32_t boot_message) +{ + acp_sw_intr_trig_t swintrtrig; + volatile acp_scratch_mem_config_t *pscratch_mem_cfg = + (volatile acp_scratch_mem_config_t *)(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET); + mailbox_dspbox_write(0, &ready, sizeof(ready)); +#ifdef CONFIG_AMD_BINARY_BUILD + mailbox_dspbox_write(sizeof(ready), &xsram_window.window, sizeof(xsram_window.window)); +#endif + pscratch_mem_cfg->acp_dsp_msg_write = 1; + acp_dsp_to_host_intr_trig(); + /* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */ + swintrtrig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG); + swintrtrig.bits.trig_dsp0_to_host_intr = INTERRUPT_DISABLE; + io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), swintrtrig.u32all); + clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ); + return 0; +} + +int platform_context_save(struct sof *sof) +{ + return 0; +} +#ifdef __XCC__ +/* This is a stub for the Xtensa libc (not their newlib version), + * which inexplicably wants to pull in an unlink() implementation when + * linked against the C++ standard library. Obviously nothing in SOF + * uses the C library filesystem layer, this is just spurious. + */ +int __attribute__((weak)) _unlink_r(struct _reent *ptr, const char *file); +int __attribute__((weak)) _unlink_r(struct _reent *ptr, const char *file) +{ + return -1; +} +#endif diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 91598a776db0..ae525295726b 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -512,6 +512,20 @@ if (CONFIG_SOC_ACP_7_0) set(PLATFORM "acp_7_0") endif() +if (CONFIG_SOC_ACP_7_X) + # Platform sources + zephyr_library_sources( + ${SOF_DRIVERS_PATH}/amd/acp_7_x/ipc.c + ${SOF_PLATFORM_PATH}/amd/acp_7_x/platform.c + ${SOF_PLATFORM_PATH}/amd/acp_7_x/lib/clk.c + ) + zephyr_library_sources(lib/dma.c) + zephyr_include_directories(${SOF_PLATFORM_PATH}/amd/acp_7_x/include) + zephyr_include_directories(${SOF_PLATFORM_PATH}/amd/common/include) + zephyr_include_directories(${SOF_PLATFORM_PATH}/amd/acp_7_x/include/arch) + set(PLATFORM "acp_7_x") +endif() + if (CONFIG_SOC_FAMILY_MTK) set(PLATFORM "mtk") From 65705d3f696ad9155b2ddaf78486c2648eb3e4d4 Mon Sep 17 00:00:00 2001 From: Sneha Voona Date: Wed, 29 Apr 2026 12:45:53 +0530 Subject: [PATCH 07/10] dai: acp_7_x: add SDW DMA and DAI support for ACP_7_X Add ACP_7_X SDW DMA channel support in zephyr/lib/dma.c for native Zephyr DMA operations. Update dai.c to set dai_index from dd->dai->index for AMD SDW DAI, add ACP_7_X SDW instance handling with per-instance pin index array, and free DAI-specific data on DMA release for AMD. Signed-off-by: Sneha Voona --- src/ipc/ipc3/dai.c | 32 ++++++++++++++++++++++++++++---- zephyr/lib/dma.c | 4 ++-- 2 files changed, 30 insertions(+), 6 deletions(-) diff --git a/src/ipc/ipc3/dai.c b/src/ipc/ipc3/dai.c index c2faa73163d8..5fb1eeb837ff 100644 --- a/src/ipc/ipc3/dai.c +++ b/src/ipc/ipc3/dai.c @@ -29,6 +29,8 @@ LOG_MODULE_DECLARE(ipc, CONFIG_SOF_LOG_LEVEL); +#define DAI_INDEX_INVALID 0xFFFF + void dai_set_link_hda_config(uint16_t *link_config, struct ipc_config_dai *common_config, const void *spec_config) @@ -93,7 +95,10 @@ int dai_config_dma_channel(struct dai_data *dd, struct comp_dev *dev, const void break; case SOF_DAI_AMD_HS: case SOF_DAI_AMD_HS_VIRTUAL: - case SOF_DAI_AMD_SDW: + case SOF_DAI_AMD_SDW: { + struct dai_config *params = (struct dai_config *)dd->dai->dev->config; + + params->dai_index = dd->dai->index; channel = dai_get_handshake(dd->dai, dai->direction, dd->stream_id); #if defined(CONFIG_SOC_ACP_7_0) @@ -102,6 +107,7 @@ int dai_config_dma_channel(struct dai_data *dd, struct comp_dev *dev, const void } #endif break; + } case SOF_DAI_MEDIATEK_AFE: handshake = dai_get_handshake(dd->dai, dai->direction, dd->stream_id); @@ -209,9 +215,15 @@ int ipc_dai_data_config(struct dai_data *dd, struct comp_dev *dev) } pin_data->pin_num = dd->dai->index; pin_data->pin_dir = dai->direction; - pin_data->dma_channel = dd->chan ? dd->chan->index : 0xFFFF; - pin_data->index = 0xFFFF; - pin_data->instance = 0xFFFF; + pin_data->dma_channel = dd->chan ? dd->chan->index : DAI_INDEX_INVALID; +#if defined(CONFIG_SOC_ACP_7_X) + for (int i = 0; i < SDW_INSTANCES; i++) { + pin_data->index[i] = DAI_INDEX_INVALID; + } +#else + pin_data->index = DAI_INDEX_INVALID; +#endif + pin_data->instance = DAI_INDEX_INVALID; dev_data->dai_index_ptr = pin_data; } #endif @@ -310,6 +322,18 @@ void dai_dma_release(struct dai_data *dd, struct comp_dev *dev) return; } +#if defined(CONFIG_AMD) + /* Free allocated DAI-specific data structures */ + if (dd->dma && dd->dma->z_dev && dd->dma->z_dev->data) { + struct acp_dma_dev_data *dev_data = dd->dma->z_dev->data; + + if (dev_data->dai_index_ptr) { + rfree(dev_data->dai_index_ptr); + dev_data->dai_index_ptr = NULL; + } + } +#endif + /* put the allocated DMA channel first */ if (dd->chan) { /* remove callback */ diff --git a/zephyr/lib/dma.c b/zephyr/lib/dma.c index 380c31d48843..176398030e29 100644 --- a/zephyr/lib/dma.c +++ b/zephyr/lib/dma.c @@ -212,7 +212,7 @@ SHARED_DATA struct sof_dma dma[] = { .z_dev = DEVICE_DT_GET(DT_NODELABEL(host_dma)), }, #endif /* CONFIG_SOC_MIMX9596_M7 */ -#if defined(CONFIG_SOC_ACP_7_0) +#if defined(CONFIG_SOC_ACP_7_0) || defined(CONFIG_SOC_ACP_7_X) { .plat_data = { .dir = SOF_DMA_DIR_LMEM_TO_HMEM | @@ -233,7 +233,7 @@ SHARED_DATA struct sof_dma dma[] = { .caps = SOF_DMA_CAP_SW, .base = DMA0_BASE, .chan_size = DMA0_SIZE, - .channels = 12, + .channels = DT_PROP(DT_NODELABEL(acp_sdw_dma), dma_channels), .period_count = 2, }, .z_dev = DEVICE_DT_GET(DT_NODELABEL(acp_sdw_dma)), From 3a8ed1423c5cd7a07258a9cb98903c44b7381ab2 Mon Sep 17 00:00:00 2001 From: Sneha Voona Date: Fri, 10 Apr 2026 11:56:01 +0530 Subject: [PATCH 08/10] volume: acp_7_x: add volume support and fix scaling function reset On AMD platforms, the scale_vol function pointer is not reset after volume reaches its maximum value (32). This causes decreasing volume after reaching max to have no effect, because is_passthrough remains set and scale_vol is never updated to the gain function. Fix by resetting is_passthrough to false and re-selecting scale_vol via set_volume_process() on every SOF_CTRL_CMD_VOLUME command under CONFIG_AMD, ensuring correct volume scaling in both directions. Changes: - src/arch/xtensa/configs/acp_7_x_defconfig: enable CONFIG_COMP_VOLUME for ACP_7_X platform - src/audio/volume/volume_ipc3.c: reset is_passthrough and call set_volume_process() after volume changes so scale_vol is re-selected correctly after max volume is reached - tools/topology/topology1/sof-acp_7_x_sdw_volume_comp.m4: add ACP_7_X SDW topology with volume pipelines for HS playback/capture, Speaker playback and DMIC capture paths Signed-off-by: Sneha Voona --- src/arch/xtensa/configs/acp_7_x_defconfig | 2 +- src/audio/volume/volume_ipc3.c | 7 + .../topology1/sof-acp_7_x_sdw_volume_comp.m4 | 229 ++++++++++++++++++ 3 files changed, 237 insertions(+), 1 deletion(-) create mode 100644 tools/topology/topology1/sof-acp_7_x_sdw_volume_comp.m4 diff --git a/src/arch/xtensa/configs/acp_7_x_defconfig b/src/arch/xtensa/configs/acp_7_x_defconfig index 9a24d5517df4..d978611fadde 100644 --- a/src/arch/xtensa/configs/acp_7_x_defconfig +++ b/src/arch/xtensa/configs/acp_7_x_defconfig @@ -6,7 +6,7 @@ CONFIG_CORE_COUNT=1 CONFIG_FORMAT_CONVERT_HIFI3=n CONFIG_LP_SRAM=n CONFIG_HAVE_AGENT=n -CONFIG_COMP_VOLUME=n +CONFIG_COMP_VOLUME=y CONFIG_COMP_SRC=n CONFIG_COMP_FIR=n CONFIG_COMP_IIR=n diff --git a/src/audio/volume/volume_ipc3.c b/src/audio/volume/volume_ipc3.c index 99a9a9c57ce1..a71f13373f7f 100644 --- a/src/audio/volume/volume_ipc3.c +++ b/src/audio/volume/volume_ipc3.c @@ -219,6 +219,13 @@ int volume_set_config(struct processing_module *mod, uint32_t config_id, volume_set_ramp_channel_counter(cd, cd->channels); volume_ramp_check(mod); +#if defined(CONFIG_AMD) + /* Update function pointer after all volume changes */ + if (comp_dev_get_first_data_consumer(dev) != NULL) { + cd->is_passthrough = false; + set_volume_process(cd, dev, false); + } +#endif break; case SOF_CTRL_CMD_SWITCH: diff --git a/tools/topology/topology1/sof-acp_7_x_sdw_volume_comp.m4 b/tools/topology/topology1/sof-acp_7_x_sdw_volume_comp.m4 new file mode 100644 index 000000000000..0b2a1fe8898e --- /dev/null +++ b/tools/topology/topology1/sof-acp_7_x_sdw_volume_comp.m4 @@ -0,0 +1,229 @@ +#Required Topology for rt721 with ACP DMIC Card for ACP_7_X +# +# PCM Description DAI LINK DAI BE +# 0 HS Playback 0 SDW0-PIN0-PLAYBACK-SimpleJack AUDIO_TX +# 1 HS Capture 1 SDW0-PIN11-CAPTURE-SimpleJack AUDIO_RX +# 2 Speaker playback 2 SDW0-PIN4-PLAYBACK-SmartAmp BT_TX +# 4 SDW DMIC 4 SDW0-PIN15-CAPTURE-SmartMic HS_RX + +# +# Define the pipelines +# +# PCM0 ----> buffer ----> AUDIO_TX +# PCM1 <---- buffer <---- AUDIO_RX +# PCM2 ----> buffer ----> BT_TX +# PCM4 <---- buffer <---- HS_RX + +# Include topology builder +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') +include(`acp-sdw.m4') +include(`acp-dmic.m4') + +# Include TLV library +include(`common/tlv.m4') + +# Include Token library +include(`sof/tokens.m4') + +# Include ACP DSP configuration +include(`platform/amd/acp.m4') + +DEBUG_START + +#/**********************************************************************************/ +# PCM 0, HS Playback, DAI link id 0, Dai index 0(Audio_Tx), BE SW0-PIN0-PLAYBACK + +#Driver dai index and dai BE +#DAI Index(Instance * 64 + base_index) DAI_BE +#0(DI_SDW0_ACP_SW_AUDIO_0_TX) SDW0-PIN0-PLAYBACK-SimpleJack +# DI_SDW0_ACP_SW_AUDIO_4_TX SDW0-PIN4-PLAYBACK-SmartAmp + +define(DI_SDW0_ACP_SW_AUDIO_0_TX, 0 ) +define(DI_SDW0_ACP_SW_AUDIO_1_TX, 1 ) +define(DI_SDW0_ACP_SW_AUDIO_2_TX, 2 ) +define(DI_SDW0_ACP_SW_AUDIO_3_TX, 3 ) +define(DI_SDW0_ACP_SW_AUDIO_4_TX, 4 ) +define(DI_SDW0_ACP_SW_AUDIO_5_TX, 5 ) +define(DI_SDW0_ACP_SW_AUDIO_6_TX, 6 ) +define(DI_SDW0_ACP_SW_AUDIO_7_TX, 7 ) +define(DI_SDW0_ACP_SW_AUDIO_8_TX, 8 ) +define(DI_SDW0_ACP_SW_AUDIO_9_TX, 9 ) +define(DI_SDW0_ACP_SW_AUDIO_10_TX, 10) +define(DI_SDW0_ACP_SW_AUDIO_0_RX, 11) +define(DI_SDW0_ACP_SW_AUDIO_1_RX, 12) +define(DI_SDW0_ACP_SW_AUDIO_2_RX, 13) +define(DI_SDW0_ACP_SW_AUDIO_3_RX, 14) +define(DI_SDW0_ACP_SW_AUDIO_4_RX, 15) +define(DI_SDW0_ACP_SW_AUDIO_5_RX, 16) +define(DI_SDW0_ACP_SW_AUDIO_6_RX, 17) +define(DI_SDW0_ACP_SW_AUDIO_7_RX, 18) +define(DI_SDW0_ACP_SW_AUDIO_8_RX, 19) +define(DI_SDW0_ACP_SW_AUDIO_9_RX, 20) +define(DI_SDW0_ACP_SW_AUDIO_10_RX, 21) + +define(DI_SDW1_ACP_SW_AUDIO_0_TX, 64) +define(DI_SDW1_ACP_SW_AUDIO_1_TX, 65) +define(DI_SDW1_ACP_SW_AUDIO_2_TX, 66) +define(DI_SDW1_ACP_SW_AUDIO_3_TX, 67) +define(DI_SDW1_ACP_SW_AUDIO_4_TX, 68) +define(DI_SDW1_ACP_SW_AUDIO_5_TX, 69) +define(DI_SDW1_ACP_SW_AUDIO_6_TX, 70) +define(DI_SDW1_ACP_SW_AUDIO_7_TX, 71) +define(DI_SDW1_ACP_SW_AUDIO_8_TX, 72) +define(DI_SDW1_ACP_SW_AUDIO_9_TX, 73) +define(DI_SDW1_ACP_SW_AUDIO_10_TX, 74) +define(DI_SDW1_ACP_SW_AUDIO_0_RX, 75) +define(DI_SDW1_ACP_SW_AUDIO_1_RX, 76) +define(DI_SDW1_ACP_SW_AUDIO_2_RX, 77) +define(DI_SDW1_ACP_SW_AUDIO_3_RX, 78) +define(DI_SDW1_ACP_SW_AUDIO_4_RX, 79) +define(DI_SDW1_ACP_SW_AUDIO_5_RX, 80) +define(DI_SDW1_ACP_SW_AUDIO_6_RX, 81) +define(DI_SDW1_ACP_SW_AUDIO_7_RX, 82) +define(DI_SDW1_ACP_SW_AUDIO_8_RX, 83) +define(DI_SDW1_ACP_SW_AUDIO_9_RX, 84) +define(DI_SDW1_ACP_SW_AUDIO_10_RX, 85) + +define(DI_SDW2_ACP_SW_AUDIO_0_TX, 128) +define(DI_SDW2_ACP_SW_AUDIO_1_TX, 129) +define(DI_SDW2_ACP_SW_AUDIO_2_TX, 130) +define(DI_SDW2_ACP_SW_AUDIO_3_TX, 131) +define(DI_SDW2_ACP_SW_AUDIO_4_TX, 132) +define(DI_SDW2_ACP_SW_AUDIO_5_TX, 133) +define(DI_SDW2_ACP_SW_AUDIO_6_TX, 134) +define(DI_SDW2_ACP_SW_AUDIO_7_TX, 135) +define(DI_SDW2_ACP_SW_AUDIO_8_TX, 136) +define(DI_SDW2_ACP_SW_AUDIO_9_TX, 137) +define(DI_SDW2_ACP_SW_AUDIO_10_TX, 138) +define(DI_SDW2_ACP_SW_AUDIO_0_RX, 139) +define(DI_SDW2_ACP_SW_AUDIO_1_RX, 140) +define(DI_SDW2_ACP_SW_AUDIO_2_RX, 141) +define(DI_SDW2_ACP_SW_AUDIO_3_RX, 142) +define(DI_SDW2_ACP_SW_AUDIO_4_RX, 143) +define(DI_SDW2_ACP_SW_AUDIO_5_RX, 144) +define(DI_SDW2_ACP_SW_AUDIO_6_RX, 145) +define(DI_SDW2_ACP_SW_AUDIO_7_RX, 146) +define(DI_SDW2_ACP_SW_AUDIO_8_RX, 147) +define(DI_SDW2_ACP_SW_AUDIO_9_RX, 148) +define(DI_SDW2_ACP_SW_AUDIO_10_RX, 149) + +define(DI_SDW3_ACP_SW_AUDIO_0_TX, 192) +define(DI_SDW3_ACP_SW_AUDIO_1_TX, 193) +define(DI_SDW3_ACP_SW_AUDIO_2_TX, 194) +define(DI_SDW3_ACP_SW_AUDIO_3_TX, 195) +define(DI_SDW3_ACP_SW_AUDIO_4_TX, 196) +define(DI_SDW3_ACP_SW_AUDIO_5_TX, 197) +define(DI_SDW3_ACP_SW_AUDIO_6_TX, 198) +define(DI_SDW3_ACP_SW_AUDIO_7_TX, 199) +define(DI_SDW3_ACP_SW_AUDIO_8_TX, 200) +define(DI_SDW3_ACP_SW_AUDIO_9_TX, 201) +define(DI_SDW3_ACP_SW_AUDIO_10_TX, 202) +define(DI_SDW3_ACP_SW_AUDIO_0_RX, 203) +define(DI_SDW3_ACP_SW_AUDIO_1_RX, 204) +define(DI_SDW3_ACP_SW_AUDIO_2_RX, 205) +define(DI_SDW3_ACP_SW_AUDIO_3_RX, 206) +define(DI_SDW3_ACP_SW_AUDIO_4_RX, 207) +define(DI_SDW3_ACP_SW_AUDIO_5_RX, 208) +define(DI_SDW3_ACP_SW_AUDIO_6_RX, 209) +define(DI_SDW3_ACP_SW_AUDIO_7_RX, 210) +define(DI_SDW3_ACP_SW_AUDIO_8_RX, 211) +define(DI_SDW3_ACP_SW_AUDIO_9_RX, 212) +define(DI_SDW3_ACP_SW_AUDIO_10_RX, 213) + + +define(DAI_BE_SDW0_ACP_SW_AUDIO_4_TX, SDW0-PIN4-PLAYBACK-SmartAmp) +define(DAI_BE_SDW0_ACP_SW_AUDIO_0_TX, SDW0-PIN0-PLAYBACK-SimpleJack) +#define(DAI_BE_SDW1_ACP_SW_AUDIO_4_TX, SDW1-PIN4-PLAYBACK-SmartAmp) + +define(DAI_BE_SDW0_ACP_SW_AUDIO_0_RX, SDW0-PIN11-CAPTURE-SimpleJack) +define(DAI_BE_SDW0_ACP_SW_AUDIO_4_RX, SDW0-PIN15-CAPTURE-SmartMic) +define(DAI_BE_SDW0_ACP_SW_AUDIO_5_RX, SDW0-PIN16-CAPTURE-SmartMic) + +#pipeline: name of the predefined pipeline +#pipe id: pipeline ID. This should be a unique ID identifying the pipeline +#pcm: PCM ID. This will be used to bind to the correct front end DAI link + +dnl PIPELINE_PCM_ADD(pipeline, +dnl pipe id, pcm, max channels, format, +dnl period, priority, core, +dnl pcm_min_rate, pcm_max_rate, pipeline_rate) + +dnl DAI_ADD(pipeline, +dnl pipe id, dai type, dai_index, dai_be, +dnl buffer, periods, format, +dnl deadline, priority, core, time_domain) + +dnl DAI_CONFIG(type, dai_index, link_id, name, acphs_config/acpdmic_config) +dnl ACPHS_CONFIG(format, mclk, bclk, fsync, tdm, acphs_config_data) +dnl ACP_CLOCK(clock, freq, codec_provider, polarity) +dnl ACPHS_CONFIG_DATA(type, idx, valid bits, mclk_id) +dnl mclk_id is optional + +#/**********************************************************************************/ +PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, + 0, 0, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +DAI_ADD(sof/pipe-dai-playback.m4, 0, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_TX, DAI_BE_SDW0_ACP_SW_AUDIO_0_TX, +PIPELINE_SOURCE_0, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_TX, 0, DAI_BE_SDW0_ACP_SW_AUDIO_0_TX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_TX, 48000, 2))) +PCM_PLAYBACK_ADD(ACP-SW0-PIN0-Playback-HS, 0, PIPELINE_PCM_0) + +#/**********************************************************************************/ +#PCM 2, Speaker Playback, PIPE line 2, DAI link id 2, Dai index 4(DI_SDW0_ACP_SW_AUDIO_4_TX), DAI BE SDW0-PIN4-PLAYBACK-SmartAmp +PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, + 2, 2, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# playback DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-playback.m4, 2, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_4_TX, DAI_BE_SDW0_ACP_SW_AUDIO_4_TX, + PIPELINE_SOURCE_2, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_4_TX, 2, DAI_BE_SDW0_ACP_SW_AUDIO_4_TX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_4_TX, 48000, 2))) + +PCM_PLAYBACK_ADD(ACP-SW0-PIN4-Playback-SPK, 2, PIPELINE_PCM_2) +#/**********************************************************************************/ + +#/**********************************************************************************/ +#PCM 1, HS Capture, DAI link id 1, Dai index 11(DI_SDW0_ACP_SW_AUDIO_0_RX), BE DAI_BE_SDW0_ACP_SW_AUDIO_0_RX +# Capture pipeline 1 on PCM 1 using max 2 channels of s16le. +PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, + 1, 1, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# Capture DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-capture.m4, 1, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_RX, DAI_BE_SDW0_ACP_SW_AUDIO_0_RX, + PIPELINE_SINK_1, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_RX, 1, DAI_BE_SDW0_ACP_SW_AUDIO_0_RX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_RX, 48000, 2))) + +PCM_CAPTURE_ADD(ACP-SW0-PIN11-Capture-HS, 1, PIPELINE_PCM_1) +#/**********************************************************************************/ +#/**********************************************************************************/ +#PCM 4, SDW Capture, DAI link id 4, Dai index 16(DI_SDW0_ACP_SW_AUDIO_5_RX), BE SDW0-PIN16-CAPTURE-SmartMic +# Capture pipeline 1 on PCM 1 using max 2 channels of s16le. +PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, + 4, 4, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# Capture DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-capture.m4, 4, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_5_RX, DAI_BE_SDW0_ACP_SW_AUDIO_5_RX, + PIPELINE_SINK_4, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_5_RX, 4, DAI_BE_SDW0_ACP_SW_AUDIO_5_RX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_5_RX, 48000, 2))) + +PCM_CAPTURE_ADD(ACP-SW0-PIN16-CAPTURE-DMIC, 4, PIPELINE_PCM_4) +#/**********************************************************************************/ + +DEBUG_END From ec35b93054fc3df767a6ef160dc157b4ae71820f Mon Sep 17 00:00:00 2001 From: Sneha Voona Date: Fri, 10 Apr 2026 11:56:01 +0530 Subject: [PATCH 09/10] acp_7_x: add 24-bit platform support Changes include: - Add sample topology sof-acp_7_x_sdw_24bit.m4 for ACP_7_X SDW 24-bit pipelines supporting playback and capture paths - Select PCM conversion functions for S24_4LE<->S32_LE as per AMD hardware requirements under CONFIG_AMD, preserving existing behaviour for all other platforms Signed-off-by: Sneha Voona --- .../pcm_converter/pcm_converter_generic.c | 5 + .../topology1/sof-acp_7_x_sdw_24bit.m4 | 139 ++++++++++++++++++ 2 files changed, 144 insertions(+) create mode 100644 tools/topology/topology1/sof-acp_7_x_sdw_24bit.m4 diff --git a/src/audio/pcm_converter/pcm_converter_generic.c b/src/audio/pcm_converter/pcm_converter_generic.c index fe96e6d1f124..2dcdbeea7996 100644 --- a/src/audio/pcm_converter/pcm_converter_generic.c +++ b/src/audio/pcm_converter/pcm_converter_generic.c @@ -712,8 +712,13 @@ const struct pcm_func_map pcm_func_map[] = { { SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S16_LE, pcm_convert_s32_to_s16 }, #endif /* CONFIG_PCM_CONVERTER_FORMAT_S32LE && CONFIG_PCM_CONVERTER_FORMAT_S16LE */ #if CONFIG_PCM_CONVERTER_FORMAT_S32LE && CONFIG_PCM_CONVERTER_FORMAT_S24LE +#if defined(CONFIG_SOC_ACP_7_X) + { SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S32_LE, just_copy }, + { SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S24_4LE, pcm_convert_s32_to_s24_be }, +#else { SOF_IPC_FRAME_S24_4LE, SOF_IPC_FRAME_S32_LE, pcm_convert_s24_to_s32 }, { SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S24_4LE, pcm_convert_s32_to_s24 }, +#endif #endif /* CONFIG_PCM_CONVERTER_FORMAT_S32LE && CONFIG_PCM_CONVERTER_FORMAT_S24LE */ #if CONFIG_PCM_CONVERTER_FORMAT_FLOAT { SOF_IPC_FRAME_FLOAT, SOF_IPC_FRAME_FLOAT, just_copy }, diff --git a/tools/topology/topology1/sof-acp_7_x_sdw_24bit.m4 b/tools/topology/topology1/sof-acp_7_x_sdw_24bit.m4 new file mode 100644 index 000000000000..852f6bf6eaa9 --- /dev/null +++ b/tools/topology/topology1/sof-acp_7_x_sdw_24bit.m4 @@ -0,0 +1,139 @@ +#Required Topology for rt721 with ACP DMIC Card for ACP_7_X +# +# PCM Description DAI LINK DAI BE +# 0 HS Playback 0 SDW0-PIN0-PLAYBACK-SimpleJack AUDIO_TX +# 1 HS Capture 1 SDW0-PIN11-CAPTURE-SimpleJack AUDIO_RX +# 2 Speaker playback 2 SDW0-PIN4-PLAYBACK-SmartAmp BT_TX +# 4 SDW DMIC 4 SDW0-PIN15-CAPTURE-SmartMic HS_RX + +# +# Define the pipelines +# +# PCM0 ----> buffer ----> AUDIO_TX +# PCM1 <---- buffer <---- AUDIO_RX +# PCM2 ----> buffer ----> BT_TX +# PCM4 <---- buffer <---- HS_RX + +# Include topology builder +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') +include(`acp-sdw.m4') +include(`acp-dmic.m4') + +# Include TLV library +include(`common/tlv.m4') + +# Include Token library +include(`sof/tokens.m4') + +# Include ACP DSP configuration +include(`platform/amd/acp.m4') + +DEBUG_START + +#/**********************************************************************************/ +# PCM 0, HS Playback, DAI link id 0, Dai index 0(Audio_Tx), BE SW0-PIN0-PLAYBACK + +#Driver dai index and dai BE +#DAI Index(Instance * 64 + base_index) DAI_BE +#0(DI_SDW0_ACP_SW_AUDIO_0_TX) SDW0-PIN0-PLAYBACK-SimpleJack +# DI_SDW0_ACP_SW_AUDIO_4_TX SDW0-PIN4-PLAYBACK-SmartAmp + +define(DI_SDW0_ACP_SW_AUDIO_0_TX, 0) +define(DI_SDW0_ACP_SW_AUDIO_4_TX, 4) +define(DI_SDW0_ACP_SW_AUDIO_0_RX, 11) +define(DI_SDW0_ACP_SW_AUDIO_5_RX, 16) + + +define(DAI_BE_SDW0_ACP_SW_AUDIO_4_TX, SDW0-PIN4-PLAYBACK-SmartAmp) +define(DAI_BE_SDW0_ACP_SW_AUDIO_0_TX, SDW0-PIN0-PLAYBACK-SimpleJack) + +define(DAI_BE_SDW0_ACP_SW_AUDIO_0_RX, SDW0-PIN11-CAPTURE-SimpleJack) +define(DAI_BE_SDW0_ACP_SW_AUDIO_5_RX, SDW0-PIN16-CAPTURE-SmartMic) + +#pipeline: name of the predefined pipeline +#pipe id: pipeline ID. This should be a unique ID identifying the pipeline +#pcm: PCM ID. This will be used to bind to the correct front end DAI link + +dnl PIPELINE_PCM_ADD(pipeline, +dnl pipe id, pcm, max channels, format, +dnl period, priority, core, +dnl pcm_min_rate, pcm_max_rate, pipeline_rate) + +dnl DAI_ADD(pipeline, +dnl pipe id, dai type, dai_index, dai_be, +dnl buffer, periods, format, +dnl deadline, priority, core, time_domain) + +dnl DAI_CONFIG(type, dai_index, link_id, name, acphs_config/acpdmic_config) +dnl ACPHS_CONFIG(format, mclk, bclk, fsync, tdm, acphs_config_data) +dnl ACP_CLOCK(clock, freq, codec_provider, polarity) +dnl ACPHS_CONFIG_DATA(type, idx, valid bits, mclk_id) +dnl mclk_id is optional + +#/**********************************************************************************/ +PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, + 0, 0, 2, s32le, + 2000, 0, 0, + 48000, 48000, 48000) + +DAI_ADD(sof/pipe-dai-playback.m4, 0, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_TX, DAI_BE_SDW0_ACP_SW_AUDIO_0_TX, +PIPELINE_SOURCE_0, 2, s24le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_TX, 0, DAI_BE_SDW0_ACP_SW_AUDIO_0_TX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_TX, 48000, 2))) +PCM_PLAYBACK_ADD(ACP-SW0-PIN0-Playback-HS, 0, PIPELINE_PCM_0) + +#/**********************************************************************************/ +#PCM 2, Speaker Playback, PIPE line 2, DAI link id 2, Dai index 4(DI_SDW0_ACP_SW_AUDIO_4_TX), DAI BE SDW0-PIN4-PLAYBACK-SmartAmp +PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, + 2, 2, 2, s32le, + 2000, 0, 0, + 48000, 48000, 48000) + +# playback DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-playback.m4, 2, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_4_TX, DAI_BE_SDW0_ACP_SW_AUDIO_4_TX, + PIPELINE_SOURCE_2, 2, s24le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_4_TX, 2, DAI_BE_SDW0_ACP_SW_AUDIO_4_TX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_4_TX, 48000, 2))) + +PCM_PLAYBACK_ADD(ACP-SW0-PIN4-Playback-SPK, 2, PIPELINE_PCM_2) +#/**********************************************************************************/ + +#/**********************************************************************************/ +#PCM 1, HS Capture, DAI link id 1, Dai index 11(DI_SDW0_ACP_SW_AUDIO_0_RX), BE DAI_BE_SDW0_ACP_SW_AUDIO_0_RX +# Capture pipeline 1 on PCM 1 using max 2 channels of s24le. +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 1, 1, 2, s32le, + 2000, 0, 0, + 48000, 48000, 48000) + +# Capture DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-capture.m4, 1, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_RX, DAI_BE_SDW0_ACP_SW_AUDIO_0_RX, + PIPELINE_SINK_1, 2, s24le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_RX, 1, DAI_BE_SDW0_ACP_SW_AUDIO_0_RX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_0_RX, 48000, 2))) + +PCM_CAPTURE_ADD(ACP-SW0-PIN11-Capture-HS, 1, PIPELINE_PCM_1) +#/**********************************************************************************/ +#/**********************************************************************************/ +#PCM 4, SDW Capture, DAI link id 4, Dai index 16(DI_SDW0_ACP_SW_AUDIO_5_RX), BE SDW0-PIN16-CAPTURE-SmartMic +# Capture pipeline 1 on PCM 1 using max 2 channels of s24le. +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 4, 4, 2, s32le, + 2000, 0, 0, + 48000, 48000, 48000) + +# Capture DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-capture.m4, 4, ACP_SDW, DI_SDW0_ACP_SW_AUDIO_5_RX, DAI_BE_SDW0_ACP_SW_AUDIO_5_RX, + PIPELINE_SINK_4, 2, s24le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_5_RX, 4, DAI_BE_SDW0_ACP_SW_AUDIO_5_RX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_AUDIO_5_RX, 48000, 2))) + +PCM_CAPTURE_ADD(ACP-SW0-PIN16-CAPTURE-DMIC, 4, PIPELINE_PCM_4) + +DEBUG_END From aab5985c6521754e6020352f99e3260ed326de78 Mon Sep 17 00:00:00 2001 From: Sneha Voona Date: Tue, 5 May 2026 16:19:04 +0530 Subject: [PATCH 10/10] schedule: amd: set LL timer period to 500us for AMD ACP platforms As per AMD internal hardware design requirement, the ACP DSP scheduler tick must run at 500 microseconds (2kHz) instead of the default 1ms (1kHz). Guard the 500us value with CONFIG_AMD so non-AMD platforms retain the existing 1ms default period unchanged. Signed-off-by: Sneha Voona --- src/include/sof/schedule/ll_schedule_domain.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/include/sof/schedule/ll_schedule_domain.h b/src/include/sof/schedule/ll_schedule_domain.h index dc28e43c7461..451ad7739f8f 100644 --- a/src/include/sof/schedule/ll_schedule_domain.h +++ b/src/include/sof/schedule/ll_schedule_domain.h @@ -22,7 +22,11 @@ #include #include +#if defined(CONFIG_AMD) +#define LL_TIMER_PERIOD_US 500ULL /* 500us period for AMD ACP platforms */ +#else #define LL_TIMER_PERIOD_US 1000ULL /* default period in microseconds */ +#endif /* Default ll watchdog timeout in microseconds. * It was decided to have a timeout of two periods to give a safe margin of time between the start