diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 5a78a865e5e..2b896f265b6 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -53,12 +53,14 @@ "at32/at32f457-start", "at32/at32m412-start", "at32/at32m416-start", - "hc32/ev_hc32f4a0_lqfp176", - "hc32/ev_hc32f4a8_lqfp176", "hc32/ev_hc32f334_lqfp64", "hc32/ev_hc32f448_lqfp80", "hc32/ev_hc32f460_lqfp100_v2", + "hc32/ev_hc32f467_lqfp144", "hc32/ev_hc32f472_lqfp100", + "hc32/ev_hc32f4a0_lqfp176", + "hc32/ev_hc32f4a2_lqfp176", + "hc32/ev_hc32f4a8_lqfp176", "hc32/lckfb-hc32f4a0-lqfp100", "hc32l196", "hc32l136", diff --git "a/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" "b/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" index b2e3c102160..1ea5d2fbb24 100644 --- "a/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" +++ "b/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" @@ -227,7 +227,7 @@ HC32 BSP 的制作规范主要分为 3 个方面：工程配置，ENV 配置和 - 系统心跳统一设置为 1000（宏：RT_TICK_PER_SECOND） - BSP 中需要打开调试选项中的断言（宏：RT_DEBUG） -- 系统空闲线程栈大小统一设置为 256（宏：IDLE_THREAD_STACK_SIZE） +- 系统空闲线程栈大小统一设置为 512（宏：IDLE_THREAD_STACK_SIZE） - 开启组件自动初始化（宏：RT_USING_COMPONENTS_INIT） - 需要开启 user main 选项（宏：RT_USING_USER_MAIN） - FinSH 默认只使用 MSH 模式（宏：FINSH_USING_MSH_ONLY） diff --git "a/bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" "b/bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" index 6cfc4b402c3..36a07e7228d 100644 --- "a/bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" +++ "b/bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" @@ -40,7 +40,7 @@ | 8 | [ADC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/adc/adc) | 测量管脚上的模拟量 | | 9 | [DAC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/dac/dac) | 通过管脚输出模拟量 | | 10 | [CAN](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/can/can) | 通过 CAN 收发数据 | -| 11 | [HWTIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/hwtimer/hwtimer) | 通过硬件定时器计时 | +| 11 | [CLOCK_TIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/clock_timer/clock_timer) | 通过硬件定时器计时 | | 12 | [PWM](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm) | 在特定的管脚输出 PWM 波形 | | 13 | [RTC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc) | 设置和读取时间 | | 14 | [WDT](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog) | 看门狗驱动 | diff --git a/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml index 84e83f68114..2fcf64d2937 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml @@ -24,9 +24,9 @@ devices.flash: devices.gpio: kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f334_lqfp64/README.md b/bsp/hc32/ev_hc32f334_lqfp64/README.md index a7e2ff21424..36242376cf8 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/README.md +++ b/bsp/hc32/ev_hc32f334_lqfp64/README.md @@ -46,7 +46,7 @@ EV_F334_LQ64 开发板常用 **板载资源** 如下： | DAC | 支持 | | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1...PF3 ---> PIN：0，1...68 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | MCAN | 支持 | | diff --git a/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h b/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h index 959fac2be73..1be4a443513 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 24 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 /* kservice options */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml index 7eb2f098c02..38498a3c9b4 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml @@ -22,11 +22,11 @@ devices.flash: - CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_SFUD=y devices.gpio: - kconfig: + kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f448_lqfp80/README.md b/bsp/hc32/ev_hc32f448_lqfp80/README.md index e614500cca8..362bce9d743 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/README.md +++ b/bsp/hc32/ev_hc32f448_lqfp80/README.md @@ -47,7 +47,7 @@ EV_F448_LQ80 开发板常用 **板载资源** 如下： | DAC | 支持 | | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1...PH2 ---> PIN：0，1...82 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | MCAN | 支持 | | diff --git a/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h b/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h index 667256b56ec..013a783681b 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 24 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 /* kservice options */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml index 047a4483ef7..1412567fb0f 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml @@ -23,11 +23,11 @@ devices.flash: - CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_SFUD=y devices.gpio: - kconfig: + kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md b/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md index 7c6a879aef8..6712d20576d 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md @@ -46,7 +46,7 @@ EV_F460_LQ100_V2 开发板常用 **板载资源** 如下： | Crypto | 支持 | CRC，HASH，RNG | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1... PH2 ---> PIN：0，1...82 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | PM | 支持 | | diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h index 9dbb237fcac..d70aa6adad1 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 24 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 /* kservice options */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f467_lqfp144/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 00000000000..a16d29885aa --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,188 @@ +# ------ device CI ------ +devices.adc: + kconfig: + - CONFIG_BSP_USING_ADC=y + - CONFIG_BSP_USING_ADC1=y + - CONFIG_BSP_ADC1_USING_DMA=y +devices.can: + kconfig: + - CONFIG_BSP_USING_CAN=y + - CONFIG_BSP_USING_CAN1=y + - CONFIG_RT_CAN_USING_HDR=y +devices.crypto: + kconfig: + - CONFIG_BSP_USING_HWCRYPTO=y + - CONFIG_BSP_USING_UQID=y + - CONFIG_BSP_USING_RNG=y + - CONFIG_BSP_USING_CRC=y + - CONFIG_BSP_USING_AES=y + - CONFIG_BSP_USING_HASH=y +devices.dac: + kconfig: + - CONFIG_BSP_USING_DAC=y + - CONFIG_BSP_USING_DAC1=y +devices.flash: + kconfig: + - CONFIG_BSP_USING_ON_CHIP_FLASH=y + - CONFIG_RT_USING_FAL=y + - CONFIG_RT_USING_SPI=y + - CONFIG_RT_USING_SFUD=y +devices.gpio: + kconfig: + - CONFIG_BSP_USING_GPIO=y +devices.clock_timer: + kconfig: + - CONFIG_BSP_USING_CLOCK_TIMER=y + - CONFIG_BSP_USING_TMRA_1=y +devices.i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1=y + - CONFIG_BSP_I2C1_TX_USING_DMA=y + - CONFIG_BSP_I2C1_RX_USING_DMA=y +devices.input_capture: + kconfig: + - CONFIG_BSP_USING_INPUT_CAPTURE=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6_1=y +devices.pm: + kconfig: + - CONFIG_BSP_USING_PM=y + - CONFIG_IDLE_THREAD_STACK_SIZE=512 +devices.pulse_encoder_tmr6: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMR6_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMR6_1=y +devices.pulse_encoder_tmra: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMRA_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMRA_1=y +devices.pwm_tmr4: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR4=y + - CONFIG_BSP_USING_PWM_TMR4_1=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUL=y +devices.pwm_tmr6: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR6=y + - CONFIG_BSP_USING_PWM_TMR6_1=y + - CONFIG_BSP_USING_PWM_TMR6_1_A=y + - CONFIG_BSP_USING_PWM_TMR6_1_B=y +devices.pwm_tmra: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMRA=y + - CONFIG_BSP_USING_PWM_TMRA_1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH2=y +devices.qspi: + kconfig: + - CONFIG_BSP_USING_QSPI=y + - CONFIG_BSP_QSPI_USING_DMA=y + - CONFIG_BSP_QSPI_USING_SOFT_CS=y +devices.rtc: + kconfig: + - CONFIG_BSP_USING_RTC=y + - CONFIG_RT_USING_ALARM=y +devices.sdio: + kconfig: + - CONFIG_BSP_USING_SDIO=y + - CONFIG_BSP_USING_SDIO1=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.soft_i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1_SW=y +devices.spi: + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI1=y + - CONFIG_BSP_SPI1_TX_USING_DMA=y + - CONFIG_BSP_SPI1_RX_USING_DMA=y + - CONFIG_BSP_SPI_USING_DMA=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.uart_v1: + kconfig: + - CONFIG_RT_USING_SERIAL_V1=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART6=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART6_RX_USING_DMA=y + - CONFIG_BSP_UART6_TX_USING_DMA=y +devices.uart_v2: + kconfig: + - CONFIG_RT_USING_SERIAL_V2=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART6=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART6_RX_USING_DMA=y + - CONFIG_BSP_UART6_TX_USING_DMA=y +devices.usb_hs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBD_HS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_hs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBH_HS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.usb_fs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBD_FS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_fs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBH_FS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.watchdog_swdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_SWDT=y +devices.watchdog_wdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_WDT=y + +# ------ peripheral CI ------ +peripheral.eth_rmii: + kconfig: + - CONFIG_BSP_USING_ETH=y + - CONFIG_ETH_INTERFACE_USING_RMII=y + - CONFIG_ETH_PHY_USING_INTERRUPT_MODE=y + - CONFIG_RT_USING_LWIP212=y + - CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +peripheral.exmc_nand: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_NAND=y + - CONFIG_FINSH_USING_MSH=y +peripheral.exmc_sdram: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_SDRAM=y + - CONFIG_FINSH_USING_MSH=y +peripheral.spi_flash: + kconfig: + - CONFIG_BSP_USING_SPI_FLASH=y diff --git a/bsp/hc32/ev_hc32f467_lqfp144/.config b/bsp/hc32/ev_hc32f467_lqfp144/.config new file mode 100644 index 00000000000..eeb684221a0 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/.config @@ -0,0 +1,1482 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=24 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart7" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_ARCH_USING_HW_ATOMIC_8=y +CONFIG_ARCH_USING_HW_ATOMIC_16=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +CONFIG_RT_USING_INPUT_CAPTURE=y +CONFIG_RT_INPUT_CAPTURE_RB_SIZE=100 +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER=y +CONFIG_PKG_HC32F4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32-f4-cmsis" +CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_HC32F4_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_HC32F4_SERIES_DRIVER=y +CONFIG_PKG_HC32F4_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32-f4-series" +CONFIG_PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_HC32F4_SERIES_DRIVER_VER="latest" +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_HC32=y +CONFIG_SOC_SERIES_HC32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HC32F467RG=y + +# +# On-chip Drivers +# +CONFIG_BSP_USING_ON_CHIP_FLASH_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_DCODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH=y +# end of On-chip Drivers + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_EXMC is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +CONFIG_BSP_USING_TCA9539=y +CONFIG_BSP_USING_EXT_IO=y +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +CONFIG_BSP_USING_UART7=y +# CONFIG_BSP_UART7_RX_USING_DMA is not set +# CONFIG_BSP_UART7_TX_USING_DMA is not set +# CONFIG_BSP_USING_UART10 is not set +CONFIG_BSP_USING_I2C=y +# CONFIG_BSP_USING_I2C1_SW is not set +CONFIG_BSP_USING_I2C_HW=y +CONFIG_BSP_USING_I2C1=y +# CONFIG_BSP_I2C1_TX_USING_DMA is not set +# CONFIG_BSP_I2C1_RX_USING_DMA is not set +# CONFIG_BSP_USING_I2C2 is not set +# CONFIG_BSP_USING_I2C3 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_WDT_TMR is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_PM is not set +# CONFIG_BSP_USING_HWCRYPTO is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_USING_PULSE_ENCODER is not set +# CONFIG_BSP_USING_CLOCK_TIMER is not set +# CONFIG_BSP_USING_INPUT_CAPTURE is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/hc32/ev_hc32f467_lqfp144/.cproject b/bsp/hc32/ev_hc32f467_lqfp144/.cproject new file mode 100644 index 00000000000..09d16161fd5 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/.cproject @@ -0,0 +1,224 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/.gitignore b/bsp/hc32/ev_hc32f467_lqfp144/.gitignore new file mode 100644 index 00000000000..7221bde019d --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32/ev_hc32f467_lqfp144/.project b/bsp/hc32/ev_hc32f467_lqfp144/.project new file mode 100644 index 00000000000..49763a6a327 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/.project @@ -0,0 +1,78 @@ + + + ev_hc32f467_lqfp144 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + rt-thread + 2 + virtual:/virtual + + + rt-thread/bsp + 2 + virtual:/virtual + + + rt-thread/components + 2 + $%7BPARENT-3-PROJECT_LOC%7D/components + + + rt-thread/include + 2 + $%7BPARENT-3-PROJECT_LOC%7D/include + + + rt-thread/libcpu + 2 + $%7BPARENT-3-PROJECT_LOC%7D/libcpu + + + rt-thread/src + 2 + $%7BPARENT-3-PROJECT_LOC%7D/src + + + rt-thread/bsp/hc32 + 2 + virtual:/virtual + + + rt-thread/bsp/hc32/libraries + 2 + $%7BPARENT-1-PROJECT_LOC%7D/libraries + + + rt-thread/bsp/hc32/platform + 2 + PARENT-1-PROJECT_LOC/platform + + + rt-thread/bsp/hc32/tests + 2 + PARENT-1-PROJECT_LOC/tests + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/EventRecorderStub.scvd b/bsp/hc32/ev_hc32f467_lqfp144/EventRecorderStub.scvd new file mode 100644 index 00000000000..2956b296838 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/Kconfig b/bsp/hc32/ev_hc32f467_lqfp144/Kconfig new file mode 100644 index 00000000000..73238d3a13b --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/hc32/ev_hc32f467_lqfp144/README.md b/bsp/hc32/ev_hc32f467_lqfp144/README.md new file mode 100644 index 00000000000..11d05b9a50b --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/README.md @@ -0,0 +1,142 @@ +# XHSC EV_F467_LQ144 开发板 BSP 说明 + +## 简介 + +本文档为小华半导体为 EV_F467_LQ144 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +EV_F467_LQ144 是 XHSC 官方推出的开发板，搭载 HC32F467RGTI 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F467RGTI 的芯片性能。 + +开发板外观如下图所示： + + ![board](figures/board.jpg) + +EV_F467_LQ144 开发板常用 **板载资源** 如下： + +- MCU：HC32F466RGTI，主频240MHz，1048KB FLASH，512KB RAM +- 外部RAM：IS62WV51216(SRAM，1MB) IS42S16400J(SDRAM，8MB) +- 外部FLASH: MT29F2G08AB(Nand，256MB) W25Q64(SPI NOR，8MB) +- 常用外设 + - LED：3 个，User LED(LED0、LED1、LED2)。 + - 按键：6 个，矩阵键盘(K1~K4)、WAKEUP(K5)、RESET(K0)。 +- 常用接口：SD卡接口、以太网接口、LCD接口、USB FS/HS接口、DVP接口、3.5mm耳机接口、Line in接口、CAN接口、LIN接口。 +- 调试接口：板载DAP调试器（含USB转串口）、标准JTAG/SWD。 + +开发板更多详细信息请参考小华半导体半导体[EV_F467_LQ144](https://www.xhsc.com.cn) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ETH | 支持 | RTL8201F | +| Nand | 支持 | MT29F2G08AB | +| SDRAM | 支持 | IS42S16400J | +| USB 转串口 | 支持 | 使用 UART7 | + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ADC | 支持 | | +| CAN | 支持 | | +| Crypto | 支持 | AES，CRC，HASH，RNG | +| DAC | 支持 | | +| FLASH | 支持 | | +| GPIO | 支持 | PA0，PA1...PI13 ---> PIN：0，1...141 | +| CLOCK_TIMER | 支持 | | +| I2C | 支持 | 软件、硬件 I2C | +| InputCapture | 支持 | | +| PM | 支持 | | +| PulseEncoder | 支持 | | +| PWM | 支持 | | +| QSPI | 支持 | | +| RTC | 支持 | 闹钟精度为1分钟 | +| SDIO | 支持 | | +| SPI | 支持 | | +| UART V1 & V2 | 支持 | | +| USB | 支持 | USBFS/HS Core， device/host模式 | +| WDT | 支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用Type-A to MircoUSB线连接开发板和PC供电。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED10会周期性闪烁。 + +USB虚拟COM端口默认连接串口7，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.1.0 build Apr 24 2022 13:32:39 + 2006 - 2022 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 7 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +| 板载外设 | 模式 | 协议栈 | 注意事项 | +| :------: | :----: | :------------: | :----------------------------------------------------------- | +| USB | device | ALL | 由于协议栈的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） | +| USB | device | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需先通过J14连接到主机（如PC），再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | ALL | ALL | 由于main()函数中的LED闪烁示例，使用的是USBFS主机的供电控制管脚，因而当配置为使用USBFS Core时，需要将main()函数中的LED示例代码手动屏蔽。 | +| USB | host | ALL | 为确保USB主机对外供电充足，建议通过J35外接5V电源供电，并短接J32的EXT跳帽。 | +| USB | host | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需通过J14先连接好OTG线，再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | host | RTT legacy USB | 目前仅实现并测试了对U盘的支持。 | +| USB | host | RTT legacy USB | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | +| USB | ALL | ALL | 由于管脚复用的原因，当配置使用USBHS Core时，无法同时使用板载SPI FLASH。 | +| USB | ALL | ALL | CherryUSB 与 RTT legacy USB 组件不可同时使用;
CherryUSB与 ”On-Chip Peripheral Driver---> []Enable USB“ 不可同时使能及配置。 | +| USB | ALL | RTT legacy USB | 通过“board/config/usb_config/usb_app_conf.h” 进行应用个性化配置（主要为FIFO分配） | +| USB | ALL | CherryUSB | 通过“board/ports/usb_config.h”进行应用个性化配置（如FIFO分配、是否使用DMA[Device]、是否使用高速PHY等） | + +## 联系人信息 + +维护人: + +- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱： diff --git a/bsp/hc32/ev_hc32f467_lqfp144/SConscript b/bsp/hc32/ev_hc32f467_lqfp144/SConscript new file mode 100644 index 00000000000..20f7689c53c --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32/ev_hc32f467_lqfp144/SConstruct b/bsp/hc32/ev_hc32f467_lqfp144/SConstruct new file mode 100644 index 00000000000..6d2a0ea7e9c --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/SConstruct @@ -0,0 +1,83 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "hc32-f4-cmsis-latest"), + os.path.join("packages", "hc32-f4-series-latest") + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +rtconfig.BSP_LIBRARY_TYPE = None + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript'))) + +# include platform +platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform' +objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript'))) + +# include tests +test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests' +objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32/ev_hc32f467_lqfp144/applications/SConscript b/bsp/hc32/ev_hc32f467_lqfp144/applications/SConscript new file mode 100644 index 00000000000..9bb9abae897 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/hc32/ev_hc32f467_lqfp144/applications/main.c b/bsp/hc32/ev_hc32f467_lqfp144/applications/main.c new file mode 100644 index 00000000000..0cb11049480 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/applications/main.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#include +#include +#include +#include + +int main(void) +{ + /* set LED_BLUE_PIN pin mode to output */ + TCA9539_ConfigPin(LED_BLUE_PORT, LED_BLUE_PIN, TCA9539_DIR_OUT); + + while (1) + { + TCA9539_WritePin(LED_BLUE_PORT, LED_BLUE_PIN, TCA9539_PIN_SET); + rt_thread_mdelay(500); + TCA9539_WritePin(LED_BLUE_PORT, LED_BLUE_PIN, TCA9539_PIN_RESET); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hc32/ev_hc32f467_lqfp144/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f467_lqfp144/applications/xtal32_fcm.c new file mode 100644 index 00000000000..ef3b07e20b1 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/applications/xtal32_fcm.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +#include +#include +#include + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_UNIT (CM_FCM) + +/** + * @brief This thread is used to monitor whether XTAL32 is stable. + * This thread only runs once after the system starts. + * When stability is detected or 2s times out, the thread will end. + * (When a timeout occurs it will be prompted via rt_kprintf) + */ +void xtal32_fcm_thread_entry(void *parameter) +{ + stc_fcm_init_t stcFcmInit; + uint32_t u32TimeOut = 0UL; + uint32_t u32Time = 200UL; /* 200*10ms = 2s */ + + /* FCM config */ + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); + (void)FCM_StructInit(&stcFcmInit); + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); + /* Enable FCM, to ensure xtal32 stable */ + FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); + + while (1) + { + if (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_END)) + { + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_END); + if ((SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR)) || (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_OVF))) + { + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR | FCM_FLAG_OVF); + } + else + { + (void)FCM_DeInit(XTAL32_FCM_UNIT); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + /* XTAL32 stabled */ + break; + } + } + u32TimeOut++; + if (u32TimeOut > u32Time) + { + (void)FCM_DeInit(XTAL32_FCM_UNIT); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + rt_kprintf("Error: XTAL32 still unstable, timeout.\n"); + break; + } + rt_thread_mdelay(10); + } +} + +int xtal32_fcm_thread_create(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL, + XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + rt_kprintf("create xtal32_fcm thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(xtal32_fcm_thread_create); + +#endif + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/Kconfig b/bsp/hc32/ev_hc32f467_lqfp144/board/Kconfig new file mode 100644 index 00000000000..b20ce601401 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/Kconfig @@ -0,0 +1,910 @@ +menu "Hardware Drivers Config" + +config SOC_HC32F467RG + bool + select SOC_SERIES_HC32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Drivers" + menuconfig BSP_USING_ON_CHIP_FLASH_CACHE + bool "Enable on-chip Flash Cache" + default y + if BSP_USING_ON_CHIP_FLASH_CACHE + config BSP_USING_ON_CHIP_FLASH_ICODE_CACHE + bool "Enable on-chip Flash ICODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_DCODE_CACHE + bool "Enable on-chip Flash DCODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH + bool "Enable on-chip Flash ICODE Prefetch" + default y + endif +endmenu + +menu "Onboard Peripheral Drivers" + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + select RT_USING_LWIP + select RT_LWIP_USING_HW_CHECKSUM + + if BSP_USING_ETH + choice + prompt "Select ETH PHY type" + default ETH_PHY_USING_RTL8201F + + config ETH_PHY_USING_RTL8201F + bool "ETH PHY USING RTL8201F" + select BSP_USING_I2C + select BSP_USING_I2C1 + select BSP_USING_TCA9539 + endchoice + + choice + prompt "Select ETH Communication Interface" + default ETH_INTERFACE_USING_RMII + + config ETH_INTERFACE_USING_RMII + bool "ETH Communication USING RMII" + endchoice + endif + + config BSP_USING_EXMC + bool "Enable EXMC" + default n + if BSP_USING_EXMC + choice + prompt "Using SDRAM or NAND" + default BSP_USING_NAND + + config BSP_USING_NAND + bool "Using NAND (MT29F2G08AB)" + select RT_USING_MTD_NAND + + config BSP_USING_SDRAM + bool "Using SDRAM (IS42S16400J7TLI)" + endchoice + endif + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (w25q64 spi1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + select BSP_USING_ON_CHIP_FLASH + select RT_USING_SFUD + select RT_USING_DFS + select RT_USING_FAL + select RT_USING_MTD_NOR + default n + + config BSP_USING_TCA9539 + bool "Enable TCA9539" + select BSP_USING_I2C + select BSP_USING_I2C1 + default n + + config BSP_USING_EXT_IO + bool + default y + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + select BSP_USING_TCA9539 + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + + config BSP_UART1_DMA_PING_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_DMA_PING_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_DMA_PING_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default y + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART7_DMA_PING_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART10 + bool "Enable UART10" + default n + if BSP_USING_UART10 + config BSP_UART10_RX_BUFSIZE + int "Set UART10 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART10_TX_BUFSIZE + int "Set UART10 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" + default n + select RT_USING_I2C + + if BSP_USING_I2C + menuconfig BSP_USING_I2C1_SW + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1_SW + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" + range 1 144 + default 8 # PA8 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 144 + default 23 # PB7 + endif + endif + + if BSP_USING_I2C + config BSP_I2C_USING_DMA + bool + default n + config BSP_USING_I2C_HW + bool + default n + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool + default n + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool + default n + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + endif + + menuconfig BSP_USING_I2C3 + bool "Enable I2C3 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool + default n + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C3_USING_DMA + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C3_USING_DMA + endif + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_SPI_USING_DMA + bool + default n + + menuconfig BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + if BSP_USING_SPI1 + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI1_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + if BSP_USING_SPI2 + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI2_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + if BSP_USING_SPI3 + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI4 + bool "Enable SPI4 BUS" + default n + if BSP_USING_SPI4 + config BSP_SPI4_TX_USING_DMA + bool "Enable SPI4 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI4_RX_USING_DMA + bool "Enable SPI4 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI4_TX_USING_DMA + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC1 + bool "Enable ADC1" + default n + if BSP_USING_ADC1 + config BSP_ADC1_USING_DMA + bool "using adc1 dma" + default n + endif + menuconfig BSP_USING_ADC2 + bool "Enable ADC2" + default n + if BSP_USING_ADC2 + config BSP_ADC2_USING_DMA + bool "using adc2 dma" + default n + endif + menuconfig BSP_USING_ADC3 + bool "Enable ADC3" + default n + if BSP_USING_ADC3 + config BSP_ADC3_USING_DMA + bool "using adc3 dma" + default n + endif + endif + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "using dac1" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + select RT_CAN_USING_HDR + select BSP_USING_TCA9539 + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using can1" + default n + config BSP_USING_CAN2 + bool "using can2" + default n + endif + + menuconfig BSP_USING_WDT_TMR + bool "Enable Watchdog Timer" + default n + select RT_USING_WDT + if BSP_USING_WDT_TMR + choice + prompt "Select SWDT/WDT" + default BSP_USING_SWDT + + config BSP_USING_SWDT + bool "SWDT(3.72hour(max))" + config BSP_USING_WDT + bool "WDT(10.7s(max))" + endchoice + + config BSP_WDT_CONTINUE_COUNT + bool "Low Power Mode Keeps Counting" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_XTAL32 + + config BSP_RTC_USING_XTAL32 + bool "RTC USING XTAL32" + + config BSP_RTC_USING_LRC + bool "RTC USING LRC" + endchoice + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + default n + select RT_USING_SDIO + select RT_USING_DFS + if BSP_USING_SDIO + config BSP_USING_SDIO1 + bool "Enable SDIO1" + default n + config BSP_USING_SDIO2 + bool "Enable SDIO2" + default n + endif + + menuconfig BSP_USING_PM + bool "Enable PM" + default n + select RT_USING_PM + if BSP_USING_PM + choice + prompt "Select WKTM Clock Src" + default BSP_USING_WKTM_LRC + + config BSP_USING_WKTM_XTAL32 + bool "Using Xtal32" + config BSP_USING_WKTM_LRC + bool "Using LRC" + if BSP_RTC_USING_XTAL32 + config BSP_USING_WKTM_64HZ + bool "Using 64HZ(Note:must use XTAL32 and run RTC)" + endif + endchoice + endif + + menuconfig BSP_USING_HWCRYPTO + bool "Using Hardware Crypto drivers" + default n + select RT_USING_HWCRYPTO + if BSP_USING_HWCRYPTO + config BSP_USING_UQID + bool "Enable UQID (unique id)" + default n + + config BSP_USING_RNG + bool "Using Hardware RNG" + default n + select RT_HWCRYPTO_USING_RNG + + config BSP_USING_CRC + bool "Using Hardware CRC" + default n + select RT_HWCRYPTO_USING_CRC + + config BSP_USING_AES + bool "Using Hardware AES" + default n + select RT_HWCRYPTO_USING_AES + if BSP_USING_AES + choice + prompt "Select AES Mode" + default BSP_USING_AES_ECB + + config BSP_USING_AES_ECB + bool "ECB mode" + select RT_HWCRYPTO_USING_AES_ECB + endchoice + endif + + config BSP_USING_HASH + bool "Using Hardware Hash" + default n + select RT_HWCRYPTO_USING_SHA2 + if BSP_USING_HASH + choice + prompt "Select Hash Mode" + default BSP_USING_SHA2_256 + + config BSP_USING_SHA2_256 + bool "SHA2_256 Mode" + select RT_HWCRYPTO_USING_SHA2_256 + endchoice + endif + + endif + + menuconfig BSP_USING_PWM + bool "Enable output PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM_TMRA + bool "Enable timerA output PWM" + default n + if BSP_USING_PWM_TMRA + menuconfig BSP_USING_PWM_TMRA_1 + bool "Enable timerA-1 output PWM" + default n + if BSP_USING_PWM_TMRA_1 + config BSP_USING_PWM_TMRA_1_CH1 + bool "Enable timerA-1 channel1" + default n + config BSP_USING_PWM_TMRA_1_CH2 + bool "Enable timerA-1 channel2" + default n + config BSP_USING_PWM_TMRA_1_CH3 + bool "Enable timerA-1 channel3" + default n + config BSP_USING_PWM_TMRA_1_CH4 + bool "Enable timerA-1 channel4" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR4 + bool "Enable timer4 output PWM" + default n + if BSP_USING_PWM_TMR4 + menuconfig BSP_USING_PWM_TMR4_1 + bool "Enable timer4-1 output PWM" + default n + if BSP_USING_PWM_TMR4_1 + config BSP_USING_PWM_TMR4_1_OUH + bool "Enable TMR4_1_OUH channel1" + default n + config BSP_USING_PWM_TMR4_1_OUL + bool "Enable TMR4_1_OUL channel2" + default n + config BSP_USING_PWM_TMR4_1_OVH + bool "Enable TMR4_1_OVH channel3" + default n + config BSP_USING_PWM_TMR4_1_OVL + bool "Enable TMR4_1_OVL channel4" + default n + config BSP_USING_PWM_TMR4_1_OWH + bool "Enable TMR4_1_OWH channel5" + default n + config BSP_USING_PWM_TMR4_1_OWL + bool "Enable TMR4_1_OWL channel6" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR6 + bool "Enable timer6 output PWM" + default n + if BSP_USING_PWM_TMR6 + menuconfig BSP_USING_PWM_TMR6_1 + bool "Enable timer6-1 output PWM" + default n + if BSP_USING_PWM_TMR6_1 + config BSP_USING_PWM_TMR6_1_A + bool "Enable TMR6_1_A channel1" + default n + config BSP_USING_PWM_TMR6_1_B + bool "Enable TMR6_1_B channel2" + default n + endif + endif + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + depends on !RT_USING_CHERRYUSB + if BSP_USING_USB + config BSP_USING_USBD + bool + default n + config BSP_USING_USBH + bool + default n + config BSP_USING_USBFS + bool "Use USBFS Core" + default n + if BSP_USING_USBFS + choice + prompt "Select USB Mode" + default BSP_USING_USBD_FS + + config BSP_USING_USBD_FS + bool "USB Device Mode" + select BSP_USING_USBD + select RT_USING_USB_DEVICE + + config BSP_USING_USBH_FS + bool "USB Host Mode" + select BSP_USING_USBH + select RT_USING_USB_HOST + endchoice + if BSP_USING_USBD_FS + config BSP_USING_USBD_VBUS_SENSING + bool "Enable VBUS Sensing for Device" + default y + endif + if BSP_USING_USBH_FS + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers for Host" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + endif + config BSP_USING_USBHS + bool "Use USBHS Core" + default n + if BSP_USING_USBHS + choice + prompt "Select USB Mode" + default BSP_USING_USBH_HS + + config BSP_USING_USBD_HS + bool "USB Device Mode" + select BSP_USING_USBD + select RT_USING_USB_DEVICE + depends on !BSP_USING_USBD_FS + + config BSP_USING_USBH_HS + bool "USB Host Mode" + select BSP_USING_USBH + select RT_USING_USB_HOST + depends on !BSP_USING_USBH_FS + endchoice + choice + prompt "Select USB PHY" + default BSP_USING_USBHS_PHY_EMBED + + config BSP_USING_USBHS_PHY_EMBED + bool "Use USBHS Embedded PHY" + + config BSP_USING_USBHS_PHY_EXTERN + bool "Use USBHS External PHY" + select BSP_USING_I2C1 + select BSP_USING_TCA9539 + endchoice + if BSP_USING_USBD_HS + config BSP_USING_USBD_VBUS_SENSING + bool "Enable VBUS Sensing for Device" + default y + endif + if BSP_USING_USBH_HS + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers for Host" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + endif + endif + + menuconfig BSP_USING_QSPI + bool "Enable QSPI BUS" + select RT_USING_QSPI + select RT_USING_SPI + default n + if BSP_USING_QSPI + config BSP_QSPI_USING_DMA + bool "Enable QSPI DMA support" + default n + config BSP_QSPI_USING_SOFT_CS + bool "Enable QSPI Soft CS Pin" + default n + endif + + menuconfig BSP_USING_PULSE_ENCODER + bool "Enable Pulse Encoder" + default n + select RT_USING_PULSE_ENCODER + if BSP_USING_PULSE_ENCODER + menuconfig BSP_USING_TMRA_PULSE_ENCODER + bool "Use TIMERA As The Pulse Encoder" + default n + if BSP_USING_TMRA_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMRA_1 + bool "Use TIMERA_1 As The Pulse Encoder" + default n + endif + menuconfig BSP_USING_TMR6_PULSE_ENCODER + bool "Use TIMER6 As The Pulse Encoder" + default n + if BSP_USING_TMR6_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMR6_1 + bool "Use TIMER6_1 As The Pulse Encoder" + default n + endif + endif + + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" + default n + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_TMRA_1 + bool "Use Timer_a1 As CLOCK_TIMER1" + default n + config BSP_USING_TMRA_2 + bool "Use Timer_a2 As CLOCK_TIMER2" + default n + config BSP_USING_TMRA_3 + bool "Use Timer_a3 As CLOCK_TIMER3" + default n + config BSP_USING_TMRA_4 + bool "Use Timer_a4 As CLOCK_TIMER4" + default n + config BSP_USING_TMRA_5 + bool "Use Timer_a5 As CLOCK_TIMER5" + default n + config BSP_USING_TMRA_6 + bool "Use Timer_a6 As CLOCK_TIMER6" + default n + config BSP_USING_TMRA_7 + bool "Use Timer_a7 As CLOCK_TIMER7" + default n + config BSP_USING_TMRA_8 + bool "Use Timer_a8 As CLOCK_TIMER8" + default n + endif + menuconfig BSP_USING_INPUT_CAPTURE + bool "Enable Input Capture" + default n + select RT_USING_INPUT_CAPTURE + if BSP_USING_INPUT_CAPTURE + menuconfig BSP_USING_INPUT_CAPTURE_TMR6 + bool "Use Timer6 As The Input Capture" + default n + if BSP_USING_INPUT_CAPTURE_TMR6 + config BSP_USING_INPUT_CAPTURE_TMR6_1 + bool "unit 1" + config BSP_USING_INPUT_CAPTURE_TMR6_2 + bool "unit 2" + config BSP_USING_INPUT_CAPTURE_TMR6_3 + bool "unit 3" + endif + endif +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/SConscript b/bsp/hc32/ev_hc32f467_lqfp144/board/SConscript new file mode 100644 index 00000000000..f7786d16aec --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/SConscript @@ -0,0 +1,20 @@ +import os +from building import * + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +path = [cwd] +path += [cwd + '/ports'] +path += [cwd + '/config'] +path += [cwd + '/config/usb_config'] + +CPPDEFINES = ['HC32F467', '__DEBUG'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/board.c b/bsp/hc32/ev_hc32f467_lqfp144/board/board.c new file mode 100644 index 00000000000..01f8e4ce9c0 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/board.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#include "board.h" +#include "board_config.h" + +/* unlock/lock peripheral */ +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) + +/** System Base Configuration +*/ +void SystemBase_Config(void) +{ +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE) + EFM_ICacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE) + EFM_DCacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH) + EFM_PrefetchCmd(ENABLE); +#endif + /* Reset the VBAT area */ + PWC_VBAT_Reset(); +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + stc_clock_xtal_init_t stcXtalInit; + stc_clock_pll_init_t stcPLLHInit; +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + stc_clock_pllx_init_t stcPLLAInit; +#endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + stc_clock_xtal32_init_t stcXtal32Init; +#endif + + /* PCLK0, HCLK Max 240MHz */ + /* PCLK1, PCLK4 Max 120MHz */ + /* PCLK2, PCLK3 Max 60MHz */ + /* EX BUS Max 120MHz */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, \ + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \ + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \ + CLK_HCLK_DIV1)); + + GPIO_AnalogCmd(XTAL_PORT, XTAL_PIN, ENABLE); + (void)CLK_XtalStructInit(&stcXtalInit); + /* Config Xtal and enable Xtal */ + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stcXtalInit); + + (void)CLK_PLLStructInit(&stcPLLHInit); + /* VCO = (8/1)*120 = 960MHz*/ + stcPLLHInit.u8PLLState = CLK_PLL_ON; + stcPLLHInit.PLLCFGR = 0UL; + stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + (void)CLK_PLLInit(&stcPLLHInit); + + /* Highspeed SRAM set to 0 Read/Write wait cycle */ + SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0); + /* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */ + SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1); + /* 0-wait @ 40MHz */ + (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5); + /* 4 cycles for 200 ~ 250MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT4); + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + /* PLLX for USB */ + (void)CLK_PLLxStructInit(&stcPLLAInit); + /* VCO = (8/2)*120 = 480MHz*/ + stcPLLAInit.u8PLLState = CLK_PLL_ON; + stcPLLAInit.PLLCFGR = 0UL; + stcPLLAInit.PLLCFGR_f.PLLM = 2UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLP = 10UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLR = 4UL - 1UL; + (void)CLK_PLLxInit(&stcPLLAInit); +#endif + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + /* Xtal32 config */ + GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); + (void)CLK_Xtal32StructInit(&stcXtal32Init); + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; + (void)CLK_Xtal32Init(&stcXtal32Init); +#endif +} + +/** Peripheral Clock Configuration +*/ +void PeripheralClock_Config(void) +{ +#if defined(BSP_USING_CAN1) + CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6); +#endif +#if defined(BSP_USING_CAN2) + CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6); +#endif + +#if defined(RT_USING_ADC) + CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP); +#endif +} + +/** Peripheral Registers Unlock +*/ +void PeripheralRegister_Unlock(void) +{ + LL_PERIPH_WE(EXAMPLE_PERIPH_WE); +} + +/*@}*/ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/board.h b/bsp/hc32/ev_hc32f467_lqfp144/board/board.h new file mode 100644 index 00000000000..c9f0dcefb1c --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/board.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ll.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (4) +#define HC32_FLASH_SIZE (1 * 1024 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) + +#define HC32_SRAM_SIZE (512) +#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION +extern int Image$$RW_IRAM2$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END HC32_SRAM_END + +void PeripheralRegister_Unlock(void); +void PeripheralClock_Config(void); +void SystemBase_Config(void); +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.c b/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.c new file mode 100644 index 00000000000..b276aae62da --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.c @@ -0,0 +1,801 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#include +#include "board_config.h" +#include "tca9539_port.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART1) + case (rt_uint32_t)CM_USART1: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC); + GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC); + break; +#endif +#if defined(BSP_USING_UART6) + case (rt_uint32_t)CM_USART6: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, USART6_RX_FUNC); + GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, USART6_TX_FUNC); + break; +#endif +#if defined(BSP_USING_UART7) + case (rt_uint32_t)CM_USART7: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART7_RX_PORT, USART7_RX_PIN, USART7_RX_FUNC); + GPIO_SetFunc(USART7_TX_PORT, USART7_TX_PIN, USART7_TX_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_I2C) +rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + (void)GPIO_StructInit(&stcGpioInit); + + switch ((rt_uint32_t)I2Cx) + { +#if defined(BSP_USING_I2C1) + case (rt_uint32_t)CM_I2C1: + /* Configure I2C1 SDA/SCL pin. */ + GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC); + GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(RT_USING_ADC) +rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)ADCx) + { +#if defined(BSP_USING_ADC1) + case (rt_uint32_t)CM_ADC1: + (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC2) + case (rt_uint32_t)CM_ADC2: + (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC3) + case (rt_uint32_t)CM_ADC3: + (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_DAC) +rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)DACx) + { +#if defined(BSP_USING_DAC1) + case (rt_uint32_t)CM_DAC1: + (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit); + (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_CAN) +void CanPhyEnable(void) +{ + TCA9539_WritePin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_DIR_OUT); +} +rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)CANx) + { +#if defined(BSP_USING_CAN1) + case (rt_uint32_t)CM_CAN1: + GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC); + GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC); + break; +#endif +#if defined(BSP_USING_CAN2) + case (rt_uint32_t)CM_CAN2: + GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC); + GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + + +#if defined (RT_USING_SPI) +rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) +{ + rt_err_t result = RT_EOK; +#if defined(BSP_USING_SPI1) + stc_gpio_init_t stcGpioInit; +#endif + + switch ((rt_uint32_t)CM_SPIx) + { +#if defined(BSP_USING_SPI1) + case (rt_uint32_t)CM_SPI1: + GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinState = PIN_STAT_SET; + stcGpioInit.u16PinDir = PIN_DIR_OUT; + GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); + GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); + GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_ETH) +/* PHY hardware reset time */ +#define PHY_HW_RST_DELAY (0x40U) + +rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) +{ + TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + return RT_EOK; +} + +rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx) +{ + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC); + GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC); + GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC); + GPIO_SetFunc(ETH_RMII_REF_CLK_PORT, ETH_RMII_REF_CLK_PIN, ETH_RMII_REF_CLK_FUNC); + GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC); + GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC); + GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC); + + return RT_EOK; +} +#endif + +#if defined (RT_USING_SDIO) +rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + switch ((rt_uint32_t)SDIOCx) + { +#if defined(BSP_USING_SDIO1) + case (rt_uint32_t)CM_SDIOC1: + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); + + GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); + GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC); + GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); + GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); + GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); + GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_PWM) +#if defined(BSP_USING_PWM_TMRA) +rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMRAx) + { +#if defined(BSP_USING_PWM_TMRA_1) + case (rt_uint32_t)CM_TMRA_1: +#ifdef BSP_USING_PWM_TMRA_1_CH1 + GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH2 + GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH3 + GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH4 + GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR4) +rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR4x) + { +#if defined(BSP_USING_PWM_TMR4_1) + case (rt_uint32_t)CM_TMR4_1: +#ifdef BSP_USING_PWM_TMR4_1_OUH + GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OUL + GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVH + GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVL + GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWH + GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWL + GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR6) +rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR6x) + { +#if defined(BSP_USING_PWM_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: +#ifdef BSP_USING_PWM_TMR6_1_A + GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR6_1_B + GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif +#endif + +#if defined (BSP_USING_INPUT_CAPTURE) +rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)tmr_instance) + { +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) + case (rt_uint32_t)CM_TMR6_2: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) + case (rt_uint32_t)CM_TMR6_3: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined (BSP_USING_SDRAM) +rt_err_t rt_hw_board_sdram_init(void) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + /* DMC_CKE */ + (void)GPIO_Init(SDRAM_CKE_PORT, SDRAM_CKE_PIN, &stcGpioInit); + /* DMC_CLK */ + (void)GPIO_Init(SDRAM_CLK_PORT, SDRAM_CLK_PIN, &stcGpioInit); + /* DMC_LDQM && DMC_UDQM */ + (void)GPIO_Init(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, &stcGpioInit); + /* DMC_BA[0:1] */ + (void)GPIO_Init(SDRAM_BA0_PORT, SDRAM_BA0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_BA1_PORT, SDRAM_BA1_PIN, &stcGpioInit); + /* DMC_CAS && DMC_RAS */ + (void)GPIO_Init(SDRAM_CAS_PORT, SDRAM_CAS_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_RAS_PORT, SDRAM_RAS_PIN, &stcGpioInit); + /* DMC_WE */ + (void)GPIO_Init(SDRAM_WE_PORT, SDRAM_WE_PIN, &stcGpioInit); + /* DMC_DATA[0:15] */ + (void)GPIO_Init(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, &stcGpioInit); + /* DMC_ADD[0:11]*/ + (void)GPIO_Init(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD12_PORT, SDRAM_ADD12_PIN, &stcGpioInit); + + /************************** Set EXMC pin function *************************/ + /* DMC_CKE */ + GPIO_SetFunc(SDRAM_CKE_PORT, SDRAM_CKE_PIN, SDRAM_CKE_FUNC); + /* DMC_CLK */ + GPIO_SetFunc(SDRAM_CLK_PORT, SDRAM_CLK_PIN, SDRAM_CLK_FUNC); + /* DMC_LDQM && DMC_UDQM */ + GPIO_SetFunc(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, SDRAM_DQM0_FUNC); + GPIO_SetFunc(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, SDRAM_DQM1_FUNC); + /* DMC_BA[0:1] */ + GPIO_SetFunc(SDRAM_BA0_PORT, SDRAM_BA0_PIN, SDRAM_BA0_FUNC); + GPIO_SetFunc(SDRAM_BA1_PORT, SDRAM_BA1_PIN, SDRAM_BA1_FUNC); + /* DMC_CS */ + GPIO_SetFunc(SDRAM_CS_PORT, SDRAM_CS_PIN, SDRAM_CS_FUNC); + /* DMC_CAS && DMC_RAS */ + GPIO_SetFunc(SDRAM_CAS_PORT, SDRAM_CAS_PIN, SDRAM_CAS_FUNC); + GPIO_SetFunc(SDRAM_RAS_PORT, SDRAM_RAS_PIN, SDRAM_RAS_FUNC); + /* DMC_WE */ + GPIO_SetFunc(SDRAM_WE_PORT, SDRAM_WE_PIN, SDRAM_WE_FUNC); + /* DMC_DATA[0:15] */ + GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC); + GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC); + GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC); + GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC); + GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC); + GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC); + GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC); + GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC); + GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC); + GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC); + GPIO_SetFunc(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, SDRAM_DATA10_FUNC); + GPIO_SetFunc(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, SDRAM_DATA11_FUNC); + GPIO_SetFunc(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, SDRAM_DATA12_FUNC); + GPIO_SetFunc(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, SDRAM_DATA13_FUNC); + GPIO_SetFunc(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, SDRAM_DATA14_FUNC); + GPIO_SetFunc(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, SDRAM_DATA15_FUNC); + /* DMC_ADD[0:11]*/ + GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC); + GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC); + GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC); + GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC); + GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC); + GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC); + GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC); + GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC); + GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC); + GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC); + GPIO_SetFunc(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, SDRAM_ADD10_FUNC); + GPIO_SetFunc(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, SDRAM_ADD11_FUNC); + GPIO_SetFunc(SDRAM_ADD12_PORT, SDRAM_ADD12_PIN, SDRAM_ADD11_FUNC); + + return result; +} +#endif + +#ifdef RT_USING_PM +void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode) +{ + switch (run_mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + break; + + case PM_RUN_MODE_LOW_SPEED: + /* Ensure that system clock less than 8M */ + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL); + + default: + break; + } +} +#endif + +#if defined(BSP_USING_USBFS) +rt_err_t rt_hw_usbfs_board_init(void) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); +#if defined(BSP_USING_USBD_FS) + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ +#endif +#if defined(BSP_USING_USBH_FS) + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ +#endif + return RT_EOK; +} +#endif + +#if defined(BSP_USING_USBHS) +rt_err_t rt_hw_usbhs_board_init(void) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + +#if defined(BSP_USING_USBHS_PHY_EMBED) + /* USBHS work in embedded PHY */ + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg); +#if defined(BSP_USING_USBD_HS) + GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC); +#endif +#if defined(BSP_USING_USBH_HS) + GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ +#endif +#else + /* Reset 3300 */ + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET); + TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT); + + (void)GPIO_StructInit(&stcGpioCfg); + /* High drive capability */ + stcGpioCfg.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg); + + GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC); + GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); + GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); + GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); +#endif + + return RT_EOK; +} +#endif + +#if defined(RT_USING_CHERRYUSB) +rt_err_t rt_hw_usbfs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ + } + else + { + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ + } + return RT_EOK; +} + +rt_err_t rt_hw_usbhs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + +#if !defined(CONFIG_USB_HS) + /* USBHS work in embedded PHY */ + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC); + } + else + { + GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ + } +#else + /* Reset 3300 */ + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET); + TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT); + + (void)GPIO_StructInit(&stcGpioCfg); + /* High drive capability */ + stcGpioCfg.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg); + + GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC); + GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); + GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); + GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); +#endif + + return RT_EOK; +} +#endif + + +#if defined(BSP_USING_QSPI) +rt_err_t rt_hw_qspi_board_init(void) +{ + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; +#ifndef BSP_QSPI_USING_SOFT_CS + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); +#endif + (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC); + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmra_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC); +#endif + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC); +#endif + + return RT_EOK; +} +#endif + +#if defined (BSP_USING_NAND) +rt_err_t rt_hw_board_nand_init(void) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + /* NFC_CE */ + (void)GPIO_Init(NAND_CE_PORT, NAND_CE_PIN, &stcGpioInit); + /* NFC_RE */ + (void)GPIO_Init(NAND_RE_PORT, NAND_RE_PIN, &stcGpioInit); + /* NFC_WE */ + (void)GPIO_Init(NAND_WE_PORT, NAND_WE_PIN, &stcGpioInit); + /* NFC_CLE */ + (void)GPIO_Init(NAND_CLE_PORT, NAND_CLE_PIN, &stcGpioInit); + /* NFC_ALE */ + (void)GPIO_Init(NAND_ALE_PORT, NAND_ALE_PIN, &stcGpioInit); + /* NFC_WP */ + (void)GPIO_Init(NAND_WP_PORT, NAND_WP_PIN, &stcGpioInit); + GPIO_SetPins(NAND_WP_PORT, NAND_WP_PIN); + + /* NFC_DATA[0:7] */ + (void)GPIO_Init(NAND_DATA0_PORT, NAND_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA1_PORT, NAND_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA2_PORT, NAND_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA3_PORT, NAND_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA4_PORT, NAND_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA5_PORT, NAND_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA6_PORT, NAND_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA7_PORT, NAND_DATA7_PIN, &stcGpioInit); + /* NFC_RB */ + (void)GPIO_Init(NAND_RB_PORT, NAND_RB_PIN, &stcGpioInit); + + /************************** Set EXMC pin function *************************/ + /* NFC_CE */ + GPIO_SetFunc(NAND_CE_PORT, NAND_CE_PIN, NAND_CE_FUNC); + /* NFC_RE */ + GPIO_SetFunc(NAND_RE_PORT, NAND_RE_PIN, NAND_RE_FUNC); + /* NFC_WE */ + GPIO_SetFunc(NAND_WE_PORT, NAND_WE_PIN, NAND_WE_FUNC); + /* NFC_CLE */ + GPIO_SetFunc(NAND_CLE_PORT, NAND_CLE_PIN, NAND_CLE_FUNC); + /* NFC_ALE */ + GPIO_SetFunc(NAND_ALE_PORT, NAND_ALE_PIN, NAND_ALE_FUNC); + /* NFC_WP */ + GPIO_SetFunc(NAND_WP_PORT, NAND_WP_PIN, NAND_WP_FUNC); + /* NFC_RB */ + GPIO_SetFunc(NAND_RB_PORT, NAND_RB_PIN, NAND_RB_FUNC); + /* NFC_DATA[0:7] */ + GPIO_SetFunc(NAND_DATA0_PORT, NAND_DATA0_PIN, NAND_DATA0_FUNC); + GPIO_SetFunc(NAND_DATA1_PORT, NAND_DATA1_PIN, NAND_DATA1_FUNC); + GPIO_SetFunc(NAND_DATA2_PORT, NAND_DATA2_PIN, NAND_DATA2_FUNC); + GPIO_SetFunc(NAND_DATA3_PORT, NAND_DATA3_PIN, NAND_DATA3_FUNC); + GPIO_SetFunc(NAND_DATA4_PORT, NAND_DATA4_PIN, NAND_DATA4_FUNC); + GPIO_SetFunc(NAND_DATA5_PORT, NAND_DATA5_PIN, NAND_DATA5_FUNC); + GPIO_SetFunc(NAND_DATA6_PORT, NAND_DATA6_PIN, NAND_DATA6_FUNC); + GPIO_SetFunc(NAND_DATA7_PORT, NAND_DATA7_PIN, NAND_DATA7_FUNC); + + return result; +} +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.h new file mode 100644 index 00000000000..483579c989a --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.h @@ -0,0 +1,630 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ll.h" +#include "drv_config.h" +#if defined(RT_USING_CHERRYUSB) + #include "usb_config.h" +#endif + +/************************* XTAL port **********************/ +#define XTAL_PORT (GPIO_PORT_H) +#define XTAL_PIN (GPIO_PIN_00 | GPIO_PIN_01) + +/************************ USART port **********************/ +#if defined(BSP_USING_UART7) + #define USART7_RX_PORT (GPIO_PORT_D) + #define USART7_RX_PIN (GPIO_PIN_06) + #define USART7_RX_FUNC (GPIO_FUNC_39) + + #define USART7_TX_PORT (GPIO_PORT_D) + #define USART7_TX_PIN (GPIO_PIN_07) + #define USART7_TX_FUNC (GPIO_FUNC_38) +#endif + +#if defined(BSP_USING_UART6) + #define USART6_RX_PORT (GPIO_PORT_D) + #define USART6_RX_PIN (GPIO_PIN_05) + #define USART6_RX_FUNC (GPIO_FUNC_37) + + #define USART6_TX_PORT (GPIO_PORT_E) + #define USART6_TX_PIN (GPIO_PIN_06) + #define USART6_TX_FUNC (GPIO_FUNC_36) +#endif + +/************************ I2C port **********************/ +#if defined(BSP_USING_I2C1) + #define I2C1_SDA_PORT (GPIO_PORT_F) + #define I2C1_SDA_PIN (GPIO_PIN_10) + #define I2C1_SDA_FUNC (GPIO_FUNC_48) + + #define I2C1_SCL_PORT (GPIO_PORT_B) + #define I2C1_SCL_PIN (GPIO_PIN_01) + #define I2C1_SCL_FUNC (GPIO_FUNC_51) +#endif + +/*********** ADC configure *********/ +#if defined(BSP_USING_ADC1) + #define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN10 */ + #define ADC1_CH_PIN (GPIO_PIN_00) +#endif + +#if defined(BSP_USING_ADC2) + #define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN11 */ + #define ADC2_CH_PIN (GPIO_PIN_01) +#endif + +#if defined(BSP_USING_ADC3) + #define ADC3_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN12 */ + #define ADC3_CH_PIN (GPIO_PIN_02) +#endif + +/*********** DAC configure *********/ +#if defined(BSP_USING_DAC1) + #define DAC1_CH1_PORT (GPIO_PORT_A) + #define DAC1_CH1_PIN (GPIO_PIN_04) + #define DAC1_CH2_PORT (GPIO_PORT_A) + #define DAC1_CH2_PIN (GPIO_PIN_05) +#endif + +/*********** CAN configure *********/ +#if defined(BSP_USING_CAN1) + #define CAN1_TX_PORT (GPIO_PORT_D) + #define CAN1_TX_PIN (GPIO_PIN_11) + #define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) + + #define CAN1_RX_PORT (GPIO_PORT_D) + #define CAN1_RX_PIN (GPIO_PIN_04) + #define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) +#endif + +#if defined(BSP_USING_CAN2) + #define CAN2_TX_PORT (GPIO_PORT_D) + #define CAN2_TX_PIN (GPIO_PIN_13) + #define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) + + #define CAN2_RX_PORT (GPIO_PORT_D) + #define CAN2_RX_PIN (GPIO_PIN_12) + #define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) +#endif + +/************************* SPI port ***********************/ +#if defined(BSP_USING_SPI1) + #define SPI1_CS_PORT (GPIO_PORT_C) + #define SPI1_CS_PIN (GPIO_PIN_07) + + #define SPI1_SCK_PORT (GPIO_PORT_C) + #define SPI1_SCK_PIN (GPIO_PIN_06) + #define SPI1_SCK_FUNC (GPIO_FUNC_40) + + #define SPI1_MOSI_PORT (GPIO_PORT_B) + #define SPI1_MOSI_PIN (GPIO_PIN_13) + #define SPI1_MOSI_FUNC (GPIO_FUNC_41) + + #define SPI1_MISO_PORT (GPIO_PORT_B) + #define SPI1_MISO_PIN (GPIO_PIN_12) + #define SPI1_MISO_FUNC (GPIO_FUNC_42) + + #define SPI1_WP_PORT (GPIO_PORT_B) + #define SPI1_WP_PIN (GPIO_PIN_10) + + #define SPI1_HOLD_PORT (GPIO_PORT_B) + #define SPI1_HOLD_PIN (GPIO_PIN_02) +#endif + +/************************* ETH port ***********************/ + +#if defined(BSP_USING_ETH) + #define ETH_SMI_MDIO_PORT (GPIO_PORT_A) + #define ETH_SMI_MDIO_PIN (GPIO_PIN_02) + #define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + + #define ETH_SMI_MDC_PORT (GPIO_PORT_C) + #define ETH_SMI_MDC_PIN (GPIO_PIN_01) + #define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_TX_EN_PORT (GPIO_PORT_G) + #define ETH_RMII_TX_EN_PIN (GPIO_PIN_11) + #define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_TXD0_PORT (GPIO_PORT_G) + #define ETH_RMII_TXD0_PIN (GPIO_PIN_13) + #define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_TXD1_PORT (GPIO_PORT_G) + #define ETH_RMII_TXD1_PIN (GPIO_PIN_14) + #define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A) + #define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01) + #define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A) + #define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07) + #define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_RXD0_PORT (GPIO_PORT_C) + #define ETH_RMII_RXD0_PIN (GPIO_PIN_04) + #define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_RXD1_PORT (GPIO_PORT_C) + #define ETH_RMII_RXD1_PIN (GPIO_PIN_05) + #define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11) +#endif + +/************************ NAND port **********************/ +#if defined(BSP_USING_NAND) + #define NAND_CE_PORT (GPIO_PORT_B) /* PB06 - EXMC_CE1 */ + #define NAND_CE_PIN (GPIO_PIN_06) + #define NAND_CE_FUNC (GPIO_FUNC_12) + + #define NAND_RE_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ + #define NAND_RE_PIN (GPIO_PIN_11) + #define NAND_RE_FUNC (GPIO_FUNC_12) + + #define NAND_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ + #define NAND_WE_PIN (GPIO_PIN_00) + #define NAND_WE_FUNC (GPIO_FUNC_12) + + #define NAND_CLE_PORT (GPIO_PORT_I) /* PI12 - EXMC_CLE */ + #define NAND_CLE_PIN (GPIO_PIN_12) + #define NAND_CLE_FUNC (GPIO_FUNC_12) + + #define NAND_ALE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ + #define NAND_ALE_PIN (GPIO_PIN_03) + #define NAND_ALE_FUNC (GPIO_FUNC_12) + + #define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ + #define NAND_WP_PIN (GPIO_PIN_15) + #define NAND_WP_FUNC (GPIO_FUNC_12) + + #define NAND_RB_PORT (GPIO_PORT_G) /* PG07 - EXMC_RB1 */ + #define NAND_RB_PIN (GPIO_PIN_07) + #define NAND_RB_FUNC (GPIO_FUNC_12) + + #define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ + #define NAND_DATA0_PIN (GPIO_PIN_14) + #define NAND_DATA0_FUNC (GPIO_FUNC_12) + #define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ + #define NAND_DATA1_PIN (GPIO_PIN_15) + #define NAND_DATA1_FUNC (GPIO_FUNC_12) + #define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */ + #define NAND_DATA2_PIN (GPIO_PIN_00) + #define NAND_DATA2_FUNC (GPIO_FUNC_12) + #define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */ + #define NAND_DATA3_PIN (GPIO_PIN_01) + #define NAND_DATA3_FUNC (GPIO_FUNC_12) + #define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */ + #define NAND_DATA4_PIN (GPIO_PIN_07) + #define NAND_DATA4_FUNC (GPIO_FUNC_12) + #define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */ + #define NAND_DATA5_PIN (GPIO_PIN_08) + #define NAND_DATA5_FUNC (GPIO_FUNC_12) + #define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */ + #define NAND_DATA6_PIN (GPIO_PIN_09) + #define NAND_DATA6_FUNC (GPIO_FUNC_12) + #define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ + #define NAND_DATA7_PIN (GPIO_PIN_10) + #define NAND_DATA7_FUNC (GPIO_FUNC_12) +#endif + +/************************ SDIOC port **********************/ +#if defined(BSP_USING_SDIO1) + #define SDIOC1_CK_PORT (GPIO_PORT_C) + #define SDIOC1_CK_PIN (GPIO_PIN_12) + #define SDIOC1_CK_FUNC (GPIO_FUNC_9) + + #define SDIOC1_CMD_PORT (GPIO_PORT_D) + #define SDIOC1_CMD_PIN (GPIO_PIN_02) + #define SDIOC1_CMD_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D0_PORT (GPIO_PORT_B) + #define SDIOC1_D0_PIN (GPIO_PIN_07) + #define SDIOC1_D0_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D1_PORT (GPIO_PORT_A) + #define SDIOC1_D1_PIN (GPIO_PIN_08) + #define SDIOC1_D1_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D2_PORT (GPIO_PORT_C) + #define SDIOC1_D2_PIN (GPIO_PIN_10) + #define SDIOC1_D2_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D3_PORT (GPIO_PORT_B) + #define SDIOC1_D3_PIN (GPIO_PIN_05) + #define SDIOC1_D3_FUNC (GPIO_FUNC_9) +#endif + +/************************ SDRAM port **********************/ +#if defined(BSP_USING_SDRAM) + #define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ + #define SDRAM_CKE_PIN (GPIO_PIN_03) + #define SDRAM_CKE_FUNC (GPIO_FUNC_12) + + #define SDRAM_CLK_PORT (GPIO_PORT_G) /* PD03 - EXMC_CLK */ + #define SDRAM_CLK_PIN (GPIO_PIN_08) + #define SDRAM_CLK_FUNC (GPIO_FUNC_12) + + #define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */ + #define SDRAM_DQM0_PIN (GPIO_PIN_00) + #define SDRAM_DQM0_FUNC (GPIO_FUNC_12) + #define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */ + #define SDRAM_DQM1_PIN (GPIO_PIN_01) + #define SDRAM_DQM1_FUNC (GPIO_FUNC_12) + + #define SDRAM_BA0_PORT (GPIO_PORT_G) /* PG04 - EXMC_ADD16 */ + #define SDRAM_BA0_PIN (GPIO_PIN_04) + #define SDRAM_BA0_FUNC (GPIO_FUNC_13) + #define SDRAM_BA1_PORT (GPIO_PORT_G) /* PG05 - EXMC_ADD17 */ + #define SDRAM_BA1_PIN (GPIO_PIN_05) + #define SDRAM_BA1_FUNC (GPIO_FUNC_13) + + #define SDRAM_CS_PORT (GPIO_PORT_C) /* PC02 - EXMC_CE0 */ + #define SDRAM_CS_PIN (GPIO_PIN_02) + #define SDRAM_CS_FUNC (GPIO_FUNC_12) + + #define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ + #define SDRAM_RAS_PIN (GPIO_PIN_11) + #define SDRAM_RAS_FUNC (GPIO_FUNC_12) + + #define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ + #define SDRAM_CAS_PIN (GPIO_PIN_15) + #define SDRAM_CAS_FUNC (GPIO_FUNC_12) + + #define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ + #define SDRAM_WE_PIN (GPIO_PIN_00) + #define SDRAM_WE_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */ + #define SDRAM_ADD0_PIN (GPIO_PIN_00) + #define SDRAM_ADD0_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */ + #define SDRAM_ADD1_PIN (GPIO_PIN_01) + #define SDRAM_ADD1_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */ + #define SDRAM_ADD2_PIN (GPIO_PIN_02) + #define SDRAM_ADD2_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */ + #define SDRAM_ADD3_PIN (GPIO_PIN_03) + #define SDRAM_ADD3_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */ + #define SDRAM_ADD4_PIN (GPIO_PIN_04) + #define SDRAM_ADD4_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */ + #define SDRAM_ADD5_PIN (GPIO_PIN_05) + #define SDRAM_ADD5_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */ + #define SDRAM_ADD6_PIN (GPIO_PIN_12) + #define SDRAM_ADD6_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */ + #define SDRAM_ADD7_PIN (GPIO_PIN_13) + #define SDRAM_ADD7_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */ + #define SDRAM_ADD8_PIN (GPIO_PIN_14) + #define SDRAM_ADD8_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */ + #define SDRAM_ADD9_PIN (GPIO_PIN_15) + #define SDRAM_ADD9_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */ + #define SDRAM_ADD10_PIN (GPIO_PIN_00) + #define SDRAM_ADD10_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */ + #define SDRAM_ADD11_PIN (GPIO_PIN_01) + #define SDRAM_ADD11_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD12_PORT (GPIO_PORT_G) /* PG02 - EXMC_ADD12 */ + #define SDRAM_ADD12_PIN (GPIO_PIN_02) + #define SDRAM_ADD12_FUNC (GPIO_FUNC_12) + + #define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ + #define SDRAM_DATA0_PIN (GPIO_PIN_14) + #define SDRAM_DATA0_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ + #define SDRAM_DATA1_PIN (GPIO_PIN_15) + #define SDRAM_DATA1_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */ + #define SDRAM_DATA2_PIN (GPIO_PIN_00) + #define SDRAM_DATA2_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */ + #define SDRAM_DATA3_PIN (GPIO_PIN_01) + #define SDRAM_DATA3_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */ + #define SDRAM_DATA4_PIN (GPIO_PIN_07) + #define SDRAM_DATA4_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */ + #define SDRAM_DATA5_PIN (GPIO_PIN_08) + #define SDRAM_DATA5_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */ + #define SDRAM_DATA6_PIN (GPIO_PIN_09) + #define SDRAM_DATA6_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ + #define SDRAM_DATA7_PIN (GPIO_PIN_10) + #define SDRAM_DATA7_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */ + #define SDRAM_DATA8_PIN (GPIO_PIN_11) + #define SDRAM_DATA8_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */ + #define SDRAM_DATA9_PIN (GPIO_PIN_12) + #define SDRAM_DATA9_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */ + #define SDRAM_DATA10_PIN (GPIO_PIN_13) + #define SDRAM_DATA10_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */ + #define SDRAM_DATA11_PIN (GPIO_PIN_14) + #define SDRAM_DATA11_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */ + #define SDRAM_DATA12_PIN (GPIO_PIN_15) + #define SDRAM_DATA12_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */ + #define SDRAM_DATA13_PIN (GPIO_PIN_08) + #define SDRAM_DATA13_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */ + #define SDRAM_DATA14_PIN (GPIO_PIN_09) + #define SDRAM_DATA14_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */ + #define SDRAM_DATA15_PIN (GPIO_PIN_10) + #define SDRAM_DATA15_FUNC (GPIO_FUNC_12) +#endif + +/************************ RTC/PM *****************************/ +#if defined(BSP_USING_RTC) || defined(RT_USING_PM) + #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + #define XTAL32_PORT (GPIO_PORT_C) + #define XTAL32_IN_PIN (GPIO_PIN_15) + #define XTAL32_OUT_PIN (GPIO_PIN_14) + #endif +#endif + +#if defined(RT_USING_PWM) + /*********** PWM_TMRA configure *********/ + #if defined(BSP_USING_PWM_TMRA_1) + #if defined(BSP_USING_PWM_TMRA_1_CH1) + #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) + #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH2) + #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) + #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH3) + #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) + #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH4) + #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) + #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) + #endif + #endif + + /*********** PWM_TMR4 configure *********/ + #if defined(BSP_USING_PWM_TMR4_1) + #if defined(BSP_USING_PWM_TMR4_1_OUH) + #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) + #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OUL) + #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) + #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OVH) + #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) + #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OVL) + #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) + #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OWH) + #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) + #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OWL) + #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) + #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) + #endif + #endif + + /*********** PWM_TMR6 configure *********/ + #if defined(BSP_USING_PWM_TMR6_1) + #if defined(BSP_USING_PWM_TMR6_1_A) + #define PWM_TMR6_1_A_PORT (GPIO_PORT_F) + #define PWM_TMR6_1_A_PIN (GPIO_PIN_13) + #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) + #endif + #if defined(BSP_USING_PWM_TMR6_1_B) + #define PWM_TMR6_1_B_PORT (GPIO_PORT_F) + #define PWM_TMR6_1_B_PIN (GPIO_PIN_14) + #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) + #endif + #endif + +#endif + +#if defined(BSP_USING_INPUT_CAPTURE) + #define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3) + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) + #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A) + #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08) + #endif + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) + #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B) + #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02) + #endif + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) + #define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) + #define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00) + #endif +#endif + +#if defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(BSP_USING_USBHS) || \ + defined(BSP_USING_USBHS_PHY_EMBED) || defined(BSP_USING_USBHS_PHY_EXTERN) || \ + defined(RT_USING_USB) + #error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" + #endif +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) + /* USBFS Core*/ + #define USBF_DP_PORT (GPIO_PORT_A) + #define USBF_DP_PIN (GPIO_PIN_12) + #define USBF_DM_PORT (GPIO_PORT_A) + #define USBF_DM_PIN (GPIO_PIN_11) + #define USBF_VBUS_PORT (GPIO_PORT_A) + #define USBF_VBUS_PIN (GPIO_PIN_09) + #define USBF_VBUS_FUNC (GPIO_FUNC_10) + #define USBF_DRVVBUS_PORT (GPIO_PORT_C) + #define USBF_DRVVBUS_PIN (GPIO_PIN_09) + #define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) + #endif + #if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) + /* USBHS Core*/ + #if defined(BSP_USING_USBHS_PHY_EMBED) || (defined(RT_USING_CHERRYUSB) && !defined(CONFIG_USB_HS)) + #define USBH_DP_PORT (GPIO_PORT_B) + #define USBH_DP_PIN (GPIO_PIN_15) + #define USBH_DP_FUNC (GPIO_FUNC_10) + #define USBH_DM_PORT (GPIO_PORT_B) + #define USBH_DM_PIN (GPIO_PIN_14) + #define USBH_DM_FUNC (GPIO_FUNC_10) + #define USBH_VBUS_PORT (GPIO_PORT_B) + #define USBH_VBUS_PIN (GPIO_PIN_13) + #define USBH_VBUS_FUNC (GPIO_FUNC_12) + #define USBH_DRVVBUS_PORT (GPIO_PORT_B) + #define USBH_DRVVBUS_PIN (GPIO_PIN_11) + #define USBH_DRVVBUS_FUNC (GPIO_FUNC_10) + #else + /* USBHS Core, external PHY */ + #define USBH_ULPI_CLK_PORT (GPIO_PORT_E) + #define USBH_ULPI_CLK_PIN (GPIO_PIN_12) + #define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_DIR_PORT (GPIO_PORT_C) + #define USBH_ULPI_DIR_PIN (GPIO_PIN_02) + #define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_NXT_PORT (GPIO_PORT_C) + #define USBH_ULPI_NXT_PIN (GPIO_PIN_03) + #define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_STP_PORT (GPIO_PORT_C) + #define USBH_ULPI_STP_PIN (GPIO_PIN_00) + #define USBH_ULPI_STP_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D0_PORT (GPIO_PORT_E) + #define USBH_ULPI_D0_PIN (GPIO_PIN_13) + #define USBH_ULPI_D0_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D1_PORT (GPIO_PORT_E) + #define USBH_ULPI_D1_PIN (GPIO_PIN_14) + #define USBH_ULPI_D1_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D2_PORT (GPIO_PORT_E) + #define USBH_ULPI_D2_PIN (GPIO_PIN_15) + #define USBH_ULPI_D2_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D3_PORT (GPIO_PORT_B) + #define USBH_ULPI_D3_PIN (GPIO_PIN_10) + #define USBH_ULPI_D3_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D4_PORT (GPIO_PORT_B) + #define USBH_ULPI_D4_PIN (GPIO_PIN_11) + #define USBH_ULPI_D4_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D5_PORT (GPIO_PORT_B) + #define USBH_ULPI_D5_PIN (GPIO_PIN_12) + #define USBH_ULPI_D5_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D6_PORT (GPIO_PORT_B) + #define USBH_ULPI_D6_PIN (GPIO_PIN_13) + #define USBH_ULPI_D6_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D7_PORT (GPIO_PORT_E) + #define USBH_ULPI_D7_PIN (GPIO_PIN_11) + #define USBH_ULPI_D7_FUNC (GPIO_FUNC_10) + /* 3300 reset */ + #define USB_3300_RESET_PORT (EIO_PORT1) + #define USB_3300_RESET_PIN (EIO_USB3300_RST) + #endif + #endif +#endif + +#if defined(BSP_USING_QSPI) + #ifndef BSP_QSPI_USING_SOFT_CS + /* QSSN */ + #define QSPI_FLASH_CS_PORT (GPIO_PORT_C) + #define QSPI_FLASH_CS_PIN (GPIO_PIN_07) + #define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18) + #endif + /* QSCK */ + #define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) + #define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) + #define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18) + /* QSIO0 */ + #define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) + #define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18) + /* QSIO1 */ + #define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO1_PIN (GPIO_PIN_12) + #define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18) + /* QSIO2 */ + #define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) + #define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18) + /* QSIO3 */ + #define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO3_PIN (GPIO_PIN_02) + #define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18) +#endif + +/*********** TMRA_PULSE_ENCODER configure *********/ +#if defined(RT_USING_PULSE_ENCODER) + #if defined(BSP_USING_TMRA_PULSE_ENCODER) + #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) + #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) + #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) + #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) + #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + #endif /* BSP_USING_TMRA_PULSE_ENCODER */ + + #if defined(BSP_USING_TMR6_PULSE_ENCODER) + #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) + #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) + #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) + #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) + #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) + #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) + #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#endif /* RT_USING_PULSE_ENCODER */ + +#endif + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/adc_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/adc_config.h new file mode 100644 index 00000000000..e3b8c4356da --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/adc_config.h @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_INIT_PARAMS +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC1_INIT_PARAMS */ + +#if defined (BSP_ADC1_USING_DMA) +#ifndef ADC1_EOCA_DMA_CONFIG +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC1_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC1_USING_DMA */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_INIT_PARAMS +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC2_INIT_PARAMS */ + +#if defined (BSP_ADC2_USING_DMA) +#ifndef ADC2_EOCA_DMA_CONFIG +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC2_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC2_USING_DMA */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_INIT_PARAMS +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC3_INIT_PARAMS */ +#if defined (BSP_ADC3_USING_DMA) +#ifndef ADC3_EOCA_DMA_CONFIG +#define ADC3_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC3_EOCA_DMA_INSTANCE, \ + .channel = ADC3_EOCA_DMA_CHANNEL, \ + .clock = ADC3_EOCA_DMA_CLOCK, \ + .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC3_EOCA, \ + .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC3_EOCA_DMA_IRQn, \ + .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ + .int_src = ADC3_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC3_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC3_USING_DMA */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/can_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/can_config.h new file mode 100644 index 00000000000..a6911f30655 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/can_config.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __CAN_CONFIG_H__ +#define __CAN_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_CAN1 +#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN1_NAME ("can1") +#ifndef CAN1_INIT_PARAMS +#define CAN1_INIT_PARAMS \ + { \ + .name = CAN1_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN1_INIT_PARAMS */ +#endif /* BSP_USING_CAN1 */ + +#ifdef BSP_USING_CAN2 +#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN2_NAME ("can2") +#ifndef CAN2_INIT_PARAMS +#define CAN2_INIT_PARAMS \ + { \ + .name = CAN2_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN2_INIT_PARAMS */ +#endif /* BSP_USING_CAN2 */ + +/* Bit time config + Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW. + + Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2)) + TQ = u32Prescaler / CANClock. + Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ. + + The following bit time configures are based on CAN Clock 40M +*/ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 20, \ + .u32TimeSeg2 = 5, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 16, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 100, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 200, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/dac_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/dac_config.h new file mode 100644 index 00000000000..926a5122a92 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/dac_config.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __DAC_CONFIG_H__ +#define __DAC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_DAC1 +#ifndef DAC1_INIT_PARAMS +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + } +#endif /* DAC1_INIT_PARAMS */ +#endif /* BSP_USING_DAC1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/dma_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/dma_config.h new file mode 100644 index 00000000000..0b2e7889acf --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/dma_config.h @@ -0,0 +1,369 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMA1 ch0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE) +#define SDIO1_RX_DMA_INSTANCE CM_DMA1 +#define SDIO1_RX_DMA_CHANNEL DMA_CH0 +#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#endif + +/* DMA1 ch1 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE) +#define SDIO1_TX_DMA_INSTANCE CM_DMA1 +#define SDIO1_TX_DMA_CHANNEL DMA_CH1 +#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#endif + +/* DMA1 ch2 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE) +#define SDIO2_RX_DMA_INSTANCE CM_DMA1 +#define SDIO2_RX_DMA_CHANNEL DMA_CH2 +#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#endif + +/* DMA1 ch3 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE) +#define SDIO2_TX_DMA_INSTANCE CM_DMA1 +#define SDIO2_TX_DMA_CHANNEL DMA_CH3 +#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE) +#define QSPI_DMA_INSTANCE CM_DMA1 +#define QSPI_DMA_CHANNEL DMA_CH3 +#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 +#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) +#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 +#endif + +/* DMA1 ch4 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH4 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) +#define I2C3_TX_DMA_INSTANCE CM_DMA1 +#define I2C3_TX_DMA_CHANNEL DMA_CH4 +#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 +#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) +#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 +#endif + +/* DMA1 ch5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH5 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) +#define I2C3_RX_DMA_INSTANCE CM_DMA1 +#define I2C3_RX_DMA_CHANNEL DMA_CH5 +#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 +#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) +#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 +#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 +#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 +#endif + +/* DMA1 ch6 */ +#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_RX_DMA_INSTANCE CM_DMA1 +#define SPI4_RX_DMA_CHANNEL DMA_CH6 +#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 +#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#endif + +/* DMA1 ch7 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_TX_DMA_INSTANCE CM_DMA1 +#define SPI4_TX_DMA_CHANNEL DMA_CH7 +#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 +#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#endif + +/* DMA1 ch8 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_TX_DMA_INSTANCE CM_DMA1 +#define SPI5_TX_DMA_CHANNEL DMA_CH8 +#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8 +#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8 +#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM +#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO +#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8 +#endif + +/* DMA1 ch9 */ +#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE) +#define SPI6_TX_DMA_INSTANCE CM_DMA1 +#define SPI6_TX_DMA_CHANNEL DMA_CH9 +#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9 +#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9 +#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM +#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO +#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9 +#endif + +/* DMA2 ch0 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#endif + +/* DMA2 ch1 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#endif + +/* DMA2 ch2 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#endif + +/* DMA2 ch3 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#endif + +/* DMA2 ch4 */ +#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) +#define UART6_RX_DMA_INSTANCE CM_DMA2 +#define UART6_RX_DMA_CHANNEL DMA_CH4 +#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#endif + +/* DMA2 ch5 */ +#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) +#define UART6_TX_DMA_INSTANCE CM_DMA2 +#define UART6_TX_DMA_CHANNEL DMA_CH5 +#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#endif + +/* DMA2 ch6 */ +#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) +#define UART7_RX_DMA_INSTANCE CM_DMA2 +#define UART7_RX_DMA_CHANNEL DMA_CH6 +#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 +#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM +#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO +#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 +#endif + +/* DMA2 ch7 */ +#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) +#define UART7_TX_DMA_INSTANCE CM_DMA2 +#define UART7_TX_DMA_CHANNEL DMA_CH7 +#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 +#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM +#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO +#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/eth_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/eth_config.h new file mode 100644 index 00000000000..f63a27cc8b5 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/eth_config.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __ETH_CONFIG_H__ +#define __ETH_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_ETH) + +#ifndef ETH_IRQ_CONFIG +#define ETH_IRQ_CONFIG \ + { \ + .irq_num = BSP_ETH_IRQ_NUM, \ + .irq_prio = BSP_ETH_IRQ_PRIO, \ + .int_src = INT_SRC_ETH_GLB_INT, \ + } +#endif /* ETH_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __ETH_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/gpio_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/gpio_config.h new file mode 100644 index 00000000000..cdbcb855f3b --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/gpio_config.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __GPIO_CONFIG_H__ +#define __GPIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(RT_USING_PIN) + +#ifndef EXTINT0_IRQ_CONFIG +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT1_IRQ_CONFIG +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT2_IRQ_CONFIG +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ + } +#endif /* EXTINT2_IRQ_CONFIG */ + +#ifndef EXTINT3_IRQ_CONFIG +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ + } +#endif /* EXTINT3_IRQ_CONFIG */ + +#ifndef EXTINT4_IRQ_CONFIG +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ + } +#endif /* EXTINT4_IRQ_CONFIG */ + +#ifndef EXTINT5_IRQ_CONFIG +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ + } +#endif /* EXTINT5_IRQ_CONFIG */ + +#ifndef EXTINT6_IRQ_CONFIG +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ + } +#endif /* EXTINT6_IRQ_CONFIG */ + +#ifndef EXTINT7_IRQ_CONFIG +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ + } +#endif /* EXTINT7_IRQ_CONFIG */ + +#ifndef EXTINT8_IRQ_CONFIG +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ + } +#endif /* EXTINT8_IRQ_CONFIG */ + +#ifndef EXTINT9_IRQ_CONFIG +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ + } +#endif /* EXTINT9_IRQ_CONFIG */ + +#ifndef EXTINT10_IRQ_CONFIG +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ + } +#endif /* EXTINT10_IRQ_CONFIG */ + +#ifndef EXTINT11_IRQ_CONFIG +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ + } +#endif /* EXTINT11_IRQ_CONFIG */ + +#ifndef EXTINT12_IRQ_CONFIG +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ + } +#endif /* EXTINT12_IRQ_CONFIG */ + +#ifndef EXTINT13_IRQ_CONFIG +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ + } +#endif /* EXTINT13_IRQ_CONFIG */ + +#ifndef EXTINT14_IRQ_CONFIG +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ + } +#endif /* EXTINT14_IRQ_CONFIG */ + +#ifndef EXTINT15_IRQ_CONFIG +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ + } +#endif /* EXTINT15_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/i2c_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/i2c_config.h new file mode 100644 index 00000000000..0a063244ae5 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/i2c_config.h @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_I2C1) +#ifndef I2C1_CONFIG +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C1_CONFIG */ +#endif + +#if defined(BSP_I2C1_USING_DMA) +#ifndef I2C1_TX_DMA_CONFIG +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_TX_DMA_CONFIG */ + +#ifndef I2C1_RX_DMA_CONFIG +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_USING_DMA */ + +#if defined(BSP_USING_I2C2) +#ifndef I2C2_CONFIG +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C2_CONFIG */ + +#if defined(BSP_I2C2_USING_DMA) +#ifndef I2C2_TX_DMA_CONFIG +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_TX_DMA_CONFIG */ + +#ifndef I2C2_RX_DMA_CONFIG +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C3) +#ifndef I2C3_CONFIG +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C3_CONFIG */ + +#if defined(BSP_I2C3_USING_DMA) +#ifndef I2C3_TX_DMA_CONFIG +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_TX_DMA_CONFIG */ + +#ifndef I2C3_RX_DMA_CONFIG +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_USING_DMA */ +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/irq_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/irq_config.h new file mode 100644 index 00000000000..fe66243abab --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/irq_config.h @@ -0,0 +1,426 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __IRQ_CONFIG_H__ +#define __IRQ_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_EXTINT0_IRQ_NUM INT022_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM INT023_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM INT024_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM INT025_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM INT026_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM INT027_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM INT028_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM INT029_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM INT030_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM INT031_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM INT032_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM INT033_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM INT034_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM INT035_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM INT036_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM INT037_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA1 ch0 */ +#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch1 */ +#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch2 */ +#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch3 */ +#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch4 */ +#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch5 */ +#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch6 */ +#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn +#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch7 */ +#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn +#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch8 */ +#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn +#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch9 */ +#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn +#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA2 ch0 */ +#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch1 */ +#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch2 */ +#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch3 */ +#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch4 */ +#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch5 */ +#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch6 */ +#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn +#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch7 */ +#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn +#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_USING_ETH) +#define BSP_ETH_IRQ_NUM INT104_IRQn +#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_UART1) +#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn +#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RX_IRQ_NUM INT089_IRQn +#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_IRQ_NUM INT088_IRQn +#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART1_RX_USING_DMA) +#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn +#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn +#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RX_IRQ_NUM INT091_IRQn +#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_IRQ_NUM INT090_IRQn +#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART2_RX_USING_DMA) +#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn +#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#elif defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) +#define BSP_SPI1_ERR_IRQ_NUM INT007_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI2_ERR_IRQ_NUM INT011_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn +#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RX_IRQ_NUM INT095_IRQn +#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_IRQ_NUM INT094_IRQn +#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn +#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RX_IRQ_NUM INT097_IRQn +#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_IRQ_NUM INT096_IRQn +#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn +#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RX_IRQ_NUM INT101_IRQn +#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_IRQ_NUM INT100_IRQn +#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn +#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RX_IRQ_NUM INT103_IRQn +#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_IRQ_NUM INT102_IRQn +#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART6_RX_USING_DMA) +#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn +#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn +#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RX_IRQ_NUM INT107_IRQn +#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_IRQ_NUM INT106_IRQn +#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART7_RX_USING_DMA) +#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn +#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_SPI3) +#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI4) +#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn +#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI5) +#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn +#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI6) +#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn +#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_UART10) +#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn +#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RX_IRQ_NUM INT114_IRQn +#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_TX_IRQ_NUM INT113_IRQn +#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART10 */ + +#if defined(BSP_USING_CAN1) +#define BSP_CAN1_IRQ_NUM INT092_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_CAN1 */ + +#if defined(BSP_USING_CAN2) +#define BSP_CAN2_IRQ_NUM INT093_IRQn +#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_CAN2 */ + +#if defined(BSP_USING_SDIO1) +#define BSP_SDIO1_IRQ_NUM INT004_IRQn +#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_SDIO1 */ + +#if defined(BSP_USING_SDIO2) +#define BSP_SDIO2_IRQ_NUM INT005_IRQn +#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_SDIO2 */ + +#if defined(RT_USING_ALARM) +#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* RT_USING_ALARM */ + + +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) +#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn +#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_USBFS */ + +#if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) +#define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn +#define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_USBHS */ + +#if defined (BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_QSPI */ + +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_2) +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_3) +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_4) +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_5) +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_6) +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_7) +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_7 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_8) +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_8 */ + +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_2) +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_3) +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */ + +#if defined(BSP_USING_TMRA_1) +#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_1 */ +#if defined(BSP_USING_TMRA_2) +#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_2 */ +#if defined(BSP_USING_TMRA_3) +#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_3 */ +#if defined(BSP_USING_TMRA_4) +#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_4 */ +#if defined(BSP_USING_TMRA_5) +#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_5 */ +#if defined(BSP_USING_TMRA_6) +#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn +#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_6 */ +#if defined(BSP_USING_TMRA_7) +#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn +#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_7 */ +#if defined(BSP_USING_TMRA_8) +#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn +#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_8 */ + +#if defined(BSP_USING_INPUT_CAPTURE) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/pm_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pm_config.h new file mode 100644 index 00000000000..6c4a7bcb052 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pm_config.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + * 2026-06-24 CDT delete PM_TICKLESS_TIMER_ENABLE_MASK for unsupport pm tickless timer + */ + +#ifndef __PM_CONFIG_H__ +#define __PM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PM +extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); + +/** + * @brief run mode config @ref pm_run_mode_config structure + */ +#ifndef PM_RUN_MODE_CFG +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ + } +#endif /* PM_RUN_MODE_CFG */ + +/** + * @brief sleep idle config @ref pm_sleep_mode_idle_config structure + */ +#ifndef PM_SLEEP_IDLE_CFG +#define PM_SLEEP_IDLE_CFG \ +{ \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ +} +#endif /*PM_SLEEP_IDLE_CFG*/ + +/** + * @brief sleep deep config @ref pm_sleep_mode_deep_config structure + */ +#ifndef PM_SLEEP_DEEP_CFG +#define PM_SLEEP_DEEP_CFG \ +{ \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ +} +#endif /*PM_SLEEP_DEEP_CFG*/ + +/** + * @brief sleep standby config @ref pm_sleep_mode_standby_config structure + */ +#ifndef PM_SLEEP_STANDBY_CFG +#define PM_SLEEP_STANDBY_CFG \ +{ \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ +} +#endif /*PM_SLEEP_STANDBY_CFG*/ + +/** + * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure + */ +#ifndef PM_SLEEP_SHUTDOWN_CFG +#define PM_SLEEP_SHUTDOWN_CFG \ +{ \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ +} +#endif /*PM_SLEEP_SHUTDOWN_CFG*/ + +#endif /* BSP_USING_PM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PM_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pulse_encoder_config.h new file mode 100644 index 00000000000..9802f480ac7 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pulse_encoder_config.h @@ -0,0 +1,310 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __PULSE_ENCODER_CONFIG_H__ +#define __PULSE_ENCODER_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_PULSE_ENCODER) + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_1 +#ifndef PULSE_ENCODER_TMRA_1_CONFIG +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ + } +#endif /* PULSE_ENCODER_TMRA_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_2 +#ifndef PULSE_ENCODER_TMRA_2_CONFIG +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ + } +#endif /* PULSE_ENCODER_TMRA_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_3 +#ifndef PULSE_ENCODER_TMRA_3_CONFIG +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ + } +#endif /* PULSE_ENCODER_TMRA_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_4 +#ifndef PULSE_ENCODER_TMRA_4_CONFIG +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ + } +#endif /* PULSE_ENCODER_TMRA_4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_5 +#ifndef PULSE_ENCODER_TMRA_5_CONFIG +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ + } +#endif /* PULSE_ENCODER_TMRA_5_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_6 +#ifndef PULSE_ENCODER_TMRA_6_CONFIG +#define PULSE_ENCODER_TMRA_6_CONFIG \ + { \ + .tmr_handler = CM_TMRA_6, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a6" \ + } +#endif /* PULSE_ENCODER_TMRA_6_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_7 +#ifndef PULSE_ENCODER_TMRA_7_CONFIG +#define PULSE_ENCODER_TMRA_7_CONFIG \ + { \ + .tmr_handler = CM_TMRA_7, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_7, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a7" \ + } +#endif /* PULSE_ENCODER_TMRA_7_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_8 +#ifndef PULSE_ENCODER_TMRA_8_CONFIG +#define PULSE_ENCODER_TMRA_8_CONFIG \ + { \ + .tmr_handler = CM_TMRA_8, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_8, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a8" \ + } +#endif /* PULSE_ENCODER_TMRA_8_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_1 +#ifndef PULSE_ENCODER_TMR6_1_CONFIG +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ + } +#endif /* PULSE_ENCODER_TMR6_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_2 +#ifndef PULSE_ENCODER_TMR6_2_CONFIG +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ + } +#endif /* PULSE_ENCODER_TMR6_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_3 +#ifndef PULSE_ENCODER_TMR6_3_CONFIG +#define PULSE_ENCODER_TMR6_3_CONFIG \ + { \ + .tmr_handler = CM_TMR6_3, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_63" \ + } +#endif /* PULSE_ENCODER_TMR6_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */ + +#endif /* RT_USING_PULSE_ENCODER */ + +#endif /* __PULSE_ENCODER_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pwm_tmr_config.h new file mode 100644 index 00000000000..b25433f420f --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pwm_tmr_config.h @@ -0,0 +1,521 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __PWM_TMR_CONFIG_H__ +#define __PWM_TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PWM_TMRA + +#ifdef BSP_USING_PWM_TMRA_1 +#ifndef PWM_TMRA_1_CONFIG +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_1_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_1 */ + +#ifdef BSP_USING_PWM_TMRA_2 +#ifndef PWM_TMRA_2_CONFIG +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_2_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_2 */ + +#ifdef BSP_USING_PWM_TMRA_3 +#ifndef PWM_TMRA_3_CONFIG +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_3_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_3 */ + +#ifdef BSP_USING_PWM_TMRA_4 +#ifndef PWM_TMRA_4_CONFIG +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_4_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_4 */ + +#ifdef BSP_USING_PWM_TMRA_5 +#ifndef PWM_TMRA_5_CONFIG +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_5_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_5 */ + +#ifdef BSP_USING_PWM_TMRA_6 +#ifndef PWM_TMRA_6_CONFIG +#define PWM_TMRA_6_CONFIG \ + { \ + .name = "pwm_a6", \ + .instance = CM_TMRA_6, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_6_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_6 */ + +#ifdef BSP_USING_PWM_TMRA_7 +#ifndef PWM_TMRA_7_CONFIG +#define PWM_TMRA_7_CONFIG \ + { \ + .name = "pwm_a7", \ + .instance = CM_TMRA_7, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_7_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_7 */ + +#ifdef BSP_USING_PWM_TMRA_8 +#ifndef PWM_TMRA_8_CONFIG +#define PWM_TMRA_8_CONFIG \ + { \ + .name = "pwm_a8", \ + .instance = CM_TMRA_8, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_8_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_8 */ + +#endif /* BSP_USING_PWM_TMRA */ + +#ifdef BSP_USING_PWM_TMR4 + +#ifdef BSP_USING_PWM_TMR4_1 +#ifndef PWM_TMR4_1_CONFIG +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_1 */ + +#ifdef BSP_USING_PWM_TMR4_2 +#ifndef PWM_TMR4_2_CONFIG +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_2 */ + +#ifdef BSP_USING_PWM_TMR4_3 +#ifndef PWM_TMR4_3_CONFIG +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_3 */ + +#endif /* BSP_USING_PWM_TMR4 */ + +#ifdef BSP_USING_PWM_TMR6 + +#ifdef BSP_USING_PWM_TMR6_1 +#ifndef PWM_TMR6_1_CONFIG +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_1 */ +#ifdef BSP_USING_PWM_TMR6_2 +#ifndef PWM_TMR6_2_CONFIG +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t62", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_2 */ +#ifdef BSP_USING_PWM_TMR6_3 +#ifndef PWM_TMR6_3_CONFIG +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t63", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_3 */ +#endif /* BSP_USING_PWM_TMR6 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_TMRA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/qspi_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/qspi_config.h new file mode 100644 index 00000000000..d2e5d3252fb --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/qspi_config.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ + } +#endif /* QSPI_BUS_CONFIG */ + +#ifndef QSPI_INIT_PARAMS +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ + } +#endif /* QSPI_INIT_PARAMS */ + +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ +#endif /* BSP_USING_SPI1 */ + +#ifdef __cplusplus +} +#endif + +#endif /*__QSPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/sdio_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/sdio_config.h new file mode 100644 index 00000000000..e2e95636a96 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/sdio_config.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_SDIO1) +#ifndef SDIO1_BUS_CONFIG +#define SDIO1_BUS_CONFIG \ + { \ + .name = "sdio1", \ + .instance = CM_SDIOC1, \ + .clock = FCG1_PERIPH_SDIOC1, \ + .irq_config = \ + { \ + .irq_num = BSP_SDIO1_IRQ_NUM, \ + .irq_prio = BSP_SDIO1_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC1_SD, \ + }, \ + .dma_rx = \ + { \ + .Instance = SDIO1_RX_DMA_INSTANCE, \ + .channel = SDIO1_RX_DMA_CHANNEL, \ + .clock = SDIO1_RX_DMA_CLOCK, \ + .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAR, \ + }, \ + .dma_tx = \ + { \ + .Instance = SDIO1_TX_DMA_INSTANCE, \ + .channel = SDIO1_TX_DMA_CHANNEL, \ + .clock = SDIO1_TX_DMA_CLOCK, \ + .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAW, \ + }, \ + } +#endif /* SDIO1_BUS_CONFIG */ +#endif /* BSP_USING_SDIO1 */ + +#if defined(BSP_USING_SDIO2) +#ifndef SDIO2_BUS_CONFIG +#define SDIO2_BUS_CONFIG \ + { \ + .name = "sdio2", \ + .instance = CM_SDIOC2, \ + .clock = FCG1_PERIPH_SDIOC2, \ + .irq_config = \ + { \ + .irq_num = BSP_SDIO2_IRQ_NUM, \ + .irq_prio = BSP_SDIO2_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC2_SD, \ + }, \ + .dma_rx = \ + { \ + .Instance = SDIO2_RX_DMA_INSTANCE, \ + .channel = SDIO2_RX_DMA_CHANNEL, \ + .clock = SDIO2_RX_DMA_CLOCK, \ + .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAR, \ + }, \ + .dma_tx = \ + { \ + .Instance = SDIO2_TX_DMA_INSTANCE, \ + .channel = SDIO2_TX_DMA_CHANNEL, \ + .clock = SDIO2_TX_DMA_CLOCK, \ + .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAW, \ + }, \ + } +#endif /* SDIO2_BUS_CONFIG */ +#endif /* BSP_USING_SDIO2 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/spi_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/spi_config.h new file mode 100644 index 00000000000..3f5a7c9054e --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/spi_config.h @@ -0,0 +1,376 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI4_SPEI, \ + }, \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .flag = SPI4_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .flag = SPI4_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = CM_SPI5, \ + .bus_name = "spi5", \ + .clock = FCG1_PERIPH_SPI5, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI5_SPEI, \ + }, \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .clock = SPI5_TX_DMA_CLOCK, \ + .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPTI, \ + .flag = SPI5_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI5_TX_DMA_IRQn, \ + .irq_prio = SPI5_TX_DMA_INT_PRIO, \ + .int_src = SPI5_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .clock = SPI5_RX_DMA_CLOCK, \ + .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPRI, \ + .flag = SPI5_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI5_RX_DMA_IRQn, \ + .irq_prio = SPI5_RX_DMA_INT_PRIO, \ + .int_src = SPI5_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + +#ifdef BSP_USING_SPI6 +#ifndef SPI6_BUS_CONFIG +#define SPI6_BUS_CONFIG \ + { \ + .Instance = CM_SPI6, \ + .bus_name = "spi6", \ + .clock = FCG1_PERIPH_SPI6, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI6_SPEI, \ + }, \ + } +#endif /* SPI6_BUS_CONFIG */ +#endif /* BSP_USING_SPI6 */ + +#ifdef BSP_SPI6_TX_USING_DMA +#ifndef SPI6_TX_DMA_CONFIG +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .channel = SPI6_TX_DMA_CHANNEL, \ + .clock = SPI6_TX_DMA_CLOCK, \ + .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPTI, \ + .flag = SPI6_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI6_TX_DMA_IRQn, \ + .irq_prio = SPI6_TX_DMA_INT_PRIO, \ + .int_src = SPI6_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_TX_DMA_CONFIG */ +#endif /* BSP_SPI6_TX_USING_DMA */ + +#ifdef BSP_SPI6_RX_USING_DMA +#ifndef SPI6_RX_DMA_CONFIG +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .channel = SPI6_RX_DMA_CHANNEL, \ + .clock = SPI6_RX_DMA_CLOCK, \ + .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPRI, \ + .flag = SPI6_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI6_RX_DMA_IRQn, \ + .irq_prio = SPI6_RX_DMA_INT_PRIO, \ + .int_src = SPI6_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_RX_DMA_CONFIG */ +#endif /* BSP_SPI6_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/timer_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/timer_config.h new file mode 100644 index 00000000000..3cfdbe5d245 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/timer_config.h @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __TMR_CONFIG_H__ +#define __TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_TMRA_1 +#ifndef TMRA_1_CONFIG +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ + } +#endif /* TMRA_1_CONFIG */ +#endif /* BSP_USING_TMRA_1 */ + +#ifdef BSP_USING_TMRA_2 +#ifndef TMRA_2_CONFIG +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ + } +#endif /* TMRA_2_CONFIG */ +#endif /* BSP_USING_TMRA_2 */ + +#ifdef BSP_USING_TMRA_3 +#ifndef TMRA_3_CONFIG +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ + } +#endif /* TMRA_3_CONFIG */ +#endif /* BSP_USING_TMRA_3 */ + +#ifdef BSP_USING_TMRA_4 +#ifndef TMRA_4_CONFIG +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ + } +#endif /* TMRA_4_CONFIG */ +#endif /* BSP_USING_TMRA_4 */ + +#ifdef BSP_USING_TMRA_5 +#ifndef TMRA_5_CONFIG +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ + } +#endif /* TMRA_5_CONFIG */ +#endif /* BSP_USING_TMRA_5 */ + +#ifdef BSP_USING_TMRA_6 +#ifndef TMRA_6_CONFIG +#define TMRA_6_CONFIG \ + { \ + .tmr_handle = CM_TMRA_6, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_6, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_6_OVF, \ + .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ + }, \ + .name = "tmra_6" \ + } +#endif /* TMRA_6_CONFIG */ +#endif /* BSP_USING_TMRA_6 */ + +#ifdef BSP_USING_TMRA_7 +#ifndef TMRA_7_CONFIG +#define TMRA_7_CONFIG \ + { \ + .tmr_handle = CM_TMRA_7, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_7, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_7_OVF, \ + .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ + }, \ + .name = "tmra_7" \ + } +#endif /* TMRA_7_CONFIG */ +#endif /* BSP_USING_TMRA_7 */ + +#ifdef BSP_USING_TMRA_8 +#ifndef TMRA_8_CONFIG +#define TMRA_8_CONFIG \ + { \ + .tmr_handle = CM_TMRA_8, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_8, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_8_OVF, \ + .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ + }, \ + .name = "tmra_8" \ + } +#endif /* TMRA_8_CONFIG */ +#endif /* BSP_USING_TMRA_8 */ +#endif /* __TMR_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/tmr_capture_config.h new file mode 100644 index 00000000000..0eef88c382a --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/tmr_capture_config.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __IC_CONFIG_H__ +#define __IC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#define IC1_NAME "ic1" +#define INPUT_CAPTURE_CFG_TMR6_1 \ +{ \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ +} +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#define IC2_NAME "ic2" +#define INPUT_CAPTURE_CFG_TMR6_2 \ +{ \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ +} +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#define IC3_NAME "ic3" +#define INPUT_CAPTURE_CFG_TMR6_3 \ +{ \ + .name = IC3_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __IC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/uart_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/uart_config.h new file mode 100644 index 00000000000..e7a73e2efb7 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/uart_config.h @@ -0,0 +1,642 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_RX_IRQ_NUM, \ + .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_TX_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TI, \ + }, \ + } +#endif /* UART1_CONFIG */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_RX_CONFIG */ + +#ifndef UART1_RXTO_CONFIG +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RTO, \ + }, \ + } +#endif /* UART1_RXTO_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#endif /* UART1_TX_CPLT_CONFIG */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_RX_IRQ_NUM, \ + .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_TX_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TI, \ + }, \ + } +#endif /* UART2_CONFIG */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_RX_CONFIG */ + +#ifndef UART2_RXTO_CONFIG +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RTO, \ + }, \ + } +#endif /* UART2_RXTO_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#endif /* UART2_TX_CPLT_CONFIG */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_RX_IRQ_NUM, \ + .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_TX_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TI, \ + }, \ + } +#endif /* UART3_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART3_TX_CPLT_CONFIG +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ + } +#endif +#endif /* UART3_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_RX_IRQ_NUM, \ + .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_TX_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TI, \ + }, \ + } +#endif /* UART4_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART4_TX_CPLT_CONFIG +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ + } +#endif +#endif /* UART4_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART5_RX_IRQ_NUM, \ + .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART5_TX_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TI, \ + }, \ + } +#endif /* UART5_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART5_TX_CPLT_CONFIG +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ + } +#endif +#endif /* UART5_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART6_RX_IRQ_NUM, \ + .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART6_TX_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TI, \ + }, \ + } +#endif /* UART6_CONFIG */ + +#if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_DMA_RX_CONFIG +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .channel = UART6_RX_DMA_CHANNEL, \ + .clock = UART6_RX_DMA_CLOCK, \ + .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_RI, \ + .flag = UART6_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART6_RX_DMA_IRQn, \ + .irq_prio = UART6_RX_DMA_INT_PRIO, \ + .int_src = UART6_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_RX_CONFIG */ + +#ifndef UART6_RXTO_CONFIG +#define UART6_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RTO, \ + }, \ + } +#endif /* UART6_RXTO_CONFIG */ +#endif /* BSP_UART6_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif +#endif /* UART6_TX_CPLT_CONFIG */ + +#if defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_DMA_TX_CONFIG +#define UART6_DMA_TX_CONFIG \ + { \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .channel = UART6_TX_DMA_CHANNEL, \ + .clock = UART6_TX_DMA_CLOCK, \ + .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_TI, \ + .flag = UART6_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART6_TX_DMA_IRQn, \ + .irq_prio = UART6_TX_DMA_INT_PRIO, \ + .int_src = UART6_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_TX_CONFIG */ +#endif /* BSP_UART6_TX_USING_DMA */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#ifndef UART7_CONFIG +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = CM_USART7, \ + .clock = FCG3_PERIPH_USART7, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART7_RX_IRQ_NUM, \ + .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART7_TX_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TI, \ + }, \ + } +#endif /* UART7_CONFIG */ + +#if defined(BSP_UART7_RX_USING_DMA) +#ifndef UART7_DMA_RX_CONFIG +#define UART7_DMA_RX_CONFIG \ + { \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .channel = UART7_RX_DMA_CHANNEL, \ + .clock = UART7_RX_DMA_CLOCK, \ + .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_RI, \ + .flag = UART7_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART7_RX_DMA_IRQn, \ + .irq_prio = UART7_RX_DMA_INT_PRIO, \ + .int_src = UART7_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_RX_CONFIG */ + +#ifndef UART7_RXTO_CONFIG +#define UART7_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RTO, \ + }, \ + } +#endif /* UART7_RXTO_CONFIG */ +#endif /* BSP_UART7_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_TX_CPLT_CONFIG +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART7_TX_CPLT_CONFIG +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ + } +#endif +#endif /* UART7_TX_CPLT_CONFIG */ + +#if defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_DMA_TX_CONFIG +#define UART7_DMA_TX_CONFIG \ + { \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .channel = UART7_TX_DMA_CHANNEL, \ + .clock = UART7_TX_DMA_CLOCK, \ + .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART7_TX_DMA_IRQn, \ + .irq_prio = UART7_TX_DMA_INT_PRIO, \ + .int_src = UART7_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_TX_CONFIG */ +#endif /* BSP_UART7_TX_USING_DMA */ +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART10) +#ifndef UART10_CONFIG +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = CM_USART10, \ + .clock = FCG3_PERIPH_USART10, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART10_RX_IRQ_NUM, \ + .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART10_TX_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TI, \ + }, \ + } +#endif /* UART10_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART10_TX_CPLT_CONFIG +#define UART10_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TCI, \ + }, \ + } +#endif +#endif /* UART10_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART10 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_app_conf.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_app_conf.h new file mode 100644 index 00000000000..b7737111327 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_app_conf.h @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __USB_APP_CONF_H__ +#define __USB_APP_CONF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "rtconfig.h" + +/* USB MODE CONFIGURATION */ +/* +USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment +(1) If only defined USB_FS_MODE: + MCU USBFS core work in full speed using internal PHY. +(2) If only defined USB_HS_MODE: + MCU USBHS core work in full speed using internal PHY. +(3) If both defined USB_HS_MODE && USB_HS_EXTERNAL_PHY + MCU USBHS core work in high speed using external PHY. +(4) Other combination: + Not support, forbid!! +*/ + +#if defined(BSP_USING_USBHS) +#define USB_HS_MODE +#endif +#if defined(BSP_USING_USBFS) +#define USB_FS_MODE +#endif +#if !defined(BSP_USING_USBHS) && !defined(BSP_USING_USBFS) +#define USB_FS_MODE +#endif + +#if defined(BSP_USING_USBD) +#define USE_DEVICE_MODE +#endif +#if defined(BSP_USING_USBH) +#define USE_HOST_MODE +#endif +#if !defined(BSP_USING_USBD) && !defined(BSP_USING_USBH) +#define USE_DEVICE_MODE +#endif + +#if defined(USB_HS_MODE) && defined(BSP_USING_USBHS_PHY_EXTERN) +#define USB_HS_EXTERNAL_PHY +#endif + +#ifndef USB_HS_MODE +#ifndef USB_FS_MODE +#error "USB_HS_MODE or USB_FS_MODE should be defined" +#endif +#endif + +#ifndef USE_DEVICE_MODE +#ifndef USE_HOST_MODE +#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" +#endif +#endif + +#if defined(BSP_USING_USBD) +/* USB DEVICE FIFO CONFIGURATION */ +#ifdef USB_FS_MODE +#define RX_FIFO_FS_SIZE (128U) +#define TX0_FIFO_FS_SIZE (32U) +#define TX1_FIFO_FS_SIZE (32U) +#define TX2_FIFO_FS_SIZE (32U) +#define TX3_FIFO_FS_SIZE (32U) +#define TX4_FIFO_FS_SIZE (32U) +#define TX5_FIFO_FS_SIZE (32U) +#define TX6_FIFO_FS_SIZE (32U) +#define TX7_FIFO_FS_SIZE (32U) +#define TX8_FIFO_FS_SIZE (32U) +#define TX9_FIFO_FS_SIZE (32U) +#define TX10_FIFO_FS_SIZE (32U) +#define TX11_FIFO_FS_SIZE (32U) +#define TX12_FIFO_FS_SIZE (32U) +#define TX13_FIFO_FS_SIZE (32U) +#define TX14_FIFO_FS_SIZE (32U) +#define TX15_FIFO_FS_SIZE (32U) + +#if ((RX_FIFO_FS_SIZE + \ + TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ + TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \ + TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \ + TX15_FIFO_FS_SIZE) > 640U) +#error "The USB max FIFO size is 640 x 4 Bytes!" +#endif +#endif + +#ifdef USB_HS_MODE +#define RX_FIFO_HS_SIZE (512U) +#define TX0_FIFO_HS_SIZE (64U) +#define TX1_FIFO_HS_SIZE (64U) +#define TX2_FIFO_HS_SIZE (64U) +#define TX3_FIFO_HS_SIZE (64U) +#define TX4_FIFO_HS_SIZE (64U) +#define TX5_FIFO_HS_SIZE (64U) +#define TX6_FIFO_HS_SIZE (64U) +#define TX7_FIFO_HS_SIZE (64U) +#define TX8_FIFO_HS_SIZE (64U) +#define TX9_FIFO_HS_SIZE (64U) +#define TX10_FIFO_HS_SIZE (64U) +#define TX11_FIFO_HS_SIZE (64U) +#define TX12_FIFO_HS_SIZE (64U) +#define TX13_FIFO_HS_SIZE (64U) +#define TX14_FIFO_HS_SIZE (64U) +#define TX15_FIFO_HS_SIZE (64U) + +#if ((RX_FIFO_HS_SIZE + \ + TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \ + TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \ + TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \ + TX15_FIFO_HS_SIZE) > 2048U) +#error "The USB max FIFO size is 2048 x 4 Bytes!" +#endif +#endif + +#if defined(BSP_USING_USBD_VBUS_SENSING) +#define VBUS_SENSING_ENABLED +#endif +#endif + +#if defined(BSP_USING_USBH) +/* USB HOST FIFO CONFIGURATION */ +#ifdef USB_FS_MODE +#define RX_FIFO_FS_SIZE (128U) +#define TXH_NP_FS_FIFOSIZ (32U) +#define TXH_P_FS_FIFOSIZ (64U) + +#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U) +#error "The USB max FIFO size is 640 x 4 Bytes!" +#endif +#endif + +#ifdef USB_HS_MODE +#define RX_FIFO_HS_SIZE (512U) +#define TXH_NP_HS_FIFOSIZ (128U) +#define TXH_P_HS_FIFOSIZ (256U) + +#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U) +#error "The USB max FIFO size is 2048 x 4 Bytes!" +#endif +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_APP_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_bsp.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_bsp.h new file mode 100644 index 00000000000..cff85f47e76 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_bsp.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __USB_BSP_H__ +#define __USB_BSP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "hc32_ll_utility.h" + +extern void usb_udelay(const uint32_t usec); +extern void usb_mdelay(const uint32_t msec); + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_BSP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/drv_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/drv_config.h new file mode 100644 index 00000000000..f938db9bcfe --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/drv_config.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dma_config.h" +#include "uart_config.h" +#include "spi_config.h" +#include "adc_config.h" +#include "dac_config.h" +#include "gpio_config.h" +#include "eth_config.h" +#include "can_config.h" +#include "sdio_config.h" +#include "pm_config.h" +#include "i2c_config.h" +#include "qspi_config.h" +#include "pulse_encoder_config.h" +#include "timer_config.h" +#include "tmr_capture_config.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f467_lqfp144/board/hc32f4xx_conf.h new file mode 100644 index 00000000000..ddbd5a6a718 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/hc32f4xx_conf.h @@ -0,0 +1,172 @@ +/** + ******************************************************************************* + * @file hc32f4xx_conf.h + * @brief This file contains HC32 Series Device Driver Library usage management. + @verbatim + Change Logs: + Date Author Notes + 2026-06-03 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_CONF_H__ +#define __HC32F4XX_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @brief This is the list of modules to be used in the Device Driver Library. + * Select the modules you need to use to DDL_ON. + * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + * properly. + * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + * Library. + * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + */ +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_ON) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_DMC_ENABLE (DDL_ON) +#define LL_DVP_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_ETH_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_ON) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_FMAC_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_I2S_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MAU_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_NFC_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SDIOC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F467_LQFP144 (12U) + +/** + * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to 0U. + */ +#define BSP_EV_HC32F4XX (BSP_EV_HC32F467_LQFP144) + +/** + * @brief This is the list of BSP components to be used. + * Select the components you need to use to DDL_ON. + */ +#define BSP_24CXX_ENABLE (DDL_ON) +#define BSP_IS62WV51216_ENABLE (DDL_ON) +#define BSP_MT29F2G08AB_ENABLE (DDL_ON) +#define BSP_NT35510_ENABLE (DDL_ON) +#define BSP_OV5640_ENABLE (DDL_ON) +#define BSP_RTL8201_ENABLE (DDL_ON) +#define BSP_TCA9539_ENABLE (DDL_ON) +#define BSP_W25QXX_ENABLE (DDL_ON) +#define BSP_W9825G6KH_ENABLE (DDL_ON) +#define BSP_WM8988_ENABLE (DDL_ON) +#define BSP_XPT20XX_ENABLE (DDL_ON) + +/** + * @brief Ethernet Configuration. + */ +/* MAC ADDRESS */ +#define ETH_MAC_ADDR0 (0x02U) +#define ETH_MAC_ADDR1 (0x00U) +#define ETH_MAC_ADDR2 (0x00U) +#define ETH_MAC_ADDR3 (0x00U) +#define ETH_MAC_ADDR4 (0x00U) +#define ETH_MAC_ADDR5 (0x00U) + +#if defined (ETH_PHY_USING_RTL8201F) +/* PHY(RTL8201F) Address*/ +#define ETH_PHY_ADDR (0x01U) + +/* PHY Status Register */ +#define PHY_SR (0x00U) /*!< PHY status register */ +#define PHY_DUPLEX_STATUS (0x0100U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS (0x2000U) /*!< PHY Speed mask */ + +#endif + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.icf new file mode 100644 index 00000000000..182f74abf29 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.icf @@ -0,0 +1,51 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$/config/ide/IcfEditor/cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x000FFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.ld new file mode 100644 index 00000000000..fae84a731ff --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.ld @@ -0,0 +1,229 @@ +/****************************************************************************** + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F467xG.ld */ +/* Abstract Linker script for HC32F467 Device with */ +/* 1MByte FLASH, 516KByte RAM */ +/* Version V1.0 */ +/* Date 2024-05-31 */ +/*****************************************************************************/ +/* OTP section(data sections are not flash multiplexed region) implementation. + You need to pay attention to the size of the specified OTP block. + Take two OTP blocks for example. */ +__OTP_DATA_BASE = 0x03000000; +__OTP_LOCK_BASE = 0x03001800; +/* OTP block 16 */ +__OTP_DATA_B16_START = 0x03000000; +__OTP_LOCK_B16_START = 0x03001840; +__OTP_DATA_B16_OFFSET = __OTP_DATA_B16_START - __OTP_DATA_BASE; +__OTP_LOCK_B16_OFFSET = __OTP_LOCK_B16_START - __OTP_LOCK_BASE; +/* OTP block 17 */ +__OTP_DATA_B17_START = 0x03000800; +__OTP_LOCK_B17_START = 0x03001844; +__OTP_DATA_B17_OFFSET = __OTP_DATA_B17_START - __OTP_DATA_BASE; +__OTP_LOCK_B17_OFFSET = __OTP_LOCK_B17_START - __OTP_LOCK_BASE; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 1M + OTP_DATA (rx): ORIGIN = 0x03000000, LENGTH = 6K + OTP_LOCK (rx): ORIGIN = 0x03001800, LENGTH = 728 + RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data : + { + . = ALIGN(4); + . = ORIGIN(OTP_DATA) + __OTP_DATA_B16_OFFSET; + KEEP(*(.otp_b16_data*)) + . = ORIGIN(OTP_DATA) + __OTP_DATA_B17_OFFSET; + KEEP(*(.otp_b17_data*)) + . = ALIGN(4); + } >OTP_DATA + + .otp_lock : + { + . = ALIGN(4); + . = ORIGIN(OTP_LOCK) + __OTP_LOCK_B16_OFFSET; + KEEP(*(.otp_b16_lock*)) + . = ORIGIN(OTP_LOCK) + __OTP_LOCK_B17_OFFSET; + KEEP(*(.otp_b17_lock*)) + . = ALIGN(4); + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + .bss (NOLOAD): + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + . = ALIGN(4); + *(.noinit*) + . = ALIGN(4); + } >RAM + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.sct b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.sct new file mode 100644 index 00000000000..eaa6131f073 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.sct @@ -0,0 +1,22 @@ +; **************************************************************** +; Scatter-Loading Description File +; **************************************************************** +LR_IROM1 0x00000000 0x00100000 { ; load region size_region + ER_IROM1 0x00000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x1FFE0000 UNINIT 0x00000008 { ; RW data + *(.bss.noinit) + } + RW_IRAM2 0x1FFE0008 0x0007FFF8 { ; RW data + .ANY (+RW +ZI) + .ANY (RAMCODE) + } + RW_IRAMB 0x200F0000 0x00001000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/fal_cfg.h new file mode 100644 index 00000000000..41994f8b80d --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/fal_cfg.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +/* enable hc32f4 onchip flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_HC32F4 +/* enable SFUD flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_SFUD + +extern const struct fal_flash_dev hc32_onchip_flash; +extern struct fal_flash_dev ext_nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ +} + +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, HC32_FLASH_SIZE, 0}, \ + {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/ports/nand_port.h b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/nand_port.h new file mode 100644 index 00000000000..e62d2041824 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/nand_port.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-03-01 CDT first version + */ + +#ifndef __NAND_PORT_H__ +#define __NAND_PORT_H__ + +/******************** NAND chip information ***********************************/ +#define NAND_BYTES_PER_PAGE 2048UL +#define NAND_SPARE_AREA_SIZE 64UL +#define NAND_PAGES_PER_BLOCK 64UL +#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE) +#define NAND_BLOCKS_PER_PLANE 1024UL +#define NAND_PLANE_PER_DEVICE 2UL +#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE) +#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK) + +/******************** EXMC_NFC configure **************************************/ +/* chip: EXMC_NFC_BANK0~7 */ +#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK1 + +/* density:2Gbit */ +#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT + +/* device width: 8-bit */ +#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT + +/* BankNum: 2BANKS */ +#define NAND_EXMC_NFC_BANK_NUMBER EXMC_NFC_2BANKS + +/* page size: 2KByte */ +#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE + +/* row address cycle: 3 */ +#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE + +/* ECC mode */ +#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC + +/* timing configuration(EXCLK clock frequency: 60MHz@3.3V) for MT29F2G08AB */ +/* TS: ALE/CLE/CE setup time(min=10ns) */ +#define NAND_TS 1U + +/* TWP: WE# pulse width (min=10ns) */ +#define NAND_TWP 1U + +/* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */ +#define NAND_TRP 2U + +/* TTH: ALE/CLE/CE hold time (min=5ns) */ +#define NAND_TH 1U + +/* TWH: WE# pulse width HIGH (min=10ns) */ +#define NAND_TWH 1U + +/* TRH: RE# pulse width HIGH (min=7ns) */ +#define NAND_TRH 1U + +/* TRR: Ready to RE# LOW (min=20ns) */ +#define NAND_TRR 2U + +/* TWB: WE# HIGH to busy (max=100ns) */ +#define NAND_TWB 1U + +/* TWB: WE# HIGH to busy (max=100ns) */ +#define NAND_TRB 1U + +/* TCCS: Change read column and Change write column delay */ +#define NAND_TCCS 5U + +/* TWTR: WE# HIGH to RE# LOW (min=60ns) */ +#define NAND_TWTR 4U + +/* TRTW: RE# HIGH to WE# LOW (min=100ns) */ +#define NAND_TRTW 7U + +/* TADL: ALE to data start (min=70ns) */ +#define NAND_TADL 5U + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/ports/sdram_port.h b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/sdram_port.h new file mode 100644 index 00000000000..7b12f8f927a --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/sdram_port.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-24 CDT first version + */ + +#ifndef __SDRAM_PORT_H__ +#define __SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ + +/* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */ +#define SDRAM_CHIP EXMC_DMC_CHIP0 +/* bank address */ +#define SDRAM_BANK_ADDR (0x80000000UL) +/* size(kbyte):8MB = 8*1024*1KBytes */ +#define SDRAM_SIZE (32UL * 1024UL * 1024UL) +/* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */ +#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 +/* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */ +#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT +/* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */ +#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM9 +/* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */ +#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM13 +/* cas latency clock number: 2, 3 */ +#define SDRAM_CAS_LATENCY 2UL +/* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */ +#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT + +/* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */ +#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD +/* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */ +#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL +/* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */ +#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED + +/* timing configuration(EXCLK clock frequency: 30MHz) for W9825G6KH*/ +/* refresh rate counter (EXCLK clock) */ +#define SDRAM_REFRESH_COUNT (450U) +/* TMDR: mode register command time (EXCLK clock) */ +#define SDRAM_TMDR 2U +/* TRAS: RAS to precharge delay time (EXCLK clock) */ +#define SDRAM_TRAS 2U +/* TRC: active bank x to active bank x delay time (EXCLK clock) */ +#define SDRAM_TRC 2U +/* TRCD: RAS to CAS minimum delay time (EXCLK clock) */ +#define SDRAM_TRCD_B 3U +#define SDRAM_TRCD_P 0U +/* TRFC: autorefresh command time (EXCLK clock) */ +#define SDRAM_TRFC_B 3U +#define SDRAM_TRFC_P 0U +/* TRP: precharge to RAS delay time (EXCLK clock) */ +#define SDRAM_TRP_B 3U +#define SDRAM_TRP_P 0U +/* TRRD: active bank x to active bank y delay time (EXCLK clock) */ +#define SDRAM_TRRD 1U +/* TWR: write to precharge delay time (EXCLK clock). */ +#define SDRAM_TWR 2U +/* TWTR: write to read delay time (EXCLK clock). */ +#define SDRAM_TWTR 1U +/* TXP: exit power-down command time (EXCLK clock). */ +#define SDRAM_TXP 1U +/* TXSR: exit self-refresh command time (EXCLK clock). */ +#define SDRAM_TXSR 5U +/* TESR: self-refresh command time (EXCLK clock). */ +#define SDRAM_TESR 5U + +/* memory mode register */ +#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) +#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) +#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) +#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) +#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) +#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/ports/tca9539_port.h b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/tca9539_port.h new file mode 100644 index 00000000000..a3883130a59 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/tca9539_port.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __TCA9539_PORT_H__ +#define __TCA9539_PORT_H__ + +#include "tca9539.h" + +/** + * @defgroup HC32F467_EV_IO_Function_Sel Expand IO function definition + * @{ + */ +#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ +#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ +#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ +#define EIO_CAM_RST (TCA9539_IO_PIN3) /* Camera module reset, output */ +#define EIO_LCD_BKL (TCA9539_IO_PIN4) /* LCD back-light, output */ +#define EIO_CAM_STB (TCA9539_IO_PIN5) /* Camera module standby, output */ +#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ + +#define EIO_SDIO1_CD (TCA9539_IO_PIN0) /* SDIO1 card detect, input */ +#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */ +#define EIO_LIN_SLEEP (TCA9539_IO_PIN2) /* LIN PHY sleep, output */ +#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ +#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +/** + * @} + */ + +/** + * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition + * @{ + */ +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) +/** + * @} + */ + +/** + * @defgroup BSP CAN PHY STB port/pin definition + * @{ + */ +#define CAN_STB_PORT (TCA9539_IO_PORT1) +#define CAN_STB_PIN (EIO_CAN_STB) +/** + * @} + */ +/** + * @defgroup BSP_ETH_PortPin_Sel BSP ETH port/pin definition + * @{ + */ +#define ETH_RST_PORT (TCA9539_IO_PORT1) +#define ETH_RST_PIN (EIO_ETH_RST) +/** + * @} + */ +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/ports/usb_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/usb_config.h new file mode 100644 index 00000000000..31852265d94 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/usb_config.h @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +/* ================ USB common Configuration ================ */ + +#ifdef __RTTHREAD__ + #include + + #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else + #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#endif + +#ifndef CONFIG_USB_DBG_LEVEL + #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +// #define CONFIG_USB_DCACHE_ENABLE + +/* data align size when use dma or use dcache */ +#ifdef CONFIG_USB_DCACHE_ENABLE + #define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#else + #define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* use usb_memcpy default for high performance but cost more flash memory. + * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4. +*/ +// #define CONFIG_USB_MEMCPY_DISABLE + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN + #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +/* enable advance desc register api */ +#define CONFIG_USBDEV_ADVANCE_DESC + +/* move ep0 setup handler from isr to thread */ +// #define CONFIG_USBDEV_EP0_THREAD + +#ifndef CONFIG_USBDEV_EP0_PRIO + #define CONFIG_USBDEV_EP0_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_EP0_STACKSIZE + #define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN + #define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE + #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING + #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING + #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING + #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ +// #define CONFIG_USBDEV_MSC_POLLING + +/* move msc read & write from isr to thread */ +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO + #define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE + #define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE + #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS + #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME + #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#endif + +#define CONFIG_USBDEV_MTP_THREAD + +#ifndef CONFIG_USBDEV_MTP_PRIO + #define CONFIG_USBDEV_MTP_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MTP_STACKSIZE + #define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE + #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE + #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID + #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC + #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP +#define CONFIG_USBDEV_CDC_ECM_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO + #define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE + #define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE + #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN + #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT + #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT + #define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS + #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM + #define CONFIG_USBDEV_EP_NUM 8 +#endif + +// #define CONFIG_USBDEV_SOF_ENABLE + +/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, + * the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. + * +*/ +//#define CONFIG_USB_HS + +/* ---------------- DWC2 Configuration ---------------- */ +/* enable dwc2 buffer dma mode for device +*/ +// #define CONFIG_USB_DWC2_DMA_ENABLE + +/* Defined FS Core device FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE (32) + +/* Defined FS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) + +/* Defined FS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (640) + +/* Defined HS Core Device FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE (1024) +#define CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE (0) + +/* Defined HS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE (512) +#define CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE (256) + +/* Defined HS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE (2048) + + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS + #define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM + #define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f467_lqfp144/bsp_compile_ci.bat new file mode 100644 index 00000000000..769eb4440a6 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/bsp_compile_ci.bat @@ -0,0 +1,127 @@ +scons --attach=devices.adc +scons -j4 +scons --attach=default + +scons --attach=devices.can +scons -j4 +scons --attach=default + +scons --attach=devices.crypto +scons -j4 +scons --attach=default + +scons --attach=devices.dac +scons -j4 +scons --attach=default + +scons --attach=devices.flash +scons -j4 +scons --attach=default + +scons --attach=devices.gpio +scons -j4 +scons --attach=default + +scons --attach=devices.clock_timer +scons -j4 +scons --attach=default + +scons --attach=devices.i2c +scons -j4 +scons --attach=default + +scons --attach=devices.input_capture +scons -j4 +scons --attach=default + +scons --attach=devices.pm +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr4 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.qspi +scons -j4 +scons --attach=default + +scons --attach=devices.rtc +scons -j4 +scons --attach=default + +scons --attach=devices.sdio +scons -j4 +scons --attach=default + +scons --attach=devices.soft_i2c +scons -j4 +scons --attach=default + +scons --attach=devices.spi +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v1 +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v2 +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_host +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_host +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_swdt +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_wdt +scons -j4 +scons --attach=default + +scons --attach=peripheral.eth_rmii +scons -j4 +scons --attach=default + +scons --attach=peripheral.exmc_nand +scons -j4 +scons --attach=default + +scons --attach=peripheral.exmc_sdram +scons -j4 +scons --attach=default + +scons --attach=peripheral.spi_flash +scons -j4 +scons --attach=default diff --git a/bsp/hc32/ev_hc32f467_lqfp144/figures/board.jpg b/bsp/hc32/ev_hc32f467_lqfp144/figures/board.jpg new file mode 100644 index 00000000000..b6f6aa49b49 Binary files /dev/null and b/bsp/hc32/ev_hc32f467_lqfp144/figures/board.jpg differ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/jlink/ev_hc32f467_lqfp144 Debug.launch b/bsp/hc32/ev_hc32f467_lqfp144/jlink/ev_hc32f467_lqfp144 Debug.launch new file mode 100644 index 00000000000..da92a552501 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/jlink/ev_hc32f467_lqfp144 Debug.launch @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/project.ewd b/bsp/hc32/ev_hc32f467_lqfp144/project.ewd new file mode 100644 index 00000000000..f3a41f97b9d --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/project.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + 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00000000000..bf00eabf996 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/project.ewp @@ -0,0 +1,2307 @@ + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_tmr6.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + defunct.c + 1 + ..\..\..\src\defunct.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + Libc + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + + + Libraries + + + system_hc32f467.c + 1 + packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f467\Source\system_hc32f467.c + + + + + startup_hc32f467.s + 2 + packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f467\Source\ARM\startup_hc32f467.s + + + + + Platform + + + tca9539.c + 1 + ..\platform\tca9539\tca9539.c + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.h b/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.h new file mode 100644 index 00000000000..bfe181689b6 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.h @@ -0,0 +1,448 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 24 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart7" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define ARCH_USING_HW_ATOMIC_8 +#define ARCH_USING_HW_ATOMIC_16 +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_INPUT_CAPTURE +#define RT_INPUT_CAPTURE_RB_SIZE 100 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +#define PKG_USING_HC32F4_CMSIS_DRIVER +#define PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_HC32F4_SERIES_DRIVER +#define PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_HC32 +#define SOC_SERIES_HC32F4 + +/* Hardware Drivers Config */ + +#define SOC_HC32F467RG + +/* On-chip Drivers */ + +#define BSP_USING_ON_CHIP_FLASH_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH +/* end of On-chip Drivers */ + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_TCA9539 +#define BSP_USING_EXT_IO +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART7 +#define BSP_USING_I2C +#define BSP_USING_I2C_HW +#define BSP_USING_I2C1 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.py b/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.py new file mode 100644 index 00000000000..0af49fd02b7 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + else: + EXEC_PATH = r'C:/Users/XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/hc32/ev_hc32f467_lqfp144/template.ewp b/bsp/hc32/ev_hc32f467_lqfp144/template.ewp new file mode 100644 index 00000000000..8e80bf1aec4 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/template.ewp @@ -0,0 +1,1927 @@ + + + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/template.eww b/bsp/hc32/ev_hc32f467_lqfp144/template.eww new file mode 100644 index 00000000000..c62178f07a5 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/template.uvoptx b/bsp/hc32/ev_hc32f467_lqfp144/template.uvoptx new file mode 100644 index 00000000000..8f16129428e --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/template.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F467_1M -FS00 -FL0100000 -FP0($$Device:HC32F467RGTI$FlashARM/HC32F467_1M.FLM) -FF1HC32F467_otp -FS13000000 -FL11800 -FP1($$Device:HC32F467RGTI$FlashARM/HC32F467_otp.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/template.uvprojx b/bsp/hc32/ev_hc32f467_lqfp144/template.uvprojx new file mode 100644 index 00000000000..49e82b81f04 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/template.uvprojx @@ -0,0 +1,390 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060020::V5.06 (build 20)::ARMCC + 0 + + + HC32F467RGTI + HDSC + HDSC.HC32F467.1.0.2 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM1(0x00000000,0x100000) IROM2(0x03000000,0x1800) IRAM1(0x1FFE0000,0x80000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE + + + CMSIS_AGDI(-S0 -C0 -P00 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F467_1M -FS00 -FL0100000 -FP0($$Device:HC32F467RGTI$FlashARM/HC32F467_1M.FLM) -FF1HC32F467_otp -FS13000000 -FL11800 -FP1($$Device:HC32F467RGTI$FlashARM/HC32F467_otp.FLM)) + 0 + $$Device:HC32F467RGTI$Device\Include\HC32F467RGTI.h + + + + + + + + + + ./packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f467/Source/ARM/sfr/HC32F467.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFE0000 + 0x80000 + + + 1 + 0x0 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x03000000 + 0x1800 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFE0000 + 0x80000 + + + 0 + 0x200F0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFE0000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml index 7ec37e6f4a7..a4c0a565b39 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml @@ -29,11 +29,11 @@ devices.flash: - CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_SFUD=y devices.gpio: - kconfig: + kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f472_lqfp100/README.md b/bsp/hc32/ev_hc32f472_lqfp100/README.md index a348e2a89e6..2eab4ce544c 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/README.md +++ b/bsp/hc32/ev_hc32f472_lqfp100/README.md @@ -48,7 +48,7 @@ EV_F472_LQ100 开发板常用 **板载资源** 如下： | DAC | 支持 | | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1... PF8 ---> PIN：0，1...89 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | PM | 支持 | | diff --git a/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h b/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h index 920411e6a25..c34f13e52e3 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 24 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 /* kservice options */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml index d4a7b92a9dc..9f5f2866382 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml @@ -29,11 +29,11 @@ devices.flash: - CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_SFUD=y devices.gpio: - kconfig: + kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/README.md b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md index bbe6eb75b4a..c7f76c2b8c2 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/README.md +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md @@ -52,7 +52,7 @@ EV_F4A0_LQ176 开发板常用 **板载资源** 如下： | DAC | 支持 | | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1...PI13 ---> PIN：0，1...141 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | PM | 支持 | | diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/nand_port.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/nand_port.h index 34b62b6fa3b..2b48008bc57 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/nand_port.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/nand_port.h @@ -31,6 +31,9 @@ /* device width: 8-bit */ #define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT +/* BankNum: 1BANK */ +#define NAND_EXMC_NFC_BANK_NUMBER EXMC_NFC_1BANK + /* page size: 2KByte */ #define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h index 692061461c1..c55cae19b80 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 24 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f4a2_lqfp176/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 00000000000..9f5f2866382 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,195 @@ +# ------ device CI ------ +devices.adc: + kconfig: + - CONFIG_BSP_USING_ADC=y + - CONFIG_BSP_USING_ADC1=y + - CONFIG_BSP_ADC1_USING_DMA=y +devices.can: + kconfig: + - CONFIG_BSP_USING_CAN=y + - CONFIG_BSP_USING_CAN1=y + - CONFIG_RT_CAN_USING_CANFD=y + - CONFIG_RT_CAN_USING_HDR=y +devices.crypto: + kconfig: + - CONFIG_BSP_USING_HWCRYPTO=y + - CONFIG_BSP_USING_UQID=y + - CONFIG_BSP_USING_RNG=y + - CONFIG_BSP_USING_CRC=y + - CONFIG_BSP_USING_AES=y + - CONFIG_BSP_USING_HASH=y +devices.dac: + kconfig: + - CONFIG_BSP_USING_DAC=y + - CONFIG_BSP_USING_DAC1=y +devices.flash: + kconfig: + - CONFIG_BSP_USING_ON_CHIP_FLASH=y + - CONFIG_RT_USING_FAL=y + - CONFIG_RT_USING_SPI=y + - CONFIG_RT_USING_SFUD=y +devices.gpio: + kconfig: + - CONFIG_BSP_USING_GPIO=y +devices.clock_timer: + kconfig: + - CONFIG_BSP_USING_CLOCK_TIMER=y + - CONFIG_BSP_USING_TMRA_1=y +devices.i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1=y + - CONFIG_BSP_I2C1_TX_USING_DMA=y + - CONFIG_BSP_I2C1_RX_USING_DMA=y +devices.input_capture: + kconfig: + - CONFIG_BSP_USING_INPUT_CAPTURE=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6_1=y +devices.pm: + kconfig: + - CONFIG_BSP_USING_PM=y + - CONFIG_IDLE_THREAD_STACK_SIZE=512 +devices.pulse_encoder_tmr6: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMR6_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMR6_1=y +devices.pulse_encoder_tmra: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMRA_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMRA_1=y +devices.pwm_tmr4: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR4=y + - CONFIG_BSP_USING_PWM_TMR4_1=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUL=y +devices.pwm_tmr6: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR6=y + - CONFIG_BSP_USING_PWM_TMR6_1=y + - CONFIG_BSP_USING_PWM_TMR6_1_A=y + - CONFIG_BSP_USING_PWM_TMR6_1_B=y +devices.pwm_tmra: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMRA=y + - CONFIG_BSP_USING_PWM_TMRA_1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH2=y +devices.qspi: + kconfig: + - CONFIG_BSP_USING_QSPI=y + - CONFIG_BSP_QSPI_USING_DMA=y + - CONFIG_BSP_QSPI_USING_SOFT_CS=y +devices.rtc: + kconfig: + - CONFIG_BSP_USING_RTC=y + - CONFIG_RT_USING_ALARM=y +devices.sdio: + kconfig: + - CONFIG_BSP_USING_SDIO=y + - CONFIG_BSP_USING_SDIO1=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.soft_i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1_SW=y +devices.spi: + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI1=y + - CONFIG_BSP_SPI1_TX_USING_DMA=y + - CONFIG_BSP_SPI1_RX_USING_DMA=y + - CONFIG_BSP_SPI_USING_DMA=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.uart_v1: + kconfig: + - CONFIG_RT_USING_SERIAL_V1=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.uart_v2: + kconfig: + - CONFIG_RT_USING_SERIAL_V2=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.usb_hs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBD_HS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_hs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBH_HS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.usb_fs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBD_FS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_fs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBH_FS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.watchdog_swdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_SWDT=y +devices.watchdog_wdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_WDT=y + +# ------ peripheral CI ------ +peripheral.eth_mii: + kconfig: + - CONFIG_BSP_USING_ETH=y + - CONFIG_ETH_INTERFACE_USING_MII=y + - CONFIG_RT_USING_LWIP212=y + - CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +peripheral.eth_rmii: + kconfig: + - CONFIG_BSP_USING_ETH=y + - CONFIG_ETH_INTERFACE_USING_RMII=y + - CONFIG_ETH_PHY_USING_INTERRUPT_MODE=y + - CONFIG_RT_USING_LWIP212=y + - CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +peripheral.exmc_nand: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_NAND=y + - CONFIG_FINSH_USING_MSH=y +peripheral.exmc_sdram: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_SDRAM=y + - CONFIG_FINSH_USING_MSH=y +peripheral.spi_flash: + kconfig: + - CONFIG_BSP_USING_SPI_FLASH=y diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/.config b/bsp/hc32/ev_hc32f4a2_lqfp176/.config new file mode 100644 index 00000000000..0d0c37eacea --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/.config @@ -0,0 +1,1486 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=24 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_ARCH_USING_HW_ATOMIC_8=y +CONFIG_ARCH_USING_HW_ATOMIC_16=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER=y +CONFIG_PKG_HC32F4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32-f4-cmsis" +CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_HC32F4_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_HC32F4_SERIES_DRIVER=y +CONFIG_PKG_HC32F4_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32-f4-series" +CONFIG_PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_HC32F4_SERIES_DRIVER_VER="latest" +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_HC32=y +CONFIG_SOC_SERIES_HC32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HC32F4A2SI=y + +# +# On-chip Drivers +# +CONFIG_BSP_USING_ON_CHIP_FLASH_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_DCODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH=y +# end of On-chip Drivers + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_EXMC is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +CONFIG_BSP_USING_TCA9539=y +CONFIG_BSP_USING_EXT_IO=y +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_UART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set +# CONFIG_BSP_USING_UART9 is not set +# CONFIG_BSP_USING_UART10 is not set +CONFIG_BSP_USING_I2C=y +# CONFIG_BSP_USING_I2C1_SW is not set +CONFIG_BSP_USING_I2C_HW=y +CONFIG_BSP_USING_I2C1=y +# CONFIG_BSP_I2C1_TX_USING_DMA is not set +# CONFIG_BSP_I2C1_RX_USING_DMA is not set +# CONFIG_BSP_USING_I2C2 is not set +# CONFIG_BSP_USING_I2C3 is not set +# CONFIG_BSP_USING_I2C4 is not set +# CONFIG_BSP_USING_I2C5 is not set +# CONFIG_BSP_USING_I2C6 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_WDT_TMR is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_PM is not set +# CONFIG_BSP_USING_HWCRYPTO is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_USING_PULSE_ENCODER is not set +# CONFIG_BSP_USING_CLOCK_TIMER is not set +# CONFIG_BSP_USING_INPUT_CAPTURE is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/.cproject b/bsp/hc32/ev_hc32f4a2_lqfp176/.cproject new file mode 100644 index 00000000000..8166ace7254 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/.cproject @@ -0,0 +1,224 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/.gitignore b/bsp/hc32/ev_hc32f4a2_lqfp176/.gitignore new file mode 100644 index 00000000000..7221bde019d --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/.project b/bsp/hc32/ev_hc32f4a2_lqfp176/.project new file mode 100644 index 00000000000..f0d0cef7e21 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/.project @@ -0,0 +1,78 @@ + + + ev_hc32f4a2_lqfp176 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + rt-thread + 2 + virtual:/virtual + + + rt-thread/bsp + 2 + virtual:/virtual + + + rt-thread/components + 2 + $%7BPARENT-3-PROJECT_LOC%7D/components + + + rt-thread/include + 2 + $%7BPARENT-3-PROJECT_LOC%7D/include + + + rt-thread/libcpu + 2 + $%7BPARENT-3-PROJECT_LOC%7D/libcpu + + + rt-thread/src + 2 + $%7BPARENT-3-PROJECT_LOC%7D/src + + + rt-thread/bsp/hc32 + 2 + virtual:/virtual + + + rt-thread/bsp/hc32/libraries + 2 + $%7BPARENT-1-PROJECT_LOC%7D/libraries + + + rt-thread/bsp/hc32/platform + 2 + PARENT-1-PROJECT_LOC/platform + + + rt-thread/bsp/hc32/tests + 2 + PARENT-1-PROJECT_LOC/tests + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/Kconfig b/bsp/hc32/ev_hc32f4a2_lqfp176/Kconfig new file mode 100644 index 00000000000..73238d3a13b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/README.md b/bsp/hc32/ev_hc32f4a2_lqfp176/README.md new file mode 100644 index 00000000000..df815c6e8db --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/README.md @@ -0,0 +1,142 @@ +# XHSC EV_F4A2_LQ176 开发板 BSP 说明 + +## 简介 + +本文档为小华半导体为 EV_F4A2_LQ176 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +EV_F4A2_LQ176 是 XHSC 官方推出的开发板，搭载 HC32F4A2SITB 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F4A2SITB 的芯片性能。 + +开发板外观如下图所示： + + ![board](figures/board.jpg) + +EV_F4A2_LQ176 开发板常用 **板载资源** 如下： + +- MCU：HC32F4A2SITB，主频240MHz，2048KB FLASH，512KB RAM +- 外部RAM：IS62WV51216(SRAM，1MB) IS42S16400J(SDRAM，8MB) +- 外部FLASH: MT29F2G08AB(Nand，256MB) W25Q64(SPI NOR，8MB) +- 常用外设 + - LED：3 个，User LED(LED0、LED1、LED2)。 + - 按键：11 个，矩阵键盘(K1~K9)、WAKEUP(K10)、RESET(K11)。 +- 常用接口：SD卡接口、以太网接口、LCD接口、USB FS/HS接口、DVP接口、3.5mm耳机接口、Line in接口、CAN接口、LIN接口。 +- 调试接口：板载DAP调试器（含USB转串口）、标准JTAG/SWD。 + +开发板更多详细信息请参考小华半导体半导体[EV_F4A2_LQ176](https://www.xhsc.com.cn) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ETH | 支持 | RTL8201F | +| Nand | 支持 | MT29F2G08AB | +| SDRAM | 支持 | IS42S16400J | +| USB 转串口 | 支持 | 使用 UART1 | + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ADC | 支持 | | +| CAN | 支持 | | +| Crypto | 支持 | AES，CRC，HASH，RNG | +| DAC | 支持 | | +| FLASH | 支持 | | +| GPIO | 支持 | PA0，PA1...PI13 ---> PIN：0，1...141 | +| CLOCK_TIMER | 支持 | | +| I2C | 支持 | 软件、硬件 I2C | +| InputCapture | 支持 | | +| PM | 支持 | | +| PulseEncoder | 支持 | | +| PWM | 支持 | | +| QSPI | 支持 | | +| RTC | 支持 | 闹钟精度为1分钟 | +| SDIO | 支持 | | +| SPI | 支持 | | +| UART V1 & V2 | 支持 | | +| USB | 支持 | USBFS/HS Core， device/host模式 | +| WDT | 支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用Type-A to MircoUSB线连接开发板和PC供电。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED11会周期性闪烁。 + +USB虚拟COM端口默认连接串口1，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.1.0 build Apr 24 2022 13:32:39 + 2006 - 2022 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 1 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +| 板载外设 | 模式 | 协议栈 | 注意事项 | +| :------: | :----: | :------------: | :----------------------------------------------------------- | +| USB | device | ALL | 由于协议栈的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） | +| USB | device | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需先通过J14连接到主机（如PC），再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | ALL | ALL | 由于main()函数中的LED闪烁示例，使用的是USBFS主机的供电控制管脚，因而当配置为使用USBFS Core时，需要将main()函数中的LED示例代码手动屏蔽。 | +| USB | host | ALL | 为确保USB主机对外供电充足，建议通过J35外接5V电源供电，并短接J32的EXT跳帽。 | +| USB | host | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需通过J14先连接好OTG线，再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | host | RTT legacy USB | 目前仅实现并测试了对U盘的支持。 | +| USB | host | RTT legacy USB | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | +| USB | ALL | ALL | 由于管脚复用的原因，当配置使用USBHS Core时，无法同时使用板载SPI FLASH。 | +| USB | ALL | ALL | CherryUSB 与 RTT legacy USB 组件不可同时使用;
CherryUSB与 ”On-Chip Peripheral Driver---> []Enable USB“ 不可同时使能及配置。 | +| USB | ALL | RTT legacy USB | 通过“board/config/usb_config/usb_app_conf.h” 进行应用个性化配置（主要为FIFO分配） | +| USB | ALL | CherryUSB | 通过“board/ports/usb_config.h”进行应用个性化配置（如FIFO分配、是否使用DMA[Device]、是否使用高速PHY等） | + +## 联系人信息 + +维护人: + +- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱： \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/SConscript b/bsp/hc32/ev_hc32f4a2_lqfp176/SConscript new file mode 100644 index 00000000000..20f7689c53c --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/SConstruct b/bsp/hc32/ev_hc32f4a2_lqfp176/SConstruct new file mode 100644 index 00000000000..6d2a0ea7e9c --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/SConstruct @@ -0,0 +1,83 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "hc32-f4-cmsis-latest"), + os.path.join("packages", "hc32-f4-series-latest") + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +rtconfig.BSP_LIBRARY_TYPE = None + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript'))) + +# include platform +platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform' +objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript'))) + +# include tests +test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests' +objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/applications/SConscript b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/SConscript new file mode 100644 index 00000000000..9bb9abae897 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/applications/main.c b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/main.c new file mode 100644 index 00000000000..492100b7a8a --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/main.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#include +#include +#include + +/* defined the LED_GREEN pin: PC9 */ +#define LED_GREEN_PIN GET_PIN(C, 9) + + +int main(void) +{ + /* set LED_GREEN_PIN pin mode to output */ + rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_GREEN_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_GREEN_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/xtal32_fcm.c new file mode 100644 index 00000000000..39612627492 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/xtal32_fcm.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +#include +#include +#include + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_UNIT (CM_FCM) + +/** + * @brief This thread is used to monitor whether XTAL32 is stable. + * This thread only runs once after the system starts. + * When stability is detected or 2s times out, the thread will end. + * (When a timeout occurs it will be prompted via rt_kprintf) + */ +void xtal32_fcm_thread_entry(void *parameter) +{ + stc_fcm_init_t stcFcmInit; + uint32_t u32TimeOut = 0UL; + uint32_t u32Time = 200UL; /* 200*10ms = 2s */ + + /* FCM config */ + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); + (void)FCM_StructInit(&stcFcmInit); + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); + /* Enable FCM, to ensure xtal32 stable */ + FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); + + while (1) + { + if (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_END)) + { + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_END); + if ((SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR)) || (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_OVF))) + { + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR | FCM_FLAG_OVF); + } + else + { + (void)FCM_DeInit(XTAL32_FCM_UNIT); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + /* XTAL32 stabled */ + break; + } + } + u32TimeOut++; + if (u32TimeOut > u32Time) + { + (void)FCM_DeInit(XTAL32_FCM_UNIT); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + rt_kprintf("Error: XTAL32 still unstable, timeout.\n"); + break; + } + rt_thread_mdelay(10); + } +} + +int xtal32_fcm_thread_create(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL, + XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + rt_kprintf("create xtal32_fcm thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(xtal32_fcm_thread_create); + +#endif + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a2_lqfp176/board/Kconfig new file mode 100644 index 00000000000..033962609b2 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/Kconfig @@ -0,0 +1,1042 @@ +menu "Hardware Drivers Config" + +config SOC_HC32F4A2SI + bool + select SOC_SERIES_HC32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Drivers" + menuconfig BSP_USING_ON_CHIP_FLASH_CACHE + bool "Enable on-chip Flash Cache" + default y + if BSP_USING_ON_CHIP_FLASH_CACHE + config BSP_USING_ON_CHIP_FLASH_ICODE_CACHE + bool "Enable on-chip Flash ICODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_DCODE_CACHE + bool "Enable on-chip Flash DCODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH + bool "Enable on-chip Flash ICODE Prefetch" + default y + endif +endmenu + +menu "Onboard Peripheral Drivers" + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + select RT_USING_LWIP + select RT_LWIP_USING_HW_CHECKSUM + + if BSP_USING_ETH + choice + prompt "Select ETH PHY type" + default ETH_PHY_USING_RTL8201F + + config ETH_PHY_USING_RTL8201F + bool "ETH PHY USING RTL8201F" + select BSP_USING_I2C + select BSP_USING_I2C1 + select BSP_USING_TCA9539 + endchoice + + choice + prompt "Select ETH Communication Interface" + default ETH_INTERFACE_USING_MII + + config ETH_INTERFACE_USING_MII + bool "ETH Communication USING MII" + config ETH_INTERFACE_USING_RMII + bool "ETH Communication USING RMII" + endchoice + + menuconfig ETH_PHY_USING_INTERRUPT_MODE + bool "Enable ETH PHY interrupt mode" + default n + if ETH_PHY_USING_INTERRUPT_MODE + config ETH_PHY_INTERRUPT_PIN + int "ETH PHY Interrupt pin number" + range 1 176 + default 16 + endif + endif + + config BSP_USING_EXMC + bool "Enable EXMC" + default n + if BSP_USING_EXMC + choice + prompt "Using SDRAM or NAND" + default BSP_USING_NAND + + config BSP_USING_NAND + bool "Using NAND (MT29F2G08AB)" + select RT_USING_MTD_NAND + + config BSP_USING_SDRAM + bool "Using SDRAM (IS42S16400J7TLI)" + endchoice + endif + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (w25q64 spi1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + select BSP_USING_ON_CHIP_FLASH + select RT_USING_SFUD + select RT_USING_DFS + select RT_USING_FAL + select RT_USING_MTD_NOR + default n + + config BSP_USING_TCA9539 + bool "Enable TCA9539" + select BSP_USING_I2C + select BSP_USING_I2C1 + default n + + config BSP_USING_EXT_IO + bool + default y + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + select BSP_USING_TCA9539 + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + + config BSP_UART1_DMA_PING_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_DMA_PING_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_DMA_PING_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART7_DMA_PING_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 64 + endif + + + menuconfig BSP_USING_UART8 + bool "Enable UART8" + default n + if BSP_USING_UART8 + config BSP_UART8_RX_BUFSIZE + int "Set UART8 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART8_TX_BUFSIZE + int "Set UART8 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART9 + bool "Enable UART9" + default n + if BSP_USING_UART9 + config BSP_UART9_RX_BUFSIZE + int "Set UART9 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART9_TX_BUFSIZE + int "Set UART9 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART10 + bool "Enable UART10" + default n + if BSP_USING_UART10 + config BSP_UART10_RX_BUFSIZE + int "Set UART10 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART10_TX_BUFSIZE + int "Set UART10 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" + default n + select RT_USING_I2C + + if BSP_USING_I2C + menuconfig BSP_USING_I2C1_SW + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1_SW + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 176 + default 8 # PA8 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 23 # PB7 + endif + endif + + if BSP_USING_I2C + config BSP_I2C_USING_DMA + bool + default n + config BSP_USING_I2C_HW + bool + default n + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool + default n + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool + default n + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + endif + + menuconfig BSP_USING_I2C3 + bool "Enable I2C3 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool + default n + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C3_USING_DMA + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C3_USING_DMA + endif + + menuconfig BSP_USING_I2C4 + bool "Enable I2C4 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C4 + config BSP_I2C4_USING_DMA + bool + default n + config BSP_I2C4_TX_USING_DMA + bool "Enable I2C4 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C4_USING_DMA + config BSP_I2C4_RX_USING_DMA + bool "Enable I2C4 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C4_USING_DMA + endif + + menuconfig BSP_USING_I2C5 + bool "Enable I2C5 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C5 + config BSP_I2C5_USING_DMA + bool + default n + config BSP_I2C5_TX_USING_DMA + bool "Enable I2C5 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C5_USING_DMA + config BSP_I2C5_RX_USING_DMA + bool "Enable I2C5 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C5_USING_DMA + endif + + menuconfig BSP_USING_I2C6 + bool "Enable I2C6 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C6 + config BSP_I2C6_USING_DMA + bool + default n + config BSP_I2C6_TX_USING_DMA + bool "Enable I2C6 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C6_USING_DMA + config BSP_I2C6_RX_USING_DMA + bool "Enable I2C6 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C6_USING_DMA + endif + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_SPI_USING_DMA + bool + default n + + menuconfig BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + if BSP_USING_SPI1 + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI1_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + if BSP_USING_SPI2 + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI2_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + if BSP_USING_SPI3 + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI4 + bool "Enable SPI4 BUS" + default n + if BSP_USING_SPI4 + config BSP_SPI4_TX_USING_DMA + bool "Enable SPI4 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI4_RX_USING_DMA + bool "Enable SPI4 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI4_TX_USING_DMA + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC1 + bool "Enable ADC1" + default n + if BSP_USING_ADC1 + config BSP_ADC1_USING_DMA + bool "using adc1 dma" + default n + endif + menuconfig BSP_USING_ADC2 + bool "Enable ADC2" + default n + if BSP_USING_ADC2 + config BSP_ADC2_USING_DMA + bool "using adc2 dma" + default n + endif + menuconfig BSP_USING_ADC3 + bool "Enable ADC3" + default n + if BSP_USING_ADC3 + config BSP_ADC3_USING_DMA + bool "using adc3 dma" + default n + endif + endif + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "using dac1" + default n + config BSP_USING_DAC2 + bool "using dac2" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + select RT_CAN_USING_HDR + select BSP_USING_TCA9539 + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using can1" + default n + config BSP_USING_CAN2 + bool "using can2" + default n + endif + + menuconfig BSP_USING_WDT_TMR + bool "Enable Watchdog Timer" + default n + select RT_USING_WDT + if BSP_USING_WDT_TMR + choice + prompt "Select SWDT/WDT" + default BSP_USING_SWDT + + config BSP_USING_SWDT + bool "SWDT(3.72hour(max))" + config BSP_USING_WDT + bool "WDT(10.7s(max))" + endchoice + + config BSP_WDT_CONTINUE_COUNT + bool "Low Power Mode Keeps Counting" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_XTAL32 + + config BSP_RTC_USING_XTAL32 + bool "RTC USING XTAL32" + + config BSP_RTC_USING_LRC + bool "RTC USING LRC" + endchoice + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + default n + select RT_USING_SDIO + select RT_USING_DFS + if BSP_USING_SDIO + config BSP_USING_SDIO1 + bool "Enable SDIO1" + default n + config BSP_USING_SDIO2 + bool "Enable SDIO2" + default n + endif + + menuconfig BSP_USING_PM + bool "Enable PM" + default n + select RT_USING_PM + if BSP_USING_PM + choice + prompt "Select WKTM Clock Src" + default BSP_USING_WKTM_LRC + + config BSP_USING_WKTM_XTAL32 + bool "Using Xtal32" + config BSP_USING_WKTM_LRC + bool "Using LRC" + if BSP_RTC_USING_XTAL32 + config BSP_USING_WKTM_64HZ + bool "Using 64HZ(Note:must use XTAL32 and run RTC)" + endif + endchoice + endif + + menuconfig BSP_USING_HWCRYPTO + bool "Using Hardware Crypto drivers" + default n + select RT_USING_HWCRYPTO + if BSP_USING_HWCRYPTO + config BSP_USING_UQID + bool "Enable UQID (unique id)" + default n + + config BSP_USING_RNG + bool "Using Hardware RNG" + default n + select RT_HWCRYPTO_USING_RNG + + config BSP_USING_CRC + bool "Using Hardware CRC" + default n + select RT_HWCRYPTO_USING_CRC + + config BSP_USING_AES + bool "Using Hardware AES" + default n + select RT_HWCRYPTO_USING_AES + if BSP_USING_AES + choice + prompt "Select AES Mode" + default BSP_USING_AES_ECB + + config BSP_USING_AES_ECB + bool "ECB mode" + select RT_HWCRYPTO_USING_AES_ECB + endchoice + endif + + config BSP_USING_HASH + bool "Using Hardware Hash" + default n + select RT_HWCRYPTO_USING_SHA2 + if BSP_USING_HASH + choice + prompt "Select Hash Mode" + default BSP_USING_SHA2_256 + + config BSP_USING_SHA2_256 + bool "SHA2_256 Mode" + select RT_HWCRYPTO_USING_SHA2_256 + endchoice + endif + + endif + + menuconfig BSP_USING_PWM + bool "Enable output PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM_TMRA + bool "Enable timerA output PWM" + default n + if BSP_USING_PWM_TMRA + menuconfig BSP_USING_PWM_TMRA_1 + bool "Enable timerA-1 output PWM" + default n + if BSP_USING_PWM_TMRA_1 + config BSP_USING_PWM_TMRA_1_CH1 + bool "Enable timerA-1 channel1" + default n + config BSP_USING_PWM_TMRA_1_CH2 + bool "Enable timerA-1 channel2" + default n + config BSP_USING_PWM_TMRA_1_CH3 + bool "Enable timerA-1 channel3" + default n + config BSP_USING_PWM_TMRA_1_CH4 + bool "Enable timerA-1 channel4" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR4 + bool "Enable timer4 output PWM" + default n + if BSP_USING_PWM_TMR4 + menuconfig BSP_USING_PWM_TMR4_1 + bool "Enable timer4-1 output PWM" + default n + if BSP_USING_PWM_TMR4_1 + config BSP_USING_PWM_TMR4_1_OUH + bool "Enable TMR4_1_OUH channel1" + default n + config BSP_USING_PWM_TMR4_1_OUL + bool "Enable TMR4_1_OUL channel2" + default n + config BSP_USING_PWM_TMR4_1_OVH + bool "Enable TMR4_1_OVH channel3" + default n + config BSP_USING_PWM_TMR4_1_OVL + bool "Enable TMR4_1_OVL channel4" + default n + config BSP_USING_PWM_TMR4_1_OWH + bool "Enable TMR4_1_OWH channel5" + default n + config BSP_USING_PWM_TMR4_1_OWL + bool "Enable TMR4_1_OWL channel6" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR6 + bool "Enable timer6 output PWM" + default n + if BSP_USING_PWM_TMR6 + menuconfig BSP_USING_PWM_TMR6_1 + bool "Enable timer6-1 output PWM" + default n + if BSP_USING_PWM_TMR6_1 + config BSP_USING_PWM_TMR6_1_A + bool "Enable TMR6_1_A channel1" + default n + config BSP_USING_PWM_TMR6_1_B + bool "Enable TMR6_1_B channel2" + default n + endif + endif + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + depends on !RT_USING_CHERRYUSB + if BSP_USING_USB + config BSP_USING_USBD + bool + default n + config BSP_USING_USBH + bool + default n + config BSP_USING_USBFS + bool "Use USBFS Core" + default n + if BSP_USING_USBFS + choice + prompt "Select USB Mode" + default BSP_USING_USBD_FS + + config BSP_USING_USBD_FS + bool "USB Device Mode" + select BSP_USING_USBD + select RT_USING_USB_DEVICE + + config BSP_USING_USBH_FS + bool "USB Host Mode" + select BSP_USING_USBH + select RT_USING_USB_HOST + endchoice + if BSP_USING_USBD_FS + config BSP_USING_USBD_VBUS_SENSING + bool "Enable VBUS Sensing for Device" + default y + endif + if BSP_USING_USBH_FS + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers for Host" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + endif + config BSP_USING_USBHS + bool "Use USBHS Core" + default n + if BSP_USING_USBHS + choice + prompt "Select USB Mode" + default BSP_USING_USBH_HS + + config BSP_USING_USBD_HS + bool "USB Device Mode" + select BSP_USING_USBD + select RT_USING_USB_DEVICE + depends on !BSP_USING_USBD_FS + + config BSP_USING_USBH_HS + bool "USB Host Mode" + select BSP_USING_USBH + select RT_USING_USB_HOST + depends on !BSP_USING_USBH_FS + endchoice + choice + prompt "Select USB PHY" + default BSP_USING_USBHS_PHY_EMBED + + config BSP_USING_USBHS_PHY_EMBED + bool "Use USBHS Embedded PHY" + + config BSP_USING_USBHS_PHY_EXTERN + bool "Use USBHS External PHY" + select BSP_USING_I2C1 + select BSP_USING_TCA9539 + endchoice + if BSP_USING_USBD_HS + config BSP_USING_USBD_VBUS_SENSING + bool "Enable VBUS Sensing for Device" + default y + endif + if BSP_USING_USBH_HS + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers for Host" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + endif + endif + + menuconfig BSP_USING_QSPI + bool "Enable QSPI BUS" + select RT_USING_QSPI + select RT_USING_SPI + default n + if BSP_USING_QSPI + config BSP_QSPI_USING_DMA + bool "Enable QSPI DMA support" + default n + config BSP_QSPI_USING_SOFT_CS + bool "Enable QSPI Soft CS Pin" + default n + endif + + menuconfig BSP_USING_PULSE_ENCODER + bool "Enable Pulse Encoder" + default n + select RT_USING_PULSE_ENCODER + if BSP_USING_PULSE_ENCODER + menuconfig BSP_USING_TMRA_PULSE_ENCODER + bool "Use TIMERA As The Pulse Encoder" + default n + if BSP_USING_TMRA_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMRA_1 + bool "Use TIMERA_1 As The Pulse Encoder" + default n + endif + menuconfig BSP_USING_TMR6_PULSE_ENCODER + bool "Use TIMER6 As The Pulse Encoder" + default n + if BSP_USING_TMR6_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMR6_1 + bool "Use TIMER6_1 As The Pulse Encoder" + default n + endif + endif + + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable Hw Timer" + default n + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_TMRA_1 + bool "Use Timer_a1 As The Hw Timer" + default n + config BSP_USING_TMRA_2 + bool "Use Timer_a2 As The Hw Timer" + default n + config BSP_USING_TMRA_3 + bool "Use Timer_a3 As The Hw Timer" + default n + config BSP_USING_TMRA_4 + bool "Use Timer_a4 As The Hw Timer" + default n + config BSP_USING_TMRA_5 + bool "Use Timer_a5 As The Hw Timer" + default n + config BSP_USING_TMRA_6 + bool "Use Timer_a6 As The Hw Timer" + default n + config BSP_USING_TMRA_7 + bool "Use Timer_a7 As The Hw Timer" + default n + config BSP_USING_TMRA_8 + bool "Use Timer_a8 As The Hw Timer" + default n + config BSP_USING_TMRA_9 + bool "Use Timer_a9 As The Hw Timer" + default n + config BSP_USING_TMRA_10 + bool "Use Timer_a10 As The Hw Timer" + default n + config BSP_USING_TMRA_11 + bool "Use Timer_a11 As The Hw Timer" + default n + config BSP_USING_TMRA_12 + bool "Use Timer_a12 As The Hw Timer" + default n + endif + menuconfig BSP_USING_INPUT_CAPTURE + bool "Enable Input Capture" + default n + select RT_USING_INPUT_CAPTURE + if BSP_USING_INPUT_CAPTURE + menuconfig BSP_USING_INPUT_CAPTURE_TMR6 + bool "Use Timer6 As The Input Capture" + default n + if BSP_USING_INPUT_CAPTURE_TMR6 + config BSP_USING_INPUT_CAPTURE_TMR6_1 + bool "unit 1" + config BSP_USING_INPUT_CAPTURE_TMR6_2 + bool "unit 2" + config BSP_USING_INPUT_CAPTURE_TMR6_3 + bool "unit 3" + config BSP_USING_INPUT_CAPTURE_TMR6_4 + bool "unit 4" + config BSP_USING_INPUT_CAPTURE_TMR6_5 + bool "unit 5" + config BSP_USING_INPUT_CAPTURE_TMR6_6 + bool "unit 6" + config BSP_USING_INPUT_CAPTURE_TMR6_7 + bool "unit 7" + config BSP_USING_INPUT_CAPTURE_TMR6_8 + bool "unit 8" + endif + endif +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/SConscript b/bsp/hc32/ev_hc32f4a2_lqfp176/board/SConscript new file mode 100644 index 00000000000..e6c4a9bbb37 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/SConscript @@ -0,0 +1,20 @@ +import os +from building import * + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +path = [cwd] +path += [cwd + '/ports'] +path += [cwd + '/config'] +path += [cwd + '/config/usb_config'] + +CPPDEFINES = ['HC32F4A2', '__DEBUG'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.c b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.c new file mode 100644 index 00000000000..0e8725d3601 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#include "board.h" +#include "board_config.h" + +/* unlock/lock peripheral */ +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) + +/** System Base Configuration +*/ +void SystemBase_Config(void) +{ +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE) + EFM_ICacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE) + EFM_DCacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH) + EFM_PrefetchCmd(ENABLE); +#endif + /* Reset the VBAT area */ + PWC_VBAT_Reset(); +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + stc_clock_xtal_init_t stcXtalInit; + stc_clock_pll_init_t stcPLLHInit; +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + stc_clock_pllx_init_t stcPLLAInit; +#endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + stc_clock_xtal32_init_t stcXtal32Init; +#endif + + /* PCLK0, HCLK Max 240MHz */ + /* PCLK1, PCLK4 Max 120MHz */ + /* PCLK2, PCLK3 Max 60MHz */ + /* EX BUS Max 120MHz */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, \ + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \ + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \ + CLK_HCLK_DIV1)); + + GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); + (void)CLK_XtalStructInit(&stcXtalInit); + /* Config Xtal and enable Xtal */ + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stcXtalInit); + + (void)CLK_PLLStructInit(&stcPLLHInit); + /* VCO = (8/1)*120 = 960MHz*/ + stcPLLHInit.u8PLLState = CLK_PLL_ON; + stcPLLHInit.PLLCFGR = 0UL; + stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + (void)CLK_PLLInit(&stcPLLHInit); + + /* Highspeed SRAM set to 0 Read/Write wait cycle */ + SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0); + /* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */ + SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1); + /* 0-wait @ 40MHz */ + (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5); + /* 4 cycles for 200 ~ 250MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT4); + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + /* PLLX for USB */ + (void)CLK_PLLxStructInit(&stcPLLAInit); + /* VCO = (8/2)*120 = 480MHz*/ + stcPLLAInit.u8PLLState = CLK_PLL_ON; + stcPLLAInit.PLLCFGR = 0UL; + stcPLLAInit.PLLCFGR_f.PLLM = 2UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLP = 10UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLR = 4UL - 1UL; + (void)CLK_PLLxInit(&stcPLLAInit); +#endif + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + /* Xtal32 config */ + GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); + (void)CLK_Xtal32StructInit(&stcXtal32Init); + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; + (void)CLK_Xtal32Init(&stcXtal32Init); +#endif +} + +/** Peripheral Clock Configuration +*/ +void PeripheralClock_Config(void) +{ +#if defined(BSP_USING_CAN1) + CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6); +#endif +#if defined(BSP_USING_CAN2) + CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6); +#endif + +#if defined(RT_USING_ADC) + CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP); +#endif +} + +/** Peripheral Registers Unlock +*/ +void PeripheralRegister_Unlock(void) +{ + LL_PERIPH_WE(EXAMPLE_PERIPH_WE); +} + +/*@}*/ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.h new file mode 100644 index 00000000000..79efe1cff4d --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ll.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (4) +#define HC32_FLASH_SIZE (2 * 1024 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) + +#define HC32_SRAM_SIZE (512) +#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION +extern int Image$$RW_IRAM2$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END HC32_SRAM_END + +void PeripheralRegister_Unlock(void); +void PeripheralClock_Config(void); +void SystemBase_Config(void); +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.c b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.c new file mode 100644 index 00000000000..70ed5ce259b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.c @@ -0,0 +1,824 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#include +#include "board_config.h" +#include "tca9539_port.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART1) + case (rt_uint32_t)CM_USART1: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC); + GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC); + break; +#endif +#if defined(BSP_USING_UART6) + case (rt_uint32_t)CM_USART6: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, USART6_RX_FUNC); + GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, USART6_TX_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_I2C) +rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + (void)GPIO_StructInit(&stcGpioInit); + + switch ((rt_uint32_t)I2Cx) + { +#if defined(BSP_USING_I2C1) + case (rt_uint32_t)CM_I2C1: + /* Configure I2C1 SDA/SCL pin. */ + GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC); + GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(RT_USING_ADC) +rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)ADCx) + { +#if defined(BSP_USING_ADC1) + case (rt_uint32_t)CM_ADC1: + (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC2) + case (rt_uint32_t)CM_ADC2: + (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC3) + case (rt_uint32_t)CM_ADC3: + (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_DAC) +#if defined(BSP_USING_DAC2) +void EthPhyDisable(void) +{ + TCA9539_WritePin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_DIR_OUT); +} +#endif +rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)DACx) + { +#if defined(BSP_USING_DAC1) + case (rt_uint32_t)CM_DAC1: + (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit); + (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_DAC2) + case (rt_uint32_t)CM_DAC2: + (void)GPIO_Init(DAC2_CH1_PORT, DAC2_CH1_PIN, &stcGpioInit); + (void)GPIO_Init(DAC2_CH2_PORT, DAC2_CH2_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_CAN) +void CanPhyEnable(void) +{ + TCA9539_WritePin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_DIR_OUT); +} +rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)CANx) + { +#if defined(BSP_USING_CAN1) + case (rt_uint32_t)CM_CAN1: + GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC); + GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC); + break; +#endif +#if defined(BSP_USING_CAN2) + case (rt_uint32_t)CM_CAN2: + GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC); + GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + + +#if defined (RT_USING_SPI) +rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) +{ + rt_err_t result = RT_EOK; +#if defined(BSP_USING_SPI1) + stc_gpio_init_t stcGpioInit; +#endif + + switch ((rt_uint32_t)CM_SPIx) + { +#if defined(BSP_USING_SPI1) + case (rt_uint32_t)CM_SPI1: + GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinState = PIN_STAT_SET; + stcGpioInit.u16PinDir = PIN_DIR_OUT; + GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); + GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); + GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_ETH) +/* PHY hardware reset time */ +#define PHY_HW_RST_DELAY (0x40U) + +rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) +{ + TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + return RT_EOK; +} + +rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx) +{ +#if defined(ETH_INTERFACE_USING_RMII) + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC); + GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC); + GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC); + GPIO_SetFunc(ETH_RMII_REF_CLK_PORT, ETH_RMII_REF_CLK_PIN, ETH_RMII_REF_CLK_FUNC); + GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC); + GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC); + GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC); +#else + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_MII_TX_CLK_PORT, ETH_MII_TX_CLK_PIN, ETH_MII_TX_CLK_FUNC); + GPIO_SetFunc(ETH_MII_TX_EN_PORT, ETH_MII_TX_EN_PIN, ETH_MII_TX_EN_FUNC); + GPIO_SetFunc(ETH_MII_TXD0_PORT, ETH_MII_TXD0_PIN, ETH_MII_TXD0_FUNC); + GPIO_SetFunc(ETH_MII_TXD1_PORT, ETH_MII_TXD1_PIN, ETH_MII_TXD1_FUNC); + GPIO_SetFunc(ETH_MII_TXD2_PORT, ETH_MII_TXD2_PIN, ETH_MII_TXD2_FUNC); + GPIO_SetFunc(ETH_MII_TXD3_PORT, ETH_MII_TXD3_PIN, ETH_MII_TXD3_FUNC); + GPIO_SetFunc(ETH_MII_RX_CLK_PORT, ETH_MII_RX_CLK_PIN, ETH_MII_RX_CLK_FUNC); + GPIO_SetFunc(ETH_MII_RX_DV_PORT, ETH_MII_RX_DV_PIN, ETH_MII_RX_DV_FUNC); + GPIO_SetFunc(ETH_MII_RXD0_PORT, ETH_MII_RXD0_PIN, ETH_MII_RXD0_FUNC); + GPIO_SetFunc(ETH_MII_RXD1_PORT, ETH_MII_RXD1_PIN, ETH_MII_RXD1_FUNC); + GPIO_SetFunc(ETH_MII_RXD2_PORT, ETH_MII_RXD2_PIN, ETH_MII_RXD2_FUNC); + GPIO_SetFunc(ETH_MII_RXD3_PORT, ETH_MII_RXD3_PIN, ETH_MII_RXD3_FUNC); + GPIO_SetFunc(ETH_MII_RX_ER_PORT, ETH_MII_RX_ER_PIN, ETH_MII_RX_ER_FUNC); + GPIO_SetFunc(ETH_MII_CRS_PORT, ETH_MII_CRS_PIN, ETH_MII_CRS_FUNC); + GPIO_SetFunc(ETH_MII_COL_PORT, ETH_MII_COL_PIN, ETH_MII_COL_FUNC); +#endif + return RT_EOK; +} +#endif + +#if defined (RT_USING_SDIO) +rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + switch ((rt_uint32_t)SDIOCx) + { +#if defined(BSP_USING_SDIO1) + case (rt_uint32_t)CM_SDIOC1: + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); + + GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); + GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC); + GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); + GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); + GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); + GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_PWM) +#if defined(BSP_USING_PWM_TMRA) +rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMRAx) + { +#if defined(BSP_USING_PWM_TMRA_1) + case (rt_uint32_t)CM_TMRA_1: +#ifdef BSP_USING_PWM_TMRA_1_CH1 + GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH2 + GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH3 + GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH4 + GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR4) +rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR4x) + { +#if defined(BSP_USING_PWM_TMR4_1) + case (rt_uint32_t)CM_TMR4_1: +#ifdef BSP_USING_PWM_TMR4_1_OUH + GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OUL + GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVH + GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVL + GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWH + GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWL + GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR6) +rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR6x) + { +#if defined(BSP_USING_PWM_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: +#ifdef BSP_USING_PWM_TMR6_1_A + GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR6_1_B + GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif +#endif + +#if defined (BSP_USING_INPUT_CAPTURE) +rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)tmr_instance) + { +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) + case (rt_uint32_t)CM_TMR6_2: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) + case (rt_uint32_t)CM_TMR6_3: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined (BSP_USING_SDRAM) +rt_err_t rt_hw_board_sdram_init(void) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + /* DMC_CKE */ + (void)GPIO_Init(SDRAM_CKE_PORT, SDRAM_CKE_PIN, &stcGpioInit); + /* DMC_CLK */ + (void)GPIO_Init(SDRAM_CLK_PORT, SDRAM_CLK_PIN, &stcGpioInit); + /* DMC_LDQM && DMC_UDQM */ + (void)GPIO_Init(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, &stcGpioInit); + /* DMC_BA[0:1] */ + (void)GPIO_Init(SDRAM_BA0_PORT, SDRAM_BA0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_BA1_PORT, SDRAM_BA1_PIN, &stcGpioInit); + /* DMC_CAS && DMC_RAS */ + (void)GPIO_Init(SDRAM_CAS_PORT, SDRAM_CAS_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_RAS_PORT, SDRAM_RAS_PIN, &stcGpioInit); + /* DMC_WE */ + (void)GPIO_Init(SDRAM_WE_PORT, SDRAM_WE_PIN, &stcGpioInit); + /* DMC_DATA[0:15] */ + (void)GPIO_Init(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, &stcGpioInit); + /* DMC_ADD[0:11]*/ + (void)GPIO_Init(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, &stcGpioInit); + + /************************** Set EXMC pin function *************************/ + /* DMC_CKE */ + GPIO_SetFunc(SDRAM_CKE_PORT, SDRAM_CKE_PIN, SDRAM_CKE_FUNC); + /* DMC_CLK */ + GPIO_SetFunc(SDRAM_CLK_PORT, SDRAM_CLK_PIN, SDRAM_CLK_FUNC); + /* DMC_LDQM && DMC_UDQM */ + GPIO_SetFunc(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, SDRAM_DQM0_FUNC); + GPIO_SetFunc(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, SDRAM_DQM1_FUNC); + /* DMC_BA[0:1] */ + GPIO_SetFunc(SDRAM_BA0_PORT, SDRAM_BA0_PIN, SDRAM_BA0_FUNC); + GPIO_SetFunc(SDRAM_BA1_PORT, SDRAM_BA1_PIN, SDRAM_BA1_FUNC); + /* DMC_CS */ + GPIO_SetFunc(SDRAM_CS_PORT, SDRAM_CS_PIN, SDRAM_CS_FUNC); + /* DMC_CAS && DMC_RAS */ + GPIO_SetFunc(SDRAM_CAS_PORT, SDRAM_CAS_PIN, SDRAM_CAS_FUNC); + GPIO_SetFunc(SDRAM_RAS_PORT, SDRAM_RAS_PIN, SDRAM_RAS_FUNC); + /* DMC_WE */ + GPIO_SetFunc(SDRAM_WE_PORT, SDRAM_WE_PIN, SDRAM_WE_FUNC); + /* DMC_DATA[0:15] */ + GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC); + GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC); + GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC); + GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC); + GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC); + GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC); + GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC); + GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC); + GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC); + GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC); + GPIO_SetFunc(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, SDRAM_DATA10_FUNC); + GPIO_SetFunc(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, SDRAM_DATA11_FUNC); + GPIO_SetFunc(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, SDRAM_DATA12_FUNC); + GPIO_SetFunc(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, SDRAM_DATA13_FUNC); + GPIO_SetFunc(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, SDRAM_DATA14_FUNC); + GPIO_SetFunc(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, SDRAM_DATA15_FUNC); + /* DMC_ADD[0:11]*/ + GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC); + GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC); + GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC); + GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC); + GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC); + GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC); + GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC); + GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC); + GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC); + GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC); + GPIO_SetFunc(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, SDRAM_ADD10_FUNC); + GPIO_SetFunc(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, SDRAM_ADD11_FUNC); + + return result; +} +#endif + +#ifdef RT_USING_PM +void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode) +{ + switch (run_mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + break; + + case PM_RUN_MODE_LOW_SPEED: + /* Ensure that system clock less than 8M */ + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL); + + default: + break; + } +} +#endif + +#if defined(BSP_USING_USBFS) +rt_err_t rt_hw_usbfs_board_init(void) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); +#if defined(BSP_USING_USBD_FS) + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ +#endif +#if defined(BSP_USING_USBH_FS) + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ +#endif + return RT_EOK; +} +#endif + +#if defined(BSP_USING_USBHS) +rt_err_t rt_hw_usbhs_board_init(void) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + +#if defined(BSP_USING_USBHS_PHY_EMBED) + /* USBHS work in embedded PHY */ + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg); +#if defined(BSP_USING_USBD_HS) + GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC); +#endif +#if defined(BSP_USING_USBH_HS) + GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ +#endif +#else + /* Reset 3300 */ + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET); + TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT); + + (void)GPIO_StructInit(&stcGpioCfg); + /* High drive capability */ + stcGpioCfg.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg); + + GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC); + GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); + GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); + GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); +#endif + + return RT_EOK; +} +#endif + +#if defined(RT_USING_CHERRYUSB) +rt_err_t rt_hw_usbfs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ + } + else + { + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ + } + return RT_EOK; +} + +rt_err_t rt_hw_usbhs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + +#if !defined(CONFIG_USB_HS) + /* USBHS work in embedded PHY */ + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC); + } + else + { + GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ + } +#else + /* Reset 3300 */ + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET); + TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT); + + (void)GPIO_StructInit(&stcGpioCfg); + /* High drive capability */ + stcGpioCfg.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg); + + GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC); + GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); + GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); + GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); +#endif + + return RT_EOK; +} +#endif + + +#if defined(BSP_USING_QSPI) +rt_err_t rt_hw_qspi_board_init(void) +{ + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; +#ifndef BSP_QSPI_USING_SOFT_CS + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); +#endif + (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC); + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmra_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC); +#endif + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC); +#endif + + return RT_EOK; +} +#endif + +#if defined (BSP_USING_NAND) +rt_err_t rt_hw_board_nand_init(void) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + /* NFC_CE */ + (void)GPIO_Init(NAND_CE_PORT, NAND_CE_PIN, &stcGpioInit); + /* NFC_RE */ + (void)GPIO_Init(NAND_RE_PORT, NAND_RE_PIN, &stcGpioInit); + /* NFC_WE */ + (void)GPIO_Init(NAND_WE_PORT, NAND_WE_PIN, &stcGpioInit); + /* NFC_CLE */ + (void)GPIO_Init(NAND_CLE_PORT, NAND_CLE_PIN, &stcGpioInit); + /* NFC_ALE */ + (void)GPIO_Init(NAND_ALE_PORT, NAND_ALE_PIN, &stcGpioInit); + /* NFC_WP */ + (void)GPIO_Init(NAND_WP_PORT, NAND_WP_PIN, &stcGpioInit); + GPIO_SetPins(NAND_WP_PORT, NAND_WP_PIN); + + /* NFC_DATA[0:7] */ + (void)GPIO_Init(NAND_DATA0_PORT, NAND_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA1_PORT, NAND_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA2_PORT, NAND_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA3_PORT, NAND_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA4_PORT, NAND_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA5_PORT, NAND_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA6_PORT, NAND_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA7_PORT, NAND_DATA7_PIN, &stcGpioInit); + /* NFC_RB */ + (void)GPIO_Init(NAND_RB_PORT, NAND_RB_PIN, &stcGpioInit); + + /************************** Set EXMC pin function *************************/ + /* NFC_CE */ + GPIO_SetFunc(NAND_CE_PORT, NAND_CE_PIN, NAND_CE_FUNC); + /* NFC_RE */ + GPIO_SetFunc(NAND_RE_PORT, NAND_RE_PIN, NAND_RE_FUNC); + /* NFC_WE */ + GPIO_SetFunc(NAND_WE_PORT, NAND_WE_PIN, NAND_WE_FUNC); + /* NFC_CLE */ + GPIO_SetFunc(NAND_CLE_PORT, NAND_CLE_PIN, NAND_CLE_FUNC); + /* NFC_ALE */ + GPIO_SetFunc(NAND_ALE_PORT, NAND_ALE_PIN, NAND_ALE_FUNC); + /* NFC_WP */ + GPIO_SetFunc(NAND_WP_PORT, NAND_WP_PIN, NAND_WP_FUNC); + /* NFC_RB */ + GPIO_SetFunc(NAND_RB_PORT, NAND_RB_PIN, NAND_RB_FUNC); + /* NFC_DATA[0:7] */ + GPIO_SetFunc(NAND_DATA0_PORT, NAND_DATA0_PIN, NAND_DATA0_FUNC); + GPIO_SetFunc(NAND_DATA1_PORT, NAND_DATA1_PIN, NAND_DATA1_FUNC); + GPIO_SetFunc(NAND_DATA2_PORT, NAND_DATA2_PIN, NAND_DATA2_FUNC); + GPIO_SetFunc(NAND_DATA3_PORT, NAND_DATA3_PIN, NAND_DATA3_FUNC); + GPIO_SetFunc(NAND_DATA4_PORT, NAND_DATA4_PIN, NAND_DATA4_FUNC); + GPIO_SetFunc(NAND_DATA5_PORT, NAND_DATA5_PIN, NAND_DATA5_FUNC); + GPIO_SetFunc(NAND_DATA6_PORT, NAND_DATA6_PIN, NAND_DATA6_FUNC); + GPIO_SetFunc(NAND_DATA7_PORT, NAND_DATA7_PIN, NAND_DATA7_FUNC); + + return result; +} +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.h new file mode 100644 index 00000000000..ea44c9923eb --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.h @@ -0,0 +1,704 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ll.h" +#include "drv_config.h" +#if defined(RT_USING_CHERRYUSB) + #include "usb_config.h" +#endif + +/************************* XTAL port **********************/ +#define XTAL_PORT (GPIO_PORT_H) +#define XTAL_IN_PIN (GPIO_PIN_01) +#define XTAL_OUT_PIN (GPIO_PIN_00) + +/************************ USART port **********************/ +#if defined(BSP_USING_UART1) + #define USART1_RX_PORT (GPIO_PORT_H) + #define USART1_RX_PIN (GPIO_PIN_13) + #define USART1_RX_FUNC (GPIO_FUNC_33) + + #define USART1_TX_PORT (GPIO_PORT_H) + #define USART1_TX_PIN (GPIO_PIN_15) + #define USART1_TX_FUNC (GPIO_FUNC_32) +#endif + +#if defined(BSP_USING_UART6) + #define USART6_RX_PORT (GPIO_PORT_H) + #define USART6_RX_PIN (GPIO_PIN_06) + #define USART6_RX_FUNC (GPIO_FUNC_37) + + #define USART6_TX_PORT (GPIO_PORT_E) + #define USART6_TX_PIN (GPIO_PIN_06) + #define USART6_TX_FUNC (GPIO_FUNC_36) +#endif + +/************************ I2C port **********************/ +#if defined(BSP_USING_I2C1) + #define I2C1_SDA_PORT (GPIO_PORT_F) + #define I2C1_SDA_PIN (GPIO_PIN_10) + #define I2C1_SDA_FUNC (GPIO_FUNC_48) + + #define I2C1_SCL_PORT (GPIO_PORT_D) + #define I2C1_SCL_PIN (GPIO_PIN_03) + #define I2C1_SCL_FUNC (GPIO_FUNC_49) +#endif + +/*********** ADC configure *********/ +#if defined(BSP_USING_ADC1) + #define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN10 */ + #define ADC1_CH_PIN (GPIO_PIN_00) +#endif + +#if defined(BSP_USING_ADC2) + #define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN11 */ + #define ADC2_CH_PIN (GPIO_PIN_01) +#endif + +#if defined(BSP_USING_ADC3) + #define ADC3_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN12 */ + #define ADC3_CH_PIN (GPIO_PIN_02) +#endif + +/*********** DAC configure *********/ +#if defined(BSP_USING_DAC1) + #define DAC1_CH1_PORT (GPIO_PORT_A) + #define DAC1_CH1_PIN (GPIO_PIN_04) + #define DAC1_CH2_PORT (GPIO_PORT_A) + #define DAC1_CH2_PIN (GPIO_PIN_05) +#endif + +#if defined(BSP_USING_DAC2) + #define DAC2_CH1_PORT (GPIO_PORT_C) + #define DAC2_CH1_PIN (GPIO_PIN_04) + #define DAC2_CH2_PORT (GPIO_PORT_C) + #define DAC2_CH2_PIN (GPIO_PIN_05) +#endif + +/*********** CAN configure *********/ +#if defined(BSP_USING_CAN1) + #define CAN1_TX_PORT (GPIO_PORT_D) + #define CAN1_TX_PIN (GPIO_PIN_05) + #define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) + + #define CAN1_RX_PORT (GPIO_PORT_D) + #define CAN1_RX_PIN (GPIO_PIN_04) + #define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) +#endif + +#if defined(BSP_USING_CAN2) + #define CAN2_TX_PORT (GPIO_PORT_D) + #define CAN2_TX_PIN (GPIO_PIN_07) + #define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) + + #define CAN2_RX_PORT (GPIO_PORT_D) + #define CAN2_RX_PIN (GPIO_PIN_06) + #define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) +#endif + +/************************* SPI port ***********************/ +#if defined(BSP_USING_SPI1) + #define SPI1_CS_PORT (GPIO_PORT_C) + #define SPI1_CS_PIN (GPIO_PIN_07) + + #define SPI1_SCK_PORT (GPIO_PORT_C) + #define SPI1_SCK_PIN (GPIO_PIN_06) + #define SPI1_SCK_FUNC (GPIO_FUNC_40) + + #define SPI1_MOSI_PORT (GPIO_PORT_B) + #define SPI1_MOSI_PIN (GPIO_PIN_13) + #define SPI1_MOSI_FUNC (GPIO_FUNC_41) + + #define SPI1_MISO_PORT (GPIO_PORT_B) + #define SPI1_MISO_PIN (GPIO_PIN_12) + #define SPI1_MISO_FUNC (GPIO_FUNC_42) + + #define SPI1_WP_PORT (GPIO_PORT_B) + #define SPI1_WP_PIN (GPIO_PIN_10) + + #define SPI1_HOLD_PORT (GPIO_PORT_B) + #define SPI1_HOLD_PIN (GPIO_PIN_02) +#endif + +/************************* ETH port ***********************/ + +#if defined(BSP_USING_ETH) + #if defined(ETH_INTERFACE_USING_RMII) + #define ETH_SMI_MDIO_PORT (GPIO_PORT_A) + #define ETH_SMI_MDIO_PIN (GPIO_PIN_02) + #define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + + #define ETH_SMI_MDC_PORT (GPIO_PORT_C) + #define ETH_SMI_MDC_PIN (GPIO_PIN_01) + #define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_TX_EN_PORT (GPIO_PORT_G) + #define ETH_RMII_TX_EN_PIN (GPIO_PIN_11) + #define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_TXD0_PORT (GPIO_PORT_G) + #define ETH_RMII_TXD0_PIN (GPIO_PIN_13) + #define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_TXD1_PORT (GPIO_PORT_G) + #define ETH_RMII_TXD1_PIN (GPIO_PIN_14) + #define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A) + #define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01) + #define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A) + #define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07) + #define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_RXD0_PORT (GPIO_PORT_C) + #define ETH_RMII_RXD0_PIN (GPIO_PIN_04) + #define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_RXD1_PORT (GPIO_PORT_C) + #define ETH_RMII_RXD1_PIN (GPIO_PIN_05) + #define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11) + #else + #define ETH_SMI_MDIO_PORT (GPIO_PORT_A) + #define ETH_SMI_MDIO_PIN (GPIO_PIN_02) + #define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + + #define ETH_SMI_MDC_PORT (GPIO_PORT_C) + #define ETH_SMI_MDC_PIN (GPIO_PIN_01) + #define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TX_CLK_PORT (GPIO_PORT_B) + #define ETH_MII_TX_CLK_PIN (GPIO_PIN_06) + #define ETH_MII_TX_CLK_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TX_EN_PORT (GPIO_PORT_G) + #define ETH_MII_TX_EN_PIN (GPIO_PIN_11) + #define ETH_MII_TX_EN_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TXD0_PORT (GPIO_PORT_G) + #define ETH_MII_TXD0_PIN (GPIO_PIN_13) + #define ETH_MII_TXD0_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TXD1_PORT (GPIO_PORT_G) + #define ETH_MII_TXD1_PIN (GPIO_PIN_14) + #define ETH_MII_TXD1_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TXD2_PORT (GPIO_PORT_B) + #define ETH_MII_TXD2_PIN (GPIO_PIN_09) + #define ETH_MII_TXD2_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TXD3_PORT (GPIO_PORT_B) + #define ETH_MII_TXD3_PIN (GPIO_PIN_08) + #define ETH_MII_TXD3_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RX_CLK_PORT (GPIO_PORT_A) + #define ETH_MII_RX_CLK_PIN (GPIO_PIN_01) + #define ETH_MII_RX_CLK_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RX_DV_PORT (GPIO_PORT_A) + #define ETH_MII_RX_DV_PIN (GPIO_PIN_07) + #define ETH_MII_RX_DV_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RXD0_PORT (GPIO_PORT_C) + #define ETH_MII_RXD0_PIN (GPIO_PIN_04) + #define ETH_MII_RXD0_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RXD1_PORT (GPIO_PORT_C) + #define ETH_MII_RXD1_PIN (GPIO_PIN_05) + #define ETH_MII_RXD1_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RXD2_PORT (GPIO_PORT_B) + #define ETH_MII_RXD2_PIN (GPIO_PIN_00) + #define ETH_MII_RXD2_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RXD3_PORT (GPIO_PORT_B) + #define ETH_MII_RXD3_PIN (GPIO_PIN_01) + #define ETH_MII_RXD3_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RX_ER_PORT (GPIO_PORT_I) + #define ETH_MII_RX_ER_PIN (GPIO_PIN_10) + #define ETH_MII_RX_ER_FUNC (GPIO_FUNC_11) + + #define ETH_MII_CRS_PORT (GPIO_PORT_H) + #define ETH_MII_CRS_PIN (GPIO_PIN_02) + #define ETH_MII_CRS_FUNC (GPIO_FUNC_11) + + #define ETH_MII_COL_PORT (GPIO_PORT_H) + #define ETH_MII_COL_PIN (GPIO_PIN_03) + #define ETH_MII_COL_FUNC (GPIO_FUNC_11) + #endif +#endif + +/************************ NAND port **********************/ +#if defined(BSP_USING_NAND) + #define NAND_CE_PORT (GPIO_PORT_C) /* PC02 - EXMC_CE0 */ + #define NAND_CE_PIN (GPIO_PIN_02) + #define NAND_CE_FUNC (GPIO_FUNC_12) + + #define NAND_RE_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ + #define NAND_RE_PIN (GPIO_PIN_11) + #define NAND_RE_FUNC (GPIO_FUNC_12) + + #define NAND_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ + #define NAND_WE_PIN (GPIO_PIN_00) + #define NAND_WE_FUNC (GPIO_FUNC_12) + + #define NAND_CLE_PORT (GPIO_PORT_I) /* PI12 - EXMC_CLE */ + #define NAND_CLE_PIN (GPIO_PIN_12) + #define NAND_CLE_FUNC (GPIO_FUNC_12) + + #define NAND_ALE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ + #define NAND_ALE_PIN (GPIO_PIN_03) + #define NAND_ALE_FUNC (GPIO_FUNC_12) + + #define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ + #define NAND_WP_PIN (GPIO_PIN_15) + #define NAND_WP_FUNC (GPIO_FUNC_12) + + #define NAND_RB_PORT (GPIO_PORT_G) /* PG06 - EXMC_RB0 */ + #define NAND_RB_PIN (GPIO_PIN_06) + #define NAND_RB_FUNC (GPIO_FUNC_12) + + #define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ + #define NAND_DATA0_PIN (GPIO_PIN_14) + #define NAND_DATA0_FUNC (GPIO_FUNC_12) + #define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ + #define NAND_DATA1_PIN (GPIO_PIN_15) + #define NAND_DATA1_FUNC (GPIO_FUNC_12) + #define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */ + #define NAND_DATA2_PIN (GPIO_PIN_00) + #define NAND_DATA2_FUNC (GPIO_FUNC_12) + #define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */ + #define NAND_DATA3_PIN (GPIO_PIN_01) + #define NAND_DATA3_FUNC (GPIO_FUNC_12) + #define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */ + #define NAND_DATA4_PIN (GPIO_PIN_07) + #define NAND_DATA4_FUNC (GPIO_FUNC_12) + #define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */ + #define NAND_DATA5_PIN (GPIO_PIN_08) + #define NAND_DATA5_FUNC (GPIO_FUNC_12) + #define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */ + #define NAND_DATA6_PIN (GPIO_PIN_09) + #define NAND_DATA6_FUNC (GPIO_FUNC_12) + #define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ + #define NAND_DATA7_PIN (GPIO_PIN_10) + #define NAND_DATA7_FUNC (GPIO_FUNC_12) +#endif + +/************************ SDIOC port **********************/ +#if defined(BSP_USING_SDIO1) + #define SDIOC1_CK_PORT (GPIO_PORT_C) + #define SDIOC1_CK_PIN (GPIO_PIN_12) + #define SDIOC1_CK_FUNC (GPIO_FUNC_9) + + #define SDIOC1_CMD_PORT (GPIO_PORT_D) + #define SDIOC1_CMD_PIN (GPIO_PIN_02) + #define SDIOC1_CMD_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D0_PORT (GPIO_PORT_B) + #define SDIOC1_D0_PIN (GPIO_PIN_07) + #define SDIOC1_D0_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D1_PORT (GPIO_PORT_A) + #define SDIOC1_D1_PIN (GPIO_PIN_08) + #define SDIOC1_D1_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D2_PORT (GPIO_PORT_C) + #define SDIOC1_D2_PIN (GPIO_PIN_10) + #define SDIOC1_D2_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D3_PORT (GPIO_PORT_B) + #define SDIOC1_D3_PIN (GPIO_PIN_05) + #define SDIOC1_D3_FUNC (GPIO_FUNC_9) +#endif + +/************************ SDRAM port **********************/ +#if defined(BSP_USING_SDRAM) + #define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ + #define SDRAM_CKE_PIN (GPIO_PIN_03) + #define SDRAM_CKE_FUNC (GPIO_FUNC_12) + + #define SDRAM_CLK_PORT (GPIO_PORT_G) /* PD03 - EXMC_CLK */ + #define SDRAM_CLK_PIN (GPIO_PIN_08) + #define SDRAM_CLK_FUNC (GPIO_FUNC_12) + + #define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */ + #define SDRAM_DQM0_PIN (GPIO_PIN_00) + #define SDRAM_DQM0_FUNC (GPIO_FUNC_12) + #define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */ + #define SDRAM_DQM1_PIN (GPIO_PIN_01) + #define SDRAM_DQM1_FUNC (GPIO_FUNC_12) + + #define SDRAM_BA0_PORT (GPIO_PORT_D) /* PD11 - EXMC_ADD16 */ + #define SDRAM_BA0_PIN (GPIO_PIN_11) + #define SDRAM_BA0_FUNC (GPIO_FUNC_12) + #define SDRAM_BA1_PORT (GPIO_PORT_D) /* PD12 - EXMC_ADD17 */ + #define SDRAM_BA1_PIN (GPIO_PIN_12) + #define SDRAM_BA1_FUNC (GPIO_FUNC_12) + + #define SDRAM_CS_PORT (GPIO_PORT_G) /* PG09 - EXMC_CE1 */ + #define SDRAM_CS_PIN (GPIO_PIN_09) + #define SDRAM_CS_FUNC (GPIO_FUNC_12) + + #define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ + #define SDRAM_RAS_PIN (GPIO_PIN_11) + #define SDRAM_RAS_FUNC (GPIO_FUNC_12) + + #define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ + #define SDRAM_CAS_PIN (GPIO_PIN_15) + #define SDRAM_CAS_FUNC (GPIO_FUNC_12) + + #define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ + #define SDRAM_WE_PIN (GPIO_PIN_00) + #define SDRAM_WE_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */ + #define SDRAM_ADD0_PIN (GPIO_PIN_00) + #define SDRAM_ADD0_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */ + #define SDRAM_ADD1_PIN (GPIO_PIN_01) + #define SDRAM_ADD1_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */ + #define SDRAM_ADD2_PIN (GPIO_PIN_02) + #define SDRAM_ADD2_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */ + #define SDRAM_ADD3_PIN (GPIO_PIN_03) + #define SDRAM_ADD3_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */ + #define SDRAM_ADD4_PIN (GPIO_PIN_04) + #define SDRAM_ADD4_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */ + #define SDRAM_ADD5_PIN (GPIO_PIN_05) + #define SDRAM_ADD5_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */ + #define SDRAM_ADD6_PIN (GPIO_PIN_12) + #define SDRAM_ADD6_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */ + #define SDRAM_ADD7_PIN (GPIO_PIN_13) + #define SDRAM_ADD7_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */ + #define SDRAM_ADD8_PIN (GPIO_PIN_14) + #define SDRAM_ADD8_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */ + #define SDRAM_ADD9_PIN (GPIO_PIN_15) + #define SDRAM_ADD9_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */ + #define SDRAM_ADD10_PIN (GPIO_PIN_00) + #define SDRAM_ADD10_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */ + #define SDRAM_ADD11_PIN (GPIO_PIN_01) + #define SDRAM_ADD11_FUNC (GPIO_FUNC_12) + + #define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ + #define SDRAM_DATA0_PIN (GPIO_PIN_14) + #define SDRAM_DATA0_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ + #define SDRAM_DATA1_PIN (GPIO_PIN_15) + #define SDRAM_DATA1_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */ + #define SDRAM_DATA2_PIN (GPIO_PIN_00) + #define SDRAM_DATA2_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */ + #define SDRAM_DATA3_PIN (GPIO_PIN_01) + #define SDRAM_DATA3_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */ + #define SDRAM_DATA4_PIN (GPIO_PIN_07) + #define SDRAM_DATA4_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */ + #define SDRAM_DATA5_PIN (GPIO_PIN_08) + #define SDRAM_DATA5_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */ + #define SDRAM_DATA6_PIN (GPIO_PIN_09) + #define SDRAM_DATA6_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ + #define SDRAM_DATA7_PIN (GPIO_PIN_10) + #define SDRAM_DATA7_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */ + #define SDRAM_DATA8_PIN (GPIO_PIN_11) + #define SDRAM_DATA8_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */ + #define SDRAM_DATA9_PIN (GPIO_PIN_12) + #define SDRAM_DATA9_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */ + #define SDRAM_DATA10_PIN (GPIO_PIN_13) + #define SDRAM_DATA10_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */ + #define SDRAM_DATA11_PIN (GPIO_PIN_14) + #define SDRAM_DATA11_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */ + #define SDRAM_DATA12_PIN (GPIO_PIN_15) + #define SDRAM_DATA12_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */ + #define SDRAM_DATA13_PIN (GPIO_PIN_08) + #define SDRAM_DATA13_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */ + #define SDRAM_DATA14_PIN (GPIO_PIN_09) + #define SDRAM_DATA14_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */ + #define SDRAM_DATA15_PIN (GPIO_PIN_10) + #define SDRAM_DATA15_FUNC (GPIO_FUNC_12) +#endif + +/************************ RTC/PM *****************************/ +#if defined(BSP_USING_RTC) || defined(RT_USING_PM) + #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + #define XTAL32_PORT (GPIO_PORT_C) + #define XTAL32_IN_PIN (GPIO_PIN_15) + #define XTAL32_OUT_PIN (GPIO_PIN_14) + #endif +#endif + +#if defined(RT_USING_PWM) + /*********** PWM_TMRA configure *********/ + #if defined(BSP_USING_PWM_TMRA_1) + #if defined(BSP_USING_PWM_TMRA_1_CH1) + #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) + #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH2) + #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) + #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH3) + #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) + #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH4) + #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) + #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) + #endif + #endif + + /*********** PWM_TMR4 configure *********/ + #if defined(BSP_USING_PWM_TMR4_1) + #if defined(BSP_USING_PWM_TMR4_1_OUH) + #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) + #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OUL) + #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) + #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OVH) + #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) + #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OVL) + #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) + #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OWH) + #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) + #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OWL) + #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) + #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) + #endif + #endif + + /*********** PWM_TMR6 configure *********/ + #if defined(BSP_USING_PWM_TMR6_1) + #if defined(BSP_USING_PWM_TMR6_1_A) + #define PWM_TMR6_1_A_PORT (GPIO_PORT_F) + #define PWM_TMR6_1_A_PIN (GPIO_PIN_13) + #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) + #endif + #if defined(BSP_USING_PWM_TMR6_1_B) + #define PWM_TMR6_1_B_PORT (GPIO_PORT_F) + #define PWM_TMR6_1_B_PIN (GPIO_PIN_14) + #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) + #endif + #endif + +#endif + +#if defined(BSP_USING_INPUT_CAPTURE) + #define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3) + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) + #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_B) + #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_09) + #endif + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) + #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_E) + #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07) + #endif + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) + #define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) + #define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00) + #endif +#endif + +#if defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(BSP_USING_USBHS) || \ + defined(BSP_USING_USBHS_PHY_EMBED) || defined(BSP_USING_USBHS_PHY_EXTERN) || \ + defined(RT_USING_USB) + #error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" + #endif +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) + /* USBFS Core*/ + #define USBF_DP_PORT (GPIO_PORT_A) + #define USBF_DP_PIN (GPIO_PIN_12) + #define USBF_DM_PORT (GPIO_PORT_A) + #define USBF_DM_PIN (GPIO_PIN_11) + #define USBF_VBUS_PORT (GPIO_PORT_A) + #define USBF_VBUS_PIN (GPIO_PIN_09) + #define USBF_VBUS_FUNC (GPIO_FUNC_10) + #define USBF_DRVVBUS_PORT (GPIO_PORT_C) + #define USBF_DRVVBUS_PIN (GPIO_PIN_09) + #define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) + #endif + #if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) + /* USBHS Core*/ + #if defined(BSP_USING_USBHS_PHY_EMBED) || (defined(RT_USING_CHERRYUSB) && !defined(CONFIG_USB_HS)) + #define USBH_DP_PORT (GPIO_PORT_B) + #define USBH_DP_PIN (GPIO_PIN_15) + #define USBH_DP_FUNC (GPIO_FUNC_10) + #define USBH_DM_PORT (GPIO_PORT_B) + #define USBH_DM_PIN (GPIO_PIN_14) + #define USBH_DM_FUNC (GPIO_FUNC_10) + #define USBH_VBUS_PORT (GPIO_PORT_B) + #define USBH_VBUS_PIN (GPIO_PIN_13) + #define USBH_VBUS_FUNC (GPIO_FUNC_12) + #define USBH_DRVVBUS_PORT (GPIO_PORT_B) + #define USBH_DRVVBUS_PIN (GPIO_PIN_11) + #define USBH_DRVVBUS_FUNC (GPIO_FUNC_10) + #else + /* USBHS Core, external PHY */ + #define USBH_ULPI_CLK_PORT (GPIO_PORT_E) + #define USBH_ULPI_CLK_PIN (GPIO_PIN_12) + #define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_DIR_PORT (GPIO_PORT_C) + #define USBH_ULPI_DIR_PIN (GPIO_PIN_02) + #define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_NXT_PORT (GPIO_PORT_C) + #define USBH_ULPI_NXT_PIN (GPIO_PIN_03) + #define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_STP_PORT (GPIO_PORT_C) + #define USBH_ULPI_STP_PIN (GPIO_PIN_00) + #define USBH_ULPI_STP_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D0_PORT (GPIO_PORT_E) + #define USBH_ULPI_D0_PIN (GPIO_PIN_13) + #define USBH_ULPI_D0_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D1_PORT (GPIO_PORT_E) + #define USBH_ULPI_D1_PIN (GPIO_PIN_14) + #define USBH_ULPI_D1_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D2_PORT (GPIO_PORT_E) + #define USBH_ULPI_D2_PIN (GPIO_PIN_15) + #define USBH_ULPI_D2_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D3_PORT (GPIO_PORT_B) + #define USBH_ULPI_D3_PIN (GPIO_PIN_10) + #define USBH_ULPI_D3_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D4_PORT (GPIO_PORT_B) + #define USBH_ULPI_D4_PIN (GPIO_PIN_11) + #define USBH_ULPI_D4_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D5_PORT (GPIO_PORT_B) + #define USBH_ULPI_D5_PIN (GPIO_PIN_12) + #define USBH_ULPI_D5_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D6_PORT (GPIO_PORT_B) + #define USBH_ULPI_D6_PIN (GPIO_PIN_13) + #define USBH_ULPI_D6_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D7_PORT (GPIO_PORT_E) + #define USBH_ULPI_D7_PIN (GPIO_PIN_11) + #define USBH_ULPI_D7_FUNC (GPIO_FUNC_10) + /* 3300 reset */ + #define USB_3300_RESET_PORT (EIO_PORT1) + #define USB_3300_RESET_PIN (EIO_USB3300_RST) + #endif + #endif +#endif + +#if defined(BSP_USING_QSPI) + #ifndef BSP_QSPI_USING_SOFT_CS + /* QSSN */ + #define QSPI_FLASH_CS_PORT (GPIO_PORT_C) + #define QSPI_FLASH_CS_PIN (GPIO_PIN_07) + #define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18) + #endif + /* QSCK */ + #define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) + #define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) + #define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18) + /* QSIO0 */ + #define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) + #define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18) + /* QSIO1 */ + #define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO1_PIN (GPIO_PIN_12) + #define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18) + /* QSIO2 */ + #define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) + #define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18) + /* QSIO3 */ + #define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO3_PIN (GPIO_PIN_02) + #define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18) +#endif + +/*********** TMRA_PULSE_ENCODER configure *********/ +#if defined(RT_USING_PULSE_ENCODER) + #if defined(BSP_USING_TMRA_PULSE_ENCODER) + #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) + #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) + #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) + #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) + #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + #endif /* BSP_USING_TMRA_PULSE_ENCODER */ + + #if defined(BSP_USING_TMR6_PULSE_ENCODER) + #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) + #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) + #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) + #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) + #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) + #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) + #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#endif /* RT_USING_PULSE_ENCODER */ + +#endif + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/adc_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/adc_config.h new file mode 100644 index 00000000000..4c50d8373d5 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/adc_config.h @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_INIT_PARAMS +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC1_INIT_PARAMS */ + +#if defined (BSP_ADC1_USING_DMA) +#ifndef ADC1_EOCA_DMA_CONFIG +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC1_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC1_USING_DMA */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_INIT_PARAMS +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC2_INIT_PARAMS */ + +#if defined (BSP_ADC2_USING_DMA) +#ifndef ADC2_EOCA_DMA_CONFIG +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC2_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC2_USING_DMA */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_INIT_PARAMS +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC3_INIT_PARAMS */ +#if defined (BSP_ADC3_USING_DMA) +#ifndef ADC3_EOCA_DMA_CONFIG +#define ADC3_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC3_EOCA_DMA_INSTANCE, \ + .channel = ADC3_EOCA_DMA_CHANNEL, \ + .clock = ADC3_EOCA_DMA_CLOCK, \ + .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC3_EOCA, \ + .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC3_EOCA_DMA_IRQn, \ + .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ + .int_src = ADC3_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC3_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC3_USING_DMA */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/can_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/can_config.h new file mode 100644 index 00000000000..22a1ae7e3da --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/can_config.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __CAN_CONFIG_H__ +#define __CAN_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_CAN1 +#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN1_NAME ("can1") +#ifndef CAN1_INIT_PARAMS +#define CAN1_INIT_PARAMS \ + { \ + .name = CAN1_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN1_INIT_PARAMS */ +#endif /* BSP_USING_CAN1 */ + +#ifdef BSP_USING_CAN2 +#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN2_NAME ("can2") +#ifndef CAN2_INIT_PARAMS +#define CAN2_INIT_PARAMS \ + { \ + .name = CAN2_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN2_INIT_PARAMS */ +#endif /* BSP_USING_CAN2 */ + +/* Bit time config + Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW. + + Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2)) + TQ = u32Prescaler / CANClock. + Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ. + + The following bit time configures are based on CAN Clock 40M +*/ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 20, \ + .u32TimeSeg2 = 5, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 16, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 100, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 200, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dac_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dac_config.h new file mode 100644 index 00000000000..c96bfa6af85 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dac_config.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __DAC_CONFIG_H__ +#define __DAC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_DAC1 +#ifndef DAC1_INIT_PARAMS +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + } +#endif /* DAC1_INIT_PARAMS */ +#endif /* BSP_USING_DAC1 */ + +#ifdef BSP_USING_DAC2 +#ifndef DAC2_INIT_PARAMS +#define DAC2_INIT_PARAMS \ + { \ + .name = "dac2", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + } +#endif /* DAC2_INIT_PARAMS */ +#endif /* BSP_USING_DAC2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dma_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dma_config.h new file mode 100644 index 00000000000..7797ffec1af --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dma_config.h @@ -0,0 +1,423 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMA1 ch0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE) +#define SDIO1_RX_DMA_INSTANCE CM_DMA1 +#define SDIO1_RX_DMA_CHANNEL DMA_CH0 +#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#endif + +/* DMA1 ch1 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE) +#define SDIO1_TX_DMA_INSTANCE CM_DMA1 +#define SDIO1_TX_DMA_CHANNEL DMA_CH1 +#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#endif + +/* DMA1 ch2 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE) +#define SDIO2_RX_DMA_INSTANCE CM_DMA1 +#define SDIO2_RX_DMA_CHANNEL DMA_CH2 +#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#endif + +/* DMA1 ch3 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE) +#define SDIO2_TX_DMA_INSTANCE CM_DMA1 +#define SDIO2_TX_DMA_CHANNEL DMA_CH3 +#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE) +#define QSPI_DMA_INSTANCE CM_DMA1 +#define QSPI_DMA_CHANNEL DMA_CH3 +#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 +#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) +#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 +#endif + +/* DMA1 ch4 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH4 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) +#define I2C3_TX_DMA_INSTANCE CM_DMA1 +#define I2C3_TX_DMA_CHANNEL DMA_CH4 +#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 +#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) +#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 +#endif + +/* DMA1 ch5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH5 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) +#define I2C3_RX_DMA_INSTANCE CM_DMA1 +#define I2C3_RX_DMA_CHANNEL DMA_CH5 +#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 +#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) +#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 +#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 +#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 +#endif + +/* DMA1 ch6 */ +#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_RX_DMA_INSTANCE CM_DMA1 +#define SPI4_RX_DMA_CHANNEL DMA_CH6 +#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 +#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE) +#define I2C4_TX_DMA_INSTANCE CM_DMA1 +#define I2C4_TX_DMA_CHANNEL DMA_CH6 +#define I2C4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_TX_DMA_TRIG_SELECT AOS_DMA1_6 +#define I2C4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define I2C4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define I2C4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define I2C4_TX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#endif + +/* DMA1 ch7 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_TX_DMA_INSTANCE CM_DMA1 +#define SPI4_TX_DMA_CHANNEL DMA_CH7 +#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 +#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE) +#define I2C4_RX_DMA_INSTANCE CM_DMA1 +#define I2C4_RX_DMA_CHANNEL DMA_CH7 +#define I2C4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_RX_DMA_TRIG_SELECT AOS_DMA1_7 +#define I2C4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define I2C4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define I2C4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#endif + +/* DMA1 ch8 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_TX_DMA_INSTANCE CM_DMA1 +#define SPI5_TX_DMA_CHANNEL DMA_CH8 +#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8 +#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8 +#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM +#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO +#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8 +#endif + +/* DMA1 ch9 */ +#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE) +#define SPI6_TX_DMA_INSTANCE CM_DMA1 +#define SPI6_TX_DMA_CHANNEL DMA_CH9 +#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9 +#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9 +#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM +#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO +#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9 +#endif + +/* DMA2 ch0 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE) +#define I2C5_TX_DMA_INSTANCE CM_DMA2 +#define I2C5_TX_DMA_CHANNEL DMA_CH0 +#define I2C5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_TX_DMA_TRIG_SELECT AOS_DMA2_0 +#define I2C5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C5_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define I2C5_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define I2C5_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#endif + +/* DMA2 ch1 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#elif defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE) +#define I2C5_RX_DMA_INSTANCE CM_DMA2 +#define I2C5_RX_DMA_CHANNEL DMA_CH1 +#define I2C5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_RX_DMA_TRIG_SELECT AOS_DMA2_1 +#define I2C5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C5_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define I2C5_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define I2C5_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#endif + +/* DMA2 ch2 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE) +#define I2C6_TX_DMA_INSTANCE CM_DMA2 +#define I2C6_TX_DMA_CHANNEL DMA_CH2 +#define I2C6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_TX_DMA_TRIG_SELECT AOS_DMA2_2 +#define I2C6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C6_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define I2C6_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define I2C6_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#endif + +/* DMA2 ch3 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#elif defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE) +#define I2C6_RX_DMA_INSTANCE CM_DMA2 +#define I2C6_RX_DMA_CHANNEL DMA_CH3 +#define I2C6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_RX_DMA_TRIG_SELECT AOS_DMA2_3 +#define I2C6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C6_RX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define I2C6_RX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define I2C6_RX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#endif + +/* DMA2 ch4 */ +#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) +#define UART6_RX_DMA_INSTANCE CM_DMA2 +#define UART6_RX_DMA_CHANNEL DMA_CH4 +#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#endif + +/* DMA2 ch5 */ +#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) +#define UART6_TX_DMA_INSTANCE CM_DMA2 +#define UART6_TX_DMA_CHANNEL DMA_CH5 +#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#endif + +/* DMA2 ch6 */ +#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) +#define UART7_RX_DMA_INSTANCE CM_DMA2 +#define UART7_RX_DMA_CHANNEL DMA_CH6 +#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 +#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM +#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO +#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 +#endif + +/* DMA2 ch7 */ +#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) +#define UART7_TX_DMA_INSTANCE CM_DMA2 +#define UART7_TX_DMA_CHANNEL DMA_CH7 +#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 +#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM +#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO +#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/eth_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/eth_config.h new file mode 100644 index 00000000000..c6001367854 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/eth_config.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __ETH_CONFIG_H__ +#define __ETH_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_ETH) + +#ifndef ETH_IRQ_CONFIG +#define ETH_IRQ_CONFIG \ + { \ + .irq_num = BSP_ETH_IRQ_NUM, \ + .irq_prio = BSP_ETH_IRQ_PRIO, \ + .int_src = INT_SRC_ETH_GLB_INT, \ + } +#endif /* ETH_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __ETH_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/gpio_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/gpio_config.h new file mode 100644 index 00000000000..ce5ceac86d4 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/gpio_config.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __GPIO_CONFIG_H__ +#define __GPIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(RT_USING_PIN) + +#ifndef EXTINT0_IRQ_CONFIG +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT1_IRQ_CONFIG +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT2_IRQ_CONFIG +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ + } +#endif /* EXTINT2_IRQ_CONFIG */ + +#ifndef EXTINT3_IRQ_CONFIG +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ + } +#endif /* EXTINT3_IRQ_CONFIG */ + +#ifndef EXTINT4_IRQ_CONFIG +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ + } +#endif /* EXTINT4_IRQ_CONFIG */ + +#ifndef EXTINT5_IRQ_CONFIG +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ + } +#endif /* EXTINT5_IRQ_CONFIG */ + +#ifndef EXTINT6_IRQ_CONFIG +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ + } +#endif /* EXTINT6_IRQ_CONFIG */ + +#ifndef EXTINT7_IRQ_CONFIG +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ + } +#endif /* EXTINT7_IRQ_CONFIG */ + +#ifndef EXTINT8_IRQ_CONFIG +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ + } +#endif /* EXTINT8_IRQ_CONFIG */ + +#ifndef EXTINT9_IRQ_CONFIG +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ + } +#endif /* EXTINT9_IRQ_CONFIG */ + +#ifndef EXTINT10_IRQ_CONFIG +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ + } +#endif /* EXTINT10_IRQ_CONFIG */ + +#ifndef EXTINT11_IRQ_CONFIG +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ + } +#endif /* EXTINT11_IRQ_CONFIG */ + +#ifndef EXTINT12_IRQ_CONFIG +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ + } +#endif /* EXTINT12_IRQ_CONFIG */ + +#ifndef EXTINT13_IRQ_CONFIG +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ + } +#endif /* EXTINT13_IRQ_CONFIG */ + +#ifndef EXTINT14_IRQ_CONFIG +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ + } +#endif /* EXTINT14_IRQ_CONFIG */ + +#ifndef EXTINT15_IRQ_CONFIG +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ + } +#endif /* EXTINT15_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/i2c_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/i2c_config.h new file mode 100644 index 00000000000..1e37bf0d7d2 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/i2c_config.h @@ -0,0 +1,331 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_I2C1) +#ifndef I2C1_CONFIG +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C1_CONFIG */ +#endif + +#if defined(BSP_I2C1_USING_DMA) +#ifndef I2C1_TX_DMA_CONFIG +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_TX_DMA_CONFIG */ + +#ifndef I2C1_RX_DMA_CONFIG +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_USING_DMA */ + +#if defined(BSP_USING_I2C2) +#ifndef I2C2_CONFIG +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C2_CONFIG */ + +#if defined(BSP_I2C2_USING_DMA) +#ifndef I2C2_TX_DMA_CONFIG +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_TX_DMA_CONFIG */ + +#ifndef I2C2_RX_DMA_CONFIG +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C3) +#ifndef I2C3_CONFIG +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C3_CONFIG */ + +#if defined(BSP_I2C3_USING_DMA) +#ifndef I2C3_TX_DMA_CONFIG +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_TX_DMA_CONFIG */ + +#ifndef I2C3_RX_DMA_CONFIG +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C4) +#ifndef I2C4_CONFIG +#define I2C4_CONFIG \ + { \ + .name = "i2c4", \ + .Instance = CM_I2C4, \ + .clock = FCG1_PERIPH_I2C4, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C4_CONFIG */ + +#if defined(BSP_I2C4_USING_DMA) +#ifndef I2C4_TX_DMA_CONFIG +#define I2C4_TX_DMA_CONFIG \ + { \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + .clock = I2C4_TX_DMA_CLOCK, \ + .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_TEI, \ + .flag = I2C4_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C4_TX_DMA_IRQn, \ + .irq_prio = I2C4_TX_DMA_INT_PRIO, \ + .int_src = I2C4_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C4_TX_DMA_CONFIG */ + +#ifndef I2C4_RX_DMA_CONFIG +#define I2C4_RX_DMA_CONFIG \ + { \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + .clock = I2C4_RX_DMA_CLOCK, \ + .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_RXI, \ + .flag = I2C4_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C4_RX_DMA_IRQn, \ + .irq_prio = I2C4_RX_DMA_INT_PRIO, \ + .int_src = I2C4_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C5) +#ifndef I2C5_CONFIG +#define I2C5_CONFIG \ + { \ + .name = "i2c5", \ + .Instance = CM_I2C5, \ + .clock = FCG1_PERIPH_I2C5, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C5_CONFIG */ + +#if defined(BSP_I2C5_USING_DMA) +#ifndef I2C5_TX_DMA_CONFIG +#define I2C5_TX_DMA_CONFIG \ + { \ + .Instance = I2C5_TX_DMA_INSTANCE, \ + .channel = I2C5_TX_DMA_CHANNEL, \ + .clock = I2C5_TX_DMA_CLOCK, \ + .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_TEI, \ + .flag = I2C5_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C5_TX_DMA_IRQn, \ + .irq_prio = I2C5_TX_DMA_INT_PRIO, \ + .int_src = I2C5_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C5_TX_DMA_CONFIG */ + +#ifndef I2C5_RX_DMA_CONFIG +#define I2C5_RX_DMA_CONFIG \ + { \ + .Instance = I2C5_RX_DMA_INSTANCE, \ + .channel = I2C5_RX_DMA_CHANNEL, \ + .clock = I2C5_RX_DMA_CLOCK, \ + .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_RXI, \ + .flag = I2C5_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C5_RX_DMA_IRQn, \ + .irq_prio = I2C5_RX_DMA_INT_PRIO, \ + .int_src = I2C5_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C5_RX_DMA_CONFIG */ +#endif /* BSP_I2C5_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C6) +#ifndef I2C6_CONFIG +#define I2C6_CONFIG \ + { \ + .name = "i2c6", \ + .Instance = CM_I2C6, \ + .clock = FCG1_PERIPH_I2C6, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C6_CONFIG */ + +#if defined(BSP_I2C6_USING_DMA) +#ifndef I2C6_TX_DMA_CONFIG +#define I2C6_TX_DMA_CONFIG \ + { \ + .Instance = I2C6_TX_DMA_INSTANCE, \ + .channel = I2C6_TX_DMA_CHANNEL, \ + .clock = I2C6_TX_DMA_CLOCK, \ + .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_TEI, \ + .flag = I2C6_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C6_TX_DMA_IRQn, \ + .irq_prio = I2C6_TX_DMA_INT_PRIO, \ + .int_src = I2C6_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C6_TX_DMA_CONFIG */ + +#ifndef I2C6_RX_DMA_CONFIG +#define I2C6_RX_DMA_CONFIG \ + { \ + .Instance = I2C6_RX_DMA_INSTANCE, \ + .channel = I2C6_RX_DMA_CHANNEL, \ + .clock = I2C6_RX_DMA_CLOCK, \ + .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_RXI, \ + .flag = I2C6_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C6_RX_DMA_IRQn, \ + .irq_prio = I2C6_RX_DMA_INT_PRIO, \ + .int_src = I2C6_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C6_RX_DMA_CONFIG */ +#endif /* BSP_I2C6_USING_DMA */ +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/irq_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/irq_config.h new file mode 100644 index 00000000000..c4cbdd605bf --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/irq_config.h @@ -0,0 +1,518 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __IRQ_CONFIG_H__ +#define __IRQ_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_EXTINT0_IRQ_NUM INT022_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM INT023_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM INT024_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM INT025_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM INT026_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM INT027_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM INT028_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM INT029_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM INT030_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM INT031_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM INT032_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM INT033_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM INT034_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM INT035_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM INT036_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM INT037_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA1 ch0 */ +#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch1 */ +#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch2 */ +#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch3 */ +#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch4 */ +#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch5 */ +#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch6 */ +#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn +#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch7 */ +#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn +#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch8 */ +#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn +#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch9 */ +#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn +#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA2 ch0 */ +#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch1 */ +#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch2 */ +#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch3 */ +#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch4 */ +#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch5 */ +#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch6 */ +#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn +#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch7 */ +#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn +#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_USING_ETH) +#define BSP_ETH_IRQ_NUM INT104_IRQn +#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_UART1) +#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn +#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RX_IRQ_NUM INT089_IRQn +#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_IRQ_NUM INT088_IRQn +#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART1_RX_USING_DMA) +#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn +#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn +#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RX_IRQ_NUM INT091_IRQn +#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_IRQ_NUM INT090_IRQn +#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART2_RX_USING_DMA) +#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn +#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn +#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RX_IRQ_NUM INT095_IRQn +#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_IRQ_NUM INT094_IRQn +#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn +#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RX_IRQ_NUM INT097_IRQn +#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_IRQ_NUM INT096_IRQn +#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn +#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RX_IRQ_NUM INT101_IRQn +#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_IRQ_NUM INT100_IRQn +#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn +#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RX_IRQ_NUM INT103_IRQn +#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_IRQ_NUM INT102_IRQn +#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART6_RX_USING_DMA) +#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn +#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn +#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RX_IRQ_NUM INT107_IRQn +#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_IRQ_NUM INT106_IRQn +#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART7_RX_USING_DMA) +#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn +#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#elif defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) +#define BSP_SPI1_ERR_IRQ_NUM INT009_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI2_ERR_IRQ_NUM INT016_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_SPI3) +#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI4) +#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn +#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI5) +#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn +#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI6) +#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn +#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_UART8) +#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn +#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_RX_IRQ_NUM INT109_IRQn +#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_TX_IRQ_NUM INT108_IRQn +#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#if defined(RT_USING_SERIAL_V2) +#define BSP_UART8_TX_CPLT_IRQ_NUM INT001_IRQn +#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn +#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_RX_IRQ_NUM INT110_IRQn +#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_TX_IRQ_NUM INT111_IRQn +#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART9 */ + +#if defined(BSP_USING_UART10) +#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn +#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RX_IRQ_NUM INT114_IRQn +#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_TX_IRQ_NUM INT113_IRQn +#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART10 */ + +#if defined(BSP_USING_CAN1) +#define BSP_CAN1_IRQ_NUM INT092_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_CAN1 */ + +#if defined(BSP_USING_CAN2) +#define BSP_CAN2_IRQ_NUM INT093_IRQn +#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_CAN2 */ + +#if defined(BSP_USING_SDIO1) +#define BSP_SDIO1_IRQ_NUM INT004_IRQn +#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_SDIO1 */ + +#if defined(BSP_USING_SDIO2) +#define BSP_SDIO2_IRQ_NUM INT005_IRQn +#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_SDIO2 */ + +#if defined(RT_USING_ALARM) +#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* RT_USING_ALARM */ + + +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) +#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn +#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_USBFS */ + +#if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) +#define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn +#define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_USBHS */ + +#if defined (BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_QSPI */ + +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_2) +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_3) +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_4) +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_5) +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_6) +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_7) +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_7 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_8) +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_8 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_9) +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM INT098_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM INT099_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_9 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_10) +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM INT100_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM INT101_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_10 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_11) +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_11 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_12) +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_12 */ + +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_2) +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_3) +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_4) +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM INT068_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM INT069_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_4 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_5) +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_5 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_6) +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_6 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_7) +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_7 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_8) +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_8 */ + +#if defined(BSP_USING_TMRA_1) +#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_1 */ +#if defined(BSP_USING_TMRA_2) +#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_2 */ +#if defined(BSP_USING_TMRA_3) +#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_3 */ +#if defined(BSP_USING_TMRA_4) +#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_4 */ +#if defined(BSP_USING_TMRA_5) +#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_5 */ +#if defined(BSP_USING_TMRA_6) +#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn +#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_6 */ +#if defined(BSP_USING_TMRA_7) +#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn +#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_7 */ +#if defined(BSP_USING_TMRA_8) +#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn +#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_8 */ +#if defined(BSP_USING_TMRA_9) +#define BSP_USING_TMRA_9_IRQ_NUM INT098_IRQn +#define BSP_USING_TMRA_9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_9 */ +#if defined(BSP_USING_TMRA_10) +#define BSP_USING_TMRA_10_IRQ_NUM INT099_IRQn +#define BSP_USING_TMRA_10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_10 */ +#if defined(BSP_USING_TMRA_11) +#define BSP_USING_TMRA_11_IRQ_NUM INT100_IRQn +#define BSP_USING_TMRA_11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_11 */ +#if defined(BSP_USING_TMRA_12) +#define BSP_USING_TMRA_12_IRQ_NUM INT101_IRQn +#define BSP_USING_TMRA_12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_12 */ + +#if defined(BSP_USING_INPUT_CAPTURE) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pm_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pm_config.h new file mode 100644 index 00000000000..5ebff888a4f --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pm_config.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + * 2026-06-24 CDT delete PM_TICKLESS_TIMER_ENABLE_MASK for unsupport pm tickless timer + */ + +#ifndef __PM_CONFIG_H__ +#define __PM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PM +extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); + +/** + * @brief run mode config @ref pm_run_mode_config structure + */ +#ifndef PM_RUN_MODE_CFG +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ + } +#endif /* PM_RUN_MODE_CFG */ + +/** + * @brief sleep idle config @ref pm_sleep_mode_idle_config structure + */ +#ifndef PM_SLEEP_IDLE_CFG +#define PM_SLEEP_IDLE_CFG \ +{ \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ +} +#endif /*PM_SLEEP_IDLE_CFG*/ + +/** + * @brief sleep deep config @ref pm_sleep_mode_deep_config structure + */ +#ifndef PM_SLEEP_DEEP_CFG +#define PM_SLEEP_DEEP_CFG \ +{ \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ +} +#endif /*PM_SLEEP_DEEP_CFG*/ + +/** + * @brief sleep standby config @ref pm_sleep_mode_standby_config structure + */ +#ifndef PM_SLEEP_STANDBY_CFG +#define PM_SLEEP_STANDBY_CFG \ +{ \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ +} +#endif /*PM_SLEEP_STANDBY_CFG*/ + +/** + * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure + */ +#ifndef PM_SLEEP_SHUTDOWN_CFG +#define PM_SLEEP_SHUTDOWN_CFG \ +{ \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ +} +#endif /*PM_SLEEP_SHUTDOWN_CFG*/ + +#endif /* BSP_USING_PM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PM_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pulse_encoder_config.h new file mode 100644 index 00000000000..1236776c8c9 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pulse_encoder_config.h @@ -0,0 +1,544 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __PULSE_ENCODER_CONFIG_H__ +#define __PULSE_ENCODER_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_PULSE_ENCODER) + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_1 +#ifndef PULSE_ENCODER_TMRA_1_CONFIG +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ + } +#endif /* PULSE_ENCODER_TMRA_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_2 +#ifndef PULSE_ENCODER_TMRA_2_CONFIG +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ + } +#endif /* PULSE_ENCODER_TMRA_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_3 +#ifndef PULSE_ENCODER_TMRA_3_CONFIG +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ + } +#endif /* PULSE_ENCODER_TMRA_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_4 +#ifndef PULSE_ENCODER_TMRA_4_CONFIG +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ + } +#endif /* PULSE_ENCODER_TMRA_4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_5 +#ifndef PULSE_ENCODER_TMRA_5_CONFIG +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ + } +#endif /* PULSE_ENCODER_TMRA_5_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_6 +#ifndef PULSE_ENCODER_TMRA_6_CONFIG +#define PULSE_ENCODER_TMRA_6_CONFIG \ + { \ + .tmr_handler = CM_TMRA_6, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a6" \ + } +#endif /* PULSE_ENCODER_TMRA_6_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_7 +#ifndef PULSE_ENCODER_TMRA_7_CONFIG +#define PULSE_ENCODER_TMRA_7_CONFIG \ + { \ + .tmr_handler = CM_TMRA_7, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_7, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a7" \ + } +#endif /* PULSE_ENCODER_TMRA_7_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_8 +#ifndef PULSE_ENCODER_TMRA_8_CONFIG +#define PULSE_ENCODER_TMRA_8_CONFIG \ + { \ + .tmr_handler = CM_TMRA_8, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_8, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a8" \ + } +#endif /* PULSE_ENCODER_TMRA_8_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_9 +#ifndef PULSE_ENCODER_TMRA_9_CONFIG +#define PULSE_ENCODER_TMRA_9_CONFIG \ + { \ + .tmr_handler = CM_TMRA_9, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_9, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_9_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_9_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a9" \ + } +#endif /* PULSE_ENCODER_TMRA_9_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_9 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_10 +#ifndef PULSE_ENCODER_TMRA_10_CONFIG +#define PULSE_ENCODER_TMRA_10_CONFIG \ + { \ + .tmr_handler = CM_TMRA_10, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_10, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_10_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_10_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a10" \ + } +#endif /* PULSE_ENCODER_TMRA_10_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_10 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_11 +#ifndef PULSE_ENCODER_TMRA_11_CONFIG +#define PULSE_ENCODER_TMRA_11_CONFIG \ + { \ + .tmr_handler = CM_TMRA_11, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_11, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_11_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_11_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a11" \ + } +#endif /* PULSE_ENCODER_TMRA_11_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_11 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_12 +#ifndef PULSE_ENCODER_TMRA_12_CONFIG +#define PULSE_ENCODER_TMRA_12_CONFIG \ + { \ + .tmr_handler = CM_TMRA_12, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_12, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_12_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_12_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a12" \ + } +#endif /* PULSE_ENCODER_TMRA_12_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_12 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_1 +#ifndef PULSE_ENCODER_TMR6_1_CONFIG +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ + } +#endif /* PULSE_ENCODER_TMR6_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_2 +#ifndef PULSE_ENCODER_TMR6_2_CONFIG +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ + } +#endif /* PULSE_ENCODER_TMR6_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_3 +#ifndef PULSE_ENCODER_TMR6_3_CONFIG +#define PULSE_ENCODER_TMR6_3_CONFIG \ + { \ + .tmr_handler = CM_TMR6_3, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_63" \ + } +#endif /* PULSE_ENCODER_TMR6_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_4 +#ifndef PULSE_ENCODER_TMR6_4_CONFIG +#define PULSE_ENCODER_TMR6_4_CONFIG \ + { \ + .tmr_handler = CM_TMR6_4, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_4, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_64" \ + } +#endif /* PULSE_ENCODER_TMR6_4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_5 +#ifndef PULSE_ENCODER_TMR6_5_CONFIG +#define PULSE_ENCODER_TMR6_5_CONFIG \ + { \ + .tmr_handler = CM_TMR6_5, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_5, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_65" \ + } +#endif /* PULSE_ENCODER_TMR6_5_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_6 +#ifndef PULSE_ENCODER_TMR6_6_CONFIG +#define PULSE_ENCODER_TMR6_6_CONFIG \ + { \ + .tmr_handler = CM_TMR6_6, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_6, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_66" \ + } +#endif /* PULSE_ENCODER_TMR6_6_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_7 +#ifndef PULSE_ENCODER_TMR6_7_CONFIG +#define PULSE_ENCODER_TMR6_7_CONFIG \ + { \ + .tmr_handler = CM_TMR6_7, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_7, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_67" \ + } +#endif /* PULSE_ENCODER_TMR6_7_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_8 +#ifndef PULSE_ENCODER_TMR6_8_CONFIG +#define PULSE_ENCODER_TMR6_8_CONFIG \ + { \ + .tmr_handler = CM_TMR6_8, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_8, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_68" \ + } +#endif /* PULSE_ENCODER_TMR6_8_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */ + +#endif /* RT_USING_PULSE_ENCODER */ + +#endif /* __PULSE_ENCODER_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pwm_tmr_config.h new file mode 100644 index 00000000000..156bf06498c --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pwm_tmr_config.h @@ -0,0 +1,881 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __PWM_TMR_CONFIG_H__ +#define __PWM_TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PWM_TMRA + +#ifdef BSP_USING_PWM_TMRA_1 +#ifndef PWM_TMRA_1_CONFIG +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_1_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_1 */ + +#ifdef BSP_USING_PWM_TMRA_2 +#ifndef PWM_TMRA_2_CONFIG +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_2_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_2 */ + +#ifdef BSP_USING_PWM_TMRA_3 +#ifndef PWM_TMRA_3_CONFIG +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_3_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_3 */ + +#ifdef BSP_USING_PWM_TMRA_4 +#ifndef PWM_TMRA_4_CONFIG +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_4_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_4 */ + +#ifdef BSP_USING_PWM_TMRA_5 +#ifndef PWM_TMRA_5_CONFIG +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_5_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_5 */ + +#ifdef BSP_USING_PWM_TMRA_6 +#ifndef PWM_TMRA_6_CONFIG +#define PWM_TMRA_6_CONFIG \ + { \ + .name = "pwm_a6", \ + .instance = CM_TMRA_6, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_6_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_6 */ + +#ifdef BSP_USING_PWM_TMRA_7 +#ifndef PWM_TMRA_7_CONFIG +#define PWM_TMRA_7_CONFIG \ + { \ + .name = "pwm_a7", \ + .instance = CM_TMRA_7, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_7_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_7 */ + +#ifdef BSP_USING_PWM_TMRA_8 +#ifndef PWM_TMRA_8_CONFIG +#define PWM_TMRA_8_CONFIG \ + { \ + .name = "pwm_a8", \ + .instance = CM_TMRA_8, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_8_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_8 */ + +#ifdef BSP_USING_PWM_TMRA_9 +#ifndef PWM_TMRA_9_CONFIG +#define PWM_TMRA_9_CONFIG \ + { \ + .name = "pwm_a9", \ + .instance = CM_TMRA_9, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_9_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_9 */ + +#ifdef BSP_USING_PWM_TMRA_10 +#ifndef PWM_TMRA_10_CONFIG +#define PWM_TMRA_10_CONFIG \ + { \ + .name = "pwm_a10", \ + .instance = CM_TMRA_10, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_10_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_10 */ + +#ifdef BSP_USING_PWM_TMRA_11 +#ifndef PWM_TMRA_11_CONFIG +#define PWM_TMRA_11_CONFIG \ + { \ + .name = "pwm_a11", \ + .instance = CM_TMRA_11, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_11_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_11 */ + +#ifdef BSP_USING_PWM_TMRA_12 +#ifndef PWM_TMRA_12_CONFIG +#define PWM_TMRA_12_CONFIG \ + { \ + .name = "pwm_a12", \ + .instance = CM_TMRA_12, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_12_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_12 */ + +#endif /* BSP_USING_PWM_TMRA */ + +#ifdef BSP_USING_PWM_TMR4 + +#ifdef BSP_USING_PWM_TMR4_1 +#ifndef PWM_TMR4_1_CONFIG +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_1 */ + +#ifdef BSP_USING_PWM_TMR4_2 +#ifndef PWM_TMR4_2_CONFIG +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_2 */ + +#ifdef BSP_USING_PWM_TMR4_3 +#ifndef PWM_TMR4_3_CONFIG +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_3 */ + +#endif /* BSP_USING_PWM_TMR4 */ + +#ifdef BSP_USING_PWM_TMR6 + +#ifdef BSP_USING_PWM_TMR6_1 +#ifndef PWM_TMR6_1_CONFIG +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_1 */ +#ifdef BSP_USING_PWM_TMR6_2 +#ifndef PWM_TMR6_2_CONFIG +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t62", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_2 */ +#ifdef BSP_USING_PWM_TMR6_3 +#ifndef PWM_TMR6_3_CONFIG +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t63", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_3 */ +#ifdef BSP_USING_PWM_TMR6_4 +#ifndef PWM_TMR6_4_CONFIG +#define PWM_TMR6_4_CONFIG \ + { \ + .name = "pwm_t64", \ + .instance = CM_TMR6_4, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_4_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_4 */ +#ifdef BSP_USING_PWM_TMR6_5 +#ifndef PWM_TMR6_5_CONFIG +#define PWM_TMR6_5_CONFIG \ + { \ + .name = "pwm_t65", \ + .instance = CM_TMR6_5, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_5_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_5 */ +#ifdef BSP_USING_PWM_TMR6_6 +#ifndef PWM_TMR6_6_CONFIG +#define PWM_TMR6_6_CONFIG \ + { \ + .name = "pwm_t66", \ + .instance = CM_TMR6_6, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_6_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_6 */ +#ifdef BSP_USING_PWM_TMR6_7 +#ifndef PWM_TMR6_7_CONFIG +#define PWM_TMR6_7_CONFIG \ + { \ + .name = "pwm_t67", \ + .instance = CM_TMR6_7, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_7_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_7 */ +#ifdef BSP_USING_PWM_TMR6_8 +#ifndef PWM_TMR6_8_CONFIG +#define PWM_TMR6_8_CONFIG \ + { \ + .name = "pwm_t68", \ + .instance = CM_TMR6_8, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_8_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_8 */ + +#endif /* BSP_USING_PWM_TMR6 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_TMRA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/qspi_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/qspi_config.h new file mode 100644 index 00000000000..aaba9297603 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/qspi_config.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ + } +#endif /* QSPI_BUS_CONFIG */ + +#ifndef QSPI_INIT_PARAMS +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ + } +#endif /* QSPI_INIT_PARAMS */ + +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ +#endif /* BSP_USING_SPI1 */ + +#ifdef __cplusplus +} +#endif + +#endif /*__QSPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/sdio_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/sdio_config.h new file mode 100644 index 00000000000..a4276039de4 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/sdio_config.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_SDIO1) +#ifndef SDIO1_BUS_CONFIG +#define SDIO1_BUS_CONFIG \ + { \ + .name = "sdio1", \ + .instance = CM_SDIOC1, \ + .clock = FCG1_PERIPH_SDIOC1, \ + .irq_config = \ + { \ + .irq_num = BSP_SDIO1_IRQ_NUM, \ + .irq_prio = BSP_SDIO1_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC1_SD, \ + }, \ + .dma_rx = \ + { \ + .Instance = SDIO1_RX_DMA_INSTANCE, \ + .channel = SDIO1_RX_DMA_CHANNEL, \ + .clock = SDIO1_RX_DMA_CLOCK, \ + .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAR, \ + }, \ + .dma_tx = \ + { \ + .Instance = SDIO1_TX_DMA_INSTANCE, \ + .channel = SDIO1_TX_DMA_CHANNEL, \ + .clock = SDIO1_TX_DMA_CLOCK, \ + .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAW, \ + }, \ + } +#endif /* SDIO1_BUS_CONFIG */ +#endif /* BSP_USING_SDIO1 */ + +#if defined(BSP_USING_SDIO2) +#ifndef SDIO2_BUS_CONFIG +#define SDIO2_BUS_CONFIG \ + { \ + .name = "sdio2", \ + .instance = CM_SDIOC2, \ + .clock = FCG1_PERIPH_SDIOC2, \ + .irq_config = \ + { \ + .irq_num = BSP_SDIO2_IRQ_NUM, \ + .irq_prio = BSP_SDIO2_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC2_SD, \ + }, \ + .dma_rx = \ + { \ + .Instance = SDIO2_RX_DMA_INSTANCE, \ + .channel = SDIO2_RX_DMA_CHANNEL, \ + .clock = SDIO2_RX_DMA_CLOCK, \ + .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAR, \ + }, \ + .dma_tx = \ + { \ + .Instance = SDIO2_TX_DMA_INSTANCE, \ + .channel = SDIO2_TX_DMA_CHANNEL, \ + .clock = SDIO2_TX_DMA_CLOCK, \ + .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAW, \ + }, \ + } +#endif /* SDIO2_BUS_CONFIG */ +#endif /* BSP_USING_SDIO2 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/spi_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/spi_config.h new file mode 100644 index 00000000000..53c1528669b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/spi_config.h @@ -0,0 +1,376 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI4_SPEI, \ + }, \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .flag = SPI4_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .flag = SPI4_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = CM_SPI5, \ + .bus_name = "spi5", \ + .clock = FCG1_PERIPH_SPI5, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI5_SPEI, \ + }, \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .clock = SPI5_TX_DMA_CLOCK, \ + .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPTI, \ + .flag = SPI5_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI5_TX_DMA_IRQn, \ + .irq_prio = SPI5_TX_DMA_INT_PRIO, \ + .int_src = SPI5_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .clock = SPI5_RX_DMA_CLOCK, \ + .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPRI, \ + .flag = SPI5_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI5_RX_DMA_IRQn, \ + .irq_prio = SPI5_RX_DMA_INT_PRIO, \ + .int_src = SPI5_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + +#ifdef BSP_USING_SPI6 +#ifndef SPI6_BUS_CONFIG +#define SPI6_BUS_CONFIG \ + { \ + .Instance = CM_SPI6, \ + .bus_name = "spi6", \ + .clock = FCG1_PERIPH_SPI6, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI6_SPEI, \ + }, \ + } +#endif /* SPI6_BUS_CONFIG */ +#endif /* BSP_USING_SPI6 */ + +#ifdef BSP_SPI6_TX_USING_DMA +#ifndef SPI6_TX_DMA_CONFIG +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .channel = SPI6_TX_DMA_CHANNEL, \ + .clock = SPI6_TX_DMA_CLOCK, \ + .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPTI, \ + .flag = SPI6_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI6_TX_DMA_IRQn, \ + .irq_prio = SPI6_TX_DMA_INT_PRIO, \ + .int_src = SPI6_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_TX_DMA_CONFIG */ +#endif /* BSP_SPI6_TX_USING_DMA */ + +#ifdef BSP_SPI6_RX_USING_DMA +#ifndef SPI6_RX_DMA_CONFIG +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .channel = SPI6_RX_DMA_CHANNEL, \ + .clock = SPI6_RX_DMA_CLOCK, \ + .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPRI, \ + .flag = SPI6_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI6_RX_DMA_IRQn, \ + .irq_prio = SPI6_RX_DMA_INT_PRIO, \ + .int_src = SPI6_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_RX_DMA_CONFIG */ +#endif /* BSP_SPI6_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/timer_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/timer_config.h new file mode 100644 index 00000000000..23f020ea757 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/timer_config.h @@ -0,0 +1,247 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __TMR_CONFIG_H__ +#define __TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_TMRA_1 +#ifndef TMRA_1_CONFIG +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ + } +#endif /* TMRA_1_CONFIG */ +#endif /* BSP_USING_TMRA_1 */ + +#ifdef BSP_USING_TMRA_2 +#ifndef TMRA_2_CONFIG +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ + } +#endif /* TMRA_2_CONFIG */ +#endif /* BSP_USING_TMRA_2 */ + +#ifdef BSP_USING_TMRA_3 +#ifndef TMRA_3_CONFIG +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ + } +#endif /* TMRA_3_CONFIG */ +#endif /* BSP_USING_TMRA_3 */ + +#ifdef BSP_USING_TMRA_4 +#ifndef TMRA_4_CONFIG +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ + } +#endif /* TMRA_4_CONFIG */ +#endif /* BSP_USING_TMRA_4 */ + +#ifdef BSP_USING_TMRA_5 +#ifndef TMRA_5_CONFIG +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ + } +#endif /* TMRA_5_CONFIG */ +#endif /* BSP_USING_TMRA_5 */ + +#ifdef BSP_USING_TMRA_6 +#ifndef TMRA_6_CONFIG +#define TMRA_6_CONFIG \ + { \ + .tmr_handle = CM_TMRA_6, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_6, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_6_OVF, \ + .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ + }, \ + .name = "tmra_6" \ + } +#endif /* TMRA_6_CONFIG */ +#endif /* BSP_USING_TMRA_6 */ + +#ifdef BSP_USING_TMRA_7 +#ifndef TMRA_7_CONFIG +#define TMRA_7_CONFIG \ + { \ + .tmr_handle = CM_TMRA_7, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_7, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_7_OVF, \ + .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ + }, \ + .name = "tmra_7" \ + } +#endif /* TMRA_7_CONFIG */ +#endif /* BSP_USING_TMRA_7 */ + +#ifdef BSP_USING_TMRA_8 +#ifndef TMRA_8_CONFIG +#define TMRA_8_CONFIG \ + { \ + .tmr_handle = CM_TMRA_8, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_8, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_8_OVF, \ + .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ + }, \ + .name = "tmra_8" \ + } +#endif /* TMRA_8_CONFIG */ +#endif /* BSP_USING_TMRA_8 */ + +#ifdef BSP_USING_TMRA_9 +#ifndef TMRA_9_CONFIG +#define TMRA_9_CONFIG \ + { \ + .tmr_handle = CM_TMRA_9, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_9, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_9_OVF, \ + .enIRQn = BSP_USING_TMRA_9_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO, \ + }, \ + .name = "tmra_9" \ + } +#endif /* TMRA_9_CONFIG */ +#endif /* BSP_USING_TMRA_9 */ + +#ifdef BSP_USING_TMRA_10 +#ifndef TMRA_10_CONFIG +#define TMRA_10_CONFIG \ + { \ + .tmr_handle = CM_TMRA_10, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_10, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_10_OVF, \ + .enIRQn = BSP_USING_TMRA_10_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO, \ + }, \ + .name = "tmra_10" \ + } +#endif /* TMRA_10_CONFIG */ +#endif /* BSP_USING_TMRA_10 */ + +#ifdef BSP_USING_TMRA_11 +#ifndef TMRA_11_CONFIG +#define TMRA_11_CONFIG \ + { \ + .tmr_handle = CM_TMRA_11, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_11, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_11_OVF, \ + .enIRQn = BSP_USING_TMRA_11_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO, \ + }, \ + .name = "tmra_11" \ + } +#endif /* TMRA_11_CONFIG */ +#endif /* BSP_USING_TMRA_11 */ + +#ifdef BSP_USING_TMRA_12 +#ifndef TMRA_12_CONFIG +#define TMRA_12_CONFIG \ + { \ + .tmr_handle = CM_TMRA_12, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_12, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_12_OVF, \ + .enIRQn = BSP_USING_TMRA_12_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO, \ + }, \ + .name = "tmra_12" \ + } +#endif /* TMRA_12_CONFIG */ +#endif /* BSP_USING_TMRA_12 */ +#endif /* __TMR_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/tmr_capture_config.h new file mode 100644 index 00000000000..ee0b5534c53 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/tmr_capture_config.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __IC_CONFIG_H__ +#define __IC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#define IC1_NAME "ic1" +#define INPUT_CAPTURE_CFG_TMR6_1 \ +{ \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ +} +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#define IC2_NAME "ic2" +#define INPUT_CAPTURE_CFG_TMR6_2 \ +{ \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ +} +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#define IC3_NAME "ic3" +#define INPUT_CAPTURE_CFG_TMR6_3 \ +{ \ + .name = IC3_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __IC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/uart_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/uart_config.h new file mode 100644 index 00000000000..c91ce442041 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/uart_config.h @@ -0,0 +1,728 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_RX_IRQ_NUM, \ + .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_TX_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TI, \ + }, \ + } +#endif /* UART1_CONFIG */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_RX_CONFIG */ + +#ifndef UART1_RXTO_CONFIG +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RTO, \ + }, \ + } +#endif /* UART1_RXTO_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#endif /* UART1_TX_CPLT_CONFIG */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_RX_IRQ_NUM, \ + .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_TX_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TI, \ + }, \ + } +#endif /* UART2_CONFIG */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_RX_CONFIG */ + +#ifndef UART2_RXTO_CONFIG +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RTO, \ + }, \ + } +#endif /* UART2_RXTO_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#endif /* UART2_TX_CPLT_CONFIG */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_RX_IRQ_NUM, \ + .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_TX_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TI, \ + }, \ + } +#endif /* UART3_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART3_TX_CPLT_CONFIG +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ + } +#endif +#endif /* UART3_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_RX_IRQ_NUM, \ + .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_TX_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TI, \ + }, \ + } +#endif /* UART4_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART4_TX_CPLT_CONFIG +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ + } +#endif +#endif /* UART4_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART5_RX_IRQ_NUM, \ + .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART5_TX_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TI, \ + }, \ + } +#endif /* UART5_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART5_TX_CPLT_CONFIG +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ + } +#endif +#endif /* UART5_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART6_RX_IRQ_NUM, \ + .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART6_TX_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TI, \ + }, \ + } +#endif /* UART6_CONFIG */ + +#if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_DMA_RX_CONFIG +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .channel = UART6_RX_DMA_CHANNEL, \ + .clock = UART6_RX_DMA_CLOCK, \ + .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_RI, \ + .flag = UART6_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART6_RX_DMA_IRQn, \ + .irq_prio = UART6_RX_DMA_INT_PRIO, \ + .int_src = UART6_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_RX_CONFIG */ + +#ifndef UART6_RXTO_CONFIG +#define UART6_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RTO, \ + }, \ + } +#endif /* UART6_RXTO_CONFIG */ +#endif /* BSP_UART6_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif +#endif /* UART6_TX_CPLT_CONFIG */ + +#if defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_DMA_TX_CONFIG +#define UART6_DMA_TX_CONFIG \ + { \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .channel = UART6_TX_DMA_CHANNEL, \ + .clock = UART6_TX_DMA_CLOCK, \ + .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_TI, \ + .flag = UART6_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART6_TX_DMA_IRQn, \ + .irq_prio = UART6_TX_DMA_INT_PRIO, \ + .int_src = UART6_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_TX_CONFIG */ +#endif /* BSP_UART6_TX_USING_DMA */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#ifndef UART7_CONFIG +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = CM_USART7, \ + .clock = FCG3_PERIPH_USART7, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART7_RX_IRQ_NUM, \ + .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART7_TX_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TI, \ + }, \ + } +#endif /* UART7_CONFIG */ + +#if defined(BSP_UART7_RX_USING_DMA) +#ifndef UART7_DMA_RX_CONFIG +#define UART7_DMA_RX_CONFIG \ + { \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .channel = UART7_RX_DMA_CHANNEL, \ + .clock = UART7_RX_DMA_CLOCK, \ + .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_RI, \ + .flag = UART7_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART7_RX_DMA_IRQn, \ + .irq_prio = UART7_RX_DMA_INT_PRIO, \ + .int_src = UART7_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_RX_CONFIG */ + +#ifndef UART7_RXTO_CONFIG +#define UART7_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RTO, \ + }, \ + } +#endif /* UART7_RXTO_CONFIG */ +#endif /* BSP_UART7_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_TX_CPLT_CONFIG +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART7_TX_CPLT_CONFIG +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ + } +#endif +#endif /* UART7_TX_CPLT_CONFIG */ + +#if defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_DMA_TX_CONFIG +#define UART7_DMA_TX_CONFIG \ + { \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .channel = UART7_TX_DMA_CHANNEL, \ + .clock = UART7_TX_DMA_CLOCK, \ + .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART7_TX_DMA_IRQn, \ + .irq_prio = UART7_TX_DMA_INT_PRIO, \ + .int_src = UART7_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_TX_CONFIG */ +#endif /* BSP_UART7_TX_USING_DMA */ +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART8) +#ifndef UART8_CONFIG +#define UART8_CONFIG \ + { \ + .name = "uart8", \ + .Instance = CM_USART8, \ + .clock = FCG3_PERIPH_USART8, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART8_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART8_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART8_RX_IRQ_NUM, \ + .irq_prio = BSP_UART8_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART8_TX_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TI, \ + }, \ + } +#endif /* UART8_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART8_TX_CPLT_CONFIG +#define UART8_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART8_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TCI, \ + }, \ + } +#endif +#endif /* UART8_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +#ifndef UART9_CONFIG +#define UART9_CONFIG \ + { \ + .name = "uart9", \ + .Instance = CM_USART9, \ + .clock = FCG3_PERIPH_USART9, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART9_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART9_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART9_RX_IRQ_NUM, \ + .irq_prio = BSP_UART9_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART9_TX_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TI, \ + }, \ + } +#endif /* UART9_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART9_TX_CPLT_CONFIG +#define UART9_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART9_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TCI, \ + }, \ + } +#endif +#endif /* UART9_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART9 */ + +#if defined(BSP_USING_UART10) +#ifndef UART10_CONFIG +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = CM_USART10, \ + .clock = FCG3_PERIPH_USART10, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART10_RX_IRQ_NUM, \ + .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART10_TX_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TI, \ + }, \ + } +#endif /* UART10_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART10_TX_CPLT_CONFIG +#define UART10_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TCI, \ + }, \ + } +#endif +#endif /* UART10_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART10 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_app_conf.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_app_conf.h new file mode 100644 index 00000000000..ee052c9e51f --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_app_conf.h @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __USB_APP_CONF_H__ +#define __USB_APP_CONF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "rtconfig.h" + +/* USB MODE CONFIGURATION */ +/* +USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment +(1) If only defined USB_FS_MODE: + MCU USBFS core work in full speed using internal PHY. +(2) If only defined USB_HS_MODE: + MCU USBHS core work in full speed using internal PHY. +(3) If both defined USB_HS_MODE && USB_HS_EXTERNAL_PHY + MCU USBHS core work in high speed using external PHY. +(4) Other combination: + Not support, forbid!! +*/ + +#if defined(BSP_USING_USBHS) +#define USB_HS_MODE +#endif +#if defined(BSP_USING_USBFS) +#define USB_FS_MODE +#endif +#if !defined(BSP_USING_USBHS) && !defined(BSP_USING_USBFS) +#define USB_FS_MODE +#endif + +#if defined(BSP_USING_USBD) +#define USE_DEVICE_MODE +#endif +#if defined(BSP_USING_USBH) +#define USE_HOST_MODE +#endif +#if !defined(BSP_USING_USBD) && !defined(BSP_USING_USBH) +#define USE_DEVICE_MODE +#endif + +#if defined(USB_HS_MODE) && defined(BSP_USING_USBHS_PHY_EXTERN) +#define USB_HS_EXTERNAL_PHY +#endif + +#ifndef USB_HS_MODE +#ifndef USB_FS_MODE +#error "USB_HS_MODE or USB_FS_MODE should be defined" +#endif +#endif + +#ifndef USE_DEVICE_MODE +#ifndef USE_HOST_MODE +#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" +#endif +#endif + +#if defined(BSP_USING_USBD) +/* USB DEVICE FIFO CONFIGURATION */ +#ifdef USB_FS_MODE +#define RX_FIFO_FS_SIZE (128U) +#define TX0_FIFO_FS_SIZE (32U) +#define TX1_FIFO_FS_SIZE (32U) +#define TX2_FIFO_FS_SIZE (32U) +#define TX3_FIFO_FS_SIZE (32U) +#define TX4_FIFO_FS_SIZE (32U) +#define TX5_FIFO_FS_SIZE (32U) +#define TX6_FIFO_FS_SIZE (32U) +#define TX7_FIFO_FS_SIZE (32U) +#define TX8_FIFO_FS_SIZE (32U) +#define TX9_FIFO_FS_SIZE (32U) +#define TX10_FIFO_FS_SIZE (32U) +#define TX11_FIFO_FS_SIZE (32U) +#define TX12_FIFO_FS_SIZE (32U) +#define TX13_FIFO_FS_SIZE (32U) +#define TX14_FIFO_FS_SIZE (32U) +#define TX15_FIFO_FS_SIZE (32U) + +#if ((RX_FIFO_FS_SIZE + \ + TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ + TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \ + TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \ + TX15_FIFO_FS_SIZE) > 640U) +#error "The USB max FIFO size is 640 x 4 Bytes!" +#endif +#endif + +#ifdef USB_HS_MODE +#define RX_FIFO_HS_SIZE (512U) +#define TX0_FIFO_HS_SIZE (64U) +#define TX1_FIFO_HS_SIZE (64U) +#define TX2_FIFO_HS_SIZE (64U) +#define TX3_FIFO_HS_SIZE (64U) +#define TX4_FIFO_HS_SIZE (64U) +#define TX5_FIFO_HS_SIZE (64U) +#define TX6_FIFO_HS_SIZE (64U) +#define TX7_FIFO_HS_SIZE (64U) +#define TX8_FIFO_HS_SIZE (64U) +#define TX9_FIFO_HS_SIZE (64U) +#define TX10_FIFO_HS_SIZE (64U) +#define TX11_FIFO_HS_SIZE (64U) +#define TX12_FIFO_HS_SIZE (64U) +#define TX13_FIFO_HS_SIZE (64U) +#define TX14_FIFO_HS_SIZE (64U) +#define TX15_FIFO_HS_SIZE (64U) + +#if ((RX_FIFO_HS_SIZE + \ + TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \ + TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \ + TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \ + TX15_FIFO_HS_SIZE) > 2048U) +#error "The USB max FIFO size is 2048 x 4 Bytes!" +#endif +#endif + +#if defined(BSP_USING_USBD_VBUS_SENSING) +#define VBUS_SENSING_ENABLED +#endif +#endif + +#if defined(BSP_USING_USBH) +/* USB HOST FIFO CONFIGURATION */ +#ifdef USB_FS_MODE +#define RX_FIFO_FS_SIZE (128U) +#define TXH_NP_FS_FIFOSIZ (32U) +#define TXH_P_FS_FIFOSIZ (64U) + +#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U) +#error "The USB max FIFO size is 640 x 4 Bytes!" +#endif +#endif + +#ifdef USB_HS_MODE +#define RX_FIFO_HS_SIZE (512U) +#define TXH_NP_HS_FIFOSIZ (128U) +#define TXH_P_HS_FIFOSIZ (256U) + +#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U) +#error "The USB max FIFO size is 2048 x 4 Bytes!" +#endif +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_APP_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_bsp.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_bsp.h new file mode 100644 index 00000000000..4c290a7fe80 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_bsp.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __USB_BSP_H__ +#define __USB_BSP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "hc32_ll_utility.h" + +extern void usb_udelay(const uint32_t usec); +extern void usb_mdelay(const uint32_t msec); + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_BSP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/drv_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/drv_config.h new file mode 100644 index 00000000000..978dbbea3c3 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/drv_config.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dma_config.h" +#include "uart_config.h" +#include "spi_config.h" +#include "adc_config.h" +#include "dac_config.h" +#include "gpio_config.h" +#include "eth_config.h" +#include "can_config.h" +#include "sdio_config.h" +#include "pm_config.h" +#include "i2c_config.h" +#include "qspi_config.h" +#include "pulse_encoder_config.h" +#include "timer_config.h" +#include "tmr_capture_config.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/hc32f4xx_conf.h new file mode 100644 index 00000000000..15eb1d955c4 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/hc32f4xx_conf.h @@ -0,0 +1,174 @@ +/** + ******************************************************************************* + * @file hc32f4xx_conf.h + * @brief This file contains HC32 Series Device Driver Library usage management. + @verbatim + Change Logs: + Date Author Notes + 2026-05-27 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_CONF_H__ +#define __HC32F4XX_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @brief This is the list of modules to be used in the Device Driver Library. + * Select the modules you need to use to DDL_ON. + * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + * properly. + * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + * Library. + * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + */ +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_DMC_ENABLE (DDL_ON) +#define LL_DVP_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_ETH_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_FMAC_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_HRPWM_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_I2S_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MAU_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_NFC_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SDIOC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR2_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F4A2_LQFP176 (1U) + +/** + * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to 0U. + */ +#define BSP_EV_HC32F4XX (0U) + +/** + * @brief This is the list of BSP components to be used. + * Select the components you need to use to DDL_ON. + */ +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_GT9XX_ENABLE (DDL_OFF) +#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF) +#define BSP_IS62WV51216_ENABLE (DDL_OFF) +#define BSP_MT29F2G08AB_ENABLE (DDL_OFF) +#define BSP_NT35510_ENABLE (DDL_OFF) +#define BSP_OV5640_ENABLE (DDL_OFF) +#define BSP_TCA9539_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_WM8731_ENABLE (DDL_OFF) + +/** + * @brief Ethernet and PHY Configuration. + */ +/* MAC ADDRESS */ +#define ETH_MAC_ADDR0 (0x02U) +#define ETH_MAC_ADDR1 (0x00U) +#define ETH_MAC_ADDR2 (0x00U) +#define ETH_MAC_ADDR3 (0x00U) +#define ETH_MAC_ADDR4 (0x00U) +#define ETH_MAC_ADDR5 (0x00U) + +#if defined (ETH_PHY_USING_RTL8201F) +/* PHY(RTL8201F) Address*/ +#define ETH_PHY_ADDR (0x01U) + +/* PHY Status Register */ +#define PHY_SR (0x00U) /*!< PHY status register */ +#define PHY_DUPLEX_STATUS (0x0100U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS (0x2000U) /*!< PHY Speed mask */ + +#endif + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.icf new file mode 100644 index 00000000000..e81ccd061fa --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.icf @@ -0,0 +1,102 @@ +/***************************************************************************//** + * \file HC32F4A2.icf + * \version 1.0 + * + * \brief Linker file for the IAR compiler. + * +******************************************************************************** +* \copyright + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause +*******************************************************************************/ +/*###ICF### Section handled by ICF editor, don't touch! *****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +// Check that necessary symbols have been passed to linker via command line interface +if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) { + error "Link location not defined or not supported!"; +} + +/******************************************************************************* + * Memory address and size definitions + ******************************************************************************/ +define symbol ram1_base_address = 0x1FFE0000; +define symbol ram1_end_address = 0x2005FFFF; + +if(isdefinedsymbol(_LINK_RAM_)) { + define symbol ram_start_reserve = 0x20000; + define symbol rom1_base_address = ram1_base_address; + define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01; + define symbol rom2_base_address = 0x0; + define symbol rom2_end_address = 0x0; + define symbol rom3_base_address = 0x0; + define symbol rom3_end_address = 0x0; +} else { + define symbol ram_start_reserve = 0x0; + define symbol rom1_base_address = 0x0; + define symbol rom3_base_address = 0x03000000; + define symbol rom3_end_address = 0x030017FF; + define symbol rom1_end_address = 0x001FFFFF; + define symbol rom2_base_address = 0x0; + define symbol rom2_end_address = 0x0; +} + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = rom1_base_address; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address; +define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address; +define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address; +define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address; +define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address; +define symbol __ICFEDIT_region_IROM3_end__ = rom3_end_address; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve; +define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +/******************************************************************************* + * Memory definitions + ******************************************************************************/ +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region OTP_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in OTP_region { readonly section .otp_data }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.ld new file mode 100644 index 00000000000..b364e25999b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.ld @@ -0,0 +1,294 @@ +/****************************************************************************** + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F4A2xI.ld */ +/* Abstract Linker script for HC32F4A2 Device with */ +/* 2MByte FLASH, 516KByte RAM */ +/* Version V1.0 */ +/* Date 2026-05-27 */ +/*****************************************************************************/ +/* OTP section(data sections are not flash multiplexed region) implementation. + You need to pay attention to the size of the specified OTP block. + Take two OTP blocks for example. */ +__OTP_DATA_BASE = 0x03000000; +__OTP_LOCK_BASE = 0x03001800; +/* OTP block 16 */ +__OTP_DATA_B16_START = 0x03000000; +__OTP_LOCK_B16_START = 0x03001840; +__OTP_DATA_B16_OFFSET = __OTP_DATA_B16_START - __OTP_DATA_BASE; +__OTP_LOCK_B16_OFFSET = __OTP_LOCK_B16_START - __OTP_LOCK_BASE; +/* OTP block 17 */ +__OTP_DATA_B17_START = 0x03000800; +__OTP_LOCK_B17_START = 0x03001844; +__OTP_DATA_B17_OFFSET = __OTP_DATA_B17_START - __OTP_DATA_BASE; +__OTP_LOCK_B17_OFFSET = __OTP_LOCK_B17_START - __OTP_LOCK_BASE; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M + OTP_DATA (rx): ORIGIN = 0x03000000, LENGTH = 6K + OTP_LOCK (rx): ORIGIN = 0x03001800, LENGTH = 728 + RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section for CherryUSB. */ + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data : + { + . = ALIGN(4); + . = ORIGIN(OTP_DATA) + __OTP_DATA_B16_OFFSET; + KEEP(*(.otp_b16_data*)) + . = ORIGIN(OTP_DATA) + __OTP_DATA_B17_OFFSET; + KEEP(*(.otp_b17_data*)) + . = ALIGN(4); + } >OTP_DATA + + .otp_lock : + { + . = ALIGN(4); + . = ORIGIN(OTP_LOCK) + __OTP_LOCK_B16_OFFSET; + KEEP(*(.otp_b16_lock*)) + . = ORIGIN(OTP_LOCK) + __OTP_LOCK_B17_OFFSET; + KEEP(*(.otp_b17_lock*)) + . = ALIGN(4); + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + __bss_start = .; + .bss __StackTop (NOLOAD): + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + . = ALIGN(4); + *(.noinit*) + . = ALIGN(4); + } >RAM + __bss_end = .; + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.sct b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.sct new file mode 100644 index 00000000000..0bf7fc8eb14 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.sct @@ -0,0 +1,22 @@ +; **************************************************************** +; Scatter-Loading Description File +; **************************************************************** +LR_IROM1 0x00000000 0x00200000 { ; load region size_region + ER_IROM1 0x00000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x1FFE0000 UNINIT 0x00000008 { ; RW data + *(.bss.noinit) + } + RW_IRAM2 0x1FFE0008 0x0007FFF8 { ; RW data + .ANY (+RW +ZI) + .ANY (RAMCODE) + } + RW_IRAMB 0x200F0000 0x00001000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/fal_cfg.h new file mode 100644 index 00000000000..6eaa4ea0704 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/fal_cfg.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +/* enable hc32f4 onchip flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_HC32F4 +/* enable SFUD flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_SFUD + +extern const struct fal_flash_dev hc32_onchip_flash; +extern struct fal_flash_dev ext_nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ +} + +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 2 * 1024 * 1024, 0}, \ + {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/nand_port.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/nand_port.h new file mode 100644 index 00000000000..fafe65de383 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/nand_port.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __NAND_PORT_H__ +#define __NAND_PORT_H__ + +/******************** NAND chip information ***********************************/ +#define NAND_BYTES_PER_PAGE 2048UL +#define NAND_SPARE_AREA_SIZE 64UL +#define NAND_PAGES_PER_BLOCK 64UL +#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE) +#define NAND_BLOCKS_PER_PLANE 1024UL +#define NAND_PLANE_PER_DEVICE 2UL +#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE) +#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK) + +/******************** EXMC_NFC configure **************************************/ +/* chip: EXMC_NFC_BANK0~7 */ +#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0 + +/* density:2Gbit */ +#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT + +/* device width: 8-bit */ +#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT + +/* BankNum: 1BANK */ +#define NAND_EXMC_NFC_BANK_NUMBER EXMC_NFC_1BANK + +/* page size: 2KByte */ +#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE + +/* row address cycle: 3 */ +#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE + +/* ECC mode */ +#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC + +/* timing configuration(EXCLK clock frequency: 60MHz@3.3V) for MT29F2G08AB */ +/* TS: ALE/CLE/CE setup time(min=10ns) */ +#define NAND_TS 1U + +/* TWP: WE# pulse width (min=10ns) */ +#define NAND_TWP 1U + +/* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */ +#define NAND_TRP 2U + +/* TTH: ALE/CLE/CE hold time (min=5ns) */ +#define NAND_TH 1U + +/* TWH: WE# pulse width HIGH (min=10ns) */ +#define NAND_TWH 1U + +/* TRH: RE# pulse width HIGH (min=7ns) */ +#define NAND_TRH 1U + +/* TRR: Ready to RE# LOW (min=20ns) */ +#define NAND_TRR 2U + +/* TWB: WE# HIGH to busy (max=100ns) */ +#define NAND_TWB 1U + +/* TWB: WE# HIGH to busy (max=100ns) */ +#define NAND_TRB 1U + +/* TCCS: Change read column and Change write column delay */ +#define NAND_TCCS 5U + +/* TWTR: WE# HIGH to RE# LOW (min=60ns) */ +#define NAND_TWTR 4U + +/* TRTW: RE# HIGH to WE# LOW (min=100ns) */ +#define NAND_TRTW 7U + +/* TADL: ALE to data start (min=70ns) */ +#define NAND_TADL 5U + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/sdram_port.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/sdram_port.h new file mode 100644 index 00000000000..ef38f5ae49e --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/sdram_port.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __SDRAM_PORT_H__ +#define __SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ + +/* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */ +#define SDRAM_CHIP EXMC_DMC_CHIP1 +/* bank address */ +#define SDRAM_BANK_ADDR (0x80000000UL) +/* size(kbyte):8MB = 8*1024*1KBytes */ +#define SDRAM_SIZE (8UL * 1024UL * 1024UL) +/* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */ +#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 +/* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */ +#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT +/* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */ +#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM8 +/* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */ +#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM12 +/* cas latency clock number: 2, 3 */ +#define SDRAM_CAS_LATENCY 2UL +/* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */ +#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT + +/* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */ +#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD +/* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */ +#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL +/* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */ +#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED + +/* timing configuration(EXCLK clock frequency: 30MHz) for IS42S16400J-7TLI */ +/* refresh rate counter (EXCLK clock) */ +#define SDRAM_REFRESH_COUNT (450U) +/* TMDR: mode register command time (EXCLK clock) */ +#define SDRAM_TMDR 2U +/* TRAS: RAS to precharge delay time (EXCLK clock) */ +#define SDRAM_TRAS 2U +/* TRC: active bank x to active bank x delay time (EXCLK clock) */ +#define SDRAM_TRC 2U +/* TRCD: RAS to CAS minimum delay time (EXCLK clock) */ +#define SDRAM_TRCD_B 3U +#define SDRAM_TRCD_P 0U +/* TRFC: autorefresh command time (EXCLK clock) */ +#define SDRAM_TRFC_B 3U +#define SDRAM_TRFC_P 0U +/* TRP: precharge to RAS delay time (EXCLK clock) */ +#define SDRAM_TRP_B 3U +#define SDRAM_TRP_P 0U +/* TRRD: active bank x to active bank y delay time (EXCLK clock) */ +#define SDRAM_TRRD 1U +/* TWR: write to precharge delay time (EXCLK clock). */ +#define SDRAM_TWR 2U +/* TWTR: write to read delay time (EXCLK clock). */ +#define SDRAM_TWTR 1U +/* TXP: exit power-down command time (EXCLK clock). */ +#define SDRAM_TXP 1U +/* TXSR: exit self-refresh command time (EXCLK clock). */ +#define SDRAM_TXSR 5U +/* TESR: self-refresh command time (EXCLK clock). */ +#define SDRAM_TESR 5U + +/* memory mode register */ +#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) +#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) +#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) +#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) +#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) +#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/tca9539_port.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/tca9539_port.h new file mode 100644 index 00000000000..77e79072e71 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/tca9539_port.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __TCA9539_PORT_H__ +#define __TCA9539_PORT_H__ + +#include "tca9539.h" + +/** + * @defgroup HC32F4A2_EV_IO_Function_Sel Expand IO function definition + * @{ + */ +#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ +#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ +#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */ +#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */ +#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */ +#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */ +#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ + +#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */ +#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */ +#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ +#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ +#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +/** + * @} + */ + +/** + * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition + * @{ + */ +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) +/** + * @} + */ + +/** + * @defgroup BSP CAN PHY STB port/pin definition + * @{ + */ +#define CAN_STB_PORT (TCA9539_IO_PORT1) +#define CAN_STB_PIN (EIO_CAN_STB) +/** + * @} + */ +/** + * @defgroup BSP_ETH_PortPin_Sel BSP ETH port/pin definition + * @{ + */ +#define ETH_RST_PORT (TCA9539_IO_PORT1) +#define ETH_RST_PIN (EIO_ETH_RST) +/** + * @} + */ +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/usb_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/usb_config.h new file mode 100644 index 00000000000..7176f9f25aa --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/usb_config.h @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +/* ================ USB common Configuration ================ */ + +#ifdef __RTTHREAD__ + #include + + #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else + #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#endif + +#ifndef CONFIG_USB_DBG_LEVEL + #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +// #define CONFIG_USB_DCACHE_ENABLE + +/* data align size when use dma or use dcache */ +#ifdef CONFIG_USB_DCACHE_ENABLE + #define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#else + #define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* use usb_memcpy default for high performance but cost more flash memory. + * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4. +*/ +// #define CONFIG_USB_MEMCPY_DISABLE + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN + #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +/* enable advance desc register api */ +#define CONFIG_USBDEV_ADVANCE_DESC + +/* move ep0 setup handler from isr to thread */ +// #define CONFIG_USBDEV_EP0_THREAD + +#ifndef CONFIG_USBDEV_EP0_PRIO + #define CONFIG_USBDEV_EP0_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_EP0_STACKSIZE + #define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN + #define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE + #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING + #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING + #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING + #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ +// #define CONFIG_USBDEV_MSC_POLLING + +/* move msc read & write from isr to thread */ +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO + #define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE + #define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE + #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS + #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME + #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#endif + +#define CONFIG_USBDEV_MTP_THREAD + +#ifndef CONFIG_USBDEV_MTP_PRIO + #define CONFIG_USBDEV_MTP_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MTP_STACKSIZE + #define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE + #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE + #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID + #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC + #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP +#define CONFIG_USBDEV_CDC_ECM_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO + #define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE + #define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE + #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN + #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT + #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT + #define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS + #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM + #define CONFIG_USBDEV_EP_NUM 8 +#endif + +// #define CONFIG_USBDEV_SOF_ENABLE + +/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, + * the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. + * +*/ +//#define CONFIG_USB_HS + +/* ---------------- DWC2 Configuration ---------------- */ +/* enable dwc2 buffer dma mode for device +*/ +// #define CONFIG_USB_DWC2_DMA_ENABLE + +/* Defined FS Core device FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE (32) + +/* Defined FS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) + +/* Defined FS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (640) + +/* Defined HS Core Device FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE (1024) +#define CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE (0) + +/* Defined HS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE (512) +#define CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE (256) + +/* Defined HS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE (2048) + + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS + #define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM + #define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f4a2_lqfp176/bsp_compile_ci.bat new file mode 100644 index 00000000000..c0cd921b13b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/bsp_compile_ci.bat @@ -0,0 +1,132 @@ +scons --attach=devices.adc +scons -j4 +scons --attach=default + +scons --attach=devices.can +scons -j4 +scons --attach=default + +scons --attach=devices.crypto +scons -j4 +scons --attach=default + +scons --attach=devices.dac +scons -j4 +scons --attach=default + +scons --attach=devices.flash +scons -j4 +scons --attach=default + +scons --attach=devices.gpio +scons -j4 +scons --attach=default + +scons --attach=devices.clock_timer +scons -j4 +scons --attach=default + +scons --attach=devices.i2c +scons -j4 +scons --attach=default + +scons --attach=devices.input_capture +scons -j4 +scons --attach=default + +scons --attach=devices.pm +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr4 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.qspi +scons -j4 +scons --attach=default + +scons --attach=devices.rtc +scons -j4 +scons --attach=default + +scons --attach=devices.sdio +scons -j4 +scons --attach=default + +scons --attach=devices.soft_i2c +scons -j4 +scons --attach=default + +scons --attach=devices.spi +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v1 +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v2 +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_host +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_host +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_swdt +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_wdt +scons -j4 +scons --attach=default + + +scons --attach=peripheral.eth_mii +scons -j4 +scons --attach=default + +scons --attach=peripheral.eth_rmii +scons -j4 +scons --attach=default + +scons --attach=peripheral.exmc_nand +scons -j4 +scons --attach=default + +scons --attach=peripheral.exmc_sdram +scons -j4 +scons --attach=default + +scons --attach=peripheral.spi_flash +scons -j4 +scons --attach=default diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/figures/board.jpg b/bsp/hc32/ev_hc32f4a2_lqfp176/figures/board.jpg new file mode 100644 index 00000000000..d2e4505dd65 Binary files /dev/null and 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2 -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM)) + + + 0 + JL2CM3 + -U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/project.uvprojx b/bsp/hc32/ev_hc32f4a2_lqfp176/project.uvprojx new file mode 100644 index 00000000000..b14b2030b43 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/project.uvprojx @@ -0,0 +1,1351 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
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+ + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + HC32F4A2-LL + + + hc32_ll.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll.c + + + + + hc32_ll_aos.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_aos.c + + + + + hc32_ll_clk.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_clk.c + + + + + hc32_ll_dma.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_dma.c + + + + + hc32_ll_efm.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_efm.c + + + + + hc32_ll_fcg.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_fcg.c + + + + + hc32_ll_gpio.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_gpio.c + + + + + hc32_ll_icg.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_icg.c + + + + + hc32_ll_interrupts.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_interrupts.c + + + + + hc32_ll_pwc.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_pwc.c + + + + + hc32_ll_rmu.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_rmu.c + + + + + hc32_ll_sram.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_sram.c + + + + + hc32_ll_utility.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_utility.c + + + + + hc32f4a2_ll_interrupts_share.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32f4a2_ll_interrupts_share.c + + + + + hc32_ll_usart.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_usart.c + + + + + hc32_ll_tmr0.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_tmr0.c + + + + + hc32_ll_i2c.c + 1 + packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_i2c.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + defunct.c + 1 + ..\..\..\src\defunct.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + Libc + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + + + Libraries + + + system_hc32f4a2.c + 1 + packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f4a2\Source\system_hc32f4a2.c + + + + + startup_hc32f4a2.s + 2 + packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f4a2\Source\ARM\startup_hc32f4a2.s + + + + + Platform + + + tca9539.c + 1 + ..\platform\tca9539\tca9539.c + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.h b/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.h new file mode 100644 index 00000000000..26d583f8724 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.h @@ -0,0 +1,446 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 24 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define ARCH_USING_HW_ATOMIC_8 +#define ARCH_USING_HW_ATOMIC_16 +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +#define PKG_USING_HC32F4_CMSIS_DRIVER +#define PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_HC32F4_SERIES_DRIVER +#define PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_HC32 +#define SOC_SERIES_HC32F4 + +/* Hardware Drivers Config */ + +#define SOC_HC32F4A2SI + +/* On-chip Drivers */ + +#define BSP_USING_ON_CHIP_FLASH_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH +/* end of On-chip Drivers */ + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_TCA9539 +#define BSP_USING_EXT_IO +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 +#define BSP_USING_I2C +#define BSP_USING_I2C_HW +#define BSP_USING_I2C1 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.py b/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.py new file mode 100644 index 00000000000..0af49fd02b7 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + else: + EXEC_PATH = r'C:/Users/XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/template.ewp b/bsp/hc32/ev_hc32f4a2_lqfp176/template.ewp new file mode 100644 index 00000000000..8283992a555 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/template.ewp @@ -0,0 +1,1927 @@ + + + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/template.eww b/bsp/hc32/ev_hc32f4a2_lqfp176/template.eww new file mode 100644 index 00000000000..bd036bb4c98 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvoptx b/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvoptx new file mode 100644 index 00000000000..5c85161ee63 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2 -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM)) + + + 0 + JL2CM3 + -U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvprojx b/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvprojx new file mode 100644 index 00000000000..6e4e85d5eb5 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvprojx @@ -0,0 +1,390 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F4A2SITB + HDSC + HDSC.HC32F4A2.1.0.8 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM(0x00000000,0x200000) IRAM(0x1FFE0000,0x80000) IRAM2(0X200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(240000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2 -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM)) + 0 + $$Device:HC32F4A2SITB$Device\Include\HC32F4A2SITB.h + + + + + + + + + + ./packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f4a2/Source/ARM/sfr/HC32F4A2.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFE0000 + 0x80000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x03000000 + 0x1800 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFE0000 + 0x80000 + + + 0 + 0x200F0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFE0000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml index e5798b47293..66e9f4c0b4b 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml @@ -29,11 +29,11 @@ devices.flash: - CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_SFUD=y devices.gpio: - kconfig: + kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/README.md b/bsp/hc32/ev_hc32f4a8_lqfp176/README.md index 65d551688a7..a9354c0e4e6 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/README.md +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/README.md @@ -52,7 +52,7 @@ EV_F4A8_LQ176 开发板常用 **板载资源** 如下： | DAC | 支持 | | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1...PI13 ---> PIN：0，1...141 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | MCAN | 支持 | | diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/nand_port.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/nand_port.h index 72c413d13da..a39a56709f8 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/nand_port.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/nand_port.h @@ -32,6 +32,9 @@ /* device width: 8-bit */ #define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT +/* BankNum: 1BANK */ +#define NAND_EXMC_NFC_BANK_NUMBER EXMC_NFC_1BANK + /* page size: 2KByte */ #define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.h b/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.h index cd2e4633170..a577e37d9bb 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 24 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h index 34b62b6fa3b..2b48008bc57 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h @@ -31,6 +31,9 @@ /* device width: 8-bit */ #define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT +/* BankNum: 1BANK */ +#define NAND_EXMC_NFC_BANK_NUMBER EXMC_NFC_1BANK + /* page size: 2KByte */ #define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h index 8d502df1467..d5d902a424e 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 24 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 diff --git a/bsp/hc32/libraries/hc32_drivers/drv_adc.c b/bsp/hc32/libraries/hc32_drivers/drv_adc.c index e4de8623d9e..38482fcd606 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_adc.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_adc.c @@ -10,6 +10,8 @@ * 2022-06-14 CDT fix a bug of internal trigger * 2024-02-20 CDT support HC32F448 * add function for associating with the dma + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-05 CDT support HC32F467 */ #include @@ -87,7 +89,7 @@ static void _adc_internal_trigger0_set(adc_device *p_adc_dev) case (rt_uint32_t)CM_ADC2: u32TriggerSel = AOS_ADC2_0; break; -#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) || defined (HC32F467) case (rt_uint32_t)CM_ADC3: u32TriggerSel = AOS_ADC3_0; break; @@ -118,7 +120,7 @@ static void _adc_internal_trigger1_set(adc_device *p_adc_dev) case (rt_uint32_t)CM_ADC2: u32TriggerSel = AOS_ADC2_1; break; -#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) || defined (HC32F467) case (rt_uint32_t)CM_ADC3: u32TriggerSel = AOS_ADC3_1; break; @@ -215,6 +217,10 @@ static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt (void)DMA_ChCmd(adc_eoca_dma->Instance, adc_eoca_dma->channel, DISABLE); rt_ret = -RT_ETIMEOUT; } + else + { + rt_ret = LL_OK; + } if (adc_dev_priv->ops->dma_trig_stop != RT_NULL) { adc_dev_priv->ops->dma_trig_stop(); @@ -355,17 +361,18 @@ int rt_hw_adc_init(void) ADC_TriggerCmd(_g_adc_dev_array[i].instance, ADC_SEQ_A, (en_functional_state_t)_g_adc_dev_array[i].init.hard_trig_enable); ADC_TriggerConfig(_g_adc_dev_array[i].instance, ADC_SEQ_A, _g_adc_dev_array[i].init.hard_trig_src); - if (_g_adc_dev_array[i].init.hard_trig_enable && _g_adc_dev_array[i].init.hard_trig_src != ADC_HARDTRIG_ADTRG_PIN) - { - _adc_internal_trigger0_set(&_g_adc_dev_array[i]); - _adc_internal_trigger1_set(&_g_adc_dev_array[i]); - } if (_g_adc_dev_array[i].init.adc_eoca_dma != RT_NULL) { hc32_adc_dma_config(&_g_adc_dev_array[i]); } + if (_g_adc_dev_array[i].init.hard_trig_enable && _g_adc_dev_array[i].init.hard_trig_src != ADC_HARDTRIG_ADTRG_PIN) + { + _adc_internal_trigger0_set(&_g_adc_dev_array[i]); + _adc_internal_trigger1_set(&_g_adc_dev_array[i]); + } + rt_hw_board_adc_init((void *)_g_adc_dev_array[i].instance); ret = rt_hw_adc_register(&_g_adc_dev_array[i].rt_adc, \ (const char *)_g_adc_dev_array[i].init.name, \ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_can.c b/bsp/hc32/libraries/hc32_drivers/drv_can.c index 9135661fa3a..8fa5692fb82 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_can.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_can.c @@ -9,6 +9,8 @@ * 2022-06-07 xiaoxiaolisunny add hc32f460 series * 2022-06-08 CDT fix a bug of RT_CAN_CMD_SET_FILTER * 2022-06-15 lianghongquan fix bug, CAN_FILTER_COUNT, RT_CAN_CMD_SET_FILTER, interrupt setup and processing. + * 2026-05-27 CDT support HC32F4A2. + * 2026-06-24 CDT Added _can_sendmsg_nonblocking. */ #include "drv_can.h" @@ -20,7 +22,7 @@ #if defined(BSP_USING_CAN1) || defined(BSP_USING_CAN2) || defined(BSP_USING_CAN3) -#if defined(RT_CAN_USING_CANFD) && defined(HC32F460) +#if defined(RT_CAN_USING_CANFD) && (defined (HC32F460) || defined (HC32F467)) #error "Selected mcu does not support canfd!" #endif @@ -28,10 +30,10 @@ #define TSEG1_MAX_FOR_CAN2_0 (65U) #define TSEG2_MIN_FOR_CAN2_0 (1U) #define TSEG2_MAX_FOR_CAN2_0 (8U) -#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F467) #define TSJW_MIN_FOR_CAN2_0 (1U) #define TSJW_MAX_FOR_CAN2_0 (16U) -#elif defined(HC32F460) +#elif defined (HC32F460) #define TSJW_MIN_FOR_CAN2_0 (1U) #define TSJW_MAX_FOR_CAN2_0 (8U) #endif @@ -88,7 +90,7 @@ #endif #define NUM_PRESCALE_MAX (256U) -#if defined(HC32F4A0) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) #define CAN_FILTER_COUNT (16U) #define CAN1_INT_SRC (INT_SRC_CAN1_HOST) #define CAN2_INT_SRC (INT_SRC_CAN2_HOST) @@ -236,7 +238,7 @@ static can_device _g_can_dev_array[] = { {0}, CAN1_INIT_PARAMS, -#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F467) .instance = CM_CAN1, #elif defined (HC32F460) .instance = CM_CAN, @@ -811,7 +813,7 @@ static rt_err_t _canfd_control(can_device *p_can_dev, int cmd, void *arg) CAN_Init(p_can_dev->instance, &p_can_dev->ll_init); p_can_dev->rt_can.config.enable_canfd = argval; argval = (argval > CAN_FRAME_CLASSIC) ? ENABLE : DISABLE; -#if defined(HC32F472) || defined(HC32F4A8) +#if defined (HC32F472) || defined (HC32F4A8) CAN_FD_Cmd(p_can_dev->instance, (en_functional_state_t)argval); #endif break; @@ -965,6 +967,7 @@ static rt_ssize_t _can_sendmsg(struct rt_can_device *can, const void *buf, rt_ui stc_can_tx_frame_t stc_tx_frame = {0}; int32_t ll_ret; + (void)box_num; RT_ASSERT(can != RT_NULL); can_device *p_can_dev = (can_device *)rt_container_of(can, can_device, rt_can); RT_ASSERT(p_can_dev); @@ -1008,6 +1011,11 @@ static rt_ssize_t _can_sendmsg(struct rt_can_device *can, const void *buf, rt_ui return RT_EOK; } +rt_ssize_t _can_sendmsg_nonblocking(struct rt_can_device *can, const void *buf) +{ + return _can_sendmsg(can, buf, 0); +} + static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) { int32_t ll_ret; @@ -1064,6 +1072,7 @@ static const struct rt_can_ops _can_ops = _can_control, _can_sendmsg, _can_recvmsg, + _can_sendmsg_nonblocking, }; rt_inline void _isr_can_rx(can_device *p_can_dev) @@ -1141,10 +1150,14 @@ rt_inline void _isr_can_tx(can_device *p_can_dev) if (need_check_single_trans) { if ((CAN_GetStatus(p_can_dev->instance, CAN_FLAG_BUS_ERR) != SET) \ - || (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST) != SET)) + && (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST) != SET)) { is_tx_done = RT_TRUE; } + else + { + rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_TX_FAIL); + } } if (is_tx_done) { @@ -1153,7 +1166,6 @@ rt_inline void _isr_can_tx(can_device *p_can_dev) if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST) == SET) { - rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_TX_FAIL); CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST); } } @@ -1223,7 +1235,7 @@ static void _irq_handler_can1(void) rt_interrupt_leave(); } -#if defined(HC32F472) +#if defined (HC32F472) void CAN1_Handler(void) { _irq_handler_can1(); @@ -1239,7 +1251,7 @@ static void _irq_handler_can2(void) rt_interrupt_leave(); } -#if defined(HC32F472) +#if defined (HC32F472) void CAN2_Handler(void) { _irq_handler_can2(); @@ -1255,7 +1267,7 @@ static void _irq_handler_can3(void) rt_interrupt_leave(); } -#if defined(HC32F472) +#if defined (HC32F472) void CAN3_Handler(void) { _irq_handler_can3(); @@ -1266,9 +1278,9 @@ void CAN3_Handler(void) static void _enable_can_clock(void) { #if defined(BSP_USING_CAN1) -#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F467) FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN1, ENABLE); -#elif defined(HC32F460) +#elif defined (HC32F460) FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN, ENABLE); #endif #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_crypto.c b/bsp/hc32/libraries/hc32_drivers/drv_crypto.c index 720ddd25728..2a9495c4654 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_crypto.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_crypto.c @@ -8,6 +8,8 @@ * 2023-02-10 CDT first version * 2024-06-11 CDT Fix compiler warning * 2025-07-29 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include "board.h" @@ -47,7 +49,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r /* if crc_cfg change we need init crc again */ if (rt_memcmp(&crc_cfgbk, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg))) { -#if defined(HC32F460) +#if defined (HC32F460) switch (ctx->crc_cfg.flags) { case 0: @@ -93,10 +95,10 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r LOG_E("crc width only support 16/32."); goto _exit; } -#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || \ - defined(HC32F334) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || \ + defined (HC32F334) || defined (HC32F467) stcCrcInit.u32InitValue = ctx->crc_cfg.last_val; -#elif defined(HC32F4A8) +#elif defined (HC32F4A8) stcCrcInit.u64InitValue = ctx->crc_cfg.last_val; #endif if (CRC_Init(&stcCrcInit) != LL_OK) @@ -107,7 +109,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r LOG_D("CRC_Init."); rt_memcpy(&crc_cfgbk, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)); } -#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) if (16U == ctx->crc_cfg.width) { (void)CRC_CRC16_AccumulateData(CRC_DATA_WIDTH_8BIT, in, length, (uint16_t *)&result); @@ -116,7 +118,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r { (void)CRC_CRC32_AccumulateData(CRC_DATA_WIDTH_8BIT, in, length, &result); } -#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) +#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) if (16U == ctx->crc_cfg.width) { result = CRC_CRC16_AccumulateData(CRC_DATA_WIDTH_8BIT, in, length); @@ -359,7 +361,8 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx, struct hwcrypto_symm result = -RT_ERROR; goto _exit; } -#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) +#elif defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F467) if (ctx->key_bitlen != (AES_KEY_SIZE_16BYTE * 8U) && ctx->key_bitlen != (AES_KEY_SIZE_24BYTE * 8U) && \ ctx->key_bitlen != (AES_KEY_SIZE_32BYTE * 8U)) { @@ -472,10 +475,11 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) case HWCRYPTO_TYPE_RC4: case HWCRYPTO_TYPE_GCM: { -#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || \ +defined (HC32F467) /* Enable AES peripheral clock. */ FCG_Fcg0PeriphClockCmd(PWC_FCG0_AES, ENABLE); -#elif defined(HC32F4A8) +#elif defined (HC32F4A8) /* Enable SKE peripheral clock */ FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SKE, ENABLE); #endif @@ -527,10 +531,11 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx) case HWCRYPTO_TYPE_3DES: case HWCRYPTO_TYPE_RC4: case HWCRYPTO_TYPE_GCM: -#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || \ + defined (HC32F467) AES_DeInit(); FCG_Fcg0PeriphClockCmd(PWC_FCG0_AES, DISABLE); -#elif defined(HC32F4A8) +#elif defined (HC32F4A8) SKE_DeInit(); FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SKE, DISABLE); #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_dac.c b/bsp/hc32/libraries/hc32_drivers/drv_dac.c index e2ef22abf49..8165d86600f 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_dac.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_dac.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2023-05-12 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-05 CDT Support HC32F467 */ #include @@ -37,7 +39,7 @@ static dac_device _g_dac_dev_array[] = #ifdef BSP_USING_DAC1 { {0}, -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) CM_DAC1, #elif defined (HC32F448) CM_DAC, @@ -148,7 +150,7 @@ static const struct rt_dac_ops g_dac_ops = static void _dac_clock_enable(void) { #if defined(BSP_USING_DAC1) -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_DAC1, ENABLE); #elif defined (HC32F448) FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_DAC, ENABLE); @@ -180,12 +182,12 @@ int rt_hw_dac_init(void) { DAC_DeInit(_g_dac_dev_array[i].instance); stcDacInit.enOutput = (en_functional_state_t)_g_dac_dev_array[i].init.ch1_output_enable; -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) || defined (HC32F448) || defined (HC32F4A8) stcDacInit.u16Src = _g_dac_dev_array[i].init.ch1_data_src; #endif ll_ret = DAC_Init((void *)_g_dac_dev_array[i].instance, DAC_CH1, &stcDacInit); -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F460) -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F460) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) || defined (HC32F448) || defined (HC32F4A8) stcDacInit.u16Src = _g_dac_dev_array[i].init.ch2_data_src; #endif stcDacInit.enOutput = _g_dac_dev_array[i].init.ch2_output_enable; @@ -213,7 +215,7 @@ int rt_hw_dac_init(void) DAC_SetAmpGain(_g_dac_dev_array[i].instance, DAC_CH2, _g_dac_dev_array[i].init.ch2_amp_gain); #endif DAC_AMPCmd(_g_dac_dev_array[i].instance, DAC_CH1, (en_functional_state_t)_g_dac_dev_array[i].init.ch1_amp_enable); -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F460) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F460) DAC_AMPCmd(_g_dac_dev_array[i].instance, DAC_CH2, _g_dac_dev_array[i].init.ch2_amp_enable); #elif defined (HC32F334) if (CM_DAC1 == (void *)_g_dac_dev_array[i].instance) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_dac.h b/bsp/hc32/libraries/hc32_drivers/drv_dac.h index 8918b63fd27..558904005cf 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_dac.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_dac.h @@ -36,7 +36,7 @@ struct dac_dev_init_params This parameter can be a value of @ref DAC_ADP_SELECT */ rt_bool_t ch1_output_enable; rt_bool_t ch2_output_enable; -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) || defined (HC32F448) || defined (HC32F4A8) uint16_t ch1_data_src; uint16_t ch2_data_src; #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_flash/drv_flash_f4.c b/bsp/hc32/libraries/hc32_drivers/drv_flash/drv_flash_f4.c index 30c02cee549..79f5f15034d 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_flash/drv_flash_f4.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_flash/drv_flash_f4.c @@ -9,6 +9,8 @@ * 2024-06-14 CDT Fixed sector number calculation * 2024-06-18 CDT Support HC32F460,HC32F448,HC32F472 * 2025-07-16 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include "board.h" @@ -81,7 +83,8 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) rt_err_t result = RT_EOK; rt_uint32_t newAddr = addr, offsetVal = 0; rt_uint32_t index = 0, u32Cnt = 0; -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) rt_uint32_t FirstSector = 0, NumOfSectors = 0; #endif @@ -101,7 +104,8 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) } /* EFM_FWMC write enable */ EFM_FWMC_Cmd(ENABLE); -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) /* calculate sector information */ FirstSector = addr / EFM_SECTOR_SIZE, NumOfSectors = GetSectorNum(addr, size); @@ -144,7 +148,8 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) } __exit: -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) /* Sectors enable write protection */ EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, DISABLE); #endif @@ -170,7 +175,8 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size) rt_err_t result = RT_EOK; rt_uint32_t NumOfSectors = 0; rt_uint32_t SectorVal = 0, u32Addr = addr; -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) rt_uint32_t FirstSector = 0; #endif @@ -188,7 +194,8 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size) EFM_FWMC_Cmd(ENABLE); /* calculate sector information */ NumOfSectors = GetSectorNum(addr, size); -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) FirstSector = addr / EFM_SECTOR_SIZE, /* Sectors disable write protection */ EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, ENABLE); @@ -203,7 +210,8 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size) } u32Addr += EFM_SECTOR_SIZE; } -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) /* Sectors enable write protection */ EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, DISABLE); #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c index a7217ec9e15..5e89765e1a8 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c @@ -9,6 +9,8 @@ * 2023-10-09 CDT support HC32F448 * 2024-06-12 CDT support external interrupt for HC32F448/HC32F472 * 2025-07-16 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include @@ -25,7 +27,7 @@ #define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) & 0x0F)) #define GPIO_PIN(pin) ((uint16_t)(0x01U << GPIO_PIN_INDEX(pin))) -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) #define PIN_MAX_NUM ((GPIO_PORT_I * 16) + (__CLZ(__RBIT(GPIO_PIN_13))) + 1) #elif defined (HC32F460) #define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_irq.c b/bsp/hc32/libraries/hc32_drivers/drv_irq.c index 501717d5d37..18f45f5a80d 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_irq.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_irq.c @@ -8,6 +8,7 @@ * 2022-04-28 CDT first version * 2024-06-07 CDT Modify the IRQ install implementation for F448/F472 * 2025-07-16 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 */ /******************************************************************************* @@ -67,13 +68,13 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, stcIrqSignConfig.enIntSrc = irq_config->int_src; stcIrqSignConfig.pfnCallback = irq_hdr; if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig)) -#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +nvic_config: +#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) stcIrqSignConfig.enIRQn = irq_config->irq_num; stcIrqSignConfig.enIntSrc = irq_config->int_src; stcIrqSignConfig.pfnCallback = irq_hdr; if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig)) #endif -nvic_config: { NVIC_ClearPendingIRQ(irq_config->irq_num); NVIC_SetPriority(irq_config->irq_num, irq_config->irq_prio); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_mcan.c b/bsp/hc32/libraries/hc32_drivers/drv_mcan.c index 5dc0217c1f9..72041bc518f 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_mcan.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_mcan.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2024-xx-xx CDT first version + * 2026-06-24 CDT Added _can_sendmsg_nonblocking. Fixed comments. */ #include "drv_mcan.h" @@ -26,7 +27,7 @@ typedef struct hc32_mcan_config_struct uint32_t int0_sel; struct hc32_irq_config int0_cfg; /* MCAN interrupt line 0 configuration */ -#if defined(HC32F4A8) +#if defined (HC32F4A8) func_ptr_t irq_callback0; #endif } hc32_mcan_config_t; @@ -186,43 +187,50 @@ static hc32_mcan_driver_t m_mcan_driver_list[] = ****************************************************************************************/ /** * @brief Configure CAN controller - * @param [in/out] can CAN device pointer + * @param [inout] device CAN device pointer * @param [in] cfg CAN configuration pointer - * @retval RT_EOK for valid configuration - * @retval -RT_ERROR for invalid configuration + * @retval RT_EOK No error + * @retval An error code on failure */ static rt_err_t mcan_configure(struct rt_can_device *device, struct can_configure *cfg); /** * @brief Control/Get CAN state * including:interrupt, mode, priority, baudrate, filter, status - * @param [in/out] can CAN device pointer + * @param [inout] device CAN device pointer * @param [in] cmd Control command - * @param [in/out] arg Argument pointer - * @retval RT_EOK for valid control command and arg - * @retval -RT_ERROR for invalid control command or arg + * @param [inout] arg Argument pointer + * @retval RT_EOK No error + * @retval An error code on failure */ static rt_err_t mcan_control(struct rt_can_device *device, int cmd, void *arg); /** * @brief Send out CAN message - * @param [in] can CAN device pointer + * @param [inout] device CAN device pointer * @param [in] buf CAN message buffer * @param [in] boxno Mailbox number, it is not used in this porting * @retval RT_EOK No error - * @retval -RT_ETIMEOUT timeout happened - * @retval -RT_EFULL Transmission buffer is full + * @retval An error code on failure */ static rt_ssize_t mcan_sendmsg(struct rt_can_device *device, const void *buf, rt_uint32_t boxno); +/** + * @brief Send out CAN message non-blocking + * @param [inout] device CAN device pointer + * @param [in] buf CAN message buffer + * @retval RT_EOK No error + * @retval An error code on failure + */ +static rt_ssize_t mcan_sendmsg_nonblocking(struct rt_can_device *device, const void *buf); + /** * @brief Receive message from CAN * @param [in] can CAN device pointer * @param [out] buf CAN receive buffer * @param [in] boxno Mailbox Number, it is not used in this porting - * @retval RT_EOK no error - * @retval -RT_ERROR Error happened during reading receive FIFO - * @retval -RT_EMPTY no data in receive FIFO + * @retval RT_EOK No error + * @retval An error code on failure */ static rt_ssize_t mcan_recvmsg(struct rt_can_device *device, void *buf, rt_uint32_t boxno); @@ -236,6 +244,7 @@ static const struct rt_can_ops m_mcan_ops = mcan_control, mcan_sendmsg, mcan_recvmsg, + mcan_sendmsg_nonblocking, }; /**************************************************************************************** @@ -763,6 +772,11 @@ static rt_ssize_t mcan_sendmsg(struct rt_can_device *device, const void *buf, rt return RT_EOK; } +static rt_ssize_t mcan_sendmsg_nonblocking(struct rt_can_device *device, const void *buf) +{ + return mcan_sendmsg(device, buf, 0); +} + /**************************************************************************************** * mcan receive message ****************************************************************************************/ @@ -951,7 +965,7 @@ rt_inline void mcan_isr(hc32_mcan_driver_t *driver, uint32_t int_sel) /**************************************************************************************** * mcan irq handler ****************************************************************************************/ -#if defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) +#if defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) #if defined(BSP_USING_MCAN1) void MCAN1_INT0_Handler(void) { @@ -984,12 +998,12 @@ void MCAN2_INT0_Handler(void) ****************************************************************************************/ static void mcan_irq_config(hc32_mcan_config_t *hard) { -#if defined(HC32F448) || defined(HC32F334) +#if defined (HC32F448) || defined (HC32F334) if (hard->int0_sel != 0) { hc32_install_irq_handler(&hard->int0_cfg, RT_NULL, RT_TRUE); } -#elif defined(HC32F4A8) +#elif defined (HC32F4A8) if (hard->int0_sel != 0) { hc32_install_irq_handler(&hard->int0_cfg, hard->irq_callback0, RT_TRUE); @@ -999,14 +1013,14 @@ static void mcan_irq_config(hc32_mcan_config_t *hard) static void mcan_enable_periph_clock(void) { -#if defined(HC32F448) || defined(HC32F4A8) +#if defined (HC32F448) || defined (HC32F4A8) #if defined(BSP_USING_MCAN1) FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_MCAN1, ENABLE); #endif #if defined(BSP_USING_MCAN2) FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_MCAN2, ENABLE); #endif -#elif defined(HC32F334) +#elif defined (HC32F334) #if defined(BSP_USING_MCAN1) || defined(BSP_USING_MCAN2) FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_MCAN1 | FCG1_PERIPH_MCAN2, ENABLE); #endif @@ -1120,7 +1134,7 @@ static void init_can_cfg(hc32_mcan_driver_t *driver) driver->can_device.config = can_cfg; } -#if defined(HC32F4A8) +#if defined (HC32F4A8) /** * @brief This function gets mcan irq handle. * @param None @@ -1147,7 +1161,7 @@ static int rt_hw_mcan_init(void) mcan_enable_periph_clock(); mcan_set_init_para(); -#if defined(HC32F4A8) +#if defined (HC32F4A8) mcan_get_irq_callback(); #endif for (i = 0; i < MCAN_DEV_CNT; i++) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_nand.c b/bsp/hc32/libraries/hc32_drivers/drv_nand.c index d7dccd7f7a7..fa036a4d820 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_nand.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_nand.c @@ -6,7 +6,9 @@ * Change Logs: * Date Author Notes * 2023-03-01 CDT first version - * 2042-12-24 CDT fix compiler warning + * 2024-12-24 CDT fix compiler warning + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-05 CDT support HC32F467 */ @@ -84,7 +86,7 @@ static rt_err_t _nand_verify_clock_frequency(void) { rt_err_t ret = RT_EOK; -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) /* EXCLK max frequency for Nand: 60MHz */ if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > (60 * 1000000)) { @@ -128,7 +130,7 @@ static rt_err_t _nand_init(struct rt_mtd_nand_device *device) nfc_init_params.u32OpenPage = EXMC_NFC_OPEN_PAGE_DISABLE; nfc_init_params.stcBaseConfig.u32CapacitySize = NAND_EXMC_NFC_BANK_CAPACITY; nfc_init_params.stcBaseConfig.u32MemoryWidth = NAND_EXMC_NFC_MEMORY_WIDTH; - nfc_init_params.stcBaseConfig.u32BankNum = EXMC_NFC_1BANK; + nfc_init_params.stcBaseConfig.u32BankNum = NAND_EXMC_NFC_BANK_NUMBER; nfc_init_params.stcBaseConfig.u32PageSize = NAND_EXMC_NFC_PAGE_SIZE; nfc_init_params.stcBaseConfig.u32WriteProtect = EXMC_NFC_WR_PROTECT_DISABLE; nfc_init_params.stcBaseConfig.u32EccMode = NAND_EXMC_NFC_ECC_MD; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pm.c b/bsp/hc32/libraries/hc32_drivers/drv_pm.c index cc84e14200a..ff257c1f4b9 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_pm.c @@ -7,6 +7,9 @@ * Date Author Notes * 2023-06-12 CDT first version * 2024-06-14 CDT Move common function SysTick_Configuration to _pm_run + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-04 CDT Support HC32F467 + * 2026-06-24 CDT rt_system_pm_init parameter timer_mask change to 0 for unsupport pm tickless timer */ #include @@ -72,7 +75,7 @@ static void _sleep_enter_deep(void) (void)PWC_STOP_Config(&sleep_deep_cfg.cfg); -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F460) || defined (HC32F467) || defined (HC32F448) || defined (HC32F4A8) if (PWC_PWRC2_DVS == (READ_REG8(CM_PWC->PWRC2) & PWC_PWRC2_DVS)) { CLR_REG8_BIT(CM_PWC->PWRC1, PWC_PWRC1_STPDAS); @@ -128,7 +131,7 @@ static void _run_switch_high_to_low(void) st_run_mode_cfg.sys_clk_cfg(PM_RUN_MODE_LOW_SPEED); -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F460) || defined (HC32F467) || defined (HC32F448) || defined (HC32F4A8) PWC_HighSpeedToLowSpeed(); #endif } @@ -137,7 +140,7 @@ static void _run_switch_low_to_high(void) { struct pm_run_mode_config st_run_mode_cfg = PM_RUN_MODE_CFG; -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F460) || defined (HC32F467) || defined (HC32F448) || defined (HC32F4A8) PWC_LowSpeedToHighSpeed(); #endif @@ -229,9 +232,8 @@ int rt_hw_pm_init(void) _timer_get_tick, }; - rt_uint8_t timer_mask = PM_TICKLESS_TIMER_ENABLE_MASK; /* initialize system pm module */ - rt_system_pm_init(&_ops, timer_mask, RT_NULL); + rt_system_pm_init(&_ops, 0U, RT_NULL); return 0; } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pm.h b/bsp/hc32/libraries/hc32_drivers/drv_pm.h index cba3d8f0669..d8c40f31a6c 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pm.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_pm.h @@ -89,15 +89,15 @@ struct pm_sleep_mode_shutdown_config /******************************************************************************* * Global pre-processor symbols/macros ('#define') ******************************************************************************/ -#if defined(HC32F4A0) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) #define PM_CHECK_EFM() ((EFM_GetStatus(EFM_FLAG_RDY) == SET) && (EFM_GetStatus(EFM_FLAG_RDY1) == SET)) -#elif defined(HC32F460) || defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined (HC32F460) || defined (HC32F448) || defined (HC32F472) || defined (HC32F334) || defined (HC32F467) #define PM_CHECK_EFM() ((EFM_GetStatus(EFM_FLAG_RDY) == SET)) #endif #define PM_CHECK_XTAL() ((CM_CMU->XTALSTDCR & CLK_XTALSTD_ON) == 0) -#if defined(HC32F334) +#if defined (HC32F334) #define PM_CHECK_DMA() (DMA_GetTransStatus(CM_DMA, DMA_STAT_TRANS_DMA) == RESET) -#elif defined(HC32F4A0) || defined(HC32F4A8) || defined(HC32F460) || defined (HC32F448) || defined (HC32F472) +#elif defined (HC32F467) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F460) || defined (HC32F448) || defined (HC32F472) #define PM_CHECK_DMA() \ ( (DMA_GetTransStatus(CM_DMA1, DMA_STAT_TRANS_DMA) == RESET) && \ (DMA_GetTransStatus(CM_DMA2, DMA_STAT_TRANS_DMA) == RESET)) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pwm.c b/bsp/hc32/libraries/hc32_drivers/drv_pwm.c index bfad2524123..1feb1cae27f 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pwm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_pwm.c @@ -9,6 +9,8 @@ * 2023-02-22 CDT support HC32F4A0 * 2024-11-20 CDT support HC32F448 * 2025-01-03 CDT support HC32F472 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ #include @@ -25,9 +27,10 @@ #if defined(BSP_USING_PWM_TMRA) -#if defined(HC32F460) || defined(HC32F448) +#if defined (HC32F460) || defined (HC32F448) #define TMRA_CHANNEL_NUM_MAX 8U -#elif defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#elif defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) #define TMRA_CHANNEL_NUM_MAX 4U #endif @@ -129,7 +132,8 @@ static rt_uint32_t tmra_get_clk_notdiv(CM_TMRA_TypeDef *TMRAx) rt_uint32_t u32clkFreq; rt_uint32_t u32BusName; -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) switch ((rt_uint32_t)TMRAx) { case (rt_uint32_t)CM_TMRA_1: @@ -142,7 +146,7 @@ static rt_uint32_t tmra_get_clk_notdiv(CM_TMRA_TypeDef *TMRAx) u32BusName = CLK_BUS_PCLK1; /* Uint5-12 */ break; } -#elif defined(HC32F460) +#elif defined (HC32F460) u32BusName = CLK_BUS_PCLK1; #endif u32clkFreq = CLK_GetBusClockFreq(u32BusName); @@ -682,7 +686,8 @@ static struct rt_pwm_ops _tmra_ops = #endif /* BSP_USING_PWM_TMRA */ #if defined(BSP_USING_PWM_TMR4) -#if defined (HC32F4A8) || defined (HC32F472) || defined (HC32F4A0) || defined (HC32F460) +#if defined (HC32F4A8) || defined (HC32F472) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F460) || \ + defined (HC32F467) #define TMR4_CHANNEL_NUM_MAX 6U #elif defined (HC32F448) || defined (HC32F334) #define TMR4_CHANNEL_NUM_MAX 8U @@ -730,10 +735,11 @@ static struct hc32_pwm_tmr4 g_pwm_tmr4_array[] = static rt_uint32_t tmr4_get_clk_notdiv(CM_TMR4_TypeDef *TMR4x) { - rt_uint32_t u32clkFreq; -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) + rt_uint32_t u32clkFreq = 0UL; +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) u32clkFreq = CLK_GetBusClockFreq(CLK_BUS_PCLK0); -#elif defined(HC32F460) +#elif defined (HC32F460) u32clkFreq = CLK_GetBusClockFreq(CLK_BUS_PCLK1); #endif @@ -935,7 +941,7 @@ static rt_err_t tmr4_pwm_set(struct rt_device_pwm *device, struct rt_pwm_configu static void enable_tmr4_unit_clk(void) { #ifdef BSP_USING_PWM_TMR4_1 -#if defined(HC32F472) || defined (HC32F334) +#if defined (HC32F472) || defined (HC32F334) FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR4, ENABLE); #else FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR4_1, ENABLE); @@ -963,13 +969,15 @@ static rt_err_t pwm_tmr4_init(struct hc32_pwm_tmr4 *device) { TMR4_OC_Init(TMR4x, i, &device->stcTmr4OcInit); TMR4_PWM_Init(TMR4x, (i >> 1), &device->stcTmr4PwmInit); -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) TMR4_PWM_SetPortOutputMode(TMR4x, i, TMR4_PWM_PIN_OUTPUT_NORMAL); #endif tmr4_pwm_set_cmpmode(TMR4x, i); } } -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) TMR4_PWM_MainOutputCmd(TMR4x, ENABLE); #endif TMR4_Start(TMR4x); @@ -1207,7 +1215,8 @@ static rt_uint32_t tmr6_get_clk_bydiv(CM_TMR6_TypeDef *TMR6x) case (TMR6_CLK_DIV1024): u32clkFreq /= 1024; break; -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) case (TMR6_CLK_DIV32): u32clkFreq /= 32; break; @@ -1228,17 +1237,19 @@ static void tmr6_duyt100or0_output(CM_TMR6_TypeDef *TMR6x, rt_uint32_t channel, { if (compare_value <= 1) { -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_OVF, TMR6_PWM_LOW); -#elif defined(HC32F460) +#elif defined (HC32F460) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_MATCH_PERIOD, TMR6_PWM_LOW); #endif } else { -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_OVF, TMR6_PWM_HIGH); -#elif defined(HC32F460) +#elif defined (HC32F460) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_MATCH_PERIOD, TMR6_PWM_HIGH); #endif } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_qspi.c b/bsp/hc32/libraries/hc32_drivers/drv_qspi.c index 3e9708c0113..823276e08ba 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_qspi.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_qspi.c @@ -11,6 +11,8 @@ * 2024-02-29 CDT Support multi line write/read * 2024-04-18 CDT support HC32F472 * 2025-04-14 CDT support HC32F4A8 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-10 CDT support HC32F467 */ /******************************************************************************* @@ -312,7 +314,7 @@ static int32_t hc32_qspi_send_cmd(struct hc32_qspi_bus *qspi_bus, struct rt_qspi else #endif { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifndef BSP_QSPI_USING_SOFT_CS if (LL_OK != hc32_qspi_check_direct_comm_param(message, QSPI_DIRECT_COMM_LINE_ONE)) { @@ -376,7 +378,7 @@ static rt_uint32_t hc32_qspi_get_dcom_protocol_line(rt_uint8_t protocol_line) static void hc32_qspi_write_direct_comm_value(rt_uint8_t protocol_line, rt_uint8_t value) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) (void)protocol_line; QSPI_WriteDirectCommValue(value); #elif defined (HC32F448) || defined (HC32F4A8) @@ -384,7 +386,7 @@ static void hc32_qspi_write_direct_comm_value(rt_uint8_t protocol_line, rt_uint8 #endif } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS static void hc32_qspi_set_trans_protocol(uint32_t u32Line) { @@ -430,7 +432,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q rt_uint32_t src_addr; #endif -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifndef BSP_QSPI_USING_SOFT_CS /* Enter direct communication mode */ SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); @@ -441,14 +443,14 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q #endif if (0UL != u32InstrLen) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->instruction.qspi_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif #endif hc32_qspi_write_direct_comm_value(message->instruction.qspi_lines, u8Instr); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif @@ -456,7 +458,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q } if ((NULL != pu8Addr) && (0UL != u32AddrLen)) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->address.qspi_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); @@ -466,7 +468,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q { hc32_qspi_write_direct_comm_value(message->address.qspi_lines, pu8Addr[u32Count]); } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif @@ -474,7 +476,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q } if ((NULL != pu8WriteBuf) && (0UL != u32BufLen)) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->qspi_data_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); @@ -486,7 +488,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q AOS_SetTriggerEventSrc(qspi_dma->trigger_select, qspi_dma->trigger_event); /* Config Dma */ DMA_StructInit(&stcDmaInit); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; #elif defined (HC32F448) || defined (HC32F4A8) rt_uint16_t dcom_line = (rt_uint16_t)hc32_qspi_get_dcom_protocol_line(message->qspi_data_lines); @@ -508,7 +510,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q u32BufLen = 0U; } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) src_addr = (rt_uint32_t)&pu8WriteBuf[u32TxIndex]; #elif defined (HC32F448) || defined (HC32F4A8) if (u32DmaTransSize > qspi_bus->config->dma_tx_buf_size) @@ -552,14 +554,14 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q } #endif -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS /* Exit direct communication mode */ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif #endif } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifndef BSP_QSPI_USING_SOFT_CS /* Exit direct communication mode */ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); @@ -589,7 +591,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs rt_uint32_t u32ReadMd; #endif -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifndef BSP_QSPI_USING_SOFT_CS /* Enter direct communication mode */ SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); @@ -606,14 +608,14 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs #endif if (0UL != u32InstrLen) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->instruction.qspi_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif #endif hc32_qspi_write_direct_comm_value(message->instruction.qspi_lines, u8Instr); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif @@ -621,7 +623,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs } if ((NULL != pu8Addr) && (0UL != u32AddrLen)) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->address.qspi_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); @@ -631,7 +633,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs { hc32_qspi_write_direct_comm_value(message->address.qspi_lines, pu8Addr[u32Count]); } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif @@ -639,7 +641,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs } if ((NULL != pu8ReadBuf) && (0UL != u32BufLen)) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->qspi_data_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); @@ -696,14 +698,14 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs } #endif -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS /* Exit direct communication mode */ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif #endif } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifndef BSP_QSPI_USING_SOFT_CS /* Exit direct communication mode */ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_rtc.c b/bsp/hc32/libraries/hc32_drivers/drv_rtc.c index 6896fb675c6..fdca4689814 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_rtc.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_rtc.c @@ -10,6 +10,8 @@ * 2022-06-10 xiaoxiaolisunny re-add this file for F460 * 2023-02-14 CDT add alarm(precision is 1 minute) * 2024-06-07 CDT Add support for F448/F472 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-09 CDT support HC32F467, fix local time calculation bug */ #include @@ -22,7 +24,7 @@ #define LOG_TAG "drv.rtc" #include -#if defined(HC32F4A0) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) /* BACKUP REG: 96~127 for RTC used */ #define RTC_BACKUP_DATA_SIZE (32U) #define RTC_BACKUP_REG_OFFSET (128U - RTC_BACKUP_DATA_SIZE) @@ -60,7 +62,7 @@ static struct stc_hc32_alarm_irq hc32_alarm_irq = }; #endif -#if defined(HC32F4A0) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void _bakup_reg_write(void) { uint8_t u8Num; @@ -172,13 +174,13 @@ static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) return RT_EOK; } -#if defined(HC32F4A0) || defined(HC32F460) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F460) || defined (HC32F467) #if defined(BSP_RTC_USING_XTAL32) #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL32) #else #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_LRC) #endif -#elif defined(HC32F448) || defined(HC32F4A8) +#elif defined (HC32F448) || defined (HC32F4A8) #if defined(BSP_RTC_USING_XTAL32) #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL32) #elif defined(BSP_RTC_USING_XTAL_DIV) @@ -186,7 +188,7 @@ static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) #else #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_LRC) #endif -#elif defined(HC32F472) || defined (HC32F334) +#elif defined (HC32F472) || defined (HC32F334) #if defined(BSP_RTC_USING_XTAL32) #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL32) #elif defined(BSP_RTC_USING_XTAL_DIV) @@ -198,7 +200,7 @@ static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) #endif #endif -#if defined(HC32F4A8) +#if defined (HC32F4A8) static en_flag_status_t VBAT_PowerDownCheck(void) { en_flag_status_t ret; @@ -215,11 +217,11 @@ static rt_err_t _rtc_init(void) { stc_rtc_init_t stcRtcInit; -#if defined(HC32F4A8) +#if defined (HC32F4A8) if ((SET == VBAT_PowerDownCheck()) || (LL_OK != _bakup_reg_check()) || (LL_OK != _hc32_rtc_rw_check())) -#elif defined(HC32F4A0) +#elif defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) if ((LL_OK != _bakup_reg_check()) || (LL_OK != _hc32_rtc_rw_check())) -#elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) || defined (HC32F334) +#elif defined (HC32F460) || defined (HC32F448) || defined (HC32F472) || defined (HC32F334) if (DISABLE == RTC_GetCounterState()) #endif { @@ -246,7 +248,7 @@ static rt_err_t _rtc_init(void) /* Startup RTC count */ RTC_Cmd(ENABLE); -#if defined(HC32F4A0) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) /* Write sequence flag to backup register */ _bakup_reg_write(); #endif @@ -297,7 +299,7 @@ static void _rtc_alarm_irq_handler(void) rt_interrupt_leave(); } -#if defined(HC32F448) || defined(HC32F472) || defined (HC32F334) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void RTC_Handler(void) { if (RTC_GetStatus(RTC_FLAG_ALARM) != RESET) @@ -334,6 +336,17 @@ static rt_err_t _rtc_get_alarm(struct rt_rtc_wkalarm *alarm) alarm->tm_hour = stcRtcAlarm.u8AlarmHour; alarm->tm_min = stcRtcAlarm.u8AlarmMinute; alarm->tm_sec = 0; /* alarms precision is 1 minute */ +#ifdef RT_ALARM_USING_LOCAL_TIME + alarm->tm_hour += RT_LIBC_TZ_DEFAULT_HOUR; + if (alarm->tm_hour < 0) + { + alarm->tm_hour += 24; + } + else if (alarm->tm_hour > 23) + { + alarm->tm_hour -= 24; + } +#endif LOG_D("GET_ALARM %d:%d:%d", alarm->tm_hour, alarm->tm_min, alarm->tm_sec); return RT_EOK; @@ -354,6 +367,17 @@ static rt_err_t _rtc_set_alarm(struct rt_rtc_wkalarm *alarm) { RTC_AlarmCmd(DISABLE); /* Configuration alarm time: precision is 1 minute */ +#ifdef RT_ALARM_USING_LOCAL_TIME + alarm->tm_hour -= RT_LIBC_TZ_DEFAULT_HOUR; + if (alarm->tm_hour < 0) + { + alarm->tm_hour += 24; + } + else if (alarm->tm_hour > 23) + { + alarm->tm_hour -= 24; + } +#endif stcRtcAlarm.u8AlarmHour = alarm->tm_hour; stcRtcAlarm.u8AlarmMinute = alarm->tm_min; stcRtcAlarm.u8AlarmWeekday = RTC_ALARM_WEEKDAY_EVERYDAY; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_sdio.c b/bsp/hc32/libraries/hc32_drivers/drv_sdio.c index 85375e5832f..12cb68eb682 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_sdio.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_sdio.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2023-02-14 CDT first version + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ @@ -682,10 +684,10 @@ static const struct rt_mmcsd_host_ops _mmcsd_host_ops = */ static rt_uint32_t _sdio_clock_get(CM_SDIOC_TypeDef *SDIOCx) { - rt_uint32_t clk; + rt_uint32_t clk = 0UL; (void)SDIOCx; -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) clk = CLK_GetBusClockFreq(CLK_BUS_PCLK1); #elif defined (HC32F460) clk = CLK_GetBusClockFreq(CLK_BUS_EXCLK); @@ -896,7 +898,7 @@ static rt_err_t _sdio_verify_bus_clock_frequency(struct hc32_sdio_config *config { rt_err_t ret = RT_EOK; -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) rt_uint32_t pclk1; rt_uint32_t exlck; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_sdram.c b/bsp/hc32/libraries/hc32_drivers/drv_sdram.c index 06be7642b93..0bbe0787901 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_sdram.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_sdram.c @@ -9,6 +9,8 @@ * 2024-02-20 CDT modify exclk clock max frequency to 40MHz for HC32F4A0 * add t_rcd_p/t_rfc_p/t_rp_p configuration * 2024-12-24 CDT modify sample clock to EXMC_DMC_SAMPLE_CLK_EXTCLK for HC32F4A0 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-05 CDT support HC32F467 */ @@ -84,7 +86,7 @@ static rt_int32_t _sdram_verify_clock_frequency(void) { rt_int32_t ret = RT_EOK; -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) /* EXCLK max frequency for SDRAM */ if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > EXMC_EXCLK_DMC_MAX_FREQ) { @@ -124,7 +126,7 @@ static rt_int32_t _sdram_init(void) /* configure DMC width && refresh period & chip & timing. */ (void)EXMC_DMC_StructInit(&stcDmcInit); -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) stcDmcInit.u32SampleClock = EXMC_DMC_SAMPLE_CLK_EXTCLK; #endif stcDmcInit.u32RefreshPeriod = SDRAM_REFRESH_COUNT; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_sdram.h b/bsp/hc32/libraries/hc32_drivers/drv_sdram.h index 5afd35dab88..48f9c60e26a 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_sdram.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_sdram.h @@ -27,7 +27,7 @@ extern "C" { /******************************************************************************* * Global pre-processor symbols/macros ('#define') ******************************************************************************/ -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) #define EXMC_EXCLK_DMC_MAX_FREQ (40UL * 1000000UL) #elif defined (HC32F4A8) #define EXMC_EXCLK_DMC_MAX_FREQ (120UL * 1000000UL) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_spi.c b/bsp/hc32/libraries/hc32_drivers/drv_spi.c index 2e4209106d4..86a015cefba 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_spi.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_spi.c @@ -11,6 +11,8 @@ * 2024-04-16 CDT Support HC32F472 * 2025-04-09 CDT Support HC32F4A8 * 2025-07-18 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-04 CDT Support HC32F467 */ /******************************************************************************* @@ -39,9 +41,9 @@ #include /* SPI max division */ -#if defined(HC32F4A0) || defined(HC32F460) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F460) || defined (HC32F467) #define SPI_MAX_DIV_VAL (0x7U) /* Div256 */ -#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) #define SPI_MAX_DIV_VAL (0x39U) #endif @@ -211,9 +213,9 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat break; } } -#if defined(HC32F4A0) || defined(HC32F460) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F460) || defined (HC32F467) stcSpiInit.u32BaudRatePrescaler = (u32Cnt << SPI_CFG2_MBR_POS); -#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) if (u32Cnt <= 15U) { stcSpiInit.u32BaudRatePrescaler = (u32Cnt << SPI_CFG1_CLKDIV_POS); @@ -324,7 +326,7 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat static void hc32_spi_enable(CM_SPI_TypeDef *SPIx) { /* Check if the SPI is already enabled */ -#if defined (HC32F460) || defined (HC32F4A0) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) if ((SPIx->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { SPI_Cmd(SPIx, ENABLE); @@ -341,7 +343,7 @@ static void hc32_spi_enable(CM_SPI_TypeDef *SPIx) static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) { -#if defined (HC32F460) || defined (HC32F4A0) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) if (SPI_SEND_ONLY == u32Mode) { SET_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); @@ -367,7 +369,7 @@ static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) #ifdef BSP_SPI_USING_DMA static uint32_t hc32_spi_get_trans_mode(CM_SPI_TypeDef *SPIx) { -#if defined (HC32F460) || defined (HC32F4A0) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) return READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); #elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) return READ_REG32_BIT(SPIx->CR, SPI_CR_TXMDS); @@ -913,7 +915,7 @@ static int hc32_hw_spi_bus_init(void) spi_bus_obj[i].config = &spi_config[i]; spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; /* register the handle */ -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) hc32_install_irq_handler(&spi_config[i].err_irq.irq_config, spi_config[i].err_irq.irq_callback, RT_FALSE); #elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) INTC_IntSrcCmd(spi_config[i].err_irq.irq_config.int_src, DISABLE); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_timer.c b/bsp/hc32/libraries/hc32_drivers/drv_timer.c index 2db13325c70..eba1d47e500 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_timer.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_timer.c @@ -8,6 +8,8 @@ * 2023-06-21 CDT first version * 2024-02-20 CDT support HC32F448 * 2024-06-17 CDT support HC32F472 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ #include @@ -73,7 +75,7 @@ struct hc32_clock_timer en_int_src_t enIntSrc; IRQn_Type enIRQn; rt_uint8_t u8Int_Prio; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) func_ptr_t irq_callback; #endif } isr; @@ -148,7 +150,7 @@ static void _timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) (void)TMRA_Init(tmr_device->tmr_handle, &stcTmraInit); TMRA_IntCmd(tmr_device->tmr_handle, TMRA_INT_OVF, ENABLE); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_TRUE); #elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) hc32_install_irq_handler(&irq_config, NULL, RT_TRUE); @@ -157,7 +159,7 @@ static void _timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) else /* close */ { TMRA_DeInit(tmr_device->tmr_handle); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_FALSE); #elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) hc32_install_irq_handler(&irq_config, NULL, RT_FALSE); @@ -395,7 +397,7 @@ void tmra_get_info_callback(void) _info[i].cntmode = CLOCK_TIMER_CNTMODE_UP; } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) #ifdef BSP_USING_TMRA_1 hc32_clock_timer_obj[TMRA_1_INDEX].isr.irq_callback = TMRA_1_callback; #endif @@ -455,7 +457,7 @@ static int rt_hw_clock_timer_init(void) hc32_clock_timer_obj[i].time_device.info = &_info[i]; hc32_clock_timer_obj[i].time_device.ops = &_ops; if (rt_clock_timer_register(&hc32_clock_timer_obj[i].time_device, - hc32_clock_timer_obj[i].name, &hc32_clock_timer_obj[i].tmr_handle) == RT_EOK) + hc32_clock_timer_obj[i].name, &hc32_clock_timer_obj[i].tmr_handle) == RT_EOK) { LOG_D("%s register success", hc32_clock_timer_obj[i].name); } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c b/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c index 16b70b13a02..de1609ec639 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2025-01-10 CDT first version + * 2026-05-27 CDT support HC32F4A2 */ #include @@ -124,9 +125,9 @@ static rt_err_t _tmr_capture_get_pulsewidth(struct rt_inputcapture_device *input /* Private define ---------------------------------------------------------------*/ #define TMR6_INSTANCE_MIN ((uint32_t)CM_TMR6_1) -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_8) -#elif defined (HC32F460) +#elif defined (HC32F460) || defined (HC32F467) #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_3) #elif defined (HC32F334) #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_4) @@ -141,7 +142,7 @@ static rt_err_t _tmr_capture_get_pulsewidth(struct rt_inputcapture_device *input #if defined (BSP_USING_INPUT_CAPTURE_TMR6) #define IS_CAPTURE_COND_RASING_EDGE(bit_pos) ((bit_pos) % 2U == 0U) - #if defined (HC32F4A0) || defined (HC32F4A8) || defined (HC32F334) || defined (HC32F472) + #if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F334) || defined (HC32F472) || defined (HC32F467) #define VALID_CAPTURE_COND (TMR6_CAPT_COND_ALL & (~(TMR6_CAPT_COND_EVT0 | TMR6_CAPT_COND_EVT1 | TMR6_CAPT_COND_EVT2 | TMR6_CAPT_COND_EVT3))) #elif defined (HC32F460) || defined (HC32F448) #define VALID_CAPTURE_COND (TMR6_CAPT_COND_ALL & (~(TMR6_CAPT_COND_EVT0 | TMR6_CAPT_COND_EVT1))) @@ -358,7 +359,7 @@ static void _tmr_capture_init_tmr6(tmr_capture_t *p_capture, CM_TMR6_TypeDef *in uint32_t pin; uint32_t bit_pos = _get_capture_cond_bit_pos(init_params->first_edge); -#if defined (HC32F4A0) || defined (HC32F4A8) || defined (HC32F334) || defined (HC32F448) || defined (HC32F472) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F334) || defined (HC32F448) || defined (HC32F472) || defined (HC32F467) if (bit_pos <= TMR6_HCPAR_HCPA3_POS) { pin = TMR6_IO_PWMA + (bit_pos / 2U); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart.c b/bsp/hc32/libraries/hc32_drivers/drv_usart.c index 5e6883a2c1a..e2cb4e5b09a 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart.c @@ -9,6 +9,8 @@ * 2023-10-09 CDT support HC32F448 * 2024-04-15 CDT support HC32F472 * 2025-07-16 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ /******************************************************************************* @@ -48,13 +50,15 @@ #if defined (HC32F460) #define FCG_USART_CLK FCG_Fcg1PeriphClockCmd -#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#elif defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || \ + defined (HC32F4A8) || defined (HC32F334) || defined (HC32F467) #define FCG_USART_CLK FCG_Fcg3PeriphClockCmd #endif #define FCG_TMR0_CLK FCG_Fcg2PeriphClockCmd #define FCG_DMA_CLK FCG_Fcg0PeriphClockCmd -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || \ + defined (HC32F467) #define USART_MAX_CLK_DIV USART_CLK_DIV64 #elif defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) #define USART_MAX_CLK_DIV USART_CLK_DIV1024 @@ -161,7 +165,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co uart_init.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; uart_init.u32Baudrate = cfg->baud_rate; uart_init.u32ClockSrc = USART_CLK_SRC_INTERNCLK; -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ (CM_USART6 == uart->config->Instance) || (CM_USART7 == uart->config->Instance)) #elif defined (HC32F460) || defined (HC32F334) @@ -225,7 +229,8 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co { uart_init.u32FirstBit = USART_FIRST_BIT_MSB; } -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) switch (cfg->flowcontrol) { case RT_SERIAL_FLOWCONTROL_NONE: @@ -280,7 +285,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co } /* Enable error interrupt */ -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num); #elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE); @@ -308,7 +313,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg case RT_DEVICE_CTRL_CLR_INT: if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num); INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num); #elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) @@ -317,7 +322,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg } else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num); USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE); INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num); @@ -339,7 +344,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg break; /* Enable interrupt */ case RT_DEVICE_CTRL_SET_INT: -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) { hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE); @@ -515,7 +520,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { RT_ASSERT(TMR0_CH_B == ch); } -#elif defined (HC32F4A0) +#elif defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) if ((CM_USART1 == uart->config->Instance) || (CM_USART6 == uart->config->Instance)) { RT_ASSERT(TMR0_CH_A == ch); @@ -555,7 +560,8 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE); } -#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F334) || \ + defined (HC32F467) FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE); #endif @@ -593,7 +599,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) /* Clear compare flag */ TMR0_ClearStatus(TMR0_Instance, (uint32_t)(0x1UL << (ch * TMR0_STFLR_CMFB_POS))); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) NVIC_EnableIRQ(uart->config->rx_timeout->irq_config.irq_num); #endif USART_ClearStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT); @@ -825,7 +831,7 @@ static void hc32_usart_handler(struct hc32_uart *uart) #endif #if defined (BSP_USING_UART1) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart1_rx_irq_handler(void) { /* enter interrupt */ @@ -882,7 +888,7 @@ void USART1_TxComplete_Handler(void) #endif /* BSP_UART1_TX_USING_DMA */ #if defined (BSP_UART1_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart1_rxto_irq_handler(void) { /* enter interrupt */ @@ -923,7 +929,7 @@ void USART1_Handler(void) #endif /* BSP_USING_UART1 */ #if defined (BSP_USING_UART2) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart2_rx_irq_handler(void) { /* enter interrupt */ @@ -980,7 +986,7 @@ void USART2_TxComplete_Handler(void) #endif /* BSP_UART2_TX_USING_DMA */ #if defined (BSP_UART2_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart2_rxto_irq_handler(void) { /* enter interrupt */ @@ -1021,7 +1027,7 @@ void USART2_Handler(void) #endif /* BSP_USING_UART2 */ #if defined (BSP_USING_UART3) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart3_rx_irq_handler(void) { /* enter interrupt */ @@ -1094,7 +1100,7 @@ static void hc32_uart3_dma_rx_irq_handler(void) } #endif /* BSP_UART3_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#endif /* HC32F460, HC32F4A0, HC32F4A8 */ +#endif /* HC32F460, HC32F4A0, HC32F4A2, HC32F4A8, HC32F467 */ #if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void USART3_Handler(void) @@ -1111,7 +1117,7 @@ void USART3_Handler(void) #endif /* BSP_USING_UART3 */ #if defined (BSP_USING_UART4) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart4_rx_irq_handler(void) { /* enter interrupt */ @@ -1209,7 +1215,7 @@ void USART4_Handler(void) #endif /* BSP_USING_UART4 */ #if defined (BSP_USING_UART5) -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart5_rx_irq_handler(void) { /* enter interrupt */ @@ -1307,7 +1313,7 @@ void USART5_Handler(void) #endif /* BSP_USING_UART5 */ #if defined (BSP_USING_UART6) -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart6_rx_irq_handler(void) { /* enter interrupt */ @@ -1379,7 +1385,7 @@ static void hc32_uart6_dma_rx_irq_handler(void) } #endif /* BSP_UART6_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#endif /* HC32F4A0, HC32F4A8 */ +#endif /* HC32F4A0, HC32F4A2, HC32F4A8, HC32F467 */ #if defined (HC32F448) || defined (HC32F472) void USART6_Handler(void) @@ -1706,7 +1712,7 @@ static void hc32_uart_get_dma_info(void) static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG; uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler; #endif uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout; @@ -1729,7 +1735,7 @@ static void hc32_uart_get_dma_info(void) static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; static struct hc32_uart_rxto uart2_rx_timeout = UART2_RXTO_CONFIG; uart2_dma_rx.irq_callback = hc32_uart2_dma_rx_irq_handler; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) uart2_rx_timeout.irq_callback = hc32_uart2_rxto_irq_handler; #endif uart_config[UART2_INDEX].rx_timeout = &uart2_rx_timeout; @@ -1918,7 +1924,7 @@ static void hc32_uart_get_dma_info(void) #endif } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) /** * @brief This function gets uart irq handle. * @param None @@ -1995,7 +2001,7 @@ int rt_hw_usart_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; hc32_uart_get_dma_info(); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) hc32_get_uart_callback(); #endif for (int i = 0; i < obj_num; i++) @@ -2004,7 +2010,7 @@ int rt_hw_usart_init(void) uart_obj[i].serial.ops = &hc32_uart_ops; uart_obj[i].serial.config = config; uart_obj[i].config = &uart_config[i]; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) /* register the handle */ hc32_install_irq_handler(&uart_config[i].rxerr_irq.irq_config, uart_config[i].rxerr_irq.irq_callback, RT_FALSE); #endif @@ -2012,7 +2018,7 @@ int rt_hw_usart_init(void) if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_RX) { hc32_install_irq_handler(&uart_config[i].dma_rx->irq_config, uart_config[i].dma_rx->irq_callback, RT_FALSE); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) hc32_install_irq_handler(&uart_config[i].rx_timeout->irq_config, uart_config[i].rx_timeout->irq_callback, RT_FALSE); #endif } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart.h b/bsp/hc32/libraries/hc32_drivers/drv_usart.h index 2b9b0cd319c..9dcd6626efc 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart.h @@ -41,7 +41,7 @@ struct hc32_uart_rxto rt_uint32_t channel; rt_uint32_t clock; rt_size_t timeout_bits; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) struct hc32_irq_config irq_config; func_ptr_t irq_callback; #endif @@ -53,7 +53,7 @@ struct hc32_uart_config const char *name; CM_USART_TypeDef *Instance; rt_uint32_t clock; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) struct hc32_uart_irq_config rxerr_irq; struct hc32_uart_irq_config rx_irq; struct hc32_uart_irq_config tx_irq; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c index 7d6d5adfd52..b78b915c114 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c @@ -9,6 +9,8 @@ * 2024-02-06 CDT support HC32F448 * 2024-04-15 CDT support HC32F472 * 2025-07-16 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ /******************************************************************************* @@ -49,14 +51,15 @@ #if defined (HC32F460) #define FCG_USART_CLK FCG_Fcg1PeriphClockCmd -#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#elif defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) #define FCG_USART_CLK FCG_Fcg3PeriphClockCmd #endif #define FCG_TMR0_CLK FCG_Fcg2PeriphClockCmd #define FCG_DMA_CLK FCG_Fcg0PeriphClockCmd -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #define USART_MAX_CLK_DIV USART_CLK_DIV64 #elif defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) #define USART_MAX_CLK_DIV USART_CLK_DIV1024 @@ -163,7 +166,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co uart_init.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; uart_init.u32Baudrate = cfg->baud_rate; uart_init.u32ClockSrc = USART_CLK_SRC_INTERNCLK; -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ (CM_USART6 == uart->config->Instance) || (CM_USART7 == uart->config->Instance)) #elif defined (HC32F460) || defined (HC32F334) @@ -227,7 +230,8 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co { uart_init.u32FirstBit = USART_FIRST_BIT_MSB; } -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F334) || defined (HC32F467) switch (cfg->flowcontrol) { case RT_SERIAL_FLOWCONTROL_NONE: @@ -279,7 +283,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co } /* Enable error interrupt */ -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num); #elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE); @@ -331,7 +335,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg case RT_DEVICE_CTRL_CLR_INT: if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num); INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num); #elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) @@ -340,7 +344,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg } else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num); NVIC_DisableIRQ(uart->config->tc_irq.irq_config.irq_num); USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE); @@ -366,7 +370,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg break; /* Enable interrupt */ case RT_DEVICE_CTRL_SET_INT: -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) { hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE); @@ -585,7 +589,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { RT_ASSERT(TMR0_CH_B == ch); } -#elif defined (HC32F4A0) +#elif defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) if ((CM_USART1 == uart->config->Instance) || (CM_USART6 == uart->config->Instance)) { RT_ASSERT(TMR0_CH_A == ch); @@ -625,7 +629,8 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE); } -#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || \ + defined (HC32F334) || defined (HC32F467) FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE); #endif @@ -663,7 +668,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) /* Clear compare flag */ TMR0_ClearStatus(TMR0_Instance, (uint32_t)(0x1UL << (ch * TMR0_STFLR_CMFB_POS))); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) NVIC_EnableIRQ(uart->config->rx_timeout->irq_config.irq_num); #endif USART_ClearStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT); @@ -879,7 +884,7 @@ static void hc32_usart_handler(struct hc32_uart *uart) #endif #if defined (BSP_USING_UART1) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart1_rx_irq_handler(void) { /* enter interrupt */ @@ -927,7 +932,7 @@ static void hc32_uart1_tc_irq_handler(void) #if defined (RT_SERIAL_USING_DMA) #if defined (BSP_UART1_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart1_rxto_irq_handler(void) { /* enter interrupt */ @@ -979,7 +984,7 @@ void USART1_TxComplete_Handler(void) #endif /* BSP_USING_UART1 */ #if defined (BSP_USING_UART2) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart2_rx_irq_handler(void) { /* enter interrupt */ @@ -1027,7 +1032,7 @@ static void hc32_uart2_tc_irq_handler(void) #if defined (RT_SERIAL_USING_DMA) #if defined (BSP_UART2_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart2_rxto_irq_handler(void) { /* enter interrupt */ @@ -1079,7 +1084,7 @@ void USART2_TxComplete_Handler(void) #endif /* BSP_USING_UART2 */ #if defined (BSP_USING_UART3) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart3_rx_irq_handler(void) { /* enter interrupt */ @@ -1127,7 +1132,7 @@ static void hc32_uart3_tc_irq_handler(void) #if defined (RT_SERIAL_USING_DMA) #if defined (BSP_UART3_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart3_rxto_irq_handler(void) { /* enter interrupt */ @@ -1180,7 +1185,7 @@ void USART3_TxComplete_Handler(void) #endif /* BSP_USING_UART3 */ #if defined (BSP_USING_UART4) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart4_rx_irq_handler(void) { /* enter interrupt */ @@ -1280,7 +1285,7 @@ void USART4_TxComplete_Handler(void) #endif /* BSP_USING_UART4 */ #if defined (BSP_USING_UART5) -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) #if defined (HC32F4A8) static void hc32_uart5_rxto_irq_handler(void) { @@ -1380,7 +1385,7 @@ void USART5_TxComplete_Handler(void) #endif /* BSP_USING_UART5 */ #if defined (BSP_USING_UART6) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) static void hc32_uart6_rx_irq_handler(void) { /* enter interrupt */ @@ -1428,7 +1433,7 @@ static void hc32_uart6_tc_irq_handler(void) #if defined (RT_SERIAL_USING_DMA) #if defined (BSP_UART6_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467) static void hc32_uart6_rxto_irq_handler(void) { /* enter interrupt */ @@ -1710,7 +1715,7 @@ static void hc32_uart_get_info(void) static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG; uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler; #endif uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout; @@ -1734,7 +1739,7 @@ static void hc32_uart_get_info(void) static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; static struct hc32_uart_rxto uart2_rx_timeout = UART2_RXTO_CONFIG; uart2_dma_rx.irq_callback = hc32_uart2_dma_rx_irq_handler; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) uart2_rx_timeout.irq_callback = hc32_uart2_rxto_irq_handler; #endif uart_config[UART2_INDEX].rx_timeout = &uart2_rx_timeout; @@ -1883,7 +1888,7 @@ static void hc32_uart_get_info(void) #endif } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) /** * @brief This function gets uart irq handle. * @param None @@ -2035,7 +2040,7 @@ int rt_hw_usart_init(void) /* init UART object */ uart_obj[i].serial.ops = &hc32_uart_ops; uart_obj[i].config = &uart_config[i]; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) /* register the handle */ hc32_install_irq_handler(&uart_config[i].rxerr_irq.irq_config, uart_config[i].rxerr_irq.irq_callback, RT_FALSE); #endif @@ -2043,7 +2048,7 @@ int rt_hw_usart_init(void) if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_RX) { hc32_install_irq_handler(&uart_config[i].dma_rx->irq_config, uart_config[i].dma_rx->irq_callback, RT_FALSE); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) hc32_install_irq_handler(&uart_config[i].rx_timeout->irq_config, uart_config[i].rx_timeout->irq_callback, RT_FALSE); #endif } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h index c513062391a..5275ab8ffab 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h @@ -41,7 +41,7 @@ struct hc32_uart_rxto rt_uint32_t channel; rt_uint32_t clock; rt_size_t timeout_bits; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) struct hc32_irq_config irq_config; func_ptr_t irq_callback; #endif @@ -53,7 +53,7 @@ struct hc32_uart_config const char *name; CM_USART_TypeDef *Instance; rt_uint32_t clock; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) struct hc32_uart_irq_config rxerr_irq; struct hc32_uart_irq_config rx_irq; struct hc32_uart_irq_config tx_irq; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usbd.c b/bsp/hc32/libraries/hc32_drivers/drv_usbd.c index b1324771683..77a11f829b3 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usbd.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usbd.c @@ -7,6 +7,8 @@ * Date Author Notes * 2023-02-14 CDT first version * 2025-07-25 CDT support HC32F4A8 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ /******************************************************************************* @@ -25,7 +27,7 @@ #include "irq_config.h" #include "drv_usbd.h" -#if defined(HC32F472) +#if defined (HC32F472) #define USBFS_VBUS_INT_PIN (rt_base_t)(((rt_uint16_t)USBF_VBUS_PORT * 16) + __CLZ(__RBIT(USBF_VBUS_PIN))) #endif @@ -53,7 +55,7 @@ static struct ep_id _ep_pool[] = {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, {0x5, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED}, {0x5, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED}, -#if defined (HC32F4A0) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) {0x6, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, {0x6, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, @@ -142,6 +144,21 @@ static void usb_shutdevep(usb_core_instance *pdev, uint8_t ep_addr) usb_epdeactive(&pdev->regs, ep); } +static void usb_flsdevep(usb_core_instance *pdev, uint8_t epnum) +{ + __IO uint8_t tmp_1; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + if (tmp_1 != 0U) + { + usb_txfifoflush(&pdev->regs, (uint32_t)epnum & (uint32_t)0x7F); + } + else + { + usb_rxfifoflush(&pdev->regs); + } +} + static void usb_readytorx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) { USB_DEV_EP *ep; @@ -400,7 +417,8 @@ static void usb_wrblanktxfifo(usb_core_instance *pdev, uint32_t epnum) } } -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F460) || defined (HC32F4A8) || \ + defined (HC32F467) #ifdef VBUS_SENSING_ENABLED static void usb_sessionrequest_isr(usb_core_instance *pdev) { @@ -718,7 +736,8 @@ static void usb_isr_handler(usb_core_instance *pdev) { usb_isooutincomplt_isr(pdev); } -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F460) || defined (HC32F4A8) || \ + defined (HC32F467) #ifdef VBUS_SENSING_ENABLED if ((u32gintsts & VBUSV_INT) != 0UL) { @@ -736,7 +755,7 @@ static void usbd_irq_handler(void) rt_interrupt_leave(); } -#if defined(HC32F472) +#if defined (HC32F472) void USBFS_Handler(void) { usbd_irq_handler(); @@ -786,6 +805,7 @@ static rt_err_t _usbd_ep_enable(uep_t ep) RT_ASSERT(ep->ep_desc != RT_NULL); usb_opendevep(&_hc32_usbd, ep->ep_desc->bEndpointAddress, ep->ep_desc->wMaxPacketSize, ep->ep_desc->bmAttributes); + usb_flsdevep(&_hc32_usbd, ep->ep_desc->bEndpointAddress); return RT_EOK; } @@ -793,6 +813,7 @@ static rt_err_t _usbd_ep_disable(uep_t ep) { RT_ASSERT(ep != RT_NULL); RT_ASSERT(ep->ep_desc != RT_NULL); + usb_flsdevep(&_hc32_usbd, ep->ep_desc->bEndpointAddress); usb_shutdevep(&_hc32_usbd, ep->ep_desc->bEndpointAddress); return RT_EOK; } @@ -852,7 +873,7 @@ static rt_err_t _usbd_init(rt_device_t device) #else stcPortIdentify.u8CoreID = USBHS_CORE_ID; #endif -#if defined (HC32F4A0) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) #if !defined(BSP_USING_USBHS_PHY_EXTERN) stcPortIdentify.u8PhyType = USBHS_PHY_EMBED; #else @@ -885,7 +906,7 @@ static rt_err_t _usbd_init(rt_device_t device) hc32_install_irq_handler(&irq_config, usbd_irq_handler, RT_TRUE); -#if defined(HC32F472) +#if defined (HC32F472) #ifdef VBUS_SENSING_ENABLED /* VBUS Extint config */ rt_pin_mode(USBFS_VBUS_INT_PIN, PIN_MODE_INPUT); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usbh.c b/bsp/hc32/libraries/hc32_drivers/drv_usbh.c index 8c0b11c6d85..660c72acc8d 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usbh.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usbh.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2023-05-25 CDT first version + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ /******************************************************************************* @@ -24,7 +26,7 @@ #include "irq_config.h" #include "drv_usbh.h" -#if defined(HC32F472) +#if defined (HC32F472) #define USBFS_DRVVBUS_PIN (rt_base_t)(((rt_uint16_t)USBF_DRVVBUS_PORT * 16) + __CLZ(__RBIT(USBF_DRVVBUS_PIN))) #endif @@ -52,13 +54,13 @@ void usb_mdelay(const uint32_t msec) void usb_bsp_cfgvbus(usb_core_instance *pdev) { -#if defined(HC32F472) +#if defined (HC32F472) rt_pin_mode(USBFS_DRVVBUS_PIN, PIN_MODE_OUTPUT); #endif } void usb_bsp_drivevbus(usb_core_instance *pdev, uint8_t state) { -#if defined(HC32F472) +#if defined (HC32F472) if (0x00U == state) { rt_pin_write(USBFS_DRVVBUS_PIN, PIN_LOW); @@ -112,7 +114,8 @@ static void usb_host_chx_out_isr(usb_core_instance *pdev, uint8_t chnum) { usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK); } -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F467) else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) { usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR); @@ -236,7 +239,8 @@ static void usb_host_chx_in_isr(usb_core_instance *pdev, uint8_t chnum) { usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK); } -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F467) else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) { usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR); @@ -682,7 +686,7 @@ static void usbh_irq_handler(void) rt_interrupt_leave(); } -#if defined(HC32F472) +#if defined (HC32F472) void USBFS_Handler(void) { usbh_irq_handler(); @@ -1106,7 +1110,7 @@ static rt_err_t _usbh_init(rt_device_t device) #else stcPortIdentify.u8CoreID = USBHS_CORE_ID; #endif -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) #if !defined(BSP_USING_USBHS_PHY_EXTERN) stcPortIdentify.u8PhyType = USBHS_PHY_EMBED; #else diff --git a/bsp/hc32/libraries/hc32_drivers/drv_wktm.c b/bsp/hc32/libraries/hc32_drivers/drv_wktm.c index 8b8b9ed3e59..fb77c58480a 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_wktm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_wktm.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2023-02-09 CDT first version + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ #include @@ -28,9 +30,9 @@ #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_64HZ) #define PWC_WKT_COUNT_FRQ (64U) #else - #if defined(HC32F4A0) || defined(HC32F4A8) + #if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_RTCLRC) - #elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) || defined(HC32F334) + #elif defined (HC32F460) || defined (HC32F448) || defined (HC32F472) || defined (HC32F334) #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_LRC) #endif #define PWC_WKT_COUNT_FRQ (32768UL) @@ -119,8 +121,8 @@ int rt_hw_wktm_init(void) /* WKTM init */ PWC_WKT_Config(PWC_WKT_CLK_SRC, CMPVAL_MAX); -#if defined(HC32F4A0) || defined(HC32F4A8) - /* F4A0 if select RTCLRC clock need open the LRCEN by RTC->CR3 register */ +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) + /* F4A0/F4A2 if select RTCLRC clock need open the LRCEN by RTC->CR3 register */ #if (PWC_WKT_CLK_SRC == PWC_WKT_CLK_SRC_RTCLRC) MODIFY_REG8(CM_RTC->CR3, RTC_CR3_LRCEN, 0x01U << RTC_CR3_LRCEN_POS); #endif diff --git a/bsp/hc32/platform/sfud/drv_spi_flash.c b/bsp/hc32/platform/sfud/drv_spi_flash.c index 70ccd18f715..bac12f9c1be 100644 --- a/bsp/hc32/platform/sfud/drv_spi_flash.c +++ b/bsp/hc32/platform/sfud/drv_spi_flash.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2022-04-28 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-04 CDT Support HC32F467 */ #include @@ -23,22 +25,22 @@ #include "dev_spi_flash_sfud.h" #endif -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F467) #define SPI_BUS_NAME "spi1" #define SPI_FLASH_DEVICE_NAME "spi10" #define SPI_FLASH_CHIP "w25q64" #define SPI_FLASH_SS_PIN GET_PIN(C, 7) -#elif defined(HC32F460) +#elif defined (HC32F460) #define SPI_BUS_NAME "spi3" #define SPI_FLASH_DEVICE_NAME "spi30" #define SPI_FLASH_CHIP "w25q64" #define SPI_FLASH_SS_PIN GET_PIN(C, 7) -#elif defined(HC32F472) +#elif defined (HC32F472) #define SPI_BUS_NAME "spi1" #define SPI_FLASH_DEVICE_NAME "spi10" #define SPI_FLASH_CHIP "w25q64" #define SPI_FLASH_SS_PIN GET_PIN(B,12) -#elif defined(HC32F334) +#elif defined (HC32F334) #define SPI_BUS_NAME "spi1" #define SPI_FLASH_DEVICE_NAME "spi10" #define SPI_FLASH_CHIP "w25q64" diff --git a/bsp/hc32/platform/tca9539/tca9539.c b/bsp/hc32/platform/tca9539/tca9539.c index 7ee4c84281b..4e98ac38374 100644 --- a/bsp/hc32/platform/tca9539/tca9539.c +++ b/bsp/hc32/platform/tca9539/tca9539.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2022-2026, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2024-02-20 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ #include @@ -27,12 +28,14 @@ #define BSP_TCA9539_I2C_BUS_NAME "i2c1" #define BSP_TCA9539_DEV_ADDR (0x74U) -#if defined(HC32F4A0) || defined(HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) #define TCA9539_RST_PIN (45) /* PC13 */ -#elif defined(HC32F448) +#elif defined (HC32F448) #define TCA9539_RST_PIN (31) /* PB15 */ -#elif defined(HC32F472) +#elif defined (HC32F472) #define TCA9539_RST_PIN (44) /* PC12 */ +#elif defined (HC32F467) + #define TCA9539_RST_PIN (141) /* PI13 */ #endif /******************************************************************************* @@ -137,6 +140,10 @@ static void TCA9539_Reset(void) rt_pin_write(TCA9539_RST_PIN, PIN_LOW); rt_thread_mdelay(3U); rt_pin_write(TCA9539_RST_PIN, PIN_HIGH); +#if defined (HC32F467) + rt_thread_mdelay(3U); + rt_pin_write(TCA9539_RST_PIN, PIN_LOW); // reused MD pin, logic low level to reset +#endif } /** diff --git a/bsp/hc32/tests/SConscript b/bsp/hc32/tests/SConscript index 3733761301b..74d279fda2a 100644 --- a/bsp/hc32/tests/SConscript +++ b/bsp/hc32/tests/SConscript @@ -15,7 +15,9 @@ if GetDepend(['RT_USING_SERIAL']): src += ['test_uart_v1.c'] if GetDepend(['BSP_USING_SPI']): - src += ['test_spi.c'] + # don't add test file when use RT_USB_DEVICE_MSTORAGE + if not (GetDepend(['BSP_USING_USBD']) and GetDepend(['RT_USB_DEVICE_MSTORAGE'])): + src += ['test_spi.c'] if GetDepend(['BSP_USING_QSPI']): src += ['test_qspi.c'] @@ -66,6 +68,7 @@ if GetDepend(['BSP_USING_INPUT_CAPTURE']): if GetDepend(['BSP_USING_PM']): src += ['test_pm.c'] + src += ['test_wktm.c'] if GetDepend('BSP_USING_HWCRYPTO'): src += ['test_crypto.c'] diff --git a/bsp/hc32/tests/test_adc.c b/bsp/hc32/tests/test_adc.c index abe95b0c9da..a5858613ea2 100644 --- a/bsp/hc32/tests/test_adc.c +++ b/bsp/hc32/tests/test_adc.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ /* @@ -33,7 +34,11 @@ #define ADC1_CH_MAX (21U) #define ADC2_CH_MAX (21U) #define ADC3_CH_MAX (22U) -#elif defined (HC32F4A0) || defined (HC32F4A8) +#elif defined (HC32F467) + #define ADC1_CH_MAX (16U) + #define ADC2_CH_MAX (16U) + #define ADC3_CH_MAX (16U) +#elif defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) #define ADC1_CH_MAX (16U) #define ADC2_CH_MAX (16U) #define ADC3_CH_MAX (20U) @@ -59,7 +64,7 @@ rt_err_t adc_dma_trig_config(void) { stc_tmr0_init_t stcTmr0Init; -#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || defined (HC32F334) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || defined (HC32F334) || defined (HC32F467) FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR0_1, ENABLE); #endif (void)TMR0_StructInit(&stcTmr0Init); @@ -105,7 +110,7 @@ static int adc_vol_sample(int argc, char **argv) rt_strcpy(adc_device, "adc2"); adc_max_channel = ADC2_CH_MAX; } -#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) || defined (HC32F467) else if (0 == rt_strcmp(argv[1], "adc3")) { rt_strcpy(adc_device, "adc3"); diff --git a/bsp/hc32/tests/test_can.c b/bsp/hc32/tests/test_can.c index b96471eacae..e271b6e9619 100644 --- a/bsp/hc32/tests/test_can.c +++ b/bsp/hc32/tests/test_can.c @@ -10,16 +10,23 @@ /* * 功能 -* 展示 CAN1、CAN2、CAN3 接收消息和回发消息。 -* 代码使用方法 -* 在终端执行：can_sample 参数选择：can1 | can2 | can3 以启动CAN收发测试 +* 测试 can 和 mcan 接收消息和回发消息 +* 注：mcan 仅部分系列MCU支持(参考宏定义MCAN_DEV_CNT) +* +* 测试方法 +* 连接 can 测试设备与MCU can(mcan）： +* 注：MCU can(mcan）通信引脚的配置位于 board_config.h， +* 若测试单元的通信引脚未配置，需测试人员自行添加，并于board_config.c中做初始化 +* 初始化测试: 在终端按需执行：can_sample canx 或 can_sample mcany +* 其中x和y是单元号， x = 1 ~ CAN_DEV_CNT, y = 1 ~ MCAN_DEV_CNT +* 测试：can 测试设备发送满足过滤条件的消息（见后文：接收和发送消息） +* 终端打印接收到的ID和消息，并将消息原样发回给测试设备。 * * 默认波特率 * 仲裁段:波特率500K,采样率80% * 数据段:波特率为4M,采样率80% (仅支持CAN FD的单元) * * 接收和发送消息 -* CAN1: * 仅接收满足以下过滤条件的消息，并发送接收到的消息 * 1）标准帧：match ID:0x100~0x1ff * 2）扩展帧：match ID:0x12345100~0x123451ff @@ -57,6 +64,22 @@ #include "rtdevice.h" #include "drv_can.h" +#if defined (HC32F452) || defined (HC32F460) + #define CAN_DEV_CNT (1) +#elif defined (HC32F472) + #define CAN_DEV_CNT (3) +#elif defined (HC32F467) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) + #define CAN_DEV_CNT (2) +#endif + +#if defined (HC32F334) || defined (HC32F336) || defined (HC32F448) || defined (HC32F4A8) + #define MCAN_DEV_CNT (2) +#elif defined (HC32K118) + #define MCAN_DEV_CNT (1) +#elif defined (HC32F558) + #define MCAN_DEV_CNT (3) +#endif + #define MSH_USAGE_CAN_SAMPLE "can_sample - open can device and test\n" #define MSH_USAGE_CAN_SET_BAUD "can set_baud - set can baud\n" #define MSH_USAGE_CAN_SET_BAUDFD "can set_baudfd - set can baudfd\n" @@ -173,7 +196,7 @@ static void _msh_cmd_set_baud(int argc, char **argv) } #ifdef RT_CAN_USING_CANFD -void _msh_cmd_set_timing(int argc, char **argv) +static void _msh_cmd_set_timing(int argc, char **argv) { rt_err_t result; @@ -218,7 +241,7 @@ void _msh_cmd_set_timing(int argc, char **argv) } } -void _msh_cmd_set_baudfd(int argc, char **argv) +static void _msh_cmd_set_baudfd(int argc, char **argv) { rt_err_t result; @@ -239,7 +262,7 @@ void _msh_cmd_set_baudfd(int argc, char **argv) } #endif -void _msh_cmd_send_msg(int argc, char **argv) +static void _msh_cmd_send_msg(int argc, char **argv) { rt_size_t size; struct rt_can_msg msg = {0}; @@ -291,7 +314,7 @@ void _msh_cmd_send_msg(int argc, char **argv) } } -void _show_usage(void) +static void _show_usage(void) { rt_kprintf("Usage: \n"); rt_kprintf(MSH_USAGE_CAN_SET_BAUD); diff --git a/bsp/hc32/tests/test_cherryusb.c b/bsp/hc32/tests/test_cherryusb.c index d8223826e70..ef7a7f3cc3e 100644 --- a/bsp/hc32/tests/test_cherryusb.c +++ b/bsp/hc32/tests/test_cherryusb.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2025-08-08 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include #include @@ -15,7 +17,7 @@ */ #if defined(RT_CHERRYUSB_HOST) && defined(RT_CHERRYUSB_DEVICE) - #if defined(HC32F4A0) || defined(HC32F4A8) + #if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) #define TEST_USBH_CORE_BASE (CM_USBFS_BASE) #define TEST_USBD_CORE_BASE (CM_USBHS_BASE) #else @@ -34,8 +36,7 @@ #if defined(RT_CHERRYUSB_HOST_CDC_ECM) || defined(RT_CHERRYUSB_HOST_CDC_RNDIS) || defined(RT_CHERRYUSB_HOST_MSC) /* 使用USB Host 时，应确保主机对设备供电充足 - menuconfig: ECM 关键配置 - + ************************* menuconfig: ECM 关键配置 ************************* RT-Thread Kernel --->[*] Enable soft timer with a timer thread (4096) The stack size of timer thread @@ -55,25 +56,11 @@ ... [*] Enable ping features - 备注:CherryUSB Host枚举设备时，默认选择Configuration 1，若指定设备(如CH397A模组CDC-ECM模式)需要选择Configuration 2，需在 - components/drivers/usb/cherryusb/core/usbh_core.c文件中usbh_enumerate()函数内添加如下代码： - int usbh_enumerate(struct usbh_hubport *hport) - { - ... - config_index = 0; - // Add code start - if((0x1A86 == ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->idVendor) && \ - (0x5397 == ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->idProduct)) { - config_index = 1; // For CH397, we need to select configuration 2 - } - // Add code end - USB_LOG_DBG("The device selects config %d\r\n", config_index); - ... - } - - - menuconfig: MSC 关键配置 + 备注:CherryUSB Host枚举设备时，默认选择Configuration 1，若指定设备(如CH397A模组CDC-ECM模式)需要选择Configuration 2，重新定义 + uint8_t usbh_get_hport_active_config_index(struct usbh_hubport *hport)。 + + ************************* menuconfig: MSC 关键配置 ************************* RT-Thread Kernel --->[*] Enable soft timer with a timer thread (4096) The stack size of timer thread @@ -84,7 +71,6 @@ [*] Enable usb msc driver ... (/)usb host dfs mount point - */ @@ -107,7 +93,7 @@ msh />ping www.baidu.com */ static int cherryusb_host_init(void) { - usbh_initialize(0, TEST_USBH_CORE_BASE); + usbh_initialize(0, TEST_USBH_CORE_BASE, RT_NULL); return 0; } INIT_APP_EXPORT(cherryusb_host_init); @@ -119,6 +105,18 @@ void ipconfig(void) list_if(); } MSH_CMD_EXPORT(ipconfig, list network interface information); + +uint8_t usbh_get_hport_active_config_index(struct usbh_hubport *hport) +{ + uint8_t config_index = 0U; /* Default to configuration index 0 */ + + if ((0x1A86U == hport->device_desc.idVendor) && (0x5397U == hport->device_desc.idProduct)) + { + config_index = 1U; /* For CH397, we need to select configuration 2 */ + } + + return config_index; +} #endif #endif @@ -127,11 +125,10 @@ MSH_CMD_EXPORT(ipconfig, list network interface information); #if defined(RT_CHERRYUSB_DEVICE) #if defined(RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM) /* - menuconfig:关键配置 - + ************************* menuconfig: ACM 关键配置 ************************* RT-Thread Components--->Devicee Drivers--->[*] Using USB with CherryUSB [*] Enable usb device mode - Selectot usb host ip.... ---> + Selectot usb device ip.... ---> [*]dwc2_hc [*] Enable usb cdc acm device Select usb device template...---> diff --git a/bsp/hc32/tests/test_crypto.c b/bsp/hc32/tests/test_crypto.c index 439433723af..45cf90dcc7a 100644 --- a/bsp/hc32/tests/test_crypto.c +++ b/bsp/hc32/tests/test_crypto.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include @@ -44,7 +46,8 @@ static void _crypto_cmd_print_usage(void) rt_kprintf(" aes: test aes module. \n"); #if defined(HC32F460) rt_kprintf(" e.g. msh >crypto_sample aes 128 \n"); -#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) +#elif defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || \ + defined (HC32F467) rt_kprintf(" e.g. msh >crypto_sample aes 128/192/256 \n"); #endif #endif @@ -58,8 +61,8 @@ static void _crypto_cmd_print_usage(void) #if defined(BSP_USING_CRC) /* menuconfig: - Hardware Drivers Config--->On-Chip Peripheral Driver--->Using Hardware Crypto ---> - [*]Enable Hardeware CRC + Hardware Drivers Config--->On-Chip Peripheral Driver--->Using Hardware Crypto Drivers ---> + [*]Using Hardeware CRC * CRC16命令调用：crypto_sample crc 16 * CRC32命令调用：crypto_sample crc 32 * 程序功能：打印CRC输入数据和计数结果，使用第三方软件计算数据，再做比较 @@ -110,18 +113,26 @@ static void crc_test(rt_uint32_t width) } rt_kprintf("\n"); result = rt_hwcrypto_crc_update(ctx, temp_in, sizeof(temp_in) / 2U); - rt_kprintf("crc%d result: 0x%x \n", width, result); + rt_kprintf("crc%d expect_result: 0x%X \n", width, (width == 16) ? 0x0A38 : 0x515Ad3CC); + rt_kprintf(" calc_result: 0x%X \n\n", result); /* Accumulate test */ PRINT_DIGIT_ARR(temp_in); result = rt_hwcrypto_crc_update(ctx, &temp_in[sizeof(temp_in) / 2U], sizeof(temp_in) / 2U); - rt_kprintf("crc%d result: 0x%x \n", width, result); + rt_kprintf("crc%d expect_result: 0x%X \n", width, (width == 16) ? 0x2FE2 : 0x456CD746); + rt_kprintf(" calc_result: 0x%X \n\n", result); rt_hwcrypto_crc_destroy(ctx); } #endif #if defined(BSP_USING_AES) +/* menuconfig: + Hardware Drivers Config--->On-Chip Peripheral Driver--->Using Hardware Crypto Drivers ---> + [*]Using Hardeware AES + * AES命令调用：crypto_sample aes 128/192/256 + * 程序功能：打印明文、密文、密文解密后的数据 + */ #define AES_DATA_LEN 32U /* data of length must be a multiple of 16(128 Bit) */ static void aes_test(rt_uint16_t key_bitlen) { @@ -214,7 +225,7 @@ static void aes_test(rt_uint16_t key_bitlen) { rt_kprintf("%c", dec_out[i]); } - rt_kprintf("\n"); + rt_kprintf("\n\n"); _exit: rt_hwcrypto_symmetric_destroy(ctx); @@ -224,11 +235,22 @@ static void aes_test(rt_uint16_t key_bitlen) #endif #if defined(BSP_USING_HASH) +/* menuconfig: + Hardware Drivers Config--->On-Chip Peripheral Driver--->Using Hardware Crypto Drivers ---> + [*]Using Hardeware Hash + * Hash命令调用：crypto_sample hash test + * 程序功能：打印hash原始消息、期望的SHA256结果和计算的SHA256结果 + */ #define HASH_SHA256_MSG_DIGEST_SIZE (32U) static void hash_sha256_test(void) { const char *in = "0123456789abcdefghijklmnopqrstuvwxyz"; - uint8_t out[HASH_SHA256_MSG_DIGEST_SIZE]; + uint8_t calc_out[HASH_SHA256_MSG_DIGEST_SIZE]; + const uint8_t expect_out[HASH_SHA256_MSG_DIGEST_SIZE] = {0x74, 0xE7, 0xE5, 0xBB, 0x9D, 0x22, 0xD6, 0xDB, 0x26, 0xBF, + 0x76, 0x94, 0x6D, 0x40, 0xFF, 0xF3, 0xEA, 0x9F, 0x03, 0x46, + 0xB8, 0x84, 0xFD, 0x06, 0x94, 0x92, 0x0F, 0xCC, 0xFA, 0xD1, + 0x5E, 0x33 + }; struct rt_hwcrypto_ctx *ctx; ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA256); @@ -242,13 +264,20 @@ static void hash_sha256_test(void) } rt_kprintf("\n"); - rt_hwcrypto_hash_finish(ctx, out, HASH_SHA256_MSG_DIGEST_SIZE); - rt_kprintf("hash out data:"); + rt_hwcrypto_hash_finish(ctx, calc_out, HASH_SHA256_MSG_DIGEST_SIZE); + rt_kprintf("hash out expect_data:"); for (int i = 0; i < HASH_SHA256_MSG_DIGEST_SIZE; i++) { - rt_kprintf("%x ", out[i]); + rt_kprintf("%x ", expect_out[i]); } rt_kprintf("\n"); + + rt_kprintf("hash out calc_data:"); + for (int i = 0; i < HASH_SHA256_MSG_DIGEST_SIZE; i++) + { + rt_kprintf("%x ", calc_out[i]); + } + rt_kprintf("\n\n"); rt_hwcrypto_hash_destroy(ctx); } } @@ -269,7 +298,7 @@ static int crypto_sample(int argc, char *argv[]) if (!rt_strcmp("get", argv[2])) { rt_uint32_t result = rt_hwcrypto_rng_update(); - rt_kprintf("random number = %x \n", result); + rt_kprintf("random number = %x \n\n", result); } else { diff --git a/bsp/hc32/tests/test_dac.c b/bsp/hc32/tests/test_dac.c index 9821993bfa6..f7889e42bc5 100644 --- a/bsp/hc32/tests/test_dac.c +++ b/bsp/hc32/tests/test_dac.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-05 CDT support HC32F467 */ /* @@ -24,7 +26,7 @@ #define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ #define DAC_MAX_OUTPUT_VALUE 4095 -#if (defined (HC32F4A8) || defined (HC32F4A0)) && defined (BSP_USING_DAC2) +#if (defined (HC32F4A8) || defined (HC32F4A0) || defined (HC32F4A2)) && defined (BSP_USING_DAC2) extern void EthPhyDisable(void); #endif /* HC32F4A8 && BSP_USING_DAC2 */ @@ -47,11 +49,11 @@ static int dac_vol_sample(int argc, char *argv[]) rt_strcpy(dac_device_name, "dac1"); max_channel = 2; } -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467)|| defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) else if (0 == rt_strcmp(argv[1], "dac2")) { rt_strcpy(dac_device_name, "dac2"); -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467)|| defined (HC32F472) || defined (HC32F4A8) max_channel = 2; #elif defined (HC32F334) max_channel = 1; @@ -76,7 +78,7 @@ static int dac_vol_sample(int argc, char *argv[]) return -RT_ERROR; } } -#if (defined (HC32F4A8) || defined (HC32F4A0)) && defined (BSP_USING_DAC2) +#if (defined (HC32F4A8) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F467)) && defined (BSP_USING_DAC2) EthPhyDisable(); #endif /* 查找设备 */ diff --git a/bsp/hc32/tests/test_eth.c b/bsp/hc32/tests/test_eth.c index ac726651928..ac052293d1e 100644 --- a/bsp/hc32/tests/test_eth.c +++ b/bsp/hc32/tests/test_eth.c @@ -29,7 +29,7 @@ * ETH Communication USING MII * 3）拨码开关J33拨到MII端，编译下载、运行代码 * 4）等待msh> - * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.120 icmp_seq=0 ttl=128 time=1 ms） + * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.10 icmp_seq=0 ttl=128 time=1 ms） * 6）msh>窗口输入命令：eth_webserver * 7）PC打开浏览器，输入IP地址：192.168.1.30再按回车键，显示lwip的简介网页（lwIP - A Lightweight TCP/IP Stack）， * 表示成功访问目标板的HTTP服务器。 @@ -41,7 +41,7 @@ * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable ETH PHY interrupt mode: (16) ETH PHY Interrupt pin number * 3）拨码开关J33拨到MII端，编译下载、运行代码 * 4）等待msh> - * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.120 icmp_seq=0 ttl=128 time=1 ms） + * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.10 icmp_seq=0 ttl=128 time=1 ms） * 6）msh>窗口输入命令：eth_webserver * 7）PC打开浏览器，输入IP地址：192.168.1.30再按回车键，显示lwip的简介网页（lwIP - A Lightweight TCP/IP Stack）， * 表示成功访问目标板的HTTP服务器。 @@ -52,10 +52,12 @@ * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable Ethernet: ETH Communication USING RMII * 3）拨码开关J33拨到RMII端，编译下载、运行代码 * 4）等待msh> - * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.120 icmp_seq=0 ttl=128 time=1 ms） + * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.10 icmp_seq=0 ttl=128 time=1 ms） * 6）msh>窗口输入命令：eth_webserver * 7）PC打开浏览器，输入IP地址：192.168.1.30再按回车键，显示lwip的简介网页（lwIP - A Lightweight TCP/IP Stack）， * 表示成功访问目标板的HTTP服务器。 + * + * 注意：HC32F467仅支持case 3，且步骤3不需要拨码。 */ #include diff --git a/bsp/hc32/tests/test_fal.c b/bsp/hc32/tests/test_fal.c index 6acb246a4ad..fff4b1bd43c 100644 --- a/bsp/hc32/tests/test_fal.c +++ b/bsp/hc32/tests/test_fal.c @@ -16,7 +16,8 @@ * menuconfig: * RT-Thread Components ---> FAL: flash abstraction layer * ---> Device Drivers ---> Using SPI Bus/Device device drivers ---> Using Serial Flash Universal Driver - * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable on-chip FLASH + * Hardware Drivers Config ---> Onboard On-chip Peripheral Drivers ----> Enable on-chip FLASH + * NOTE: 忽略‘[E/SFUD] ERROR: Flash device w25q64 not found!’错误，不影响测试 */ #include #include diff --git a/bsp/hc32/tests/test_gpio.c b/bsp/hc32/tests/test_gpio.c index 9107abe83ff..3f38b52c450 100644 --- a/bsp/hc32/tests/test_gpio.c +++ b/bsp/hc32/tests/test_gpio.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ /* @@ -27,20 +28,24 @@ * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable TCA9539 */ #if defined(HC32F460) - #define LED1_PIN_NUM GET_PIN(D, 3) /* LED0 */ - #define KEY1_PIN_NUM GET_PIN(B, 1) /* K10 */ -#elif defined(HC32F4A0) || defined(HC32F4A8) - #define LED1_PIN_NUM GET_PIN(B, 11) /* LED10 */ - #define KEY1_PIN_NUM GET_PIN(A, 0) /* K10 */ + #define LED_PIN_NUM GET_PIN(D, 3) /* LED0 */ + #define KEY_PIN_NUM GET_PIN(B, 1) /* K10 */ +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) + #define LED_PIN_NUM GET_PIN(B, 11) /* LED10 */ + #define KEY_PIN_NUM GET_PIN(A, 0) /* K10 */ #elif defined(HC32F448) - #define LED1_PIN_NUM GET_PIN(A, 2) /* LED3 */ - #define KEY1_PIN_NUM GET_PIN(B, 6) /* K5 */ + #define LED_PIN_NUM GET_PIN(A, 2) /* LED3 */ + #define KEY_PIN_NUM GET_PIN(B, 6) /* K5 */ #elif defined(HC32F472) - #define LED1_PIN_NUM GET_PIN(C, 9) /* LED5 */ - #define KEY1_PIN_NUM GET_PIN(B, 5) /* K10 */ + #define LED_PIN_NUM GET_PIN(C, 9) /* LED5 */ + #define KEY_PIN_NUM GET_PIN(B, 5) /* K10 */ #elif defined(HC32F334) - #define LED1_PIN_NUM GET_PIN(C, 13) /* LED1 */ - #define KEY1_PIN_NUM GET_PIN(C, 3) /* K1 */ + #define LED_PIN_NUM GET_PIN(C, 13) /* LED1 */ + #define KEY_PIN_NUM GET_PIN(C, 3) /* K1 */ +#elif defined(HC32F467) + /* NOTE: NEED short J13 to use LED11. */ + #define LED_PIN_NUM GET_PIN(C, 9) /* LED11 */ + #define KEY_PIN_NUM GET_PIN(A, 0) /* K5 */ #endif static uint8_t u8LedState = 1; @@ -50,29 +55,29 @@ void led_control(void *args) u8LedState = !u8LedState; if (0 == u8LedState) { - rt_pin_write(LED1_PIN_NUM, PIN_LOW); + rt_pin_write(LED_PIN_NUM, PIN_LOW); } else { - rt_pin_write(LED1_PIN_NUM, PIN_HIGH); + rt_pin_write(LED_PIN_NUM, PIN_HIGH); } } static void pin_sample(void) { /* LED引脚为输出模式 */ - rt_pin_mode(LED1_PIN_NUM, PIN_MODE_OUTPUT); + rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT); /* 默认高电平 */ - rt_pin_write(LED1_PIN_NUM, PIN_HIGH); + rt_pin_write(LED_PIN_NUM, PIN_HIGH); /* 按键1引脚为输入模式 */ - rt_pin_mode(KEY1_PIN_NUM, PIN_MODE_INPUT_PULLUP); + rt_pin_mode(KEY_PIN_NUM, PIN_MODE_INPUT_PULLUP); /* 绑定中断，下降沿模式，回调函数名为led_control */ - // rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_RISING, led_control, RT_NULL); - // rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_FALLING, led_control, RT_NULL); - rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_RISING_FALLING, led_control, RT_NULL); + // rt_pin_attach_irq(KEY_PIN_NUM, PIN_IRQ_MODE_RISING, led_control, RT_NULL); + // rt_pin_attach_irq(KEY_PIN_NUM, PIN_IRQ_MODE_FALLING, led_control, RT_NULL); + rt_pin_attach_irq(KEY_PIN_NUM, PIN_IRQ_MODE_RISING_FALLING, led_control, RT_NULL); /* 使能中断 */ - rt_pin_irq_enable(KEY1_PIN_NUM, PIN_IRQ_ENABLE); + rt_pin_irq_enable(KEY_PIN_NUM, PIN_IRQ_ENABLE); } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pin_sample, pin sample); diff --git a/bsp/hc32/tests/test_i2c.c b/bsp/hc32/tests/test_i2c.c index ecfea2f1004..a30a4291a7d 100644 --- a/bsp/hc32/tests/test_i2c.c +++ b/bsp/hc32/tests/test_i2c.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ /* @@ -30,16 +31,17 @@ #define USING_RT_I2C_TRANSFER /* defined EEPROM */ -#if defined(HC32F472) || defined(HC32F460) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) || \ - defined(HC32F334) +#if defined(HC32F472) || defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || \ + defined(HC32F4A8) || defined(HC32F334) || defined(HC32F467) #define EE_DEV_ADDR 0x50 #define EE_TEST_PAGE_CNT 8 // Test 8 pages #endif /* define EEPROM hardware */ -#if defined(HC32F472) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) +#if defined(HC32F472) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) #define EE24C256 -#elif defined(HC32F4A0) +#elif defined(HC32F4A0) || defined(HC32F4A2) #define EE24C02 #endif @@ -55,7 +57,8 @@ #endif /* device information */ -#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) +#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || \ + defined(HC32F4A8) || defined(HC32F334) || defined(HC32F467) #define HW_I2C_DEV "i2c1" #define SW_I2C_DEV "i2c1_sw" #elif defined(HC32F460) @@ -119,15 +122,12 @@ static void eeprom_page_read(uint32_t page, uint8_t *pBuf) hc32_i2c = rt_i2c_bus_device_find(SW_I2C_DEV); //sw i2c #endif - if (EE_WORD_ADR_SIZE == 2) - { - readAddr[0] = (page * EE_PAGE_SIZE) / 256; // addrH - readAddr[1] = page * EE_PAGE_SIZE; // addrL - } - else - { - readAddr[0] = page * EE_PAGE_SIZE; - } +#if (EE_WORD_ADR_SIZE == 2) + readAddr[0] = (page * EE_PAGE_SIZE) / 256; // addrH + readAddr[1] = page * EE_PAGE_SIZE; // addrL +#else + readAddr[0] = page * EE_PAGE_SIZE; +#endif #if defined(USING_RT_I2C_TRANSFER) msg[0].addr = EE_DEV_ADDR; @@ -191,7 +191,8 @@ void eeprom_test(void) } /* TCA9539 device */ -#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || \ + defined(HC32F4A8) || defined(HC32F467) /* TCA9539 define */ #define TCA9539_DEV_ADDR (0x74) // TCA9539 chip address on I2C bus @@ -262,7 +263,8 @@ void tca9539_test(void) static void i2c_sample(int argc, char *argv[]) { eeprom_test(); -#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F4A8) || \ + defined(HC32F467) tca9539_test(); #endif } diff --git a/bsp/hc32/tests/test_nand.c b/bsp/hc32/tests/test_nand.c index 5958ba93384..c64d9a24bd1 100644 --- a/bsp/hc32/tests/test_nand.c +++ b/bsp/hc32/tests/test_nand.c @@ -14,7 +14,7 @@ * 程序功能：对整个Nand存储空间进行擦除、写和读操作，比较数据是否一致 * * 注意: - * F4A0: 修改函数SystemClock_Config，调用函数CLK_SetClockDiv参数，CLK_EXCLK_DIV2改为CLK_EXCLK_DIV4; + * F4A0/F4A2: 修改函数SystemClock_Config，调用函数CLK_SetClockDiv参数，CLK_EXCLK_DIV2改为CLK_EXCLK_DIV4; * * menuconfig: * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable EXMC ----> Using SDRAM or NAND ----> Using NAND diff --git a/bsp/hc32/tests/test_pm.c b/bsp/hc32/tests/test_pm.c index cb334e2b55d..1f9d0eccd2e 100644 --- a/bsp/hc32/tests/test_pm.c +++ b/bsp/hc32/tests/test_pm.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-04 CDT Support HC32F467 */ /* @@ -41,7 +43,7 @@ #if defined(BSP_USING_PM) -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F467) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) #define BSP_KEY_PORT (GPIO_PORT_A) #define BSP_KEY_PIN (GPIO_PIN_00) @@ -49,7 +51,7 @@ #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ0) #define BSP_KEY_IRQn (INT001_IRQn) #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH0) - #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ0) + #define BSP_KEY_EVT (INTC_EVT1) #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP0) #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP00) @@ -68,7 +70,7 @@ #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ1) #define BSP_KEY_IRQn (INT001_IRQn) #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH1) - #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ1) + #define BSP_KEY_EVT (INTC_EVT1) #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP01) @@ -87,7 +89,7 @@ #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ6) #define BSP_KEY_IRQn (INT001_IRQn) #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH6) - #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ6) + #define BSP_KEY_EVT (INTC_EVT1) #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP12) @@ -106,7 +108,7 @@ #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ5) #define BSP_KEY_IRQn (INT001_IRQn) #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH5) - #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ5) + #define BSP_KEY_EVT (INTC_EVT1) #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP11) @@ -121,7 +123,7 @@ #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ9) #define BSP_KEY_IRQn (INT001_IRQn) #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH9) - #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ9) + #define BSP_KEY_EVT (INTC_EVT1) #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP2) #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP21) @@ -198,10 +200,10 @@ static void _key_int_init(void) NVIC_EnableIRQ(stcIrqSignConfig.enIRQn); } - static void _wkup_cfg_sleep_deep() { INTC_WakeupSrcCmd(BSP_KEY_INTC_STOP_WKUP_EXTINT, ENABLE); + INTC_EventCmd(BSP_KEY_EVT, ENABLE); } static void _wkup_cfg_sleep_standby(void) @@ -232,7 +234,7 @@ static void _sleep_enter_event_deep(void) static void _sleep_enter_event_standby(void) { _wkup_cfg_sleep_standby(); -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F467) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) PWC_BKR_Write(0, g_keycnt_cmd & 0xFF); #endif *KEYCNT_BACKUP_ADDR = g_keycnt_cmd; @@ -290,12 +292,14 @@ static void _notify_func(uint8_t event, uint8_t mode, void *data) { if (event == RT_PM_ENTER_SLEEP) { - SysTick_Suspend(); if (sleep_enter_func[mode] == RT_NULL) { return; } - GPIO_ResetPins(LED_GREEN_PORT, LED_GREEN_PIN); + /* shutdown LED before enter sleep mode to decrease power consumption */ + rt_pin_write(LED_GREEN_PIN, PIN_LOW); + + SysTick_Suspend(); sleep_enter_func[mode](); } else @@ -350,7 +354,7 @@ static void pm_cmd_handler(void *parameter) } } -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) +#if defined (HC32F467) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) static void pm_run_main(void *parameter) { static rt_uint8_t run_index = 0; @@ -383,7 +387,7 @@ static void pm_run_main(void *parameter) static void _keycnt_cmd_init_after_power_on(void) { en_flag_status_t wkup_from_ptwk = PWC_PD_GetWakeupStatus(PWC_PD_WKUP_FLAG_WKUP0); -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F467) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) en_flag_status_t bakram_pd = PWC_BKR_GetStatus(PWC_BACKUP_RAM_FLAG_RAMPDF); uint8_t bkr0 = PWC_BKR_Read(0); @@ -421,7 +425,7 @@ static void _keycnt_cmd_init_after_power_on(void) pm_dbg("KEYCNT_BACKUP_ADDR addr =0x%p,value = %d\n", KEYCNT_BACKUP_ADDR, *KEYCNT_BACKUP_ADDR); pm_dbg("wkup_from_ptwk = %d\n", wkup_from_ptwk); -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F467) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) pm_dbg("bakram_pd = %d\n", bakram_pd); pm_dbg("bkr0 = %d\n", bkr0); #endif @@ -429,7 +433,7 @@ static void _keycnt_cmd_init_after_power_on(void) static void _vbat_init(void) { -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F467) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) while (PWC_BKR_GetStatus(PWC_BACKUP_RAM_FLAG_RAMVALID) == RESET) { rt_thread_delay(10); @@ -465,7 +469,7 @@ int pm_sample_init(void) rt_kprintf("create pm sample thread failed!\n"); } -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) +#if defined (HC32F467) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) thread = rt_thread_create("pm_run_main", pm_run_main, RT_NULL, 1024, 25, 10); if (thread != RT_NULL) { diff --git a/bsp/hc32/tests/test_pulse_encoder.c b/bsp/hc32/tests/test_pulse_encoder.c index 641e45d00f0..06e2ebd7237 100644 --- a/bsp/hc32/tests/test_pulse_encoder.c +++ b/bsp/hc32/tests/test_pulse_encoder.c @@ -6,11 +6,16 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-09 CDT Support HC32F467 */ /* - * 程序清单： Pulse encoder 设备使用例程, 请在图形化配置界面打开pulse encoder device， - * 并使能tmra_1和tmr6_1. + * 程序清单： Pulse encoder 设备使用例程 + * + * menuconfig: + * Hardware Drivers Config ---> On-Chip Peripheral Drivers ----> [*] Enable Pulse Encoder ----> [*] Use TIMERA As The Pulse Encoder ---> [*] Use TIMERA_1 As The Pulse Encoder + * [*] Use TIMER6 As The Pulse Encoder ---> [*] Use TIMER6_1 As The Pulse Encoder * 例程导出了 encoder_sample 命令到控制终端, 通过串口可查看当前的count数值 * 命令调用格式：pulse_encoder_sample devname [option1] [option2] * devname: [pulse_a1/pulse_61] 编码器单元名称 @@ -19,7 +24,6 @@ * eg:encoder_sample pulse_a1 2000 1000 * 编码器的分辨率是1000 * 硬件IO查看对应board/board_config.h中相关端口定义，并且需要正确连接到对应模拟脉冲生成的端口 - * 程序功能： */ #include @@ -30,7 +34,7 @@ #ifdef BSP_USING_PULSE_ENCODER -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) #define TEST_IO_A_PIN GET_PIN(A, 5) #define TEST_IO_B_PIN GET_PIN(A, 6) #else @@ -42,7 +46,7 @@ static rt_device_t pulse_encoder_dev = RT_NULL; static void printf_connect(void) { -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) rt_kprintf(" [tmra]*connect PA5-->PA8 PA6-->PA9\n"); #endif diff --git a/bsp/hc32/tests/test_qspi.c b/bsp/hc32/tests/test_qspi.c index 66bd0106d77..d785f79b4c5 100644 --- a/bsp/hc32/tests/test_qspi.c +++ b/bsp/hc32/tests/test_qspi.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-10 CDT Support HC32F467 */ /* @@ -59,7 +61,7 @@ #define W25Q_QSPI_DATA_BUF_LEN 0x2000 #define W25Q_QSPI_WR_CMD W25Q64_QUAD_INPUT_PAGE_PROGRAM -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F467) #ifndef BSP_QSPI_USING_SOFT_CS #if (W25Q_QSPI_WR_CMD == W25Q64_QUAD_INPUT_PAGE_PROGRAM) #error "QUAD PAGE PROGRAM must use soft CS pin!!" @@ -107,7 +109,7 @@ static int rt_hw_qspi_flash_init(void) #else #if defined (HC32F472) if (RT_EOK != rt_hw_qspi_bus_attach_device("qspi1", "qspi10", GET_PIN(B, 12), W25Q_QSPI_DATA_LINE_WIDTH, RT_NULL, RT_NULL)) -#elif defined (HC32F4A0) || defined (HC32F460) || defined (HC32F448) || defined (HC32F4A8) +#elif defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F460) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F467) if (RT_EOK != rt_hw_qspi_bus_attach_device("qspi1", "qspi10", GET_PIN(C, 7), W25Q_QSPI_DATA_LINE_WIDTH, RT_NULL, RT_NULL)) #endif #endif diff --git a/bsp/hc32/tests/test_rtc.c b/bsp/hc32/tests/test_rtc.c index 8aa0bde8d87..ce4a67b0749 100644 --- a/bsp/hc32/tests/test_rtc.c +++ b/bsp/hc32/tests/test_rtc.c @@ -11,9 +11,15 @@ /* * 程序清单：这是 RTC 设备使用例程和 Alarm 使用示例。 * 例程导出了 rtc_sample 命令到控制终端。 + * menuconfig: + * 1.Hardware Drivers Config--->On-Chip Peripheral Driver--->Enable RTC---> Select clock source(RTC USING XTAL32) + * 2.RT-Thread Components---> Device Drivers ---> [-*-] Using RTC device drivers ---> [*] Using RTC alarm + * (1024) stack size for alarm thread + * [*] Using local time for the alarm calculation * 命令调用格式：rtc_sample x * 命令解释：命令第二个参数是要使用的功能对应的编号， * RTC 基本功能对应的编号为 0~3，Alarm 功能对应的编号为 4~9 + * NOTE: 注意时间和日期格式，请严格按照提示位数输入！ */ #include @@ -33,7 +39,6 @@ static rt_device_t rtc_dev; #if defined(RT_USING_ALARM) extern void rt_alarm_dump(void); - static rt_uint16_t callback_counter, alarm_idx = 0; static struct rt_alarm *ptr_alarm = RT_NULL; static struct rt_alarm_setup alarm_setup; #endif /* RT_USING_ALARM */ @@ -56,18 +61,7 @@ enum RTC_CMD void alarm_callback_fun(rt_alarm_t alarm, time_t timestamp) { - rt_kprintf("\nuser alarm %d callback function.\n", alarm_idx); - if ((0 == (--callback_counter)) && (alarm_idx)) - { - rt_kprintf("stop alarm %d \n", alarm_idx); - if (RT_EOK != rt_alarm_stop(alarm)) - { - rt_kprintf("failed to stop alarm\n"); - } - /* enter callback 2 times */ - callback_counter = 2; - --alarm_idx; - } + rt_kprintf("User alarm callback function.\nNow time is: %s", ctime(×tamp)); } #else }; @@ -85,18 +79,20 @@ static int rtc_sample(int argc, char *argv[]) if (argc < 2) { rt_kprintf("unkown rtc command, rtc [usage] as the following: \n"); - rt_kprintf("\'0\': find and open rtc \n"); - rt_kprintf("\'1 xx:xx:xx\': set time with \n"); - rt_kprintf("\'2 xxxx-xx-xx\': set date with \n"); - rt_kprintf("\'3\': get time and date \n"); + rt_kprintf("\'rtc_sample 0\': find and open rtc \n"); + rt_kprintf("\'rtc_sample 1 HH:MM:SS\': set time with \n"); + rt_kprintf("\'rtc_sample 2 yyyy-mm-dd\': set date with \n"); + rt_kprintf("\'rtc_sample 3\': get time and date \n"); #if defined(RT_USING_ALARM) - rt_kprintf("\'4\': set current time + 10s as alarm \n"); - rt_kprintf("\'5\': start alarm \n"); - rt_kprintf("\'6\': stop alarm \n"); + rt_kprintf("\'rtc_sample 4\': set current time + 1 Min as alarm \n"); + rt_kprintf("\'rtc_sample 5\': start alarm \n"); + rt_kprintf("\'rtc_sample 6\': stop alarm \n"); rt_kprintf("cmd-7 based on cmd-4\n"); - rt_kprintf("\'7\' o: oneshot,\n\'7\' s: second,\n\'7\' m: minute \n"); - rt_kprintf("\'8\': dump all alarm \n"); - rt_kprintf("\'9\': delete all alarm \n"); + rt_kprintf("\'rtc_sample 7 o\': oneshot \n"); + rt_kprintf("\'rtc_sample 7 s\': second \n"); + rt_kprintf("\'rtc_sample 7 m\': minute \n"); + rt_kprintf("\'rtc_sample 8\': dump all alarm \n"); + rt_kprintf("\'rtc_sample 9\': delete all alarm \n"); #endif /* RT_USING_ALARM */ return -RT_ERROR; } @@ -120,7 +116,7 @@ static int rtc_sample(int argc, char *argv[]) rt_kprintf("rtc opened\n"); break; case CMD_SET_TIME: - /* set time with xx:xx:xx format characters */ + /* set time with hh:mm:ss format characters */ if (argc < 3) { rt_kprintf("unsurpported command\n"); @@ -140,7 +136,7 @@ static int rtc_sample(int argc, char *argv[]) rt_kprintf("\nset RTC time as %2d:%2d:%2d\n", temp1, temp2, temp3); break; case CMD_SET_DATE: - /* set data xxxx-xx-xx format characters */ + /* set data yyyy-mm-dd format characters */ temp1 = ((argv[2][0] - '0') * 1000) + \ ((argv[2][1] - '0') * 100) + \ ((argv[2][2] - '0') * 10) + \ @@ -154,7 +150,7 @@ static int rtc_sample(int argc, char *argv[]) rt_kprintf("failed to set date for %s\n", SAMPLE_RTC_NAME); return -RT_ERROR; } - rt_kprintf("\nset RTC date as %4d-%2d-%2d\n", temp1, temp2, temp3); + rt_kprintf("\nset RTC date as %4d-%02d-%02d\n", temp1, temp2, temp3); break; case CMD_GET_DATE_TIME: /* get current time and print it */ @@ -166,9 +162,12 @@ static int rtc_sample(int argc, char *argv[]) /* get current time (uint: second) from 1970-01-01 */ now = time(NULL); rt_kprintf("GMT time is: \n%s\n", ctime(&now)); - now += 60; + /* converts the local time into the calendar time. */ +#ifdef RT_ALARM_USING_LOCAL_TIME + localtime_r(&now, &p_tm); +#else gmtime_r(&now, &p_tm); - // localtime_r(&now, &p_tm); +#endif alarm_setup.flag = RT_ALARM_MINUTE; alarm_setup.wktime.tm_year = p_tm.tm_year; alarm_setup.wktime.tm_mon = p_tm.tm_mon; @@ -177,23 +176,31 @@ static int rtc_sample(int argc, char *argv[]) alarm_setup.wktime.tm_wday = p_tm.tm_wday; alarm_setup.wktime.tm_hour = p_tm.tm_hour; alarm_setup.wktime.tm_min = p_tm.tm_min; - alarm_setup.wktime.tm_sec = p_tm.tm_sec; + alarm_setup.wktime.tm_sec = 0; //p_tm.tm_sec; alarm_setup.wktime.tm_isdst = -1; + alarm_setup.wktime.tm_min += 1; + if (alarm_setup.wktime.tm_min > 59) + { + alarm_setup.wktime.tm_min = 0; + alarm_setup.wktime.tm_hour += 1; + if (alarm_setup.wktime.tm_hour > 23) + { + alarm_setup.wktime.tm_hour = 0; + } + } rt_kprintf("UTC alarm Time: \n%d-%02d-%02d %02d:%02d:%02d\n\n", - p_tm.tm_year + 1900, - p_tm.tm_mon + 1, - p_tm.tm_mday, - p_tm.tm_hour, - p_tm.tm_min, - p_tm.tm_sec); + alarm_setup.wktime.tm_year + 1900, + alarm_setup.wktime.tm_mon + 1, + alarm_setup.wktime.tm_mday, + alarm_setup.wktime.tm_hour, + alarm_setup.wktime.tm_min, + alarm_setup.wktime.tm_sec); ptr_alarm = rt_alarm_create(alarm_callback_fun, &alarm_setup); if (RT_NULL == ptr_alarm) { rt_kprintf("failed to create rtc alarm\n"); return -RT_ERROR; } - callback_counter = 2; - ++alarm_idx; rt_alarm_dump(); break; case CMD_SET_START_ALARM: @@ -245,7 +252,6 @@ static int rtc_sample(int argc, char *argv[]) { rt_kprintf("failed to delete alarm\n"); } - alarm_idx = 0; rt_kprintf("alarm deleted\n"); break; #endif /* RT_USING_ALARM */ diff --git a/bsp/hc32/tests/test_sdmmc.c b/bsp/hc32/tests/test_sdmmc.c index 9cebb78e161..e0cacdd22d9 100644 --- a/bsp/hc32/tests/test_sdmmc.c +++ b/bsp/hc32/tests/test_sdmmc.c @@ -18,6 +18,11 @@ * stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL; * 改为 * stcPLLHInit.PLLCFGR_f.PLLN = 100UL - 1UL; + * + * menuconfig: + * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable SDIO ----> Enable SDIOx（x：测试板硬件决定） + * + * RT-Thread Components ---> Device Drivers ---> Using SD/MMC device drivers ---> (1024) The stack size for mmcsd thread */ #include diff --git a/bsp/hc32/tests/test_sdram.c b/bsp/hc32/tests/test_sdram.c index c02c78f0d38..ef37650e98f 100644 --- a/bsp/hc32/tests/test_sdram.c +++ b/bsp/hc32/tests/test_sdram.c @@ -14,7 +14,7 @@ * 程序功能：以8/16/32bit方式分别对整个SDRAM存储空间进行写和读操作，比较数据是否一致 * * 注意: - * F4A0: 修改函数SystemClock_Config，调用函数CLK_SetClockDiv参数，CLK_EXCLK_DIV2改为CLK_EXCLK_DIV8(EXCLK: 30MHz); + * F4A0/F4A2/F467: 修改函数SystemClock_Config，调用函数CLK_SetClockDiv参数，CLK_EXCLK_DIV2改为CLK_EXCLK_DIV8(EXCLK: 30MHz); * * menuconfig: * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable EXMC ----> Using SDRAM or NAND ----> Using SDRAM diff --git a/bsp/hc32/tests/test_spi.c b/bsp/hc32/tests/test_spi.c index 171c70da8d4..d8f272ebc5e 100644 --- a/bsp/hc32/tests/test_spi.c +++ b/bsp/hc32/tests/test_spi.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-04 CDT Support HC32F467 */ /* @@ -37,14 +39,14 @@ #define W25Q_MAX_ADDR (0x800000UL) #define W25Q_SPI_WR_RD_ADDR 0x4000 -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F467) #define W25Q_SPI_DATA_BUF_LEN 0x2000 #elif defined (HC32F334) #define W25Q_SPI_DATA_BUF_LEN 0x1000 #endif -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F4A8) || defined (HC32F467) #define SPI_CS_PORT SPI1_CS_PORT #define SPI_CS_PIN SPI1_CS_PIN #define SPI_CS_PORT_PIN GET_PIN(C, 7) diff --git a/bsp/hc32/tests/test_tmr_capture.c b/bsp/hc32/tests/test_tmr_capture.c index 2a94e5aee78..1a0ecf6d90f 100644 --- a/bsp/hc32/tests/test_tmr_capture.c +++ b/bsp/hc32/tests/test_tmr_capture.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2025-01-10 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ /* @@ -16,7 +17,8 @@ * 默认配置 * input pin： * icx: INPUT_CAPTURE_TMR6_x_PORT, INPUT_CAPTURE_TMR6_x_PIN (x=1~IC_DEV_CNT) - 注：该引脚配置位于 board_config.h，若测试单元的input pin未配置，需测试人员自行添加 + 注：该引脚配置位于 board_config.h，若测试单元的input pin未配置，需测试人员自行添加,并于 + board_config.c中做初始化 * watermark： * 默认值为 5 * @@ -58,9 +60,9 @@ #define MSH_USAGE_IC_SET_WM " ic wm - e.g., set warter mark of ic3 to 11: ic wm 3 11\n" #define MSH_USAGE_IC_CLR " ic clr - e.g., clear data buffer of ic3: ic clr 3 \n" -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) #define IC_DEV_CNT (8) -#elif defined (HC32F460) +#elif defined (HC32F460) || defined (HC32F467) #define IC_DEV_CNT (3) #elif defined (HC32F334) #define IC_DEV_CNT (4) @@ -223,7 +225,7 @@ static rt_err_t _msh_cmd_parse_unit(char *n, uint32_t *u_out) return RT_EOK; } -void _show_usage(void) +static void _show_usage(void) { rt_kprintf("Usage: \n"); rt_kprintf(MSH_USAGE_IC_OPEN); diff --git a/bsp/hc32/tests/test_uart_v1.c b/bsp/hc32/tests/test_uart_v1.c index 9d5958c0939..0fd63a1b764 100644 --- a/bsp/hc32/tests/test_uart_v1.c +++ b/bsp/hc32/tests/test_uart_v1.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ /* @@ -40,8 +41,8 @@ #if defined(HC32F460) && defined(BSP_USING_UART2) #define SAMPLE_DEFAULT_UART_NAME "uart2" -#elif defined(HC32F4A0) && defined (BSP_USING_UART6) - #define SAMPLE_DEFAULT_UART_NAME "uart6" +#elif (defined(HC32F4A0) || defined(HC32F4A2)) && defined (BSP_USING_UART6) + #define SAMPLE_DEFAULT_UART_NAME "uart6" /* TX:PE6, RX:PH6 */ #elif defined(HC32F448) && defined (BSP_USING_UART1) #define SAMPLE_DEFAULT_UART_NAME "uart1" #elif defined(HC32F472) && defined (BSP_USING_UART1) @@ -50,6 +51,8 @@ #define SAMPLE_DEFAULT_UART_NAME "uart6" #elif defined(HC32F334) && defined (BSP_USING_UART1) #define SAMPLE_DEFAULT_UART_NAME "uart1" +#elif defined (HC32F467) && defined (BSP_USING_UART6) + #define SAMPLE_DEFAULT_UART_NAME "uart6" #endif #if defined(SAMPLE_DEFAULT_UART_NAME) diff --git a/bsp/hc32/tests/test_uart_v2.c b/bsp/hc32/tests/test_uart_v2.c index 11ab6c466de..b79cbed75da 100644 --- a/bsp/hc32/tests/test_uart_v2.c +++ b/bsp/hc32/tests/test_uart_v2.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ /* @@ -14,7 +16,7 @@ * * 命令解释：命令第二个参数是要使用的串口设备名称，为空则使用默认的串口设备(uart1) * 程序功能：通过串口输出字符串: - * drv_usart: drv_usart_v1 + * drv_usart: drv_usart_v2 * commnucation：using DMA/interrupt, * uart_ch: uartx (x对应测试通道) * 输出输入的字符 @@ -68,8 +70,8 @@ #if defined(HC32F460) && defined(BSP_USING_UART2) #define SAMPLE_DEFAULT_UART_NAME "uart2" -#elif defined(HC32F4A0) && defined (BSP_USING_UART6) - #define SAMPLE_DEFAULT_UART_NAME "uart6" +#elif (defined(HC32F4A0) || defined(HC32F4A2)) && defined (BSP_USING_UART6) + #define SAMPLE_DEFAULT_UART_NAME "uart6" /* TX:PE6, RX:PH6 */ #elif defined(HC32F448) && defined (BSP_USING_UART1) #define SAMPLE_DEFAULT_UART_NAME "uart1" #elif defined(HC32F472) && defined (BSP_USING_UART1) @@ -78,6 +80,8 @@ #define SAMPLE_DEFAULT_UART_NAME "uart6" #elif defined(HC32F334) && defined (BSP_USING_UART1) #define SAMPLE_DEFAULT_UART_NAME "uart1" +#elif defined (HC32F467) && defined (BSP_USING_UART6) + #define SAMPLE_DEFAULT_UART_NAME "uart6" #endif #if defined(SAMPLE_DEFAULT_UART_NAME) diff --git a/bsp/hc32/tests/test_usbd.c b/bsp/hc32/tests/test_usbd.c index 5a4a19027bd..f6790f73786 100644 --- a/bsp/hc32/tests/test_usbd.c +++ b/bsp/hc32/tests/test_usbd.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include @@ -32,13 +34,18 @@ */ #define USBD_DEV_NAME "vcom" /* 名称 */ -rt_uint8_t str_read[255]; +static rt_uint8_t cdc_str_read[256]; static rt_err_t cdc_rx_handle(rt_device_t dev, rt_size_t size) { + if (size >= sizeof(cdc_str_read)) + { + size = sizeof(cdc_str_read) - 1; + } /* 读取虚拟串口接收内容 */ - rt_device_read(dev, 0, str_read, size); - rt_kprintf("Read message: %s\n", str_read); + rt_device_read(dev, 0, cdc_str_read, size); + cdc_str_read[size] = '\0'; + rt_kprintf("Read message: %s\n", cdc_str_read); return RT_EOK; } @@ -90,8 +97,8 @@ MSH_CMD_EXPORT(cdc_sample, usbd cdc sample); #if defined(RT_USB_DEVICE_MSTORAGE) -/* F4A0 only FS can used with spi flash */ -#if ((defined(HC32F4A0) || defined(HC32F4A8)) && defined(BSP_USING_USBFS)) || \ +/* F4A0/F4A2/HC32F467 only FS can used with spi flash */ +#if ((defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467)) && defined(BSP_USING_USBFS)) || \ defined(HC32F460) || defined(HC32F472) /* Enable spibus1, SFUD, usb msc */ @@ -108,8 +115,8 @@ MSH_CMD_EXPORT(cdc_sample, usbd cdc sample); (50000000)Default spi maximum speed(HZ) 4. RT-Thread Components--->Using USB legacy version [*]Using USB device---> - Device type--->...Mass Storage device - (spiflash)msc class disk name + [*]Device type---> Enable to use device as Mass Storage device + (spiflash)msc class disk name */ #include "drv_gpio.h" @@ -117,7 +124,7 @@ MSH_CMD_EXPORT(cdc_sample, usbd cdc sample); #include "dev_spi_flash_sfud.h" #define SPI_FLASH_CHIP RT_USB_MSTORAGE_DISK_NAME /* msc class disk name */ -#if defined(HC32F4A0) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) #define SPI_FLASH_SS_PORT GPIO_PORT_C #define SPI_FLASH_SS_PIN GPIO_PIN_07 #define SPI_BUS_NAME "spi1" @@ -157,7 +164,8 @@ static void rt_hw_spi_flash_reset(char *spi_dev_name) static int rt_hw_spi_flash_with_sfud_init(void) { -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F4A8) || \ + defined(HC32F467) rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, GET_PIN(C, 7)); #elif defined(HC32F472) rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, GET_PIN(B, 12)); @@ -201,7 +209,7 @@ INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init); */ #define USBD_DEV_NAME "hidd" /* 名称 */ -#if defined(HC32F4A0) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) #define KEY_PIN_NUM GET_PIN(A,0) /* PA0 */ #elif defined(HC32F460) #define KEY_PIN_NUM GET_PIN(B,1) /* PB1 */ @@ -246,7 +254,8 @@ static int hid_sample(void) } } - //return ret; + /* unreachable, but keeps static analyzers happy */ + return ret; } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(hid_sample, usbd hid sample); @@ -274,25 +283,29 @@ MSH_CMD_EXPORT(hid_sample, usbd hid sample); * 通过llcom.exe可发送bulk数据（100字符以内）到设备，设备收到后会回发给主机(llcom.exe)，同时通过MSH终端显示收到的HEX数据。 * 注意：1、llcom.exe中的GUID与驱动程序中设定保持一致(通过设备管理器选择RTT Win USB设备的属性来查看)； * 2、win_usb_read()函数中的UIO_REQUEST_READ_FULL改为UIO_REQUEST_READ_BEST，实现数据即读即取; - * 否则需要接满传入的size数量，才会回调接收函数。 + * 否则需要接满传入的sizeof(winusb_str_read)数量的数据，才会回调接收函数。 * */ #define WINUSB_DEV_NAME "winusb" /* 名称 */ -uint8_t str_read[100]; +static rt_uint8_t winusb_str_read[100]; static rt_err_t winusb_rx_handle(rt_device_t dev, rt_size_t size) { uint8_t i; + if (size > sizeof(winusb_str_read)) + { + size = sizeof(winusb_str_read); + } /* 读取定时器当前值 */ rt_kprintf("Rx:"); for (i = 0; i < size; i++) { - rt_kprintf("%x", str_read[i]); + rt_kprintf("%x", winusb_str_read[i]); } rt_kprintf("\r\n"); - rt_device_write(dev, 0, str_read, size); + rt_device_write(dev, 0, winusb_str_read, size); /* prepare read config */ - rt_device_read(dev, 0, str_read, sizeof(str_read)); + rt_device_read(dev, 0, winusb_str_read, sizeof(winusb_str_read)); return RT_EOK; } @@ -322,7 +335,7 @@ static int winusb_sample(void) if (ret == RT_EOK) { /* prepare read config,set once,read once, */ - rt_device_read(winusb_dev, 0, str_read, sizeof(str_read)); + rt_device_read(winusb_dev, 0, winusb_str_read, sizeof(winusb_str_read)); } return ret; } diff --git a/bsp/hc32/tests/test_wktm.c b/bsp/hc32/tests/test_wktm.c new file mode 100644 index 00000000000..371878839be --- /dev/null +++ b/bsp/hc32/tests/test_wktm.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-24 CDT first version + */ + +/** + * menuconfig: + * Hardware Drivers Config ---> On-Chip Peripheral Driver---> [*] Enable PM + * RT-Thread Kernel ---> (1024) The stack size of idle thread + */ + +#include +#include "board.h" +#include "drv_wktm.h" + +#if defined(BSP_USING_PM) + +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) + #define WKTM_IRQn (INT131_IRQn) +#elif defined (HC32F460) + #define WKTM_IRQn (INT130_IRQn) +#endif + +static volatile rt_uint32_t last_tick; + +#if defined (HC32F334) || defined (HC32F448) || defined (HC32F472) + void PWC_WKTM_Handler(void) +#elif defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) || defined (HC32F460) + void PWC_WakeupTimer_IrqHandler(void) +#endif +{ + static rt_uint32_t delta_tick; + + rt_interrupt_enter(); + + delta_tick = rt_tick_get() - last_tick; + last_tick = rt_tick_get(); + + /* 打印出的tick值由于printf原因可能有误差 */ + rt_kprintf("Wakeup-timer irq interval ticks: approximate %d.\r\n", delta_tick); + + rt_interrupt_leave(); + +#if defined (HC32F334) || defined (HC32F448) || defined (HC32F472) + __DSB(); /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ +#endif +} + +void wktm_sample(int argc, char **argv) +{ + rt_base_t level; + rt_uint32_t cmp_value; + rt_uint32_t cmp_max = hc32_wktm_get_tick_max(); + + if (argc >= 2) + { + cmp_value = atol(argv[1]); + if (0UL == cmp_value) + { + /*********************** Stop wakeup-timer ************************/ + hc32_wktm_stop(); + + NVIC_DisableIRQ(WKTM_IRQn); + NVIC_ClearPendingIRQ(WKTM_IRQn); + + rt_kprintf("Stop Wakeup-timer\n\n"); + } + else if (cmp_value > cmp_max) + { + /*********************** Hold the wakeup timer configuration ******/ + rt_kprintf("compare value %d is out of %d(max), so hold the wakeup timer configuration \n\n", cmp_value, cmp_max); + } + else if (cmp_value < (cmp_max / 2)) + { + /*********************** Hold the wakeup timer configuration ******/ + rt_kprintf("compare value %d is less of %d(max/2), so hold the wakeup timer configuration: ", cmp_value, cmp_max / 2); + rt_kprintf("to avoid frequent interruptions: too much printed information affcets console commands \n\n"); + } + else + { + /*********************** Start wakeup-timer ***********************/ + /* Wakeup timer NVIC config */ +#if defined (HC32F4A0) || defined (HC32F4A2) || defined (HC32F4A8) || defined (HC32F467) || defined (HC32F460) + (void)INTC_ShareIrqCmd(INT_SRC_WKTM_PRD, ENABLE); +#endif + NVIC_ClearPendingIRQ(WKTM_IRQn); + NVIC_SetPriority(WKTM_IRQn, DDL_IRQ_PRIO_DEFAULT); + NVIC_EnableIRQ(WKTM_IRQn); + + if (RT_EOK == hc32_wktm_start(cmp_value)) + { + level = rt_hw_interrupt_disable(); + last_tick = rt_tick_get(); + rt_hw_interrupt_enable(level); + rt_kprintf("Update wakeup-timer compare value = %d, and start timer \n\n", cmp_value); + } + else + { + rt_kprintf("Fail to set wakeup-timer compare value \n\n", cmp_value); + } + } + } + else + { + rt_kprintf("wktm_sample 0: stop wakeup-timer \n"); + rt_kprintf("wktm_sample %d~%d: set wakeup-timer compare value and start timer \n\n", cmp_max / 2, cmp_max); + } +} +MSH_CMD_EXPORT(wktm_sample, wktm_sample compare_value); +#endif