From c35af3497a10d55c2957711238a0c255725677e9 Mon Sep 17 00:00:00 2001 From: Le Minh Dang - C70167 Date: Mon, 24 Jun 2024 11:59:30 -0700 Subject: [PATCH] Added SAMD, SAME HAL Drivers. Co-authored-by: Katie Lin Co-authored-by: Le Minh Dang deleted some redundant qspi stuff compiles, need testing fixed makefiles blinky test can't get anything out of i2c and uart i2c, uart working Tests passing --- .../ext/Microchip/SAME54/component-version.h | 56 + os/common/ext/Microchip/SAME54/component/ac.h | 413 ++ .../ext/Microchip/SAME54/component/adc.h | 630 +++ .../ext/Microchip/SAME54/component/aes.h | 314 ++ .../ext/Microchip/SAME54/component/can.h | 2519 ++++++++++++ .../ext/Microchip/SAME54/component/ccl.h | 220 + .../ext/Microchip/SAME54/component/cmcc.h | 214 + .../ext/Microchip/SAME54/component/dac.h | 444 ++ .../ext/Microchip/SAME54/component/dmac.h | 1186 ++++++ .../ext/Microchip/SAME54/component/dsu.h | 425 ++ .../ext/Microchip/SAME54/component/eic.h | 420 ++ .../ext/Microchip/SAME54/component/evsys.h | 516 +++ .../ext/Microchip/SAME54/component/freqm.h | 147 + .../ext/Microchip/SAME54/component/fuses.h | 313 ++ .../ext/Microchip/SAME54/component/gclk.h | 245 ++ .../ext/Microchip/SAME54/component/gmac.h | 1724 ++++++++ .../ext/Microchip/SAME54/component/hmatrixb.h | 63 + .../ext/Microchip/SAME54/component/i2s.h | 579 +++ .../ext/Microchip/SAME54/component/icm.h | 408 ++ .../ext/Microchip/SAME54/component/mclk.h | 414 ++ .../ext/Microchip/SAME54/component/nvmctrl.h | 507 +++ .../Microchip/SAME54/component/osc32kctrl.h | 216 + .../ext/Microchip/SAME54/component/oscctrl.h | 691 ++++ .../ext/Microchip/SAME54/component/pac.h | 633 +++ .../ext/Microchip/SAME54/component/pcc.h | 182 + .../ext/Microchip/SAME54/component/pdec.h | 522 +++ os/common/ext/Microchip/SAME54/component/pm.h | 191 + .../ext/Microchip/SAME54/component/port.h | 382 ++ .../ext/Microchip/SAME54/component/pukcc.h | 36 + .../ext/Microchip/SAME54/component/qspi.h | 380 ++ .../ext/Microchip/SAME54/component/ramecc.h | 117 + .../ext/Microchip/SAME54/component/rstc.h | 86 + .../ext/Microchip/SAME54/component/rtc.h | 1698 ++++++++ .../ext/Microchip/SAME54/component/sdhc.h | 1790 ++++++++ .../ext/Microchip/SAME54/component/sercom.h | 2208 ++++++++++ .../ext/Microchip/SAME54/component/supc.h | 341 ++ os/common/ext/Microchip/SAME54/component/tc.h | 600 +++ .../ext/Microchip/SAME54/component/tcc.h | 1405 +++++++ .../ext/Microchip/SAME54/component/trng.h | 110 + .../ext/Microchip/SAME54/component/usb.h | 1230 ++++++ .../ext/Microchip/SAME54/component/wdt.h | 218 + os/common/ext/Microchip/SAME54/instance/ac.h | 34 + .../ext/Microchip/SAME54/instance/adc0.h | 40 + .../ext/Microchip/SAME54/instance/adc1.h | 40 + os/common/ext/Microchip/SAME54/instance/aes.h | 33 + .../ext/Microchip/SAME54/instance/can0.h | 32 + .../ext/Microchip/SAME54/instance/can1.h | 32 + os/common/ext/Microchip/SAME54/instance/ccl.h | 31 + .../ext/Microchip/SAME54/instance/cmcc.h | 28 + os/common/ext/Microchip/SAME54/instance/dac.h | 36 + .../ext/Microchip/SAME54/instance/dmac.h | 73 + os/common/ext/Microchip/SAME54/instance/dsu.h | 30 + os/common/ext/Microchip/SAME54/instance/eic.h | 33 + .../ext/Microchip/SAME54/instance/evsys.h | 50 + .../ext/Microchip/SAME54/instance/freqm.h | 30 + .../ext/Microchip/SAME54/instance/fuses.h | 24 + .../ext/Microchip/SAME54/instance/gclk.h | 38 + .../ext/Microchip/SAME54/instance/gmac.h | 28 + .../ext/Microchip/SAME54/instance/hmatrix.h | 53 + os/common/ext/Microchip/SAME54/instance/i2s.h | 38 + os/common/ext/Microchip/SAME54/instance/icm.h | 28 + .../ext/Microchip/SAME54/instance/mclk.h | 29 + .../ext/Microchip/SAME54/instance/nvmctrl.h | 40 + .../Microchip/SAME54/instance/osc32kctrl.h | 29 + .../ext/Microchip/SAME54/instance/oscctrl.h | 74 + os/common/ext/Microchip/SAME54/instance/pac.h | 29 + os/common/ext/Microchip/SAME54/instance/pcc.h | 30 + .../ext/Microchip/SAME54/instance/pdec.h | 30 + os/common/ext/Microchip/SAME54/instance/pm.h | 29 + .../ext/Microchip/SAME54/instance/port.h | 34 + .../ext/Microchip/SAME54/instance/qspi.h | 32 + .../ext/Microchip/SAME54/instance/ramecc.h | 30 + .../ext/Microchip/SAME54/instance/rstc.h | 32 + os/common/ext/Microchip/SAME54/instance/rtc.h | 36 + .../ext/Microchip/SAME54/instance/sdhc0.h | 33 + .../ext/Microchip/SAME54/instance/sdhc1.h | 33 + .../ext/Microchip/SAME54/instance/sercom0.h | 81 + .../ext/Microchip/SAME54/instance/sercom1.h | 81 + .../ext/Microchip/SAME54/instance/sercom2.h | 81 + .../ext/Microchip/SAME54/instance/sercom3.h | 81 + .../ext/Microchip/SAME54/instance/sercom4.h | 81 + .../ext/Microchip/SAME54/instance/sercom5.h | 81 + .../ext/Microchip/SAME54/instance/sercom6.h | 81 + .../ext/Microchip/SAME54/instance/sercom7.h | 81 + .../ext/Microchip/SAME54/instance/supc.h | 30 + os/common/ext/Microchip/SAME54/instance/tc0.h | 36 + os/common/ext/Microchip/SAME54/instance/tc1.h | 36 + os/common/ext/Microchip/SAME54/instance/tc2.h | 36 + os/common/ext/Microchip/SAME54/instance/tc3.h | 36 + os/common/ext/Microchip/SAME54/instance/tc4.h | 36 + os/common/ext/Microchip/SAME54/instance/tc5.h | 36 + os/common/ext/Microchip/SAME54/instance/tc6.h | 36 + os/common/ext/Microchip/SAME54/instance/tc7.h | 36 + .../ext/Microchip/SAME54/instance/tcc0.h | 46 + .../ext/Microchip/SAME54/instance/tcc1.h | 44 + .../ext/Microchip/SAME54/instance/tcc2.h | 43 + .../ext/Microchip/SAME54/instance/tcc3.h | 42 + .../ext/Microchip/SAME54/instance/tcc4.h | 42 + .../ext/Microchip/SAME54/instance/trng.h | 28 + os/common/ext/Microchip/SAME54/instance/usb.h | 45 + os/common/ext/Microchip/SAME54/instance/wdt.h | 28 + .../ext/Microchip/SAME54/pio/same54n19a.h | 3262 +++++++++++++++ .../ext/Microchip/SAME54/pio/same54n20a.h | 3262 +++++++++++++++ .../ext/Microchip/SAME54/pio/same54p19a.h | 3651 +++++++++++++++++ .../ext/Microchip/SAME54/pio/same54p20a.h | 3651 +++++++++++++++++ os/common/ext/Microchip/SAME54/sam.h | 36 + os/common/ext/Microchip/SAME54/same54n19a.h | 1135 +++++ os/common/ext/Microchip/SAME54/same54n20a.h | 1135 +++++ os/common/ext/Microchip/SAME54/same54p19a.h | 1135 +++++ os/common/ext/Microchip/SAME54/same54p20a.h | 1135 +++++ .../ext/Microchip/SAME54/system_same54.h | 38 + .../ARMCMx/compilers/GCC/ld/SAME54P20.ld | 86 + .../ARMCMx/compilers/GCC/mk/startup_same54.mk | 19 + .../startup/ARMCMx/devices/SAME54/cmparams.h | 91 + os/hal/boards/SAME54_XPlainedPro/board.c | 6 + os/hal/boards/SAME54_XPlainedPro/board.h | 24 + os/hal/boards/SAME54_XPlainedPro/board.mk | 8 + .../serial_nor/devices/AT25FF321A/at25ff.h | 165 + .../devices/AT25FF321A/at25ff321a.mk | 10 + .../devices/AT25FF321A/hal_flash_device.c | 636 +++ .../devices/AT25FF321A/hal_flash_device.h | 262 ++ .../devices/SST26VF/hal_flash_device.c | 589 +++ .../devices/SST26VF/hal_flash_device.h | 264 ++ .../serial_nor/devices/SST26VF/sst26vf.h | 112 + .../serial_nor/devices/SST26VF/sst26vf.mk | 11 + os/hal/ports/SAM/LLD/ADCv1/hal_adc_lld.c | 93 +- os/hal/ports/SAM/LLD/ADCv1/hal_adc_lld.h | 52 +- os/hal/ports/SAM/LLD/DMACv1/sam_dmac.c | 100 +- os/hal/ports/SAM/LLD/DMACv1/sam_dmac.h | 128 +- os/hal/ports/SAM/LLD/DMACv2/driver.mk | 2 + os/hal/ports/SAM/LLD/DMACv2/sam_dmac.c | 219 + os/hal/ports/SAM/LLD/DMACv2/sam_dmac.h | 357 ++ os/hal/ports/SAM/LLD/PORTv1/hal_pal_lld.c | 361 +- os/hal/ports/SAM/LLD/PORTv1/hal_pal_lld.h | 225 +- os/hal/ports/SAM/LLD/SERCOMv1/driver.mk | 2 +- os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld.c | 426 +- os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld.h | 70 +- .../SAM/LLD/SERCOMv1/hal_i2c_lld_samd2x.inc | 287 ++ .../SAM/LLD/SERCOMv1/hal_i2c_lld_same5x.inc | 555 +++ os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld.c | 564 +-- os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld.h | 75 +- .../SAM/LLD/SERCOMv1/hal_sio_lld_samd2x.inc | 329 ++ .../SAM/LLD/SERCOMv1/hal_sio_lld_same5x.inc | 628 +++ .../ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld.c | 694 ---- .../SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom.c | 383 ++ ...l_spi_v2_lld.h => hal_spi_v2_lld_sercom.h} | 116 +- .../SERCOMv1/hal_spi_v2_lld_sercom_samd2x.inc | 316 ++ .../SERCOMv1/hal_spi_v2_lld_sercom_same5x.inc | 396 ++ os/hal/ports/SAM/LLD/SERCOMv1/sercom_clk.h | 238 +- os/hal/ports/SAM/LLD/SPIv1/driver.mk | 4 + os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld.c | 266 ++ os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld.h | 231 ++ .../ports/SAM/LLD/SPIv1/hal_spi_v2_lld_qspi.c | 305 ++ .../ports/SAM/LLD/SPIv1/hal_spi_v2_lld_qspi.h | 147 + os/hal/ports/SAM/LLD/SYSTICKv1/hal_st_lld.c | 64 +- os/hal/ports/SAM/LLD/SYSTICKv1/hal_st_lld.h | 45 +- os/hal/ports/SAM/SAMD21A/hal_efl_lld.c | 165 +- os/hal/ports/SAM/SAMD21A/hal_efl_lld.h | 41 +- os/hal/ports/SAM/SAMD21A/hal_lld.c | 181 +- os/hal/ports/SAM/SAMD21A/hal_lld.h | 89 +- os/hal/ports/SAM/SAMD21A/sam_clk.c | 45 +- os/hal/ports/SAM/SAMD21A/sam_clk.h | 64 +- os/hal/ports/SAM/SAMD21A/sam_extint.h | 76 +- os/hal/ports/SAM/SAME54/hal_lld.c | 302 ++ os/hal/ports/SAM/SAME54/hal_lld.h | 178 + os/hal/ports/SAM/SAME54/platform.mk | 38 + os/hal/ports/SAM/SAME54/sam_clk.c | 36 + os/hal/ports/SAM/SAME54/sam_clk.h | 336 ++ os/hal/ports/SAM/SAME54/sam_extint.h | 99 + os/hal/ports/SAM/SAME54/sam_gclk_add.h | 32 + os/hal/ports/SAM/SAME54/sam_irq.h | 82 + testhal/{ => SAM}/SAMD21A/Blinky/Makefile | 0 testhal/{ => SAM}/SAMD21A/Blinky/cfg/chconf.h | 0 .../{ => SAM}/SAMD21A/Blinky/cfg/halconf.h | 0 .../{ => SAM}/SAMD21A/Blinky/cfg/mcuconf.h | 0 testhal/{ => SAM}/SAMD21A/Blinky/main.c | 0 testhal/{ => SAM}/SAMD21A/EFL-MFS/Makefile | 0 .../{ => SAM}/SAMD21A/EFL-MFS/cfg/chconf.h | 0 .../{ => SAM}/SAMD21A/EFL-MFS/cfg/halconf.h | 0 .../{ => SAM}/SAMD21A/EFL-MFS/cfg/mcuconf.h | 0 testhal/{ => SAM}/SAMD21A/EFL-MFS/main.c | 0 testhal/{ => SAM}/SAMD21A/SIO/Makefile | 0 testhal/{ => SAM}/SAMD21A/SIO/cfg/chconf.h | 0 testhal/{ => SAM}/SAMD21A/SIO/cfg/halconf.h | 0 testhal/{ => SAM}/SAMD21A/SIO/cfg/mcuconf.h | 0 testhal/{ => SAM}/SAMD21A/SIO/main.c | 4 +- testhal/SAM/SAMD51_SAME54/Main/Makefile | 216 + testhal/SAM/SAMD51_SAME54/Main/cfg/chconf.h | 849 ++++ testhal/SAM/SAMD51_SAME54/Main/cfg/halconf.h | 571 +++ testhal/SAM/SAMD51_SAME54/Main/cfg/mcuconf.h | 184 + testhal/SAM/SAMD51_SAME54/Main/cfg/osalconf.h | 67 + testhal/SAM/SAMD51_SAME54/Main/main.c | 167 + 192 files changed, 57134 insertions(+), 2417 deletions(-) create mode 100644 os/common/ext/Microchip/SAME54/component-version.h create mode 100644 os/common/ext/Microchip/SAME54/component/ac.h create mode 100644 os/common/ext/Microchip/SAME54/component/adc.h create mode 100644 os/common/ext/Microchip/SAME54/component/aes.h create mode 100644 os/common/ext/Microchip/SAME54/component/can.h create mode 100644 os/common/ext/Microchip/SAME54/component/ccl.h create mode 100644 os/common/ext/Microchip/SAME54/component/cmcc.h create mode 100644 os/common/ext/Microchip/SAME54/component/dac.h create mode 100644 os/common/ext/Microchip/SAME54/component/dmac.h create mode 100644 os/common/ext/Microchip/SAME54/component/dsu.h create mode 100644 os/common/ext/Microchip/SAME54/component/eic.h create mode 100644 os/common/ext/Microchip/SAME54/component/evsys.h create mode 100644 os/common/ext/Microchip/SAME54/component/freqm.h create mode 100644 os/common/ext/Microchip/SAME54/component/fuses.h create mode 100644 os/common/ext/Microchip/SAME54/component/gclk.h create mode 100644 os/common/ext/Microchip/SAME54/component/gmac.h create mode 100644 os/common/ext/Microchip/SAME54/component/hmatrixb.h create mode 100644 os/common/ext/Microchip/SAME54/component/i2s.h create mode 100644 os/common/ext/Microchip/SAME54/component/icm.h create mode 100644 os/common/ext/Microchip/SAME54/component/mclk.h create mode 100644 os/common/ext/Microchip/SAME54/component/nvmctrl.h create mode 100644 os/common/ext/Microchip/SAME54/component/osc32kctrl.h create mode 100644 os/common/ext/Microchip/SAME54/component/oscctrl.h create mode 100644 os/common/ext/Microchip/SAME54/component/pac.h create mode 100644 os/common/ext/Microchip/SAME54/component/pcc.h create mode 100644 os/common/ext/Microchip/SAME54/component/pdec.h create mode 100644 os/common/ext/Microchip/SAME54/component/pm.h create mode 100644 os/common/ext/Microchip/SAME54/component/port.h create mode 100644 os/common/ext/Microchip/SAME54/component/pukcc.h create mode 100644 os/common/ext/Microchip/SAME54/component/qspi.h create mode 100644 os/common/ext/Microchip/SAME54/component/ramecc.h create mode 100644 os/common/ext/Microchip/SAME54/component/rstc.h create mode 100644 os/common/ext/Microchip/SAME54/component/rtc.h create mode 100644 os/common/ext/Microchip/SAME54/component/sdhc.h create mode 100644 os/common/ext/Microchip/SAME54/component/sercom.h create mode 100644 os/common/ext/Microchip/SAME54/component/supc.h create mode 100644 os/common/ext/Microchip/SAME54/component/tc.h create mode 100644 os/common/ext/Microchip/SAME54/component/tcc.h create mode 100644 os/common/ext/Microchip/SAME54/component/trng.h create mode 100644 os/common/ext/Microchip/SAME54/component/usb.h create mode 100644 os/common/ext/Microchip/SAME54/component/wdt.h create mode 100644 os/common/ext/Microchip/SAME54/instance/ac.h create mode 100644 os/common/ext/Microchip/SAME54/instance/adc0.h create mode 100644 os/common/ext/Microchip/SAME54/instance/adc1.h create mode 100644 os/common/ext/Microchip/SAME54/instance/aes.h create mode 100644 os/common/ext/Microchip/SAME54/instance/can0.h create mode 100644 os/common/ext/Microchip/SAME54/instance/can1.h create mode 100644 os/common/ext/Microchip/SAME54/instance/ccl.h create mode 100644 os/common/ext/Microchip/SAME54/instance/cmcc.h create mode 100644 os/common/ext/Microchip/SAME54/instance/dac.h create mode 100644 os/common/ext/Microchip/SAME54/instance/dmac.h create mode 100644 os/common/ext/Microchip/SAME54/instance/dsu.h create mode 100644 os/common/ext/Microchip/SAME54/instance/eic.h create mode 100644 os/common/ext/Microchip/SAME54/instance/evsys.h create mode 100644 os/common/ext/Microchip/SAME54/instance/freqm.h create mode 100644 os/common/ext/Microchip/SAME54/instance/fuses.h create mode 100644 os/common/ext/Microchip/SAME54/instance/gclk.h create mode 100644 os/common/ext/Microchip/SAME54/instance/gmac.h create mode 100644 os/common/ext/Microchip/SAME54/instance/hmatrix.h create mode 100644 os/common/ext/Microchip/SAME54/instance/i2s.h create mode 100644 os/common/ext/Microchip/SAME54/instance/icm.h create mode 100644 os/common/ext/Microchip/SAME54/instance/mclk.h create mode 100644 os/common/ext/Microchip/SAME54/instance/nvmctrl.h create mode 100644 os/common/ext/Microchip/SAME54/instance/osc32kctrl.h create mode 100644 os/common/ext/Microchip/SAME54/instance/oscctrl.h create mode 100644 os/common/ext/Microchip/SAME54/instance/pac.h create mode 100644 os/common/ext/Microchip/SAME54/instance/pcc.h create mode 100644 os/common/ext/Microchip/SAME54/instance/pdec.h create mode 100644 os/common/ext/Microchip/SAME54/instance/pm.h create mode 100644 os/common/ext/Microchip/SAME54/instance/port.h create mode 100644 os/common/ext/Microchip/SAME54/instance/qspi.h create mode 100644 os/common/ext/Microchip/SAME54/instance/ramecc.h create mode 100644 os/common/ext/Microchip/SAME54/instance/rstc.h create mode 100644 os/common/ext/Microchip/SAME54/instance/rtc.h create mode 100644 os/common/ext/Microchip/SAME54/instance/sdhc0.h create mode 100644 os/common/ext/Microchip/SAME54/instance/sdhc1.h create mode 100644 os/common/ext/Microchip/SAME54/instance/sercom0.h create mode 100644 os/common/ext/Microchip/SAME54/instance/sercom1.h create mode 100644 os/common/ext/Microchip/SAME54/instance/sercom2.h create mode 100644 os/common/ext/Microchip/SAME54/instance/sercom3.h create mode 100644 os/common/ext/Microchip/SAME54/instance/sercom4.h create mode 100644 os/common/ext/Microchip/SAME54/instance/sercom5.h create mode 100644 os/common/ext/Microchip/SAME54/instance/sercom6.h create mode 100644 os/common/ext/Microchip/SAME54/instance/sercom7.h create mode 100644 os/common/ext/Microchip/SAME54/instance/supc.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tc0.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tc1.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tc2.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tc3.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tc4.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tc5.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tc6.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tc7.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tcc0.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tcc1.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tcc2.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tcc3.h create mode 100644 os/common/ext/Microchip/SAME54/instance/tcc4.h create mode 100644 os/common/ext/Microchip/SAME54/instance/trng.h create mode 100644 os/common/ext/Microchip/SAME54/instance/usb.h create mode 100644 os/common/ext/Microchip/SAME54/instance/wdt.h create mode 100644 os/common/ext/Microchip/SAME54/pio/same54n19a.h create mode 100644 os/common/ext/Microchip/SAME54/pio/same54n20a.h create mode 100644 os/common/ext/Microchip/SAME54/pio/same54p19a.h create mode 100644 os/common/ext/Microchip/SAME54/pio/same54p20a.h create mode 100644 os/common/ext/Microchip/SAME54/sam.h create mode 100644 os/common/ext/Microchip/SAME54/same54n19a.h create mode 100644 os/common/ext/Microchip/SAME54/same54n20a.h create mode 100644 os/common/ext/Microchip/SAME54/same54p19a.h create mode 100644 os/common/ext/Microchip/SAME54/same54p20a.h create mode 100644 os/common/ext/Microchip/SAME54/system_same54.h create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/SAME54P20.ld create mode 100644 os/common/startup/ARMCMx/compilers/GCC/mk/startup_same54.mk create mode 100644 os/common/startup/ARMCMx/devices/SAME54/cmparams.h create mode 100644 os/hal/boards/SAME54_XPlainedPro/board.c create mode 100644 os/hal/boards/SAME54_XPlainedPro/board.h create mode 100644 os/hal/boards/SAME54_XPlainedPro/board.mk create mode 100644 os/hal/lib/complex/serial_nor/devices/AT25FF321A/at25ff.h create mode 100644 os/hal/lib/complex/serial_nor/devices/AT25FF321A/at25ff321a.mk create mode 100644 os/hal/lib/complex/serial_nor/devices/AT25FF321A/hal_flash_device.c create mode 100644 os/hal/lib/complex/serial_nor/devices/AT25FF321A/hal_flash_device.h create mode 100644 os/hal/lib/complex/serial_nor/devices/SST26VF/hal_flash_device.c create mode 100644 os/hal/lib/complex/serial_nor/devices/SST26VF/hal_flash_device.h create mode 100644 os/hal/lib/complex/serial_nor/devices/SST26VF/sst26vf.h create mode 100644 os/hal/lib/complex/serial_nor/devices/SST26VF/sst26vf.mk create mode 100644 os/hal/ports/SAM/LLD/DMACv2/driver.mk create mode 100644 os/hal/ports/SAM/LLD/DMACv2/sam_dmac.c create mode 100644 os/hal/ports/SAM/LLD/DMACv2/sam_dmac.h create mode 100644 os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld_samd2x.inc create mode 100644 os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld_same5x.inc create mode 100644 os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld_samd2x.inc create mode 100644 os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld_same5x.inc delete mode 100644 os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld.c create mode 100644 os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom.c rename os/hal/ports/SAM/LLD/SERCOMv1/{hal_spi_v2_lld.h => hal_spi_v2_lld_sercom.h} (77%) create mode 100644 os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom_samd2x.inc create mode 100644 os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom_same5x.inc create mode 100644 os/hal/ports/SAM/LLD/SPIv1/driver.mk create mode 100644 os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld.c create mode 100644 os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld.h create mode 100644 os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld_qspi.c create mode 100644 os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld_qspi.h create mode 100644 os/hal/ports/SAM/SAME54/hal_lld.c create mode 100644 os/hal/ports/SAM/SAME54/hal_lld.h create mode 100644 os/hal/ports/SAM/SAME54/platform.mk create mode 100644 os/hal/ports/SAM/SAME54/sam_clk.c create mode 100644 os/hal/ports/SAM/SAME54/sam_clk.h create mode 100644 os/hal/ports/SAM/SAME54/sam_extint.h create mode 100644 os/hal/ports/SAM/SAME54/sam_gclk_add.h create mode 100644 os/hal/ports/SAM/SAME54/sam_irq.h rename testhal/{ => SAM}/SAMD21A/Blinky/Makefile (100%) rename testhal/{ => SAM}/SAMD21A/Blinky/cfg/chconf.h (100%) rename testhal/{ => SAM}/SAMD21A/Blinky/cfg/halconf.h (100%) rename testhal/{ => SAM}/SAMD21A/Blinky/cfg/mcuconf.h (100%) rename testhal/{ => SAM}/SAMD21A/Blinky/main.c (100%) rename testhal/{ => SAM}/SAMD21A/EFL-MFS/Makefile (100%) rename testhal/{ => SAM}/SAMD21A/EFL-MFS/cfg/chconf.h (100%) rename testhal/{ => SAM}/SAMD21A/EFL-MFS/cfg/halconf.h (100%) rename testhal/{ => SAM}/SAMD21A/EFL-MFS/cfg/mcuconf.h (100%) rename testhal/{ => SAM}/SAMD21A/EFL-MFS/main.c (100%) rename testhal/{ => SAM}/SAMD21A/SIO/Makefile (100%) rename testhal/{ => SAM}/SAMD21A/SIO/cfg/chconf.h (100%) rename testhal/{ => SAM}/SAMD21A/SIO/cfg/halconf.h (100%) rename testhal/{ => SAM}/SAMD21A/SIO/cfg/mcuconf.h (100%) rename testhal/{ => SAM}/SAMD21A/SIO/main.c (98%) create mode 100644 testhal/SAM/SAMD51_SAME54/Main/Makefile create mode 100644 testhal/SAM/SAMD51_SAME54/Main/cfg/chconf.h create mode 100644 testhal/SAM/SAMD51_SAME54/Main/cfg/halconf.h create mode 100644 testhal/SAM/SAMD51_SAME54/Main/cfg/mcuconf.h create mode 100644 testhal/SAM/SAMD51_SAME54/Main/cfg/osalconf.h create mode 100644 testhal/SAM/SAMD51_SAME54/Main/main.c diff --git a/os/common/ext/Microchip/SAME54/component-version.h b/os/common/ext/Microchip/SAME54/component-version.h new file mode 100644 index 0000000000..5ee98196c5 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/component-version.h @@ -0,0 +1,56 @@ +/* + * Component version header file + * + * Copyright (c) 2024 Microchip Technology Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 3 +#define COMPONENT_VERSION_MINOR 9 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 30009 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 244 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "3.9" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2024-04-18 13:21:57" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/os/common/ext/Microchip/SAME54/component/ac.h b/os/common/ext/Microchip/SAME54/component/ac.h new file mode 100644 index 0000000000..8a32245140 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/component/ac.h @@ -0,0 +1,413 @@ +/* + * Component description for AC + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:08Z */ +#ifndef _SAME54_AC_COMPONENT_H_ +#define _SAME54_AC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AC */ +/* ************************************************************************** */ + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#define AC_CTRLA_RESETVALUE _UINT8_(0x00) /* (AC_CTRLA) Control A Reset Value */ + +#define AC_CTRLA_SWRST_Pos _UINT8_(0) /* (AC_CTRLA) Software Reset Position */ +#define AC_CTRLA_SWRST_Msk (_UINT8_(0x1) << AC_CTRLA_SWRST_Pos) /* (AC_CTRLA) Software Reset Mask */ +#define AC_CTRLA_SWRST(value) (AC_CTRLA_SWRST_Msk & (_UINT8_(value) << AC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the AC_CTRLA register */ +#define AC_CTRLA_ENABLE_Pos _UINT8_(1) /* (AC_CTRLA) Enable Position */ +#define AC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << AC_CTRLA_ENABLE_Pos) /* (AC_CTRLA) Enable Mask */ +#define AC_CTRLA_ENABLE(value) (AC_CTRLA_ENABLE_Msk & (_UINT8_(value) << AC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_CTRLA register */ +#define AC_CTRLA_Msk _UINT8_(0x03) /* (AC_CTRLA) Register Mask */ + + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#define AC_CTRLB_RESETVALUE _UINT8_(0x00) /* (AC_CTRLB) Control B Reset Value */ + +#define AC_CTRLB_START0_Pos _UINT8_(0) /* (AC_CTRLB) Comparator 0 Start Comparison Position */ +#define AC_CTRLB_START0_Msk (_UINT8_(0x1) << AC_CTRLB_START0_Pos) /* (AC_CTRLB) Comparator 0 Start Comparison Mask */ +#define AC_CTRLB_START0(value) (AC_CTRLB_START0_Msk & (_UINT8_(value) << AC_CTRLB_START0_Pos)) /* Assigment of value for START0 in the AC_CTRLB register */ +#define AC_CTRLB_START1_Pos _UINT8_(1) /* (AC_CTRLB) Comparator 1 Start Comparison Position */ +#define AC_CTRLB_START1_Msk (_UINT8_(0x1) << AC_CTRLB_START1_Pos) /* (AC_CTRLB) Comparator 1 Start Comparison Mask */ +#define AC_CTRLB_START1(value) (AC_CTRLB_START1_Msk & (_UINT8_(value) << AC_CTRLB_START1_Pos)) /* Assigment of value for START1 in the AC_CTRLB register */ +#define AC_CTRLB_Msk _UINT8_(0x03) /* (AC_CTRLB) Register Mask */ + +#define AC_CTRLB_START_Pos _UINT8_(0) /* (AC_CTRLB Position) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_UINT8_(0x3) << AC_CTRLB_START_Pos) /* (AC_CTRLB Mask) START */ +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & (_UINT8_(value) << AC_CTRLB_START_Pos)) + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#define AC_EVCTRL_RESETVALUE _UINT16_(0x00) /* (AC_EVCTRL) Event Control Reset Value */ + +#define AC_EVCTRL_COMPEO0_Pos _UINT16_(0) /* (AC_EVCTRL) Comparator 0 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO0_Pos) /* (AC_EVCTRL) Comparator 0 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO0(value) (AC_EVCTRL_COMPEO0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO0_Pos)) /* Assigment of value for COMPEO0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEO1_Pos _UINT16_(1) /* (AC_EVCTRL) Comparator 1 Event Output Enable Position */ +#define AC_EVCTRL_COMPEO1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEO1_Pos) /* (AC_EVCTRL) Comparator 1 Event Output Enable Mask */ +#define AC_EVCTRL_COMPEO1(value) (AC_EVCTRL_COMPEO1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO1_Pos)) /* Assigment of value for COMPEO1 in the AC_EVCTRL register */ +#define AC_EVCTRL_WINEO0_Pos _UINT16_(4) /* (AC_EVCTRL) Window 0 Event Output Enable Position */ +#define AC_EVCTRL_WINEO0_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO0_Pos) /* (AC_EVCTRL) Window 0 Event Output Enable Mask */ +#define AC_EVCTRL_WINEO0(value) (AC_EVCTRL_WINEO0_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO0_Pos)) /* Assigment of value for WINEO0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI0_Pos _UINT16_(8) /* (AC_EVCTRL) Comparator 0 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI0_Pos) /* (AC_EVCTRL) Comparator 0 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI0(value) (AC_EVCTRL_COMPEI0_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI0_Pos)) /* Assigment of value for COMPEI0 in the AC_EVCTRL register */ +#define AC_EVCTRL_COMPEI1_Pos _UINT16_(9) /* (AC_EVCTRL) Comparator 1 Event Input Enable Position */ +#define AC_EVCTRL_COMPEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_COMPEI1_Pos) /* (AC_EVCTRL) Comparator 1 Event Input Enable Mask */ +#define AC_EVCTRL_COMPEI1(value) (AC_EVCTRL_COMPEI1_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI1_Pos)) /* Assigment of value for COMPEI1 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI0_Pos _UINT16_(12) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI0_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI0_Pos) /* (AC_EVCTRL) Comparator 0 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI0(value) (AC_EVCTRL_INVEI0_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI0_Pos)) /* Assigment of value for INVEI0 in the AC_EVCTRL register */ +#define AC_EVCTRL_INVEI1_Pos _UINT16_(13) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Position */ +#define AC_EVCTRL_INVEI1_Msk (_UINT16_(0x1) << AC_EVCTRL_INVEI1_Pos) /* (AC_EVCTRL) Comparator 1 Input Event Invert Enable Mask */ +#define AC_EVCTRL_INVEI1(value) (AC_EVCTRL_INVEI1_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI1_Pos)) /* Assigment of value for INVEI1 in the AC_EVCTRL register */ +#define AC_EVCTRL_Msk _UINT16_(0x3313) /* (AC_EVCTRL) Register Mask */ + +#define AC_EVCTRL_COMPEO_Pos _UINT16_(0) /* (AC_EVCTRL Position) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_UINT16_(0x3) << AC_EVCTRL_COMPEO_Pos) /* (AC_EVCTRL Mask) COMPEO */ +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO_Pos _UINT16_(4) /* (AC_EVCTRL Position) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_UINT16_(0x1) << AC_EVCTRL_WINEO_Pos) /* (AC_EVCTRL Mask) WINEO */ +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & (_UINT16_(value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI_Pos _UINT16_(8) /* (AC_EVCTRL Position) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_UINT16_(0x3) << AC_EVCTRL_COMPEI_Pos) /* (AC_EVCTRL Mask) COMPEI */ +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & (_UINT16_(value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI_Pos _UINT16_(12) /* (AC_EVCTRL Position) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_UINT16_(0x3) << AC_EVCTRL_INVEI_Pos) /* (AC_EVCTRL Mask) INVEI */ +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & (_UINT16_(value) << AC_EVCTRL_INVEI_Pos)) + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define AC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (AC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define AC_INTENCLR_COMP0_Pos _UINT8_(0) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Position */ +#define AC_INTENCLR_COMP0_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP0_Pos) /* (AC_INTENCLR) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP0(value) (AC_INTENCLR_COMP0_Msk & (_UINT8_(value) << AC_INTENCLR_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTENCLR register */ +#define AC_INTENCLR_COMP1_Pos _UINT8_(1) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Position */ +#define AC_INTENCLR_COMP1_Msk (_UINT8_(0x1) << AC_INTENCLR_COMP1_Pos) /* (AC_INTENCLR) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENCLR_COMP1(value) (AC_INTENCLR_COMP1_Msk & (_UINT8_(value) << AC_INTENCLR_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTENCLR register */ +#define AC_INTENCLR_WIN0_Pos _UINT8_(4) /* (AC_INTENCLR) Window 0 Interrupt Enable Position */ +#define AC_INTENCLR_WIN0_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN0_Pos) /* (AC_INTENCLR) Window 0 Interrupt Enable Mask */ +#define AC_INTENCLR_WIN0(value) (AC_INTENCLR_WIN0_Msk & (_UINT8_(value) << AC_INTENCLR_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTENCLR register */ +#define AC_INTENCLR_Msk _UINT8_(0x13) /* (AC_INTENCLR) Register Mask */ + +#define AC_INTENCLR_COMP_Pos _UINT8_(0) /* (AC_INTENCLR Position) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_UINT8_(0x3) << AC_INTENCLR_COMP_Pos) /* (AC_INTENCLR Mask) COMP */ +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & (_UINT8_(value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN_Pos _UINT8_(4) /* (AC_INTENCLR Position) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_UINT8_(0x1) << AC_INTENCLR_WIN_Pos) /* (AC_INTENCLR Mask) WIN */ +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & (_UINT8_(value) << AC_INTENCLR_WIN_Pos)) + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define AC_INTENSET_RESETVALUE _UINT8_(0x00) /* (AC_INTENSET) Interrupt Enable Set Reset Value */ + +#define AC_INTENSET_COMP0_Pos _UINT8_(0) /* (AC_INTENSET) Comparator 0 Interrupt Enable Position */ +#define AC_INTENSET_COMP0_Msk (_UINT8_(0x1) << AC_INTENSET_COMP0_Pos) /* (AC_INTENSET) Comparator 0 Interrupt Enable Mask */ +#define AC_INTENSET_COMP0(value) (AC_INTENSET_COMP0_Msk & (_UINT8_(value) << AC_INTENSET_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTENSET register */ +#define AC_INTENSET_COMP1_Pos _UINT8_(1) /* (AC_INTENSET) Comparator 1 Interrupt Enable Position */ +#define AC_INTENSET_COMP1_Msk (_UINT8_(0x1) << AC_INTENSET_COMP1_Pos) /* (AC_INTENSET) Comparator 1 Interrupt Enable Mask */ +#define AC_INTENSET_COMP1(value) (AC_INTENSET_COMP1_Msk & (_UINT8_(value) << AC_INTENSET_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTENSET register */ +#define AC_INTENSET_WIN0_Pos _UINT8_(4) /* (AC_INTENSET) Window 0 Interrupt Enable Position */ +#define AC_INTENSET_WIN0_Msk (_UINT8_(0x1) << AC_INTENSET_WIN0_Pos) /* (AC_INTENSET) Window 0 Interrupt Enable Mask */ +#define AC_INTENSET_WIN0(value) (AC_INTENSET_WIN0_Msk & (_UINT8_(value) << AC_INTENSET_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTENSET register */ +#define AC_INTENSET_Msk _UINT8_(0x13) /* (AC_INTENSET) Register Mask */ + +#define AC_INTENSET_COMP_Pos _UINT8_(0) /* (AC_INTENSET Position) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_UINT8_(0x3) << AC_INTENSET_COMP_Pos) /* (AC_INTENSET Mask) COMP */ +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & (_UINT8_(value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN_Pos _UINT8_(4) /* (AC_INTENSET Position) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_UINT8_(0x1) << AC_INTENSET_WIN_Pos) /* (AC_INTENSET Mask) WIN */ +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & (_UINT8_(value) << AC_INTENSET_WIN_Pos)) + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define AC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (AC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define AC_INTFLAG_COMP0_Pos _UINT8_(0) /* (AC_INTFLAG) Comparator 0 Position */ +#define AC_INTFLAG_COMP0_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP0_Pos) /* (AC_INTFLAG) Comparator 0 Mask */ +#define AC_INTFLAG_COMP0(value) (AC_INTFLAG_COMP0_Msk & (_UINT8_(value) << AC_INTFLAG_COMP0_Pos)) /* Assigment of value for COMP0 in the AC_INTFLAG register */ +#define AC_INTFLAG_COMP1_Pos _UINT8_(1) /* (AC_INTFLAG) Comparator 1 Position */ +#define AC_INTFLAG_COMP1_Msk (_UINT8_(0x1) << AC_INTFLAG_COMP1_Pos) /* (AC_INTFLAG) Comparator 1 Mask */ +#define AC_INTFLAG_COMP1(value) (AC_INTFLAG_COMP1_Msk & (_UINT8_(value) << AC_INTFLAG_COMP1_Pos)) /* Assigment of value for COMP1 in the AC_INTFLAG register */ +#define AC_INTFLAG_WIN0_Pos _UINT8_(4) /* (AC_INTFLAG) Window 0 Position */ +#define AC_INTFLAG_WIN0_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN0_Pos) /* (AC_INTFLAG) Window 0 Mask */ +#define AC_INTFLAG_WIN0(value) (AC_INTFLAG_WIN0_Msk & (_UINT8_(value) << AC_INTFLAG_WIN0_Pos)) /* Assigment of value for WIN0 in the AC_INTFLAG register */ +#define AC_INTFLAG_Msk _UINT8_(0x13) /* (AC_INTFLAG) Register Mask */ + +#define AC_INTFLAG_COMP_Pos _UINT8_(0) /* (AC_INTFLAG Position) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_UINT8_(0x3) << AC_INTFLAG_COMP_Pos) /* (AC_INTFLAG Mask) COMP */ +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & (_UINT8_(value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN_Pos _UINT8_(4) /* (AC_INTFLAG Position) Window x */ +#define AC_INTFLAG_WIN_Msk (_UINT8_(0x1) << AC_INTFLAG_WIN_Pos) /* (AC_INTFLAG Mask) WIN */ +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & (_UINT8_(value) << AC_INTFLAG_WIN_Pos)) + +/* -------- AC_STATUSA : (AC Offset: 0x07) ( R/ 8) Status A -------- */ +#define AC_STATUSA_RESETVALUE _UINT8_(0x00) /* (AC_STATUSA) Status A Reset Value */ + +#define AC_STATUSA_STATE0_Pos _UINT8_(0) /* (AC_STATUSA) Comparator 0 Current State Position */ +#define AC_STATUSA_STATE0_Msk (_UINT8_(0x1) << AC_STATUSA_STATE0_Pos) /* (AC_STATUSA) Comparator 0 Current State Mask */ +#define AC_STATUSA_STATE0(value) (AC_STATUSA_STATE0_Msk & (_UINT8_(value) << AC_STATUSA_STATE0_Pos)) /* Assigment of value for STATE0 in the AC_STATUSA register */ +#define AC_STATUSA_STATE1_Pos _UINT8_(1) /* (AC_STATUSA) Comparator 1 Current State Position */ +#define AC_STATUSA_STATE1_Msk (_UINT8_(0x1) << AC_STATUSA_STATE1_Pos) /* (AC_STATUSA) Comparator 1 Current State Mask */ +#define AC_STATUSA_STATE1(value) (AC_STATUSA_STATE1_Msk & (_UINT8_(value) << AC_STATUSA_STATE1_Pos)) /* Assigment of value for STATE1 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE0_Pos _UINT8_(4) /* (AC_STATUSA) Window 0 Current State Position */ +#define AC_STATUSA_WSTATE0_Msk (_UINT8_(0x3) << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Window 0 Current State Mask */ +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & (_UINT8_(value) << AC_STATUSA_WSTATE0_Pos)) /* Assigment of value for WSTATE0 in the AC_STATUSA register */ +#define AC_STATUSA_WSTATE0_ABOVE_Val _UINT8_(0x0) /* (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _UINT8_(0x1) /* (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _UINT8_(0x2) /* (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is above window Position */ +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is inside window Position */ +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) /* (AC_STATUSA) Signal is below window Position */ +#define AC_STATUSA_Msk _UINT8_(0x33) /* (AC_STATUSA) Register Mask */ + +#define AC_STATUSA_STATE_Pos _UINT8_(0) /* (AC_STATUSA Position) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_UINT8_(0x3) << AC_STATUSA_STATE_Pos) /* (AC_STATUSA Mask) STATE */ +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & (_UINT8_(value) << AC_STATUSA_STATE_Pos)) + +/* -------- AC_STATUSB : (AC Offset: 0x08) ( R/ 8) Status B -------- */ +#define AC_STATUSB_RESETVALUE _UINT8_(0x00) /* (AC_STATUSB) Status B Reset Value */ + +#define AC_STATUSB_READY0_Pos _UINT8_(0) /* (AC_STATUSB) Comparator 0 Ready Position */ +#define AC_STATUSB_READY0_Msk (_UINT8_(0x1) << AC_STATUSB_READY0_Pos) /* (AC_STATUSB) Comparator 0 Ready Mask */ +#define AC_STATUSB_READY0(value) (AC_STATUSB_READY0_Msk & (_UINT8_(value) << AC_STATUSB_READY0_Pos)) /* Assigment of value for READY0 in the AC_STATUSB register */ +#define AC_STATUSB_READY1_Pos _UINT8_(1) /* (AC_STATUSB) Comparator 1 Ready Position */ +#define AC_STATUSB_READY1_Msk (_UINT8_(0x1) << AC_STATUSB_READY1_Pos) /* (AC_STATUSB) Comparator 1 Ready Mask */ +#define AC_STATUSB_READY1(value) (AC_STATUSB_READY1_Msk & (_UINT8_(value) << AC_STATUSB_READY1_Pos)) /* Assigment of value for READY1 in the AC_STATUSB register */ +#define AC_STATUSB_Msk _UINT8_(0x03) /* (AC_STATUSB) Register Mask */ + +#define AC_STATUSB_READY_Pos _UINT8_(0) /* (AC_STATUSB Position) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_UINT8_(0x3) << AC_STATUSB_READY_Pos) /* (AC_STATUSB Mask) READY */ +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & (_UINT8_(value) << AC_STATUSB_READY_Pos)) + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#define AC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (AC_DBGCTRL) Debug Control Reset Value */ + +#define AC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (AC_DBGCTRL) Debug Run Position */ +#define AC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << AC_DBGCTRL_DBGRUN_Pos) /* (AC_DBGCTRL) Debug Run Mask */ +#define AC_DBGCTRL_DBGRUN(value) (AC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << AC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the AC_DBGCTRL register */ +#define AC_DBGCTRL_Msk _UINT8_(0x01) /* (AC_DBGCTRL) Register Mask */ + + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#define AC_WINCTRL_RESETVALUE _UINT8_(0x00) /* (AC_WINCTRL) Window Control Reset Value */ + +#define AC_WINCTRL_WEN0_Pos _UINT8_(0) /* (AC_WINCTRL) Window 0 Mode Enable Position */ +#define AC_WINCTRL_WEN0_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN0_Pos) /* (AC_WINCTRL) Window 0 Mode Enable Mask */ +#define AC_WINCTRL_WEN0(value) (AC_WINCTRL_WEN0_Msk & (_UINT8_(value) << AC_WINCTRL_WEN0_Pos)) /* Assigment of value for WEN0 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL0_Pos _UINT8_(1) /* (AC_WINCTRL) Window 0 Interrupt Selection Position */ +#define AC_WINCTRL_WINTSEL0_Msk (_UINT8_(0x3) << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Window 0 Interrupt Selection Mask */ +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & (_UINT8_(value) << AC_WINCTRL_WINTSEL0_Pos)) /* Assigment of value for WINTSEL0 in the AC_WINCTRL register */ +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _UINT8_(0x0) /* (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _UINT8_(0x1) /* (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _UINT8_(0x2) /* (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _UINT8_(0x3) /* (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal above window Position */ +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal inside window Position */ +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal below window Position */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /* (AC_WINCTRL) Interrupt on signal outside window Position */ +#define AC_WINCTRL_Msk _UINT8_(0x07) /* (AC_WINCTRL) Register Mask */ + +#define AC_WINCTRL_WEN_Pos _UINT8_(0) /* (AC_WINCTRL Position) Window x Mode Enable */ +#define AC_WINCTRL_WEN_Msk (_UINT8_(0x1) << AC_WINCTRL_WEN_Pos) /* (AC_WINCTRL Mask) WEN */ +#define AC_WINCTRL_WEN(value) (AC_WINCTRL_WEN_Msk & (_UINT8_(value) << AC_WINCTRL_WEN_Pos)) + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#define AC_SCALER_RESETVALUE _UINT8_(0x00) /* (AC_SCALER) Scaler n Reset Value */ + +#define AC_SCALER_VALUE_Pos _UINT8_(0) /* (AC_SCALER) Scaler Value Position */ +#define AC_SCALER_VALUE_Msk (_UINT8_(0x3F) << AC_SCALER_VALUE_Pos) /* (AC_SCALER) Scaler Value Mask */ +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & (_UINT8_(value) << AC_SCALER_VALUE_Pos)) /* Assigment of value for VALUE in the AC_SCALER register */ +#define AC_SCALER_Msk _UINT8_(0x3F) /* (AC_SCALER) Register Mask */ + + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#define AC_COMPCTRL_RESETVALUE _UINT32_(0x00) /* (AC_COMPCTRL) Comparator Control n Reset Value */ + +#define AC_COMPCTRL_ENABLE_Pos _UINT32_(1) /* (AC_COMPCTRL) Enable Position */ +#define AC_COMPCTRL_ENABLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_ENABLE_Pos) /* (AC_COMPCTRL) Enable Mask */ +#define AC_COMPCTRL_ENABLE(value) (AC_COMPCTRL_ENABLE_Msk & (_UINT32_(value) << AC_COMPCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SINGLE_Pos _UINT32_(2) /* (AC_COMPCTRL) Single-Shot Mode Position */ +#define AC_COMPCTRL_SINGLE_Msk (_UINT32_(0x1) << AC_COMPCTRL_SINGLE_Pos) /* (AC_COMPCTRL) Single-Shot Mode Mask */ +#define AC_COMPCTRL_SINGLE(value) (AC_COMPCTRL_SINGLE_Msk & (_UINT32_(value) << AC_COMPCTRL_SINGLE_Pos)) /* Assigment of value for SINGLE in the AC_COMPCTRL register */ +#define AC_COMPCTRL_INTSEL_Pos _UINT32_(3) /* (AC_COMPCTRL) Interrupt Selection Position */ +#define AC_COMPCTRL_INTSEL_Msk (_UINT32_(0x3) << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt Selection Mask */ +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & (_UINT32_(value) << AC_COMPCTRL_INTSEL_Pos)) /* Assigment of value for INTSEL in the AC_COMPCTRL register */ +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _UINT32_(0x0) /* (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _UINT32_(0x1) /* (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _UINT32_(0x2) /* (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _UINT32_(0x3) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output toggle Position */ +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output rising Position */ +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on comparator output falling Position */ +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) /* (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) Position */ +#define AC_COMPCTRL_RUNSTDBY_Pos _UINT32_(6) /* (AC_COMPCTRL) Run in Standby Position */ +#define AC_COMPCTRL_RUNSTDBY_Msk (_UINT32_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) /* (AC_COMPCTRL) Run in Standby Mask */ +#define AC_COMPCTRL_RUNSTDBY(value) (AC_COMPCTRL_RUNSTDBY_Msk & (_UINT32_(value) << AC_COMPCTRL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXNEG_Pos _UINT32_(8) /* (AC_COMPCTRL) Negative Input Mux Selection Position */ +#define AC_COMPCTRL_MUXNEG_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Negative Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXNEG_Pos)) /* Assigment of value for MUXNEG in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXNEG_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _UINT32_(0x4) /* (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _UINT32_(0x5) /* (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _UINT32_(0x6) /* (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _UINT32_(0x7) /* (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Ground Position */ +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) VDD scaler Position */ +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) Internal bandgap voltage Position */ +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) /* (AC_COMPCTRL) DAC output Position */ +#define AC_COMPCTRL_MUXPOS_Pos _UINT32_(12) /* (AC_COMPCTRL) Positive Input Mux Selection Position */ +#define AC_COMPCTRL_MUXPOS_Msk (_UINT32_(0x7) << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) Positive Input Mux Selection Mask */ +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & (_UINT32_(value) << AC_COMPCTRL_MUXPOS_Pos)) /* Assigment of value for MUXPOS in the AC_COMPCTRL register */ +#define AC_COMPCTRL_MUXPOS_PIN0_Val _UINT32_(0x0) /* (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _UINT32_(0x1) /* (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _UINT32_(0x2) /* (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _UINT32_(0x3) /* (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _UINT32_(0x4) /* (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 0 Position */ +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 1 Position */ +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 2 Position */ +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) I/O pin 3 Position */ +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) /* (AC_COMPCTRL) VDD Scaler Position */ +#define AC_COMPCTRL_SWAP_Pos _UINT32_(15) /* (AC_COMPCTRL) Swap Inputs and Invert Position */ +#define AC_COMPCTRL_SWAP_Msk (_UINT32_(0x1) << AC_COMPCTRL_SWAP_Pos) /* (AC_COMPCTRL) Swap Inputs and Invert Mask */ +#define AC_COMPCTRL_SWAP(value) (AC_COMPCTRL_SWAP_Msk & (_UINT32_(value) << AC_COMPCTRL_SWAP_Pos)) /* Assigment of value for SWAP in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SPEED_Pos _UINT32_(16) /* (AC_COMPCTRL) Speed Selection Position */ +#define AC_COMPCTRL_SPEED_Msk (_UINT32_(0x3) << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) Speed Selection Mask */ +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & (_UINT32_(value) << AC_COMPCTRL_SPEED_Pos)) /* Assigment of value for SPEED in the AC_COMPCTRL register */ +#define AC_COMPCTRL_SPEED_HIGH_Val _UINT32_(0x3) /* (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) /* (AC_COMPCTRL) High speed Position */ +#define AC_COMPCTRL_HYSTEN_Pos _UINT32_(19) /* (AC_COMPCTRL) Hysteresis Enable Position */ +#define AC_COMPCTRL_HYSTEN_Msk (_UINT32_(0x1) << AC_COMPCTRL_HYSTEN_Pos) /* (AC_COMPCTRL) Hysteresis Enable Mask */ +#define AC_COMPCTRL_HYSTEN(value) (AC_COMPCTRL_HYSTEN_Msk & (_UINT32_(value) << AC_COMPCTRL_HYSTEN_Pos)) /* Assigment of value for HYSTEN in the AC_COMPCTRL register */ +#define AC_COMPCTRL_HYST_Pos _UINT32_(20) /* (AC_COMPCTRL) Hysteresis Level Position */ +#define AC_COMPCTRL_HYST_Msk (_UINT32_(0x3) << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) Hysteresis Level Mask */ +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & (_UINT32_(value) << AC_COMPCTRL_HYST_Pos)) /* Assigment of value for HYST in the AC_COMPCTRL register */ +#define AC_COMPCTRL_HYST_HYST25_Val _UINT32_(0x0) /* (AC_COMPCTRL) 25mV */ +#define AC_COMPCTRL_HYST_HYST50_Val _UINT32_(0x1) /* (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST75_Val _UINT32_(0x2) /* (AC_COMPCTRL) 75mV */ +#define AC_COMPCTRL_HYST_HYST100_Val _UINT32_(0x3) /* (AC_COMPCTRL) 100mV */ +#define AC_COMPCTRL_HYST_HYST25 (AC_COMPCTRL_HYST_HYST25_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 25mV Position */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 50mV Position */ +#define AC_COMPCTRL_HYST_HYST75 (AC_COMPCTRL_HYST_HYST75_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 75mV Position */ +#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) /* (AC_COMPCTRL) 100mV Position */ +#define AC_COMPCTRL_FLEN_Pos _UINT32_(24) /* (AC_COMPCTRL) Filter Length Position */ +#define AC_COMPCTRL_FLEN_Msk (_UINT32_(0x7) << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) Filter Length Mask */ +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & (_UINT32_(value) << AC_COMPCTRL_FLEN_Pos)) /* Assigment of value for FLEN in the AC_COMPCTRL register */ +#define AC_COMPCTRL_FLEN_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _UINT32_(0x1) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _UINT32_(0x2) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) No filtering Position */ +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 3-bit majority function (2 of 3) Position */ +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) /* (AC_COMPCTRL) 5-bit majority function (3 of 5) Position */ +#define AC_COMPCTRL_OUT_Pos _UINT32_(28) /* (AC_COMPCTRL) Output Position */ +#define AC_COMPCTRL_OUT_Msk (_UINT32_(0x3) << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) Output Mask */ +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & (_UINT32_(value) << AC_COMPCTRL_OUT_Pos)) /* Assigment of value for OUT in the AC_COMPCTRL register */ +#define AC_COMPCTRL_OUT_OFF_Val _UINT32_(0x0) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _UINT32_(0x1) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _UINT32_(0x2) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) /* (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Position */ +#define AC_COMPCTRL_Msk _UINT32_(0x373BF75E) /* (AC_COMPCTRL) Register Mask */ + + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) ( R/ 32) Synchronization Busy -------- */ +#define AC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (AC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define AC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Position */ +#define AC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << AC_SYNCBUSY_SWRST_Pos) /* (AC_SYNCBUSY) Software Reset Synchronization Busy Mask */ +#define AC_SYNCBUSY_SWRST(value) (AC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << AC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (AC_SYNCBUSY) Enable Synchronization Busy Position */ +#define AC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << AC_SYNCBUSY_ENABLE_Pos) /* (AC_SYNCBUSY) Enable Synchronization Busy Mask */ +#define AC_SYNCBUSY_ENABLE(value) (AC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << AC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_WINCTRL_Pos _UINT32_(2) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Position */ +#define AC_SYNCBUSY_WINCTRL_Msk (_UINT32_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) /* (AC_SYNCBUSY) WINCTRL Synchronization Busy Mask */ +#define AC_SYNCBUSY_WINCTRL(value) (AC_SYNCBUSY_WINCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_WINCTRL_Pos)) /* Assigment of value for WINCTRL in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL0_Pos _UINT32_(3) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL0_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL0_Pos) /* (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL0(value) (AC_SYNCBUSY_COMPCTRL0_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL0_Pos)) /* Assigment of value for COMPCTRL0 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_COMPCTRL1_Pos _UINT32_(4) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Position */ +#define AC_SYNCBUSY_COMPCTRL1_Msk (_UINT32_(0x1) << AC_SYNCBUSY_COMPCTRL1_Pos) /* (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Mask */ +#define AC_SYNCBUSY_COMPCTRL1(value) (AC_SYNCBUSY_COMPCTRL1_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL1_Pos)) /* Assigment of value for COMPCTRL1 in the AC_SYNCBUSY register */ +#define AC_SYNCBUSY_Msk _UINT32_(0x0000001F) /* (AC_SYNCBUSY) Register Mask */ + +#define AC_SYNCBUSY_COMPCTRL_Pos _UINT32_(3) /* (AC_SYNCBUSY Position) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_UINT32_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) /* (AC_SYNCBUSY Mask) COMPCTRL */ +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & (_UINT32_(value) << AC_SYNCBUSY_COMPCTRL_Pos)) + +/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ +#define AC_CALIB_RESETVALUE _UINT16_(0x101) /* (AC_CALIB) Calibration Reset Value */ + +#define AC_CALIB_BIAS0_Pos _UINT16_(0) /* (AC_CALIB) COMP0/1 Bias Scaling Position */ +#define AC_CALIB_BIAS0_Msk (_UINT16_(0x3) << AC_CALIB_BIAS0_Pos) /* (AC_CALIB) COMP0/1 Bias Scaling Mask */ +#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & (_UINT16_(value) << AC_CALIB_BIAS0_Pos)) /* Assigment of value for BIAS0 in the AC_CALIB register */ +#define AC_CALIB_Msk _UINT16_(0x0003) /* (AC_CALIB) Register Mask */ + + +/** \brief AC register offsets definitions */ +#define AC_CTRLA_REG_OFST _UINT32_(0x00) /* (AC_CTRLA) Control A Offset */ +#define AC_CTRLB_REG_OFST _UINT32_(0x01) /* (AC_CTRLB) Control B Offset */ +#define AC_EVCTRL_REG_OFST _UINT32_(0x02) /* (AC_EVCTRL) Event Control Offset */ +#define AC_INTENCLR_REG_OFST _UINT32_(0x04) /* (AC_INTENCLR) Interrupt Enable Clear Offset */ +#define AC_INTENSET_REG_OFST _UINT32_(0x05) /* (AC_INTENSET) Interrupt Enable Set Offset */ +#define AC_INTFLAG_REG_OFST _UINT32_(0x06) /* (AC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define AC_STATUSA_REG_OFST _UINT32_(0x07) /* (AC_STATUSA) Status A Offset */ +#define AC_STATUSB_REG_OFST _UINT32_(0x08) /* (AC_STATUSB) Status B Offset */ +#define AC_DBGCTRL_REG_OFST _UINT32_(0x09) /* (AC_DBGCTRL) Debug Control Offset */ +#define AC_WINCTRL_REG_OFST _UINT32_(0x0A) /* (AC_WINCTRL) Window Control Offset */ +#define AC_SCALER_REG_OFST _UINT32_(0x0C) /* (AC_SCALER) Scaler n Offset */ +#define AC_SCALER0_REG_OFST _UINT32_(0x0C) /* (AC_SCALER0) Scaler n Offset */ +#define AC_SCALER1_REG_OFST _UINT32_(0x0D) /* (AC_SCALER1) Scaler n Offset */ +#define AC_COMPCTRL_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL) Comparator Control n Offset */ +#define AC_COMPCTRL0_REG_OFST _UINT32_(0x10) /* (AC_COMPCTRL0) Comparator Control n Offset */ +#define AC_COMPCTRL1_REG_OFST _UINT32_(0x14) /* (AC_COMPCTRL1) Comparator Control n Offset */ +#define AC_SYNCBUSY_REG_OFST _UINT32_(0x20) /* (AC_SYNCBUSY) Synchronization Busy Offset */ +#define AC_CALIB_REG_OFST _UINT32_(0x24) /* (AC_CALIB) Calibration Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AC register API structure */ +typedef struct +{ /* Analog Comparators */ + __IO uint8_t AC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __O uint8_t AC_CTRLB; /**< Offset: 0x01 ( /W 8) Control B */ + __IO uint16_t AC_EVCTRL; /**< Offset: 0x02 (R/W 16) Event Control */ + __IO uint8_t AC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t AC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t AC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t AC_STATUSA; /**< Offset: 0x07 (R/ 8) Status A */ + __I uint8_t AC_STATUSB; /**< Offset: 0x08 (R/ 8) Status B */ + __IO uint8_t AC_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug Control */ + __IO uint8_t AC_WINCTRL; /**< Offset: 0x0A (R/W 8) Window Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t AC_SCALER[2]; /**< Offset: 0x0C (R/W 8) Scaler n */ + __I uint8_t Reserved2[0x02]; + __IO uint32_t AC_COMPCTRL[2]; /**< Offset: 0x10 (R/W 32) Comparator Control n */ + __I uint8_t Reserved3[0x08]; + __I uint32_t AC_SYNCBUSY; /**< Offset: 0x20 (R/ 32) Synchronization Busy */ + __IO uint16_t AC_CALIB; /**< Offset: 0x24 (R/W 16) Calibration */ +} ac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_AC_COMPONENT_H_ */ diff --git a/os/common/ext/Microchip/SAME54/component/adc.h b/os/common/ext/Microchip/SAME54/component/adc.h new file mode 100644 index 0000000000..280af2fd8f --- /dev/null +++ b/os/common/ext/Microchip/SAME54/component/adc.h @@ -0,0 +1,630 @@ +/* + * Component description for ADC + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:08Z */ +#ifndef _SAME54_ADC_COMPONENT_H_ +#define _SAME54_ADC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ADC */ +/* ************************************************************************** */ + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ +#define ADC_CTRLA_RESETVALUE _UINT16_(0x00) /* (ADC_CTRLA) Control A Reset Value */ + +#define ADC_CTRLA_SWRST_Pos _UINT16_(0) /* (ADC_CTRLA) Software Reset Position */ +#define ADC_CTRLA_SWRST_Msk (_UINT16_(0x1) << ADC_CTRLA_SWRST_Pos) /* (ADC_CTRLA) Software Reset Mask */ +#define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & (_UINT16_(value) << ADC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the ADC_CTRLA register */ +#define ADC_CTRLA_ENABLE_Pos _UINT16_(1) /* (ADC_CTRLA) Enable Position */ +#define ADC_CTRLA_ENABLE_Msk (_UINT16_(0x1) << ADC_CTRLA_ENABLE_Pos) /* (ADC_CTRLA) Enable Mask */ +#define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & (_UINT16_(value) << ADC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the ADC_CTRLA register */ +#define ADC_CTRLA_DUALSEL_Pos _UINT16_(3) /* (ADC_CTRLA) Dual Mode Trigger Selection Position */ +#define ADC_CTRLA_DUALSEL_Msk (_UINT16_(0x3) << ADC_CTRLA_DUALSEL_Pos) /* (ADC_CTRLA) Dual Mode Trigger Selection Mask */ +#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & (_UINT16_(value) << ADC_CTRLA_DUALSEL_Pos)) /* Assigment of value for DUALSEL in the ADC_CTRLA register */ +#define ADC_CTRLA_DUALSEL_BOTH_Val _UINT16_(0x0) /* (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _UINT16_(0x1) /* (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) /* (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs Position */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) /* (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 Position */ +#define ADC_CTRLA_SLAVEEN_Pos _UINT16_(5) /* (ADC_CTRLA) Slave Enable Position */ +#define ADC_CTRLA_SLAVEEN_Msk (_UINT16_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /* (ADC_CTRLA) Slave Enable Mask */ +#define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & (_UINT16_(value) << ADC_CTRLA_SLAVEEN_Pos)) /* Assigment of value for SLAVEEN in the ADC_CTRLA register */ +#define ADC_CTRLA_RUNSTDBY_Pos _UINT16_(6) /* (ADC_CTRLA) Run in Standby Position */ +#define ADC_CTRLA_RUNSTDBY_Msk (_UINT16_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /* (ADC_CTRLA) Run in Standby Mask */ +#define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & (_UINT16_(value) << ADC_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the ADC_CTRLA register */ +#define ADC_CTRLA_ONDEMAND_Pos _UINT16_(7) /* (ADC_CTRLA) On Demand Control Position */ +#define ADC_CTRLA_ONDEMAND_Msk (_UINT16_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /* (ADC_CTRLA) On Demand Control Mask */ +#define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & (_UINT16_(value) << ADC_CTRLA_ONDEMAND_Pos)) /* Assigment of value for ONDEMAND in the ADC_CTRLA register */ +#define ADC_CTRLA_PRESCALER_Pos _UINT16_(8) /* (ADC_CTRLA) Prescaler Configuration Position */ +#define ADC_CTRLA_PRESCALER_Msk (_UINT16_(0x7) << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Prescaler Configuration Mask */ +#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & (_UINT16_(value) << ADC_CTRLA_PRESCALER_Pos)) /* Assigment of value for PRESCALER in the ADC_CTRLA register */ +#define ADC_CTRLA_PRESCALER_DIV2_Val _UINT16_(0x0) /* (ADC_CTRLA) Peripheral clock divided by 2 */ +#define ADC_CTRLA_PRESCALER_DIV4_Val _UINT16_(0x1) /* (ADC_CTRLA) Peripheral clock divided by 4 */ +#define ADC_CTRLA_PRESCALER_DIV8_Val _UINT16_(0x2) /* (ADC_CTRLA) Peripheral clock divided by 8 */ +#define ADC_CTRLA_PRESCALER_DIV16_Val _UINT16_(0x3) /* (ADC_CTRLA) Peripheral clock divided by 16 */ +#define ADC_CTRLA_PRESCALER_DIV32_Val _UINT16_(0x4) /* (ADC_CTRLA) Peripheral clock divided by 32 */ +#define ADC_CTRLA_PRESCALER_DIV64_Val _UINT16_(0x5) /* (ADC_CTRLA) Peripheral clock divided by 64 */ +#define ADC_CTRLA_PRESCALER_DIV128_Val _UINT16_(0x6) /* (ADC_CTRLA) Peripheral clock divided by 128 */ +#define ADC_CTRLA_PRESCALER_DIV256_Val _UINT16_(0x7) /* (ADC_CTRLA) Peripheral clock divided by 256 */ +#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 2 Position */ +#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 4 Position */ +#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 8 Position */ +#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 16 Position */ +#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 32 Position */ +#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 64 Position */ +#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 128 Position */ +#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) /* (ADC_CTRLA) Peripheral clock divided by 256 Position */ +#define ADC_CTRLA_R2R_Pos _UINT16_(15) /* (ADC_CTRLA) Rail to Rail Operation Enable Position */ +#define ADC_CTRLA_R2R_Msk (_UINT16_(0x1) << ADC_CTRLA_R2R_Pos) /* (ADC_CTRLA) Rail to Rail Operation Enable Mask */ +#define ADC_CTRLA_R2R(value) (ADC_CTRLA_R2R_Msk & (_UINT16_(value) << ADC_CTRLA_R2R_Pos)) /* Assigment of value for R2R in the ADC_CTRLA register */ +#define ADC_CTRLA_Msk _UINT16_(0x87FB) /* (ADC_CTRLA) Register Mask */ + + +/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ +#define ADC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_EVCTRL) Event Control Reset Value */ + +#define ADC_EVCTRL_FLUSHEI_Pos _UINT8_(0) /* (ADC_EVCTRL) Flush Event Input Enable Position */ +#define ADC_EVCTRL_FLUSHEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /* (ADC_EVCTRL) Flush Event Input Enable Mask */ +#define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHEI_Pos)) /* Assigment of value for FLUSHEI in the ADC_EVCTRL register */ +#define ADC_EVCTRL_STARTEI_Pos _UINT8_(1) /* (ADC_EVCTRL) Start Conversion Event Input Enable Position */ +#define ADC_EVCTRL_STARTEI_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTEI_Pos) /* (ADC_EVCTRL) Start Conversion Event Input Enable Mask */ +#define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTEI_Pos)) /* Assigment of value for STARTEI in the ADC_EVCTRL register */ +#define ADC_EVCTRL_FLUSHINV_Pos _UINT8_(2) /* (ADC_EVCTRL) Flush Event Invert Enable Position */ +#define ADC_EVCTRL_FLUSHINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /* (ADC_EVCTRL) Flush Event Invert Enable Mask */ +#define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & (_UINT8_(value) << ADC_EVCTRL_FLUSHINV_Pos)) /* Assigment of value for FLUSHINV in the ADC_EVCTRL register */ +#define ADC_EVCTRL_STARTINV_Pos _UINT8_(3) /* (ADC_EVCTRL) Start Conversion Event Invert Enable Position */ +#define ADC_EVCTRL_STARTINV_Msk (_UINT8_(0x1) << ADC_EVCTRL_STARTINV_Pos) /* (ADC_EVCTRL) Start Conversion Event Invert Enable Mask */ +#define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & (_UINT8_(value) << ADC_EVCTRL_STARTINV_Pos)) /* Assigment of value for STARTINV in the ADC_EVCTRL register */ +#define ADC_EVCTRL_RESRDYEO_Pos _UINT8_(4) /* (ADC_EVCTRL) Result Ready Event Out Position */ +#define ADC_EVCTRL_RESRDYEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /* (ADC_EVCTRL) Result Ready Event Out Mask */ +#define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & (_UINT8_(value) << ADC_EVCTRL_RESRDYEO_Pos)) /* Assigment of value for RESRDYEO in the ADC_EVCTRL register */ +#define ADC_EVCTRL_WINMONEO_Pos _UINT8_(5) /* (ADC_EVCTRL) Window Monitor Event Out Position */ +#define ADC_EVCTRL_WINMONEO_Msk (_UINT8_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /* (ADC_EVCTRL) Window Monitor Event Out Mask */ +#define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & (_UINT8_(value) << ADC_EVCTRL_WINMONEO_Pos)) /* Assigment of value for WINMONEO in the ADC_EVCTRL register */ +#define ADC_EVCTRL_Msk _UINT8_(0x3F) /* (ADC_EVCTRL) Register Mask */ + + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ +#define ADC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_DBGCTRL) Debug Control Reset Value */ + +#define ADC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (ADC_DBGCTRL) Debug Run Position */ +#define ADC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /* (ADC_DBGCTRL) Debug Run Mask */ +#define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << ADC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the ADC_DBGCTRL register */ +#define ADC_DBGCTRL_Msk _UINT8_(0x01) /* (ADC_DBGCTRL) Register Mask */ + + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ +#define ADC_INPUTCTRL_RESETVALUE _UINT16_(0x00) /* (ADC_INPUTCTRL) Input Control Reset Value */ + +#define ADC_INPUTCTRL_MUXPOS_Pos _UINT16_(0) /* (ADC_INPUTCTRL) Positive Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Positive Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXPOS_Pos)) /* Assigment of value for MUXPOS in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _UINT16_(0x6) /* (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _UINT16_(0x7) /* (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _UINT16_(0x8) /* (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _UINT16_(0x9) /* (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _UINT16_(0xA) /* (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _UINT16_(0xB) /* (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _UINT16_(0xC) /* (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _UINT16_(0xD) /* (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _UINT16_(0xE) /* (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _UINT16_(0xF) /* (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _UINT16_(0x18) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _UINT16_(0x19) /* (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _UINT16_(0x1A) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _UINT16_(0x1B) /* (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _UINT16_(0x1C) /* (ADC_INPUTCTRL) Temperature Sensor TSENSP */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _UINT16_(0x1D) /* (ADC_INPUTCTRL) Temperature Sensor TSENSC */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _UINT16_(0x1E) /* (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PTC_Val _UINT16_(0x1F) /* (ADC_INPUTCTRL) PTC output (only on ADC0) */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN6 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN7 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN8 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN9 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN10 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN11 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN12 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN13 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN14 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) ADC AIN15 Pin Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled Core Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) 1/4 Scaled I/O Supply Position */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Bandgap Voltage Position */ +#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Temperature Sensor TSENSP Position */ +#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) Temperature Sensor TSENSC Position */ +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) DAC Output Position */ +#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /* (ADC_INPUTCTRL) PTC output (only on ADC0) Position */ +#define ADC_INPUTCTRL_DIFFMODE_Pos _UINT16_(7) /* (ADC_INPUTCTRL) Differential Mode Position */ +#define ADC_INPUTCTRL_DIFFMODE_Msk (_UINT16_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) /* (ADC_INPUTCTRL) Differential Mode Mask */ +#define ADC_INPUTCTRL_DIFFMODE(value) (ADC_INPUTCTRL_DIFFMODE_Msk & (_UINT16_(value) << ADC_INPUTCTRL_DIFFMODE_Pos)) /* Assigment of value for DIFFMODE in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXNEG_Pos _UINT16_(8) /* (ADC_INPUTCTRL) Negative Mux Input Selection Position */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_UINT16_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Negative Mux Input Selection Mask */ +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & (_UINT16_(value) << ADC_INPUTCTRL_MUXNEG_Pos)) /* Assigment of value for MUXNEG in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _UINT16_(0x0) /* (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _UINT16_(0x1) /* (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _UINT16_(0x2) /* (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _UINT16_(0x3) /* (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _UINT16_(0x4) /* (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _UINT16_(0x5) /* (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _UINT16_(0x6) /* (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _UINT16_(0x7) /* (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _UINT16_(0x18) /* (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN0 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN1 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN2 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN3 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN4 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN5 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN6 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) ADC AIN7 Pin Position */ +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /* (ADC_INPUTCTRL) Internal Ground Position */ +#define ADC_INPUTCTRL_DSEQSTOP_Pos _UINT16_(15) /* (ADC_INPUTCTRL) Stop DMA Sequencing Position */ +#define ADC_INPUTCTRL_DSEQSTOP_Msk (_UINT16_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) /* (ADC_INPUTCTRL) Stop DMA Sequencing Mask */ +#define ADC_INPUTCTRL_DSEQSTOP(value) (ADC_INPUTCTRL_DSEQSTOP_Msk & (_UINT16_(value) << ADC_INPUTCTRL_DSEQSTOP_Pos)) /* Assigment of value for DSEQSTOP in the ADC_INPUTCTRL register */ +#define ADC_INPUTCTRL_Msk _UINT16_(0x9F9F) /* (ADC_INPUTCTRL) Register Mask */ + + +/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ +#define ADC_CTRLB_RESETVALUE _UINT16_(0x00) /* (ADC_CTRLB) Control B Reset Value */ + +#define ADC_CTRLB_LEFTADJ_Pos _UINT16_(0) /* (ADC_CTRLB) Left-Adjusted Result Position */ +#define ADC_CTRLB_LEFTADJ_Msk (_UINT16_(0x1) << ADC_CTRLB_LEFTADJ_Pos) /* (ADC_CTRLB) Left-Adjusted Result Mask */ +#define ADC_CTRLB_LEFTADJ(value) (ADC_CTRLB_LEFTADJ_Msk & (_UINT16_(value) << ADC_CTRLB_LEFTADJ_Pos)) /* Assigment of value for LEFTADJ in the ADC_CTRLB register */ +#define ADC_CTRLB_FREERUN_Pos _UINT16_(1) /* (ADC_CTRLB) Free Running Mode Position */ +#define ADC_CTRLB_FREERUN_Msk (_UINT16_(0x1) << ADC_CTRLB_FREERUN_Pos) /* (ADC_CTRLB) Free Running Mode Mask */ +#define ADC_CTRLB_FREERUN(value) (ADC_CTRLB_FREERUN_Msk & (_UINT16_(value) << ADC_CTRLB_FREERUN_Pos)) /* Assigment of value for FREERUN in the ADC_CTRLB register */ +#define ADC_CTRLB_CORREN_Pos _UINT16_(2) /* (ADC_CTRLB) Digital Correction Logic Enable Position */ +#define ADC_CTRLB_CORREN_Msk (_UINT16_(0x1) << ADC_CTRLB_CORREN_Pos) /* (ADC_CTRLB) Digital Correction Logic Enable Mask */ +#define ADC_CTRLB_CORREN(value) (ADC_CTRLB_CORREN_Msk & (_UINT16_(value) << ADC_CTRLB_CORREN_Pos)) /* Assigment of value for CORREN in the ADC_CTRLB register */ +#define ADC_CTRLB_RESSEL_Pos _UINT16_(3) /* (ADC_CTRLB) Conversion Result Resolution Position */ +#define ADC_CTRLB_RESSEL_Msk (_UINT16_(0x3) << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) Conversion Result Resolution Mask */ +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & (_UINT16_(value) << ADC_CTRLB_RESSEL_Pos)) /* Assigment of value for RESSEL in the ADC_CTRLB register */ +#define ADC_CTRLB_RESSEL_12BIT_Val _UINT16_(0x0) /* (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _UINT16_(0x1) /* (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _UINT16_(0x2) /* (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _UINT16_(0x3) /* (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) 12-bit result Position */ +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) For averaging mode output Position */ +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) 10-bit result Position */ +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) /* (ADC_CTRLB) 8-bit result Position */ +#define ADC_CTRLB_WINMODE_Pos _UINT16_(8) /* (ADC_CTRLB) Window Monitor Mode Position */ +#define ADC_CTRLB_WINMODE_Msk (_UINT16_(0x7) << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) Window Monitor Mode Mask */ +#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & (_UINT16_(value) << ADC_CTRLB_WINMODE_Pos)) /* Assigment of value for WINMODE in the ADC_CTRLB register */ +#define ADC_CTRLB_WINMODE_DISABLE_Val _UINT16_(0x0) /* (ADC_CTRLB) No window mode (default) */ +#define ADC_CTRLB_WINMODE_MODE1_Val _UINT16_(0x1) /* (ADC_CTRLB) RESULT > WINLT */ +#define ADC_CTRLB_WINMODE_MODE2_Val _UINT16_(0x2) /* (ADC_CTRLB) RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE3_Val _UINT16_(0x3) /* (ADC_CTRLB) WINLT < RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE4_Val _UINT16_(0x4) /* (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) No window mode (default) Position */ +#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) RESULT > WINLT Position */ +#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) RESULT < WINUT Position */ +#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) WINLT < RESULT < WINUT Position */ +#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) /* (ADC_CTRLB) !(WINLT < RESULT < WINUT) Position */ +#define ADC_CTRLB_WINSS_Pos _UINT16_(11) /* (ADC_CTRLB) Window Single Sample Position */ +#define ADC_CTRLB_WINSS_Msk (_UINT16_(0x1) << ADC_CTRLB_WINSS_Pos) /* (ADC_CTRLB) Window Single Sample Mask */ +#define ADC_CTRLB_WINSS(value) (ADC_CTRLB_WINSS_Msk & (_UINT16_(value) << ADC_CTRLB_WINSS_Pos)) /* Assigment of value for WINSS in the ADC_CTRLB register */ +#define ADC_CTRLB_Msk _UINT16_(0x0F1F) /* (ADC_CTRLB) Register Mask */ + + +/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ +#define ADC_REFCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_REFCTRL) Reference Control Reset Value */ + +#define ADC_REFCTRL_REFSEL_Pos _UINT8_(0) /* (ADC_REFCTRL) Reference Selection Position */ +#define ADC_REFCTRL_REFSEL_Msk (_UINT8_(0xF) << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Reference Selection Mask */ +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & (_UINT8_(value) << ADC_REFCTRL_REFSEL_Pos)) /* Assigment of value for REFSEL in the ADC_REFCTRL register */ +#define ADC_REFCTRL_REFSEL_INTREF_Val _UINT8_(0x0) /* (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _UINT8_(0x2) /* (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _UINT8_(0x3) /* (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _UINT8_(0x4) /* (ADC_REFCTRL) External Reference A */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _UINT8_(0x5) /* (ADC_REFCTRL) External Reference B */ +#define ADC_REFCTRL_REFSEL_AREFC_Val _UINT8_(0x6) /* (ADC_REFCTRL) External Reference C (only on ADC1) */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) Internal Bandgap Reference Position */ +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) 1/2 VDDANA Position */ +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) VDDANA Position */ +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference A Position */ +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference B Position */ +#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) /* (ADC_REFCTRL) External Reference C (only on ADC1) Position */ +#define ADC_REFCTRL_REFCOMP_Pos _UINT8_(7) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */ +#define ADC_REFCTRL_REFCOMP_Msk (_UINT8_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /* (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */ +#define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & (_UINT8_(value) << ADC_REFCTRL_REFCOMP_Pos)) /* Assigment of value for REFCOMP in the ADC_REFCTRL register */ +#define ADC_REFCTRL_Msk _UINT8_(0x8F) /* (ADC_REFCTRL) Register Mask */ + + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ +#define ADC_AVGCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_AVGCTRL) Average Control Reset Value */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos _UINT8_(0) /* (ADC_AVGCTRL) Number of Samples to be Collected Position */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_UINT8_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) Number of Samples to be Collected Mask */ +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & (_UINT8_(value) << ADC_AVGCTRL_SAMPLENUM_Pos)) /* Assigment of value for SAMPLENUM in the ADC_AVGCTRL register */ +#define ADC_AVGCTRL_SAMPLENUM_1_Val _UINT8_(0x0) /* (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _UINT8_(0x1) /* (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _UINT8_(0x2) /* (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _UINT8_(0x3) /* (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _UINT8_(0x4) /* (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _UINT8_(0x5) /* (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _UINT8_(0x6) /* (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _UINT8_(0x7) /* (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _UINT8_(0x8) /* (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _UINT8_(0x9) /* (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _UINT8_(0xA) /* (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1 sample Position */ +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 2 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 4 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 8 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 16 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 32 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 64 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 128 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 256 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 512 samples Position */ +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /* (ADC_AVGCTRL) 1024 samples Position */ +#define ADC_AVGCTRL_ADJRES_Pos _UINT8_(4) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */ +#define ADC_AVGCTRL_ADJRES_Msk (_UINT8_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /* (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */ +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & (_UINT8_(value) << ADC_AVGCTRL_ADJRES_Pos)) /* Assigment of value for ADJRES in the ADC_AVGCTRL register */ +#define ADC_AVGCTRL_Msk _UINT8_(0x7F) /* (ADC_AVGCTRL) Register Mask */ + + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ +#define ADC_SAMPCTRL_RESETVALUE _UINT8_(0x00) /* (ADC_SAMPCTRL) Sample Time Control Reset Value */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos _UINT8_(0) /* (ADC_SAMPCTRL) Sampling Time Length Position */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_UINT8_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /* (ADC_SAMPCTRL) Sampling Time Length Mask */ +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & (_UINT8_(value) << ADC_SAMPCTRL_SAMPLEN_Pos)) /* Assigment of value for SAMPLEN in the ADC_SAMPCTRL register */ +#define ADC_SAMPCTRL_OFFCOMP_Pos _UINT8_(7) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */ +#define ADC_SAMPCTRL_OFFCOMP_Msk (_UINT8_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /* (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */ +#define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & (_UINT8_(value) << ADC_SAMPCTRL_OFFCOMP_Pos)) /* Assigment of value for OFFCOMP in the ADC_SAMPCTRL register */ +#define ADC_SAMPCTRL_Msk _UINT8_(0xBF) /* (ADC_SAMPCTRL) Register Mask */ + + +/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ +#define ADC_WINLT_RESETVALUE _UINT16_(0x00) /* (ADC_WINLT) Window Monitor Lower Threshold Reset Value */ + +#define ADC_WINLT_WINLT_Pos _UINT16_(0) /* (ADC_WINLT) Window Lower Threshold Position */ +#define ADC_WINLT_WINLT_Msk (_UINT16_(0xFFFF) << ADC_WINLT_WINLT_Pos) /* (ADC_WINLT) Window Lower Threshold Mask */ +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & (_UINT16_(value) << ADC_WINLT_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_WINLT register */ +#define ADC_WINLT_Msk _UINT16_(0xFFFF) /* (ADC_WINLT) Register Mask */ + + +/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ +#define ADC_WINUT_RESETVALUE _UINT16_(0x00) /* (ADC_WINUT) Window Monitor Upper Threshold Reset Value */ + +#define ADC_WINUT_WINUT_Pos _UINT16_(0) /* (ADC_WINUT) Window Upper Threshold Position */ +#define ADC_WINUT_WINUT_Msk (_UINT16_(0xFFFF) << ADC_WINUT_WINUT_Pos) /* (ADC_WINUT) Window Upper Threshold Mask */ +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & (_UINT16_(value) << ADC_WINUT_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_WINUT register */ +#define ADC_WINUT_Msk _UINT16_(0xFFFF) /* (ADC_WINUT) Register Mask */ + + +/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ +#define ADC_GAINCORR_RESETVALUE _UINT16_(0x00) /* (ADC_GAINCORR) Gain Correction Reset Value */ + +#define ADC_GAINCORR_GAINCORR_Pos _UINT16_(0) /* (ADC_GAINCORR) Gain Correction Value Position */ +#define ADC_GAINCORR_GAINCORR_Msk (_UINT16_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /* (ADC_GAINCORR) Gain Correction Value Mask */ +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & (_UINT16_(value) << ADC_GAINCORR_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_GAINCORR register */ +#define ADC_GAINCORR_Msk _UINT16_(0x0FFF) /* (ADC_GAINCORR) Register Mask */ + + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ +#define ADC_OFFSETCORR_RESETVALUE _UINT16_(0x00) /* (ADC_OFFSETCORR) Offset Correction Reset Value */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos _UINT16_(0) /* (ADC_OFFSETCORR) Offset Correction Value Position */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_UINT16_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /* (ADC_OFFSETCORR) Offset Correction Value Mask */ +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & (_UINT16_(value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_OFFSETCORR register */ +#define ADC_OFFSETCORR_Msk _UINT16_(0x0FFF) /* (ADC_OFFSETCORR) Register Mask */ + + +/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ +#define ADC_SWTRIG_RESETVALUE _UINT8_(0x00) /* (ADC_SWTRIG) Software Trigger Reset Value */ + +#define ADC_SWTRIG_FLUSH_Pos _UINT8_(0) /* (ADC_SWTRIG) ADC Conversion Flush Position */ +#define ADC_SWTRIG_FLUSH_Msk (_UINT8_(0x1) << ADC_SWTRIG_FLUSH_Pos) /* (ADC_SWTRIG) ADC Conversion Flush Mask */ +#define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & (_UINT8_(value) << ADC_SWTRIG_FLUSH_Pos)) /* Assigment of value for FLUSH in the ADC_SWTRIG register */ +#define ADC_SWTRIG_START_Pos _UINT8_(1) /* (ADC_SWTRIG) Start ADC Conversion Position */ +#define ADC_SWTRIG_START_Msk (_UINT8_(0x1) << ADC_SWTRIG_START_Pos) /* (ADC_SWTRIG) Start ADC Conversion Mask */ +#define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & (_UINT8_(value) << ADC_SWTRIG_START_Pos)) /* Assigment of value for START in the ADC_SWTRIG register */ +#define ADC_SWTRIG_Msk _UINT8_(0x03) /* (ADC_SWTRIG) Register Mask */ + + +/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ +#define ADC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (ADC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define ADC_INTENCLR_RESRDY_Pos _UINT8_(0) /* (ADC_INTENCLR) Result Ready Interrupt Disable Position */ +#define ADC_INTENCLR_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENCLR_RESRDY_Pos) /* (ADC_INTENCLR) Result Ready Interrupt Disable Mask */ +#define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & (_UINT8_(value) << ADC_INTENCLR_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTENCLR register */ +#define ADC_INTENCLR_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENCLR) Overrun Interrupt Disable Position */ +#define ADC_INTENCLR_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /* (ADC_INTENCLR) Overrun Interrupt Disable Mask */ +#define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENCLR_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTENCLR register */ +#define ADC_INTENCLR_WINMON_Pos _UINT8_(2) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Position */ +#define ADC_INTENCLR_WINMON_Msk (_UINT8_(0x1) << ADC_INTENCLR_WINMON_Pos) /* (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */ +#define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & (_UINT8_(value) << ADC_INTENCLR_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTENCLR register */ +#define ADC_INTENCLR_Msk _UINT8_(0x07) /* (ADC_INTENCLR) Register Mask */ + + +/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ +#define ADC_INTENSET_RESETVALUE _UINT8_(0x00) /* (ADC_INTENSET) Interrupt Enable Set Reset Value */ + +#define ADC_INTENSET_RESRDY_Pos _UINT8_(0) /* (ADC_INTENSET) Result Ready Interrupt Enable Position */ +#define ADC_INTENSET_RESRDY_Msk (_UINT8_(0x1) << ADC_INTENSET_RESRDY_Pos) /* (ADC_INTENSET) Result Ready Interrupt Enable Mask */ +#define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & (_UINT8_(value) << ADC_INTENSET_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTENSET register */ +#define ADC_INTENSET_OVERRUN_Pos _UINT8_(1) /* (ADC_INTENSET) Overrun Interrupt Enable Position */ +#define ADC_INTENSET_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTENSET_OVERRUN_Pos) /* (ADC_INTENSET) Overrun Interrupt Enable Mask */ +#define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & (_UINT8_(value) << ADC_INTENSET_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTENSET register */ +#define ADC_INTENSET_WINMON_Pos _UINT8_(2) /* (ADC_INTENSET) Window Monitor Interrupt Enable Position */ +#define ADC_INTENSET_WINMON_Msk (_UINT8_(0x1) << ADC_INTENSET_WINMON_Pos) /* (ADC_INTENSET) Window Monitor Interrupt Enable Mask */ +#define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & (_UINT8_(value) << ADC_INTENSET_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTENSET register */ +#define ADC_INTENSET_Msk _UINT8_(0x07) /* (ADC_INTENSET) Register Mask */ + + +/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define ADC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define ADC_INTFLAG_RESRDY_Pos _UINT8_(0) /* (ADC_INTFLAG) Result Ready Interrupt Flag Position */ +#define ADC_INTFLAG_RESRDY_Msk (_UINT8_(0x1) << ADC_INTFLAG_RESRDY_Pos) /* (ADC_INTFLAG) Result Ready Interrupt Flag Mask */ +#define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & (_UINT8_(value) << ADC_INTFLAG_RESRDY_Pos)) /* Assigment of value for RESRDY in the ADC_INTFLAG register */ +#define ADC_INTFLAG_OVERRUN_Pos _UINT8_(1) /* (ADC_INTFLAG) Overrun Interrupt Flag Position */ +#define ADC_INTFLAG_OVERRUN_Msk (_UINT8_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /* (ADC_INTFLAG) Overrun Interrupt Flag Mask */ +#define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & (_UINT8_(value) << ADC_INTFLAG_OVERRUN_Pos)) /* Assigment of value for OVERRUN in the ADC_INTFLAG register */ +#define ADC_INTFLAG_WINMON_Pos _UINT8_(2) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Position */ +#define ADC_INTFLAG_WINMON_Msk (_UINT8_(0x1) << ADC_INTFLAG_WINMON_Pos) /* (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */ +#define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & (_UINT8_(value) << ADC_INTFLAG_WINMON_Pos)) /* Assigment of value for WINMON in the ADC_INTFLAG register */ +#define ADC_INTFLAG_Msk _UINT8_(0x07) /* (ADC_INTFLAG) Register Mask */ + + +/* -------- ADC_STATUS : (ADC Offset: 0x2F) ( R/ 8) Status -------- */ +#define ADC_STATUS_RESETVALUE _UINT8_(0x00) /* (ADC_STATUS) Status Reset Value */ + +#define ADC_STATUS_ADCBUSY_Pos _UINT8_(0) /* (ADC_STATUS) ADC Busy Status Position */ +#define ADC_STATUS_ADCBUSY_Msk (_UINT8_(0x1) << ADC_STATUS_ADCBUSY_Pos) /* (ADC_STATUS) ADC Busy Status Mask */ +#define ADC_STATUS_ADCBUSY(value) (ADC_STATUS_ADCBUSY_Msk & (_UINT8_(value) << ADC_STATUS_ADCBUSY_Pos)) /* Assigment of value for ADCBUSY in the ADC_STATUS register */ +#define ADC_STATUS_WCC_Pos _UINT8_(2) /* (ADC_STATUS) Window Comparator Counter Position */ +#define ADC_STATUS_WCC_Msk (_UINT8_(0x3F) << ADC_STATUS_WCC_Pos) /* (ADC_STATUS) Window Comparator Counter Mask */ +#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & (_UINT8_(value) << ADC_STATUS_WCC_Pos)) /* Assigment of value for WCC in the ADC_STATUS register */ +#define ADC_STATUS_Msk _UINT8_(0xFD) /* (ADC_STATUS) Register Mask */ + + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) ( R/ 32) Synchronization Busy -------- */ +#define ADC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (ADC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define ADC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /* (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << ADC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */ +#define ADC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /* (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */ +#define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << ADC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_INPUTCTRL_Pos _UINT32_(2) /* (ADC_SYNCBUSY) Input Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_INPUTCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /* (ADC_SYNCBUSY) Input Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_INPUTCTRL_Pos)) /* Assigment of value for INPUTCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_CTRLB_Pos _UINT32_(3) /* (ADC_SYNCBUSY) Control B Synchronization Busy Position */ +#define ADC_SYNCBUSY_CTRLB_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) /* (ADC_SYNCBUSY) Control B Synchronization Busy Mask */ +#define ADC_SYNCBUSY_CTRLB(value) (ADC_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << ADC_SYNCBUSY_CTRLB_Pos)) /* Assigment of value for CTRLB in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_REFCTRL_Pos _UINT32_(4) /* (ADC_SYNCBUSY) Reference Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_REFCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) /* (ADC_SYNCBUSY) Reference Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_REFCTRL(value) (ADC_SYNCBUSY_REFCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_REFCTRL_Pos)) /* Assigment of value for REFCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_AVGCTRL_Pos _UINT32_(5) /* (ADC_SYNCBUSY) Average Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_AVGCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /* (ADC_SYNCBUSY) Average Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_AVGCTRL_Pos)) /* Assigment of value for AVGCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_SAMPCTRL_Pos _UINT32_(6) /* (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Position */ +#define ADC_SYNCBUSY_SAMPCTRL_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /* (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & (_UINT32_(value) << ADC_SYNCBUSY_SAMPCTRL_Pos)) /* Assigment of value for SAMPCTRL in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_WINLT_Pos _UINT32_(7) /* (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINLT_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /* (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & (_UINT32_(value) << ADC_SYNCBUSY_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_WINUT_Pos _UINT32_(8) /* (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Position */ +#define ADC_SYNCBUSY_WINUT_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /* (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Mask */ +#define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & (_UINT32_(value) << ADC_SYNCBUSY_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_GAINCORR_Pos _UINT32_(9) /* (ADC_SYNCBUSY) Gain Correction Synchronization Busy Position */ +#define ADC_SYNCBUSY_GAINCORR_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /* (ADC_SYNCBUSY) Gain Correction Synchronization Busy Mask */ +#define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & (_UINT32_(value) << ADC_SYNCBUSY_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_OFFSETCORR_Pos _UINT32_(10) /* (ADC_SYNCBUSY) Offset Correction Synchronization Busy Position */ +#define ADC_SYNCBUSY_OFFSETCORR_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /* (ADC_SYNCBUSY) Offset Correction Synchronization Busy Mask */ +#define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & (_UINT32_(value) << ADC_SYNCBUSY_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_SWTRIG_Pos _UINT32_(11) /* (ADC_SYNCBUSY) Software Trigger Synchronization Busy Position */ +#define ADC_SYNCBUSY_SWTRIG_Msk (_UINT32_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /* (ADC_SYNCBUSY) Software Trigger Synchronization Busy Mask */ +#define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & (_UINT32_(value) << ADC_SYNCBUSY_SWTRIG_Pos)) /* Assigment of value for SWTRIG in the ADC_SYNCBUSY register */ +#define ADC_SYNCBUSY_Msk _UINT32_(0x00000FFF) /* (ADC_SYNCBUSY) Register Mask */ + + +/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ +#define ADC_DSEQDATA_RESETVALUE _UINT32_(0x00) /* (ADC_DSEQDATA) DMA Sequencial Data Reset Value */ + +#define ADC_DSEQDATA_DATA_Pos _UINT32_(0) /* (ADC_DSEQDATA) DMA Sequential Data Position */ +#define ADC_DSEQDATA_DATA_Msk (_UINT32_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) /* (ADC_DSEQDATA) DMA Sequential Data Mask */ +#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & (_UINT32_(value) << ADC_DSEQDATA_DATA_Pos)) /* Assigment of value for DATA in the ADC_DSEQDATA register */ +#define ADC_DSEQDATA_Msk _UINT32_(0xFFFFFFFF) /* (ADC_DSEQDATA) Register Mask */ + + +/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ +#define ADC_DSEQCTRL_RESETVALUE _UINT32_(0x00) /* (ADC_DSEQCTRL) DMA Sequential Control Reset Value */ + +#define ADC_DSEQCTRL_INPUTCTRL_Pos _UINT32_(0) /* (ADC_DSEQCTRL) Input Control Position */ +#define ADC_DSEQCTRL_INPUTCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) /* (ADC_DSEQCTRL) Input Control Mask */ +#define ADC_DSEQCTRL_INPUTCTRL(value) (ADC_DSEQCTRL_INPUTCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_INPUTCTRL_Pos)) /* Assigment of value for INPUTCTRL in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_CTRLB_Pos _UINT32_(1) /* (ADC_DSEQCTRL) Control B Position */ +#define ADC_DSEQCTRL_CTRLB_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) /* (ADC_DSEQCTRL) Control B Mask */ +#define ADC_DSEQCTRL_CTRLB(value) (ADC_DSEQCTRL_CTRLB_Msk & (_UINT32_(value) << ADC_DSEQCTRL_CTRLB_Pos)) /* Assigment of value for CTRLB in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_REFCTRL_Pos _UINT32_(2) /* (ADC_DSEQCTRL) Reference Control Position */ +#define ADC_DSEQCTRL_REFCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) /* (ADC_DSEQCTRL) Reference Control Mask */ +#define ADC_DSEQCTRL_REFCTRL(value) (ADC_DSEQCTRL_REFCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_REFCTRL_Pos)) /* Assigment of value for REFCTRL in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_AVGCTRL_Pos _UINT32_(3) /* (ADC_DSEQCTRL) Average Control Position */ +#define ADC_DSEQCTRL_AVGCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) /* (ADC_DSEQCTRL) Average Control Mask */ +#define ADC_DSEQCTRL_AVGCTRL(value) (ADC_DSEQCTRL_AVGCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_AVGCTRL_Pos)) /* Assigment of value for AVGCTRL in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_SAMPCTRL_Pos _UINT32_(4) /* (ADC_DSEQCTRL) Sampling Time Control Position */ +#define ADC_DSEQCTRL_SAMPCTRL_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) /* (ADC_DSEQCTRL) Sampling Time Control Mask */ +#define ADC_DSEQCTRL_SAMPCTRL(value) (ADC_DSEQCTRL_SAMPCTRL_Msk & (_UINT32_(value) << ADC_DSEQCTRL_SAMPCTRL_Pos)) /* Assigment of value for SAMPCTRL in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_WINLT_Pos _UINT32_(5) /* (ADC_DSEQCTRL) Window Monitor Lower Threshold Position */ +#define ADC_DSEQCTRL_WINLT_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_WINLT_Pos) /* (ADC_DSEQCTRL) Window Monitor Lower Threshold Mask */ +#define ADC_DSEQCTRL_WINLT(value) (ADC_DSEQCTRL_WINLT_Msk & (_UINT32_(value) << ADC_DSEQCTRL_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_WINUT_Pos _UINT32_(6) /* (ADC_DSEQCTRL) Window Monitor Upper Threshold Position */ +#define ADC_DSEQCTRL_WINUT_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_WINUT_Pos) /* (ADC_DSEQCTRL) Window Monitor Upper Threshold Mask */ +#define ADC_DSEQCTRL_WINUT(value) (ADC_DSEQCTRL_WINUT_Msk & (_UINT32_(value) << ADC_DSEQCTRL_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_GAINCORR_Pos _UINT32_(7) /* (ADC_DSEQCTRL) Gain Correction Position */ +#define ADC_DSEQCTRL_GAINCORR_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) /* (ADC_DSEQCTRL) Gain Correction Mask */ +#define ADC_DSEQCTRL_GAINCORR(value) (ADC_DSEQCTRL_GAINCORR_Msk & (_UINT32_(value) << ADC_DSEQCTRL_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_OFFSETCORR_Pos _UINT32_(8) /* (ADC_DSEQCTRL) Offset Correction Position */ +#define ADC_DSEQCTRL_OFFSETCORR_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) /* (ADC_DSEQCTRL) Offset Correction Mask */ +#define ADC_DSEQCTRL_OFFSETCORR(value) (ADC_DSEQCTRL_OFFSETCORR_Msk & (_UINT32_(value) << ADC_DSEQCTRL_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_AUTOSTART_Pos _UINT32_(31) /* (ADC_DSEQCTRL) ADC Auto-Start Conversion Position */ +#define ADC_DSEQCTRL_AUTOSTART_Msk (_UINT32_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) /* (ADC_DSEQCTRL) ADC Auto-Start Conversion Mask */ +#define ADC_DSEQCTRL_AUTOSTART(value) (ADC_DSEQCTRL_AUTOSTART_Msk & (_UINT32_(value) << ADC_DSEQCTRL_AUTOSTART_Pos)) /* Assigment of value for AUTOSTART in the ADC_DSEQCTRL register */ +#define ADC_DSEQCTRL_Msk _UINT32_(0x800001FF) /* (ADC_DSEQCTRL) Register Mask */ + + +/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) ( R/ 32) DMA Sequencial Status -------- */ +#define ADC_DSEQSTAT_RESETVALUE _UINT32_(0x00) /* (ADC_DSEQSTAT) DMA Sequencial Status Reset Value */ + +#define ADC_DSEQSTAT_INPUTCTRL_Pos _UINT32_(0) /* (ADC_DSEQSTAT) Input Control Position */ +#define ADC_DSEQSTAT_INPUTCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) /* (ADC_DSEQSTAT) Input Control Mask */ +#define ADC_DSEQSTAT_INPUTCTRL(value) (ADC_DSEQSTAT_INPUTCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_INPUTCTRL_Pos)) /* Assigment of value for INPUTCTRL in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_CTRLB_Pos _UINT32_(1) /* (ADC_DSEQSTAT) Control B Position */ +#define ADC_DSEQSTAT_CTRLB_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) /* (ADC_DSEQSTAT) Control B Mask */ +#define ADC_DSEQSTAT_CTRLB(value) (ADC_DSEQSTAT_CTRLB_Msk & (_UINT32_(value) << ADC_DSEQSTAT_CTRLB_Pos)) /* Assigment of value for CTRLB in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_REFCTRL_Pos _UINT32_(2) /* (ADC_DSEQSTAT) Reference Control Position */ +#define ADC_DSEQSTAT_REFCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) /* (ADC_DSEQSTAT) Reference Control Mask */ +#define ADC_DSEQSTAT_REFCTRL(value) (ADC_DSEQSTAT_REFCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_REFCTRL_Pos)) /* Assigment of value for REFCTRL in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_AVGCTRL_Pos _UINT32_(3) /* (ADC_DSEQSTAT) Average Control Position */ +#define ADC_DSEQSTAT_AVGCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) /* (ADC_DSEQSTAT) Average Control Mask */ +#define ADC_DSEQSTAT_AVGCTRL(value) (ADC_DSEQSTAT_AVGCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_AVGCTRL_Pos)) /* Assigment of value for AVGCTRL in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_SAMPCTRL_Pos _UINT32_(4) /* (ADC_DSEQSTAT) Sampling Time Control Position */ +#define ADC_DSEQSTAT_SAMPCTRL_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) /* (ADC_DSEQSTAT) Sampling Time Control Mask */ +#define ADC_DSEQSTAT_SAMPCTRL(value) (ADC_DSEQSTAT_SAMPCTRL_Msk & (_UINT32_(value) << ADC_DSEQSTAT_SAMPCTRL_Pos)) /* Assigment of value for SAMPCTRL in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_WINLT_Pos _UINT32_(5) /* (ADC_DSEQSTAT) Window Monitor Lower Threshold Position */ +#define ADC_DSEQSTAT_WINLT_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_WINLT_Pos) /* (ADC_DSEQSTAT) Window Monitor Lower Threshold Mask */ +#define ADC_DSEQSTAT_WINLT(value) (ADC_DSEQSTAT_WINLT_Msk & (_UINT32_(value) << ADC_DSEQSTAT_WINLT_Pos)) /* Assigment of value for WINLT in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_WINUT_Pos _UINT32_(6) /* (ADC_DSEQSTAT) Window Monitor Upper Threshold Position */ +#define ADC_DSEQSTAT_WINUT_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_WINUT_Pos) /* (ADC_DSEQSTAT) Window Monitor Upper Threshold Mask */ +#define ADC_DSEQSTAT_WINUT(value) (ADC_DSEQSTAT_WINUT_Msk & (_UINT32_(value) << ADC_DSEQSTAT_WINUT_Pos)) /* Assigment of value for WINUT in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_GAINCORR_Pos _UINT32_(7) /* (ADC_DSEQSTAT) Gain Correction Position */ +#define ADC_DSEQSTAT_GAINCORR_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) /* (ADC_DSEQSTAT) Gain Correction Mask */ +#define ADC_DSEQSTAT_GAINCORR(value) (ADC_DSEQSTAT_GAINCORR_Msk & (_UINT32_(value) << ADC_DSEQSTAT_GAINCORR_Pos)) /* Assigment of value for GAINCORR in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_OFFSETCORR_Pos _UINT32_(8) /* (ADC_DSEQSTAT) Offset Correction Position */ +#define ADC_DSEQSTAT_OFFSETCORR_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) /* (ADC_DSEQSTAT) Offset Correction Mask */ +#define ADC_DSEQSTAT_OFFSETCORR(value) (ADC_DSEQSTAT_OFFSETCORR_Msk & (_UINT32_(value) << ADC_DSEQSTAT_OFFSETCORR_Pos)) /* Assigment of value for OFFSETCORR in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_BUSY_Pos _UINT32_(31) /* (ADC_DSEQSTAT) DMA Sequencing Busy Position */ +#define ADC_DSEQSTAT_BUSY_Msk (_UINT32_(0x1) << ADC_DSEQSTAT_BUSY_Pos) /* (ADC_DSEQSTAT) DMA Sequencing Busy Mask */ +#define ADC_DSEQSTAT_BUSY(value) (ADC_DSEQSTAT_BUSY_Msk & (_UINT32_(value) << ADC_DSEQSTAT_BUSY_Pos)) /* Assigment of value for BUSY in the ADC_DSEQSTAT register */ +#define ADC_DSEQSTAT_Msk _UINT32_(0x800001FF) /* (ADC_DSEQSTAT) Register Mask */ + + +/* -------- ADC_RESULT : (ADC Offset: 0x40) ( R/ 16) Result Conversion Value -------- */ +#define ADC_RESULT_RESETVALUE _UINT16_(0x00) /* (ADC_RESULT) Result Conversion Value Reset Value */ + +#define ADC_RESULT_RESULT_Pos _UINT16_(0) /* (ADC_RESULT) Result Conversion Value Position */ +#define ADC_RESULT_RESULT_Msk (_UINT16_(0xFFFF) << ADC_RESULT_RESULT_Pos) /* (ADC_RESULT) Result Conversion Value Mask */ +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & (_UINT16_(value) << ADC_RESULT_RESULT_Pos)) /* Assigment of value for RESULT in the ADC_RESULT register */ +#define ADC_RESULT_Msk _UINT16_(0xFFFF) /* (ADC_RESULT) Register Mask */ + + +/* -------- ADC_RESS : (ADC Offset: 0x44) ( R/ 16) Last Sample Result -------- */ +#define ADC_RESS_RESETVALUE _UINT16_(0x00) /* (ADC_RESS) Last Sample Result Reset Value */ + +#define ADC_RESS_RESS_Pos _UINT16_(0) /* (ADC_RESS) Last ADC conversion result Position */ +#define ADC_RESS_RESS_Msk (_UINT16_(0xFFFF) << ADC_RESS_RESS_Pos) /* (ADC_RESS) Last ADC conversion result Mask */ +#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & (_UINT16_(value) << ADC_RESS_RESS_Pos)) /* Assigment of value for RESS in the ADC_RESS register */ +#define ADC_RESS_Msk _UINT16_(0xFFFF) /* (ADC_RESS) Register Mask */ + + +/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ +#define ADC_CALIB_RESETVALUE _UINT16_(0x00) /* (ADC_CALIB) Calibration Reset Value */ + +#define ADC_CALIB_BIASCOMP_Pos _UINT16_(0) /* (ADC_CALIB) Bias Comparator Scaling Position */ +#define ADC_CALIB_BIASCOMP_Msk (_UINT16_(0x7) << ADC_CALIB_BIASCOMP_Pos) /* (ADC_CALIB) Bias Comparator Scaling Mask */ +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & (_UINT16_(value) << ADC_CALIB_BIASCOMP_Pos)) /* Assigment of value for BIASCOMP in the ADC_CALIB register */ +#define ADC_CALIB_BIASR2R_Pos _UINT16_(4) /* (ADC_CALIB) Bias R2R Ampli scaling Position */ +#define ADC_CALIB_BIASR2R_Msk (_UINT16_(0x7) << ADC_CALIB_BIASR2R_Pos) /* (ADC_CALIB) Bias R2R Ampli scaling Mask */ +#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & (_UINT16_(value) << ADC_CALIB_BIASR2R_Pos)) /* Assigment of value for BIASR2R in the ADC_CALIB register */ +#define ADC_CALIB_BIASREFBUF_Pos _UINT16_(8) /* (ADC_CALIB) Bias Reference Buffer Scaling Position */ +#define ADC_CALIB_BIASREFBUF_Msk (_UINT16_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /* (ADC_CALIB) Bias Reference Buffer Scaling Mask */ +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & (_UINT16_(value) << ADC_CALIB_BIASREFBUF_Pos)) /* Assigment of value for BIASREFBUF in the ADC_CALIB register */ +#define ADC_CALIB_Msk _UINT16_(0x0777) /* (ADC_CALIB) Register Mask */ + + +/** \brief ADC register offsets definitions */ +#define ADC_CTRLA_REG_OFST _UINT32_(0x00) /* (ADC_CTRLA) Control A Offset */ +#define ADC_EVCTRL_REG_OFST _UINT32_(0x02) /* (ADC_EVCTRL) Event Control Offset */ +#define ADC_DBGCTRL_REG_OFST _UINT32_(0x03) /* (ADC_DBGCTRL) Debug Control Offset */ +#define ADC_INPUTCTRL_REG_OFST _UINT32_(0x04) /* (ADC_INPUTCTRL) Input Control Offset */ +#define ADC_CTRLB_REG_OFST _UINT32_(0x06) /* (ADC_CTRLB) Control B Offset */ +#define ADC_REFCTRL_REG_OFST _UINT32_(0x08) /* (ADC_REFCTRL) Reference Control Offset */ +#define ADC_AVGCTRL_REG_OFST _UINT32_(0x0A) /* (ADC_AVGCTRL) Average Control Offset */ +#define ADC_SAMPCTRL_REG_OFST _UINT32_(0x0B) /* (ADC_SAMPCTRL) Sample Time Control Offset */ +#define ADC_WINLT_REG_OFST _UINT32_(0x0C) /* (ADC_WINLT) Window Monitor Lower Threshold Offset */ +#define ADC_WINUT_REG_OFST _UINT32_(0x0E) /* (ADC_WINUT) Window Monitor Upper Threshold Offset */ +#define ADC_GAINCORR_REG_OFST _UINT32_(0x10) /* (ADC_GAINCORR) Gain Correction Offset */ +#define ADC_OFFSETCORR_REG_OFST _UINT32_(0x12) /* (ADC_OFFSETCORR) Offset Correction Offset */ +#define ADC_SWTRIG_REG_OFST _UINT32_(0x14) /* (ADC_SWTRIG) Software Trigger Offset */ +#define ADC_INTENCLR_REG_OFST _UINT32_(0x2C) /* (ADC_INTENCLR) Interrupt Enable Clear Offset */ +#define ADC_INTENSET_REG_OFST _UINT32_(0x2D) /* (ADC_INTENSET) Interrupt Enable Set Offset */ +#define ADC_INTFLAG_REG_OFST _UINT32_(0x2E) /* (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define ADC_STATUS_REG_OFST _UINT32_(0x2F) /* (ADC_STATUS) Status Offset */ +#define ADC_SYNCBUSY_REG_OFST _UINT32_(0x30) /* (ADC_SYNCBUSY) Synchronization Busy Offset */ +#define ADC_DSEQDATA_REG_OFST _UINT32_(0x34) /* (ADC_DSEQDATA) DMA Sequencial Data Offset */ +#define ADC_DSEQCTRL_REG_OFST _UINT32_(0x38) /* (ADC_DSEQCTRL) DMA Sequential Control Offset */ +#define ADC_DSEQSTAT_REG_OFST _UINT32_(0x3C) /* (ADC_DSEQSTAT) DMA Sequencial Status Offset */ +#define ADC_RESULT_REG_OFST _UINT32_(0x40) /* (ADC_RESULT) Result Conversion Value Offset */ +#define ADC_RESS_REG_OFST _UINT32_(0x44) /* (ADC_RESS) Last Sample Result Offset */ +#define ADC_CALIB_REG_OFST _UINT32_(0x48) /* (ADC_CALIB) Calibration Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ADC register API structure */ +typedef struct +{ /* Analog Digital Converter */ + __IO uint16_t ADC_CTRLA; /**< Offset: 0x00 (R/W 16) Control A */ + __IO uint8_t ADC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ + __IO uint8_t ADC_DBGCTRL; /**< Offset: 0x03 (R/W 8) Debug Control */ + __IO uint16_t ADC_INPUTCTRL; /**< Offset: 0x04 (R/W 16) Input Control */ + __IO uint16_t ADC_CTRLB; /**< Offset: 0x06 (R/W 16) Control B */ + __IO uint8_t ADC_REFCTRL; /**< Offset: 0x08 (R/W 8) Reference Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t ADC_AVGCTRL; /**< Offset: 0x0A (R/W 8) Average Control */ + __IO uint8_t ADC_SAMPCTRL; /**< Offset: 0x0B (R/W 8) Sample Time Control */ + __IO uint16_t ADC_WINLT; /**< Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ + __IO uint16_t ADC_WINUT; /**< Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ + __IO uint16_t ADC_GAINCORR; /**< Offset: 0x10 (R/W 16) Gain Correction */ + __IO uint16_t ADC_OFFSETCORR; /**< Offset: 0x12 (R/W 16) Offset Correction */ + __IO uint8_t ADC_SWTRIG; /**< Offset: 0x14 (R/W 8) Software Trigger */ + __I uint8_t Reserved2[0x17]; + __IO uint8_t ADC_INTENCLR; /**< Offset: 0x2C (R/W 8) Interrupt Enable Clear */ + __IO uint8_t ADC_INTENSET; /**< Offset: 0x2D (R/W 8) Interrupt Enable Set */ + __IO uint8_t ADC_INTFLAG; /**< Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t ADC_STATUS; /**< Offset: 0x2F (R/ 8) Status */ + __I uint32_t ADC_SYNCBUSY; /**< Offset: 0x30 (R/ 32) Synchronization Busy */ + __O uint32_t ADC_DSEQDATA; /**< Offset: 0x34 ( /W 32) DMA Sequencial Data */ + __IO uint32_t ADC_DSEQCTRL; /**< Offset: 0x38 (R/W 32) DMA Sequential Control */ + __I uint32_t ADC_DSEQSTAT; /**< Offset: 0x3C (R/ 32) DMA Sequencial Status */ + __I uint16_t ADC_RESULT; /**< Offset: 0x40 (R/ 16) Result Conversion Value */ + __I uint8_t Reserved3[0x02]; + __I uint16_t ADC_RESS; /**< Offset: 0x44 (R/ 16) Last Sample Result */ + __I uint8_t Reserved4[0x02]; + __IO uint16_t ADC_CALIB; /**< Offset: 0x48 (R/W 16) Calibration */ +} adc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_ADC_COMPONENT_H_ */ diff --git a/os/common/ext/Microchip/SAME54/component/aes.h b/os/common/ext/Microchip/SAME54/component/aes.h new file mode 100644 index 0000000000..f97afdd5da --- /dev/null +++ b/os/common/ext/Microchip/SAME54/component/aes.h @@ -0,0 +1,314 @@ +/* + * Component description for AES + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:08Z */ +#ifndef _SAME54_AES_COMPONENT_H_ +#define _SAME54_AES_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AES */ +/* ************************************************************************** */ + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#define AES_CTRLA_RESETVALUE _UINT32_(0x00) /* (AES_CTRLA) Control A Reset Value */ + +#define AES_CTRLA_SWRST_Pos _UINT32_(0) /* (AES_CTRLA) Software Reset Position */ +#define AES_CTRLA_SWRST_Msk (_UINT32_(0x1) << AES_CTRLA_SWRST_Pos) /* (AES_CTRLA) Software Reset Mask */ +#define AES_CTRLA_SWRST(value) (AES_CTRLA_SWRST_Msk & (_UINT32_(value) << AES_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the AES_CTRLA register */ +#define AES_CTRLA_ENABLE_Pos _UINT32_(1) /* (AES_CTRLA) Enable Position */ +#define AES_CTRLA_ENABLE_Msk (_UINT32_(0x1) << AES_CTRLA_ENABLE_Pos) /* (AES_CTRLA) Enable Mask */ +#define AES_CTRLA_ENABLE(value) (AES_CTRLA_ENABLE_Msk & (_UINT32_(value) << AES_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the AES_CTRLA register */ +#define AES_CTRLA_AESMODE_Pos _UINT32_(2) /* (AES_CTRLA) AES Modes of operation Position */ +#define AES_CTRLA_AESMODE_Msk (_UINT32_(0x7) << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) AES Modes of operation Mask */ +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & (_UINT32_(value) << AES_CTRLA_AESMODE_Pos)) /* Assigment of value for AESMODE in the AES_CTRLA register */ +#define AES_CTRLA_AESMODE_ECB_Val _UINT32_(0x0) /* (AES_CTRLA) Electronic code book mode */ +#define AES_CTRLA_AESMODE_CBC_Val _UINT32_(0x1) /* (AES_CTRLA) Cipher block chaining mode */ +#define AES_CTRLA_AESMODE_OFB_Val _UINT32_(0x2) /* (AES_CTRLA) Output feedback mode */ +#define AES_CTRLA_AESMODE_CFB_Val _UINT32_(0x3) /* (AES_CTRLA) Cipher feedback mode */ +#define AES_CTRLA_AESMODE_COUNTER_Val _UINT32_(0x4) /* (AES_CTRLA) Counter mode */ +#define AES_CTRLA_AESMODE_CCM_Val _UINT32_(0x5) /* (AES_CTRLA) CCM mode */ +#define AES_CTRLA_AESMODE_GCM_Val _UINT32_(0x6) /* (AES_CTRLA) Galois counter mode */ +#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Electronic code book mode Position */ +#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Cipher block chaining mode Position */ +#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Output feedback mode Position */ +#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Cipher feedback mode Position */ +#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Counter mode Position */ +#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) CCM mode Position */ +#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) /* (AES_CTRLA) Galois counter mode Position */ +#define AES_CTRLA_CFBS_Pos _UINT32_(5) /* (AES_CTRLA) Cipher Feedback Block Size Position */ +#define AES_CTRLA_CFBS_Msk (_UINT32_(0x7) << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) Cipher Feedback Block Size Mask */ +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & (_UINT32_(value) << AES_CTRLA_CFBS_Pos)) /* Assigment of value for CFBS in the AES_CTRLA register */ +#define AES_CTRLA_CFBS_128BIT_Val _UINT32_(0x0) /* (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_64BIT_Val _UINT32_(0x1) /* (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_32BIT_Val _UINT32_(0x2) /* (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_16BIT_Val _UINT32_(0x3) /* (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_8BIT_Val _UINT32_(0x4) /* (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) /* (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ +#define AES_CTRLA_KEYSIZE_Pos _UINT32_(8) /* (AES_CTRLA) Encryption Key Size Position */ +#define AES_CTRLA_KEYSIZE_Msk (_UINT32_(0x3) << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) Encryption Key Size Mask */ +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & (_UINT32_(value) << AES_CTRLA_KEYSIZE_Pos)) /* Assigment of value for KEYSIZE in the AES_CTRLA register */ +#define AES_CTRLA_KEYSIZE_128BIT_Val _UINT32_(0x0) /* (AES_CTRLA) 128-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_192BIT_Val _UINT32_(0x1) /* (AES_CTRLA) 192-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_256BIT_Val _UINT32_(0x2) /* (AES_CTRLA) 256-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) 128-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) 192-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) /* (AES_CTRLA) 256-bit Key for Encryption / Decryption Position */ +#define AES_CTRLA_CIPHER_Pos _UINT32_(10) /* (AES_CTRLA) Cipher Mode Position */ +#define AES_CTRLA_CIPHER_Msk (_UINT32_(0x1) << AES_CTRLA_CIPHER_Pos) /* (AES_CTRLA) Cipher Mode Mask */ +#define AES_CTRLA_CIPHER(value) (AES_CTRLA_CIPHER_Msk & (_UINT32_(value) << AES_CTRLA_CIPHER_Pos)) /* Assigment of value for CIPHER in the AES_CTRLA register */ +#define AES_CTRLA_CIPHER_DEC_Val _UINT32_(0x0) /* (AES_CTRLA) Decryption */ +#define AES_CTRLA_CIPHER_ENC_Val _UINT32_(0x1) /* (AES_CTRLA) Encryption */ +#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) /* (AES_CTRLA) Decryption Position */ +#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) /* (AES_CTRLA) Encryption Position */ +#define AES_CTRLA_STARTMODE_Pos _UINT32_(11) /* (AES_CTRLA) Start Mode Select Position */ +#define AES_CTRLA_STARTMODE_Msk (_UINT32_(0x1) << AES_CTRLA_STARTMODE_Pos) /* (AES_CTRLA) Start Mode Select Mask */ +#define AES_CTRLA_STARTMODE(value) (AES_CTRLA_STARTMODE_Msk & (_UINT32_(value) << AES_CTRLA_STARTMODE_Pos)) /* Assigment of value for STARTMODE in the AES_CTRLA register */ +#define AES_CTRLA_STARTMODE_MANUAL_Val _UINT32_(0x0) /* (AES_CTRLA) Start Encryption / Decryption in Manual mode */ +#define AES_CTRLA_STARTMODE_AUTO_Val _UINT32_(0x1) /* (AES_CTRLA) Start Encryption / Decryption in Auto mode */ +#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) /* (AES_CTRLA) Start Encryption / Decryption in Manual mode Position */ +#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) /* (AES_CTRLA) Start Encryption / Decryption in Auto mode Position */ +#define AES_CTRLA_LOD_Pos _UINT32_(12) /* (AES_CTRLA) Last Output Data Mode Position */ +#define AES_CTRLA_LOD_Msk (_UINT32_(0x1) << AES_CTRLA_LOD_Pos) /* (AES_CTRLA) Last Output Data Mode Mask */ +#define AES_CTRLA_LOD(value) (AES_CTRLA_LOD_Msk & (_UINT32_(value) << AES_CTRLA_LOD_Pos)) /* Assigment of value for LOD in the AES_CTRLA register */ +#define AES_CTRLA_LOD_NONE_Val _UINT32_(0x0) /* (AES_CTRLA) No effect */ +#define AES_CTRLA_LOD_LAST_Val _UINT32_(0x1) /* (AES_CTRLA) Start encryption in Last Output Data mode */ +#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) /* (AES_CTRLA) No effect Position */ +#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) /* (AES_CTRLA) Start encryption in Last Output Data mode Position */ +#define AES_CTRLA_KEYGEN_Pos _UINT32_(13) /* (AES_CTRLA) Last Key Generation Position */ +#define AES_CTRLA_KEYGEN_Msk (_UINT32_(0x1) << AES_CTRLA_KEYGEN_Pos) /* (AES_CTRLA) Last Key Generation Mask */ +#define AES_CTRLA_KEYGEN(value) (AES_CTRLA_KEYGEN_Msk & (_UINT32_(value) << AES_CTRLA_KEYGEN_Pos)) /* Assigment of value for KEYGEN in the AES_CTRLA register */ +#define AES_CTRLA_KEYGEN_NONE_Val _UINT32_(0x0) /* (AES_CTRLA) No effect */ +#define AES_CTRLA_KEYGEN_LAST_Val _UINT32_(0x1) /* (AES_CTRLA) Start Computation of the last NK words of the expanded key */ +#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) /* (AES_CTRLA) No effect Position */ +#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) /* (AES_CTRLA) Start Computation of the last NK words of the expanded key Position */ +#define AES_CTRLA_XORKEY_Pos _UINT32_(14) /* (AES_CTRLA) XOR Key Operation Position */ +#define AES_CTRLA_XORKEY_Msk (_UINT32_(0x1) << AES_CTRLA_XORKEY_Pos) /* (AES_CTRLA) XOR Key Operation Mask */ +#define AES_CTRLA_XORKEY(value) (AES_CTRLA_XORKEY_Msk & (_UINT32_(value) << AES_CTRLA_XORKEY_Pos)) /* Assigment of value for XORKEY in the AES_CTRLA register */ +#define AES_CTRLA_XORKEY_NONE_Val _UINT32_(0x0) /* (AES_CTRLA) No effect */ +#define AES_CTRLA_XORKEY_XOR_Val _UINT32_(0x1) /* (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ +#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) /* (AES_CTRLA) No effect Position */ +#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) /* (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. Position */ +#define AES_CTRLA_CTYPE_Pos _UINT32_(16) /* (AES_CTRLA) Counter Measure Type Position */ +#define AES_CTRLA_CTYPE_Msk (_UINT32_(0xF) << AES_CTRLA_CTYPE_Pos) /* (AES_CTRLA) Counter Measure Type Mask */ +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & (_UINT32_(value) << AES_CTRLA_CTYPE_Pos)) /* Assigment of value for CTYPE in the AES_CTRLA register */ +#define AES_CTRLA_Msk _UINT32_(0x000F7FFF) /* (AES_CTRLA) Register Mask */ + + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#define AES_CTRLB_RESETVALUE _UINT8_(0x00) /* (AES_CTRLB) Control B Reset Value */ + +#define AES_CTRLB_START_Pos _UINT8_(0) /* (AES_CTRLB) Start Encryption/Decryption Position */ +#define AES_CTRLB_START_Msk (_UINT8_(0x1) << AES_CTRLB_START_Pos) /* (AES_CTRLB) Start Encryption/Decryption Mask */ +#define AES_CTRLB_START(value) (AES_CTRLB_START_Msk & (_UINT8_(value) << AES_CTRLB_START_Pos)) /* Assigment of value for START in the AES_CTRLB register */ +#define AES_CTRLB_NEWMSG_Pos _UINT8_(1) /* (AES_CTRLB) New message Position */ +#define AES_CTRLB_NEWMSG_Msk (_UINT8_(0x1) << AES_CTRLB_NEWMSG_Pos) /* (AES_CTRLB) New message Mask */ +#define AES_CTRLB_NEWMSG(value) (AES_CTRLB_NEWMSG_Msk & (_UINT8_(value) << AES_CTRLB_NEWMSG_Pos)) /* Assigment of value for NEWMSG in the AES_CTRLB register */ +#define AES_CTRLB_EOM_Pos _UINT8_(2) /* (AES_CTRLB) End of message Position */ +#define AES_CTRLB_EOM_Msk (_UINT8_(0x1) << AES_CTRLB_EOM_Pos) /* (AES_CTRLB) End of message Mask */ +#define AES_CTRLB_EOM(value) (AES_CTRLB_EOM_Msk & (_UINT8_(value) << AES_CTRLB_EOM_Pos)) /* Assigment of value for EOM in the AES_CTRLB register */ +#define AES_CTRLB_GFMUL_Pos _UINT8_(3) /* (AES_CTRLB) GF Multiplication Position */ +#define AES_CTRLB_GFMUL_Msk (_UINT8_(0x1) << AES_CTRLB_GFMUL_Pos) /* (AES_CTRLB) GF Multiplication Mask */ +#define AES_CTRLB_GFMUL(value) (AES_CTRLB_GFMUL_Msk & (_UINT8_(value) << AES_CTRLB_GFMUL_Pos)) /* Assigment of value for GFMUL in the AES_CTRLB register */ +#define AES_CTRLB_Msk _UINT8_(0x0F) /* (AES_CTRLB) Register Mask */ + + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#define AES_INTENCLR_RESETVALUE _UINT8_(0x00) /* (AES_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define AES_INTENCLR_ENCCMP_Pos _UINT8_(0) /* (AES_INTENCLR) Encryption Complete Interrupt Enable Position */ +#define AES_INTENCLR_ENCCMP_Msk (_UINT8_(0x1) << AES_INTENCLR_ENCCMP_Pos) /* (AES_INTENCLR) Encryption Complete Interrupt Enable Mask */ +#define AES_INTENCLR_ENCCMP(value) (AES_INTENCLR_ENCCMP_Msk & (_UINT8_(value) << AES_INTENCLR_ENCCMP_Pos)) /* Assigment of value for ENCCMP in the AES_INTENCLR register */ +#define AES_INTENCLR_GFMCMP_Pos _UINT8_(1) /* (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Position */ +#define AES_INTENCLR_GFMCMP_Msk (_UINT8_(0x1) << AES_INTENCLR_GFMCMP_Pos) /* (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Mask */ +#define AES_INTENCLR_GFMCMP(value) (AES_INTENCLR_GFMCMP_Msk & (_UINT8_(value) << AES_INTENCLR_GFMCMP_Pos)) /* Assigment of value for GFMCMP in the AES_INTENCLR register */ +#define AES_INTENCLR_Msk _UINT8_(0x03) /* (AES_INTENCLR) Register Mask */ + + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#define AES_INTENSET_RESETVALUE _UINT8_(0x00) /* (AES_INTENSET) Interrupt Enable Set Reset Value */ + +#define AES_INTENSET_ENCCMP_Pos _UINT8_(0) /* (AES_INTENSET) Encryption Complete Interrupt Enable Position */ +#define AES_INTENSET_ENCCMP_Msk (_UINT8_(0x1) << AES_INTENSET_ENCCMP_Pos) /* (AES_INTENSET) Encryption Complete Interrupt Enable Mask */ +#define AES_INTENSET_ENCCMP(value) (AES_INTENSET_ENCCMP_Msk & (_UINT8_(value) << AES_INTENSET_ENCCMP_Pos)) /* Assigment of value for ENCCMP in the AES_INTENSET register */ +#define AES_INTENSET_GFMCMP_Pos _UINT8_(1) /* (AES_INTENSET) GF Multiplication Complete Interrupt Enable Position */ +#define AES_INTENSET_GFMCMP_Msk (_UINT8_(0x1) << AES_INTENSET_GFMCMP_Pos) /* (AES_INTENSET) GF Multiplication Complete Interrupt Enable Mask */ +#define AES_INTENSET_GFMCMP(value) (AES_INTENSET_GFMCMP_Msk & (_UINT8_(value) << AES_INTENSET_GFMCMP_Pos)) /* Assigment of value for GFMCMP in the AES_INTENSET register */ +#define AES_INTENSET_Msk _UINT8_(0x03) /* (AES_INTENSET) Register Mask */ + + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#define AES_INTFLAG_RESETVALUE _UINT8_(0x00) /* (AES_INTFLAG) Interrupt Flag Status Reset Value */ + +#define AES_INTFLAG_ENCCMP_Pos _UINT8_(0) /* (AES_INTFLAG) Encryption Complete Position */ +#define AES_INTFLAG_ENCCMP_Msk (_UINT8_(0x1) << AES_INTFLAG_ENCCMP_Pos) /* (AES_INTFLAG) Encryption Complete Mask */ +#define AES_INTFLAG_ENCCMP(value) (AES_INTFLAG_ENCCMP_Msk & (_UINT8_(value) << AES_INTFLAG_ENCCMP_Pos)) /* Assigment of value for ENCCMP in the AES_INTFLAG register */ +#define AES_INTFLAG_GFMCMP_Pos _UINT8_(1) /* (AES_INTFLAG) GF Multiplication Complete Position */ +#define AES_INTFLAG_GFMCMP_Msk (_UINT8_(0x1) << AES_INTFLAG_GFMCMP_Pos) /* (AES_INTFLAG) GF Multiplication Complete Mask */ +#define AES_INTFLAG_GFMCMP(value) (AES_INTFLAG_GFMCMP_Msk & (_UINT8_(value) << AES_INTFLAG_GFMCMP_Pos)) /* Assigment of value for GFMCMP in the AES_INTFLAG register */ +#define AES_INTFLAG_Msk _UINT8_(0x03) /* (AES_INTFLAG) Register Mask */ + + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#define AES_DATABUFPTR_RESETVALUE _UINT8_(0x00) /* (AES_DATABUFPTR) Data buffer pointer Reset Value */ + +#define AES_DATABUFPTR_INDATAPTR_Pos _UINT8_(0) /* (AES_DATABUFPTR) Input Data Pointer Position */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_UINT8_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) /* (AES_DATABUFPTR) Input Data Pointer Mask */ +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & (_UINT8_(value) << AES_DATABUFPTR_INDATAPTR_Pos)) /* Assigment of value for INDATAPTR in the AES_DATABUFPTR register */ +#define AES_DATABUFPTR_Msk _UINT8_(0x03) /* (AES_DATABUFPTR) Register Mask */ + + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ +#define AES_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (AES_DBGCTRL) Debug control Reset Value */ + +#define AES_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (AES_DBGCTRL) Debug Run Position */ +#define AES_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << AES_DBGCTRL_DBGRUN_Pos) /* (AES_DBGCTRL) Debug Run Mask */ +#define AES_DBGCTRL_DBGRUN(value) (AES_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << AES_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the AES_DBGCTRL register */ +#define AES_DBGCTRL_Msk _UINT8_(0x01) /* (AES_DBGCTRL) Register Mask */ + + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#define AES_KEYWORD_RESETVALUE _UINT32_(0x00) /* (AES_KEYWORD) Keyword n Reset Value */ + +#define AES_KEYWORD_KEYWORD_Pos _UINT32_(0) /* (AES_KEYWORD) Key Word Value Position */ +#define AES_KEYWORD_KEYWORD_Msk (_UINT32_(0xFFFFFFFF) << AES_KEYWORD_KEYWORD_Pos) /* (AES_KEYWORD) Key Word Value Mask */ +#define AES_KEYWORD_KEYWORD(value) (AES_KEYWORD_KEYWORD_Msk & (_UINT32_(value) << AES_KEYWORD_KEYWORD_Pos)) /* Assigment of value for KEYWORD in the AES_KEYWORD register */ +#define AES_KEYWORD_Msk _UINT32_(0xFFFFFFFF) /* (AES_KEYWORD) Register Mask */ + + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#define AES_INDATA_RESETVALUE _UINT32_(0x00) /* (AES_INDATA) Indata Reset Value */ + +#define AES_INDATA_INDATA_Pos _UINT32_(0) /* (AES_INDATA) Data Value Position */ +#define AES_INDATA_INDATA_Msk (_UINT32_(0xFFFFFFFF) << AES_INDATA_INDATA_Pos) /* (AES_INDATA) Data Value Mask */ +#define AES_INDATA_INDATA(value) (AES_INDATA_INDATA_Msk & (_UINT32_(value) << AES_INDATA_INDATA_Pos)) /* Assigment of value for INDATA in the AES_INDATA register */ +#define AES_INDATA_Msk _UINT32_(0xFFFFFFFF) /* (AES_INDATA) Register Mask */ + + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#define AES_INTVECTV_RESETVALUE _UINT32_(0x00) /* (AES_INTVECTV) Initialisation Vector n Reset Value */ + +#define AES_INTVECTV_INTVECTV_Pos _UINT32_(0) /* (AES_INTVECTV) Initialization Vector Value Position */ +#define AES_INTVECTV_INTVECTV_Msk (_UINT32_(0xFFFFFFFF) << AES_INTVECTV_INTVECTV_Pos) /* (AES_INTVECTV) Initialization Vector Value Mask */ +#define AES_INTVECTV_INTVECTV(value) (AES_INTVECTV_INTVECTV_Msk & (_UINT32_(value) << AES_INTVECTV_INTVECTV_Pos)) /* Assigment of value for INTVECTV in the AES_INTVECTV register */ +#define AES_INTVECTV_Msk _UINT32_(0xFFFFFFFF) /* (AES_INTVECTV) Register Mask */ + + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#define AES_HASHKEY_RESETVALUE _UINT32_(0x00) /* (AES_HASHKEY) Hash key n Reset Value */ + +#define AES_HASHKEY_HASHKEY_Pos _UINT32_(0) /* (AES_HASHKEY) Hash Key Value Position */ +#define AES_HASHKEY_HASHKEY_Msk (_UINT32_(0xFFFFFFFF) << AES_HASHKEY_HASHKEY_Pos) /* (AES_HASHKEY) Hash Key Value Mask */ +#define AES_HASHKEY_HASHKEY(value) (AES_HASHKEY_HASHKEY_Msk & (_UINT32_(value) << AES_HASHKEY_HASHKEY_Pos)) /* Assigment of value for HASHKEY in the AES_HASHKEY register */ +#define AES_HASHKEY_Msk _UINT32_(0xFFFFFFFF) /* (AES_HASHKEY) Register Mask */ + + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#define AES_GHASH_RESETVALUE _UINT32_(0x00) /* (AES_GHASH) Galois Hash n Reset Value */ + +#define AES_GHASH_GHASH_Pos _UINT32_(0) /* (AES_GHASH) Galois Hash Value Position */ +#define AES_GHASH_GHASH_Msk (_UINT32_(0xFFFFFFFF) << AES_GHASH_GHASH_Pos) /* (AES_GHASH) Galois Hash Value Mask */ +#define AES_GHASH_GHASH(value) (AES_GHASH_GHASH_Msk & (_UINT32_(value) << AES_GHASH_GHASH_Pos)) /* Assigment of value for GHASH in the AES_GHASH register */ +#define AES_GHASH_Msk _UINT32_(0xFFFFFFFF) /* (AES_GHASH) Register Mask */ + + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#define AES_CIPLEN_RESETVALUE _UINT32_(0x00) /* (AES_CIPLEN) Cipher Length Reset Value */ + +#define AES_CIPLEN_CIPLEN_Pos _UINT32_(0) /* (AES_CIPLEN) Cipher Length Position */ +#define AES_CIPLEN_CIPLEN_Msk (_UINT32_(0xFFFFFFFF) << AES_CIPLEN_CIPLEN_Pos) /* (AES_CIPLEN) Cipher Length Mask */ +#define AES_CIPLEN_CIPLEN(value) (AES_CIPLEN_CIPLEN_Msk & (_UINT32_(value) << AES_CIPLEN_CIPLEN_Pos)) /* Assigment of value for CIPLEN in the AES_CIPLEN register */ +#define AES_CIPLEN_Msk _UINT32_(0xFFFFFFFF) /* (AES_CIPLEN) Register Mask */ + + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#define AES_RANDSEED_RESETVALUE _UINT32_(0x00) /* (AES_RANDSEED) Random Seed Reset Value */ + +#define AES_RANDSEED_RANDSEED_Pos _UINT32_(0) /* (AES_RANDSEED) Random Seed Position */ +#define AES_RANDSEED_RANDSEED_Msk (_UINT32_(0xFFFFFFFF) << AES_RANDSEED_RANDSEED_Pos) /* (AES_RANDSEED) Random Seed Mask */ +#define AES_RANDSEED_RANDSEED(value) (AES_RANDSEED_RANDSEED_Msk & (_UINT32_(value) << AES_RANDSEED_RANDSEED_Pos)) /* Assigment of value for RANDSEED in the AES_RANDSEED register */ +#define AES_RANDSEED_Msk _UINT32_(0xFFFFFFFF) /* (AES_RANDSEED) Register Mask */ + + +/** \brief AES register offsets definitions */ +#define AES_CTRLA_REG_OFST _UINT32_(0x00) /* (AES_CTRLA) Control A Offset */ +#define AES_CTRLB_REG_OFST _UINT32_(0x04) /* (AES_CTRLB) Control B Offset */ +#define AES_INTENCLR_REG_OFST _UINT32_(0x05) /* (AES_INTENCLR) Interrupt Enable Clear Offset */ +#define AES_INTENSET_REG_OFST _UINT32_(0x06) /* (AES_INTENSET) Interrupt Enable Set Offset */ +#define AES_INTFLAG_REG_OFST _UINT32_(0x07) /* (AES_INTFLAG) Interrupt Flag Status Offset */ +#define AES_DATABUFPTR_REG_OFST _UINT32_(0x08) /* (AES_DATABUFPTR) Data buffer pointer Offset */ +#define AES_DBGCTRL_REG_OFST _UINT32_(0x09) /* (AES_DBGCTRL) Debug control Offset */ +#define AES_KEYWORD_REG_OFST _UINT32_(0x0C) /* (AES_KEYWORD) Keyword n Offset */ +#define AES_KEYWORD0_REG_OFST _UINT32_(0x0C) /* (AES_KEYWORD0) Keyword n Offset */ +#define AES_KEYWORD1_REG_OFST _UINT32_(0x10) /* (AES_KEYWORD1) Keyword n Offset */ +#define AES_KEYWORD2_REG_OFST _UINT32_(0x14) /* (AES_KEYWORD2) Keyword n Offset */ +#define AES_KEYWORD3_REG_OFST _UINT32_(0x18) /* (AES_KEYWORD3) Keyword n Offset */ +#define AES_KEYWORD4_REG_OFST _UINT32_(0x1C) /* (AES_KEYWORD4) Keyword n Offset */ +#define AES_KEYWORD5_REG_OFST _UINT32_(0x20) /* (AES_KEYWORD5) Keyword n Offset */ +#define AES_KEYWORD6_REG_OFST _UINT32_(0x24) /* (AES_KEYWORD6) Keyword n Offset */ +#define AES_KEYWORD7_REG_OFST _UINT32_(0x28) /* (AES_KEYWORD7) Keyword n Offset */ +#define AES_INDATA_REG_OFST _UINT32_(0x38) /* (AES_INDATA) Indata Offset */ +#define AES_INTVECTV_REG_OFST _UINT32_(0x3C) /* (AES_INTVECTV) Initialisation Vector n Offset */ +#define AES_INTVECTV0_REG_OFST _UINT32_(0x3C) /* (AES_INTVECTV0) Initialisation Vector n Offset */ +#define AES_INTVECTV1_REG_OFST _UINT32_(0x40) /* (AES_INTVECTV1) Initialisation Vector n Offset */ +#define AES_INTVECTV2_REG_OFST _UINT32_(0x44) /* (AES_INTVECTV2) Initialisation Vector n Offset */ +#define AES_INTVECTV3_REG_OFST _UINT32_(0x48) /* (AES_INTVECTV3) Initialisation Vector n Offset */ +#define AES_HASHKEY_REG_OFST _UINT32_(0x5C) /* (AES_HASHKEY) Hash key n Offset */ +#define AES_HASHKEY0_REG_OFST _UINT32_(0x5C) /* (AES_HASHKEY0) Hash key n Offset */ +#define AES_HASHKEY1_REG_OFST _UINT32_(0x60) /* (AES_HASHKEY1) Hash key n Offset */ +#define AES_HASHKEY2_REG_OFST _UINT32_(0x64) /* (AES_HASHKEY2) Hash key n Offset */ +#define AES_HASHKEY3_REG_OFST _UINT32_(0x68) /* (AES_HASHKEY3) Hash key n Offset */ +#define AES_GHASH_REG_OFST _UINT32_(0x6C) /* (AES_GHASH) Galois Hash n Offset */ +#define AES_GHASH0_REG_OFST _UINT32_(0x6C) /* (AES_GHASH0) Galois Hash n Offset */ +#define AES_GHASH1_REG_OFST _UINT32_(0x70) /* (AES_GHASH1) Galois Hash n Offset */ +#define AES_GHASH2_REG_OFST _UINT32_(0x74) /* (AES_GHASH2) Galois Hash n Offset */ +#define AES_GHASH3_REG_OFST _UINT32_(0x78) /* (AES_GHASH3) Galois Hash n Offset */ +#define AES_CIPLEN_REG_OFST _UINT32_(0x80) /* (AES_CIPLEN) Cipher Length Offset */ +#define AES_RANDSEED_REG_OFST _UINT32_(0x84) /* (AES_RANDSEED) Random Seed Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AES register API structure */ +typedef struct +{ /* Advanced Encryption Standard */ + __IO uint32_t AES_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */ + __IO uint8_t AES_CTRLB; /**< Offset: 0x04 (R/W 8) Control B */ + __IO uint8_t AES_INTENCLR; /**< Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t AES_INTENSET; /**< Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO uint8_t AES_INTFLAG; /**< Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO uint8_t AES_DATABUFPTR; /**< Offset: 0x08 (R/W 8) Data buffer pointer */ + __IO uint8_t AES_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug control */ + __I uint8_t Reserved1[0x02]; + __O uint32_t AES_KEYWORD[8]; /**< Offset: 0x0C ( /W 32) Keyword n */ + __I uint8_t Reserved2[0x0C]; + __IO uint32_t AES_INDATA; /**< Offset: 0x38 (R/W 32) Indata */ + __O uint32_t AES_INTVECTV[4]; /**< Offset: 0x3C ( /W 32) Initialisation Vector n */ + __I uint8_t Reserved3[0x10]; + __IO uint32_t AES_HASHKEY[4]; /**< Offset: 0x5C (R/W 32) Hash key n */ + __IO uint32_t AES_GHASH[4]; /**< Offset: 0x6C (R/W 32) Galois Hash n */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t AES_CIPLEN; /**< Offset: 0x80 (R/W 32) Cipher Length */ + __IO uint32_t AES_RANDSEED; /**< Offset: 0x84 (R/W 32) Random Seed */ +} aes_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_AES_COMPONENT_H_ */ diff --git a/os/common/ext/Microchip/SAME54/component/can.h b/os/common/ext/Microchip/SAME54/component/can.h new file mode 100644 index 0000000000..851e0716f7 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/component/can.h @@ -0,0 +1,2519 @@ +/* + * Component description for CAN + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:08Z */ +#ifndef _SAME54_CAN_COMPONENT_H_ +#define _SAME54_CAN_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CAN */ +/* ************************************************************************** */ + +/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#define CAN_RXBE_0_ID_Pos _UINT32_(0) /* (CAN_RXBE_0) Identifier Position */ +#define CAN_RXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) /* (CAN_RXBE_0) Identifier Mask */ +#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & (_UINT32_(value) << CAN_RXBE_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_RTR_Pos _UINT32_(29) /* (CAN_RXBE_0) Remote Transmission Request Position */ +#define CAN_RXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_RXBE_0_RTR_Pos) /* (CAN_RXBE_0) Remote Transmission Request Mask */ +#define CAN_RXBE_0_RTR(value) (CAN_RXBE_0_RTR_Msk & (_UINT32_(value) << CAN_RXBE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_XTD_Pos _UINT32_(30) /* (CAN_RXBE_0) Extended Identifier Position */ +#define CAN_RXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_RXBE_0_XTD_Pos) /* (CAN_RXBE_0) Extended Identifier Mask */ +#define CAN_RXBE_0_XTD(value) (CAN_RXBE_0_XTD_Msk & (_UINT32_(value) << CAN_RXBE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_ESI_Pos _UINT32_(31) /* (CAN_RXBE_0) Error State Indicator Position */ +#define CAN_RXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_RXBE_0_ESI_Pos) /* (CAN_RXBE_0) Error State Indicator Mask */ +#define CAN_RXBE_0_ESI(value) (CAN_RXBE_0_ESI_Msk & (_UINT32_(value) << CAN_RXBE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXBE_0 register */ +#define CAN_RXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_0) Register Mask */ + + +/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#define CAN_RXBE_1_RXTS_Pos _UINT32_(0) /* (CAN_RXBE_1) Rx Timestamp Position */ +#define CAN_RXBE_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) /* (CAN_RXBE_1) Rx Timestamp Mask */ +#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & (_UINT32_(value) << CAN_RXBE_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_DLC_Pos _UINT32_(16) /* (CAN_RXBE_1) Data Length Code Position */ +#define CAN_RXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_RXBE_1_DLC_Pos) /* (CAN_RXBE_1) Data Length Code Mask */ +#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & (_UINT32_(value) << CAN_RXBE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_BRS_Pos _UINT32_(20) /* (CAN_RXBE_1) Bit Rate Switch Position */ +#define CAN_RXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_RXBE_1_BRS_Pos) /* (CAN_RXBE_1) Bit Rate Switch Mask */ +#define CAN_RXBE_1_BRS(value) (CAN_RXBE_1_BRS_Msk & (_UINT32_(value) << CAN_RXBE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_FDF_Pos _UINT32_(21) /* (CAN_RXBE_1) FD Format Position */ +#define CAN_RXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_RXBE_1_FDF_Pos) /* (CAN_RXBE_1) FD Format Mask */ +#define CAN_RXBE_1_FDF(value) (CAN_RXBE_1_FDF_Msk & (_UINT32_(value) << CAN_RXBE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_FIDX_Pos _UINT32_(24) /* (CAN_RXBE_1) Filter Index Position */ +#define CAN_RXBE_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXBE_1_FIDX_Pos) /* (CAN_RXBE_1) Filter Index Mask */ +#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & (_UINT32_(value) << CAN_RXBE_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_ANMF_Pos _UINT32_(31) /* (CAN_RXBE_1) Accepted Non-matching Frame Position */ +#define CAN_RXBE_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXBE_1_ANMF_Pos) /* (CAN_RXBE_1) Accepted Non-matching Frame Mask */ +#define CAN_RXBE_1_ANMF(value) (CAN_RXBE_1_ANMF_Msk & (_UINT32_(value) << CAN_RXBE_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXBE_1 register */ +#define CAN_RXBE_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXBE_1) Register Mask */ + + +/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#define CAN_RXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXBE_DATA) Data Byte 0 Position */ +#define CAN_RXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB0_Pos) /* (CAN_RXBE_DATA) Data Byte 0 Mask */ +#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXBE_DATA) Data Byte 1 Position */ +#define CAN_RXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB1_Pos) /* (CAN_RXBE_DATA) Data Byte 1 Mask */ +#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXBE_DATA) Data Byte 2 Position */ +#define CAN_RXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB2_Pos) /* (CAN_RXBE_DATA) Data Byte 2 Mask */ +#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXBE_DATA) Data Byte 3 Position */ +#define CAN_RXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB3_Pos) /* (CAN_RXBE_DATA) Data Byte 3 Mask */ +#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXBE_DATA register */ +#define CAN_RXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_DATA) Register Mask */ + + +/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#define CAN_RXF0E_0_ID_Pos _UINT32_(0) /* (CAN_RXF0E_0) Identifier Position */ +#define CAN_RXF0E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) /* (CAN_RXF0E_0) Identifier Mask */ +#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & (_UINT32_(value) << CAN_RXF0E_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF0E_0) Remote Transmission Request Position */ +#define CAN_RXF0E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF0E_0_RTR_Pos) /* (CAN_RXF0E_0) Remote Transmission Request Mask */ +#define CAN_RXF0E_0_RTR(value) (CAN_RXF0E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF0E_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF0E_0) Extended Identifier Position */ +#define CAN_RXF0E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF0E_0_XTD_Pos) /* (CAN_RXF0E_0) Extended Identifier Mask */ +#define CAN_RXF0E_0_XTD(value) (CAN_RXF0E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF0E_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF0E_0) Error State Indicator Position */ +#define CAN_RXF0E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF0E_0_ESI_Pos) /* (CAN_RXF0E_0) Error State Indicator Mask */ +#define CAN_RXF0E_0_ESI(value) (CAN_RXF0E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF0E_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXF0E_0 register */ +#define CAN_RXF0E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_0) Register Mask */ + + +/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#define CAN_RXF0E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF0E_1) Rx Timestamp Position */ +#define CAN_RXF0E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) /* (CAN_RXF0E_1) Rx Timestamp Mask */ +#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF0E_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF0E_1) Data Length Code Position */ +#define CAN_RXF0E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF0E_1_DLC_Pos) /* (CAN_RXF0E_1) Data Length Code Mask */ +#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF0E_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF0E_1) Bit Rate Switch Position */ +#define CAN_RXF0E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF0E_1_BRS_Pos) /* (CAN_RXF0E_1) Bit Rate Switch Mask */ +#define CAN_RXF0E_1_BRS(value) (CAN_RXF0E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF0E_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF0E_1) FD Format Position */ +#define CAN_RXF0E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_FDF_Pos) /* (CAN_RXF0E_1) FD Format Mask */ +#define CAN_RXF0E_1_FDF(value) (CAN_RXF0E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF0E_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF0E_1) Filter Index Position */ +#define CAN_RXF0E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF0E_1_FIDX_Pos) /* (CAN_RXF0E_1) Filter Index Mask */ +#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF0E_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF0E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF0E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_ANMF_Pos) /* (CAN_RXF0E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF0E_1_ANMF(value) (CAN_RXF0E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF0E_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXF0E_1 register */ +#define CAN_RXF0E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF0E_1) Register Mask */ + + +/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#define CAN_RXF0E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF0E_DATA) Data Byte 0 Position */ +#define CAN_RXF0E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) /* (CAN_RXF0E_DATA) Data Byte 0 Mask */ +#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF0E_DATA) Data Byte 1 Position */ +#define CAN_RXF0E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) /* (CAN_RXF0E_DATA) Data Byte 1 Mask */ +#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF0E_DATA) Data Byte 2 Position */ +#define CAN_RXF0E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) /* (CAN_RXF0E_DATA) Data Byte 2 Mask */ +#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF0E_DATA) Data Byte 3 Position */ +#define CAN_RXF0E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) /* (CAN_RXF0E_DATA) Data Byte 3 Mask */ +#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXF0E_DATA register */ +#define CAN_RXF0E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_DATA) Register Mask */ + + +/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#define CAN_RXF1E_0_ID_Pos _UINT32_(0) /* (CAN_RXF1E_0) Identifier Position */ +#define CAN_RXF1E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) /* (CAN_RXF1E_0) Identifier Mask */ +#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & (_UINT32_(value) << CAN_RXF1E_0_ID_Pos)) /* Assigment of value for ID in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF1E_0) Remote Transmission Request Position */ +#define CAN_RXF1E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF1E_0_RTR_Pos) /* (CAN_RXF1E_0) Remote Transmission Request Mask */ +#define CAN_RXF1E_0_RTR(value) (CAN_RXF1E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF1E_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF1E_0) Extended Identifier Position */ +#define CAN_RXF1E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF1E_0_XTD_Pos) /* (CAN_RXF1E_0) Extended Identifier Mask */ +#define CAN_RXF1E_0_XTD(value) (CAN_RXF1E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF1E_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF1E_0) Error State Indicator Position */ +#define CAN_RXF1E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF1E_0_ESI_Pos) /* (CAN_RXF1E_0) Error State Indicator Mask */ +#define CAN_RXF1E_0_ESI(value) (CAN_RXF1E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF1E_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_RXF1E_0 register */ +#define CAN_RXF1E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_0) Register Mask */ + + +/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#define CAN_RXF1E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF1E_1) Rx Timestamp Position */ +#define CAN_RXF1E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) /* (CAN_RXF1E_1) Rx Timestamp Mask */ +#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF1E_1_RXTS_Pos)) /* Assigment of value for RXTS in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF1E_1) Data Length Code Position */ +#define CAN_RXF1E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF1E_1_DLC_Pos) /* (CAN_RXF1E_1) Data Length Code Mask */ +#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF1E_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF1E_1) Bit Rate Switch Position */ +#define CAN_RXF1E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF1E_1_BRS_Pos) /* (CAN_RXF1E_1) Bit Rate Switch Mask */ +#define CAN_RXF1E_1_BRS(value) (CAN_RXF1E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF1E_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF1E_1) FD Format Position */ +#define CAN_RXF1E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_FDF_Pos) /* (CAN_RXF1E_1) FD Format Mask */ +#define CAN_RXF1E_1_FDF(value) (CAN_RXF1E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF1E_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF1E_1) Filter Index Position */ +#define CAN_RXF1E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF1E_1_FIDX_Pos) /* (CAN_RXF1E_1) Filter Index Mask */ +#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF1E_1_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF1E_1) Accepted Non-matching Frame Position */ +#define CAN_RXF1E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_ANMF_Pos) /* (CAN_RXF1E_1) Accepted Non-matching Frame Mask */ +#define CAN_RXF1E_1_ANMF(value) (CAN_RXF1E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF1E_1_ANMF_Pos)) /* Assigment of value for ANMF in the CAN_RXF1E_1 register */ +#define CAN_RXF1E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF1E_1) Register Mask */ + + +/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#define CAN_RXF1E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF1E_DATA) Data Byte 0 Position */ +#define CAN_RXF1E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) /* (CAN_RXF1E_DATA) Data Byte 0 Mask */ +#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF1E_DATA) Data Byte 1 Position */ +#define CAN_RXF1E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) /* (CAN_RXF1E_DATA) Data Byte 1 Mask */ +#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF1E_DATA) Data Byte 2 Position */ +#define CAN_RXF1E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) /* (CAN_RXF1E_DATA) Data Byte 2 Mask */ +#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF1E_DATA) Data Byte 3 Position */ +#define CAN_RXF1E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) /* (CAN_RXF1E_DATA) Data Byte 3 Mask */ +#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_RXF1E_DATA register */ +#define CAN_RXF1E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_DATA) Register Mask */ + + +/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#define CAN_TXBE_0_ID_Pos _UINT32_(0) /* (CAN_TXBE_0) Identifier Position */ +#define CAN_TXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) /* (CAN_TXBE_0) Identifier Mask */ +#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & (_UINT32_(value) << CAN_TXBE_0_ID_Pos)) /* Assigment of value for ID in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_RTR_Pos _UINT32_(29) /* (CAN_TXBE_0) Remote Transmission Request Position */ +#define CAN_TXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXBE_0_RTR_Pos) /* (CAN_TXBE_0) Remote Transmission Request Mask */ +#define CAN_TXBE_0_RTR(value) (CAN_TXBE_0_RTR_Msk & (_UINT32_(value) << CAN_TXBE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_XTD_Pos _UINT32_(30) /* (CAN_TXBE_0) Extended Identifier Position */ +#define CAN_TXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXBE_0_XTD_Pos) /* (CAN_TXBE_0) Extended Identifier Mask */ +#define CAN_TXBE_0_XTD(value) (CAN_TXBE_0_XTD_Msk & (_UINT32_(value) << CAN_TXBE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_ESI_Pos _UINT32_(31) /* (CAN_TXBE_0) Error State Indicator Position */ +#define CAN_TXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXBE_0_ESI_Pos) /* (CAN_TXBE_0) Error State Indicator Mask */ +#define CAN_TXBE_0_ESI(value) (CAN_TXBE_0_ESI_Msk & (_UINT32_(value) << CAN_TXBE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_TXBE_0 register */ +#define CAN_TXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_0) Register Mask */ + + +/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#define CAN_TXBE_1_DLC_Pos _UINT32_(16) /* (CAN_TXBE_1) Data Length Code Position */ +#define CAN_TXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXBE_1_DLC_Pos) /* (CAN_TXBE_1) Data Length Code Mask */ +#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & (_UINT32_(value) << CAN_TXBE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_BRS_Pos _UINT32_(20) /* (CAN_TXBE_1) Bit Rate Switch Position */ +#define CAN_TXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXBE_1_BRS_Pos) /* (CAN_TXBE_1) Bit Rate Switch Mask */ +#define CAN_TXBE_1_BRS(value) (CAN_TXBE_1_BRS_Msk & (_UINT32_(value) << CAN_TXBE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_FDF_Pos _UINT32_(21) /* (CAN_TXBE_1) FD Format Position */ +#define CAN_TXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXBE_1_FDF_Pos) /* (CAN_TXBE_1) FD Format Mask */ +#define CAN_TXBE_1_FDF(value) (CAN_TXBE_1_FDF_Msk & (_UINT32_(value) << CAN_TXBE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_EFC_Pos _UINT32_(23) /* (CAN_TXBE_1) Event FIFO Control Position */ +#define CAN_TXBE_1_EFC_Msk (_UINT32_(0x1) << CAN_TXBE_1_EFC_Pos) /* (CAN_TXBE_1) Event FIFO Control Mask */ +#define CAN_TXBE_1_EFC(value) (CAN_TXBE_1_EFC_Msk & (_UINT32_(value) << CAN_TXBE_1_EFC_Pos)) /* Assigment of value for EFC in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_MM_Pos _UINT32_(24) /* (CAN_TXBE_1) Message Marker Position */ +#define CAN_TXBE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXBE_1_MM_Pos) /* (CAN_TXBE_1) Message Marker Mask */ +#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & (_UINT32_(value) << CAN_TXBE_1_MM_Pos)) /* Assigment of value for MM in the CAN_TXBE_1 register */ +#define CAN_TXBE_1_Msk _UINT32_(0xFFBF0000) /* (CAN_TXBE_1) Register Mask */ + + +/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#define CAN_TXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_TXBE_DATA) Data Byte 0 Position */ +#define CAN_TXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB0_Pos) /* (CAN_TXBE_DATA) Data Byte 0 Mask */ +#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB0_Pos)) /* Assigment of value for DB0 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_TXBE_DATA) Data Byte 1 Position */ +#define CAN_TXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB1_Pos) /* (CAN_TXBE_DATA) Data Byte 1 Mask */ +#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB1_Pos)) /* Assigment of value for DB1 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_TXBE_DATA) Data Byte 2 Position */ +#define CAN_TXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB2_Pos) /* (CAN_TXBE_DATA) Data Byte 2 Mask */ +#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB2_Pos)) /* Assigment of value for DB2 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_TXBE_DATA) Data Byte 3 Position */ +#define CAN_TXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB3_Pos) /* (CAN_TXBE_DATA) Data Byte 3 Mask */ +#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB3_Pos)) /* Assigment of value for DB3 in the CAN_TXBE_DATA register */ +#define CAN_TXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_DATA) Register Mask */ + + +/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#define CAN_TXEFE_0_ID_Pos _UINT32_(0) /* (CAN_TXEFE_0) Identifier Position */ +#define CAN_TXEFE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) /* (CAN_TXEFE_0) Identifier Mask */ +#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & (_UINT32_(value) << CAN_TXEFE_0_ID_Pos)) /* Assigment of value for ID in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_RTR_Pos _UINT32_(29) /* (CAN_TXEFE_0) Remote Transmission Request Position */ +#define CAN_TXEFE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXEFE_0_RTR_Pos) /* (CAN_TXEFE_0) Remote Transmission Request Mask */ +#define CAN_TXEFE_0_RTR(value) (CAN_TXEFE_0_RTR_Msk & (_UINT32_(value) << CAN_TXEFE_0_RTR_Pos)) /* Assigment of value for RTR in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_XTD_Pos _UINT32_(30) /* (CAN_TXEFE_0) Extended Identifier Position */ +#define CAN_TXEFE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXEFE_0_XTD_Pos) /* (CAN_TXEFE_0) Extended Identifier Mask */ +#define CAN_TXEFE_0_XTD(value) (CAN_TXEFE_0_XTD_Msk & (_UINT32_(value) << CAN_TXEFE_0_XTD_Pos)) /* Assigment of value for XTD in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_ESI_Pos _UINT32_(31) /* (CAN_TXEFE_0) Error State Indicator Position */ +#define CAN_TXEFE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXEFE_0_ESI_Pos) /* (CAN_TXEFE_0) Error State Indicator Mask */ +#define CAN_TXEFE_0_ESI(value) (CAN_TXEFE_0_ESI_Msk & (_UINT32_(value) << CAN_TXEFE_0_ESI_Pos)) /* Assigment of value for ESI in the CAN_TXEFE_0 register */ +#define CAN_TXEFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_0) Register Mask */ + + +/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#define CAN_TXEFE_1_TXTS_Pos _UINT32_(0) /* (CAN_TXEFE_1) Tx Timestamp Position */ +#define CAN_TXEFE_1_TXTS_Msk (_UINT32_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) /* (CAN_TXEFE_1) Tx Timestamp Mask */ +#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & (_UINT32_(value) << CAN_TXEFE_1_TXTS_Pos)) /* Assigment of value for TXTS in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_DLC_Pos _UINT32_(16) /* (CAN_TXEFE_1) Data Length Code Position */ +#define CAN_TXEFE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXEFE_1_DLC_Pos) /* (CAN_TXEFE_1) Data Length Code Mask */ +#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & (_UINT32_(value) << CAN_TXEFE_1_DLC_Pos)) /* Assigment of value for DLC in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_BRS_Pos _UINT32_(20) /* (CAN_TXEFE_1) Bit Rate Switch Position */ +#define CAN_TXEFE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXEFE_1_BRS_Pos) /* (CAN_TXEFE_1) Bit Rate Switch Mask */ +#define CAN_TXEFE_1_BRS(value) (CAN_TXEFE_1_BRS_Msk & (_UINT32_(value) << CAN_TXEFE_1_BRS_Pos)) /* Assigment of value for BRS in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_FDF_Pos _UINT32_(21) /* (CAN_TXEFE_1) FD Format Position */ +#define CAN_TXEFE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXEFE_1_FDF_Pos) /* (CAN_TXEFE_1) FD Format Mask */ +#define CAN_TXEFE_1_FDF(value) (CAN_TXEFE_1_FDF_Msk & (_UINT32_(value) << CAN_TXEFE_1_FDF_Pos)) /* Assigment of value for FDF in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_ET_Pos _UINT32_(22) /* (CAN_TXEFE_1) Event Type Position */ +#define CAN_TXEFE_1_ET_Msk (_UINT32_(0x3) << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Event Type Mask */ +#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & (_UINT32_(value) << CAN_TXEFE_1_ET_Pos)) /* Assigment of value for ET in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_ET_TXE_Val _UINT32_(0x1) /* (CAN_TXEFE_1) Tx event */ +#define CAN_TXEFE_1_ET_TXC_Val _UINT32_(0x2) /* (CAN_TXEFE_1) Transmission in spite of cancellation */ +#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Tx event Position */ +#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Transmission in spite of cancellation Position */ +#define CAN_TXEFE_1_MM_Pos _UINT32_(24) /* (CAN_TXEFE_1) Message Marker Position */ +#define CAN_TXEFE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXEFE_1_MM_Pos) /* (CAN_TXEFE_1) Message Marker Mask */ +#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & (_UINT32_(value) << CAN_TXEFE_1_MM_Pos)) /* Assigment of value for MM in the CAN_TXEFE_1 register */ +#define CAN_TXEFE_1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_1) Register Mask */ + + +/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ +#define CAN_SIDFE_0_SFID2_Pos _UINT32_(0) /* (CAN_SIDFE_0) Standard Filter ID 2 Position */ +#define CAN_SIDFE_0_SFID2_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) /* (CAN_SIDFE_0) Standard Filter ID 2 Mask */ +#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID2_Pos)) /* Assigment of value for SFID2 in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFID1_Pos _UINT32_(16) /* (CAN_SIDFE_0) Standard Filter ID 1 Position */ +#define CAN_SIDFE_0_SFID1_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) /* (CAN_SIDFE_0) Standard Filter ID 1 Mask */ +#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID1_Pos)) /* Assigment of value for SFID1 in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFEC_Pos _UINT32_(27) /* (CAN_SIDFE_0) Standard Filter Element Configuration Position */ +#define CAN_SIDFE_0_SFEC_Msk (_UINT32_(0x7) << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Standard Filter Element Configuration Mask */ +#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFEC_Pos)) /* Assigment of value for SFEC in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Disable filter element */ +#define CAN_SIDFE_0_SFEC_STF0M_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_STF1M_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_REJECT_Val _UINT32_(0x3) /* (CAN_SIDFE_0) Reject ID if filter match */ +#define CAN_SIDFE_0_SFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_SIDFE_0) Set priority if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_SIDFE_0) Store into Rx Buffer */ +#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Disable filter element Position */ +#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Reject ID if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store into Rx Buffer Position */ +#define CAN_SIDFE_0_SFT_Pos _UINT32_(30) /* (CAN_SIDFE_0) Standard Filter Type Position */ +#define CAN_SIDFE_0_SFT_Msk (_UINT32_(0x3) << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Standard Filter Type Mask */ +#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFT_Pos)) /* Assigment of value for SFT in the CAN_SIDFE_0 register */ +#define CAN_SIDFE_0_SFT_RANGE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define CAN_SIDFE_0_SFT_DUAL_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ +#define CAN_SIDFE_0_SFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Classic filter */ +#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ +#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 Position */ +#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Classic filter Position */ +#define CAN_SIDFE_0_Msk _UINT32_(0xFFFF07FF) /* (CAN_SIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#define CAN_XIDFE_0_EFID1_Pos _UINT32_(0) /* (CAN_XIDFE_0) Extended Filter ID 1 Position */ +#define CAN_XIDFE_0_EFID1_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) /* (CAN_XIDFE_0) Extended Filter ID 1 Mask */ +#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFID1_Pos)) /* Assigment of value for EFID1 in the CAN_XIDFE_0 register */ +#define CAN_XIDFE_0_EFEC_Pos _UINT32_(29) /* (CAN_XIDFE_0) Extended Filter Element Configuration Position */ +#define CAN_XIDFE_0_EFEC_Msk (_UINT32_(0x7) << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Extended Filter Element Configuration Mask */ +#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFEC_Pos)) /* Assigment of value for EFEC in the CAN_XIDFE_0 register */ +#define CAN_XIDFE_0_EFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_XIDFE_0) Disable filter element */ +#define CAN_XIDFE_0_EFEC_STF0M_Val _UINT32_(0x1) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_STF1M_Val _UINT32_(0x2) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_REJECT_Val _UINT32_(0x3) /* (CAN_XIDFE_0) Reject ID if filter match */ +#define CAN_XIDFE_0_EFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_XIDFE_0) Set priority if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_XIDFE_0) Store into Rx Buffer */ +#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Disable filter element Position */ +#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Reject ID if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match Position */ +#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match Position */ +#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store into Rx Buffer Position */ +#define CAN_XIDFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_XIDFE_0) Register Mask */ + + +/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#define CAN_XIDFE_1_EFID2_Pos _UINT32_(0) /* (CAN_XIDFE_1) Extended Filter ID 2 Position */ +#define CAN_XIDFE_1_EFID2_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) /* (CAN_XIDFE_1) Extended Filter ID 2 Mask */ +#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFID2_Pos)) /* Assigment of value for EFID2 in the CAN_XIDFE_1 register */ +#define CAN_XIDFE_1_EFT_Pos _UINT32_(30) /* (CAN_XIDFE_1) Extended Filter Type Position */ +#define CAN_XIDFE_1_EFT_Msk (_UINT32_(0x3) << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Extended Filter Type Mask */ +#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFT_Pos)) /* Assigment of value for EFT in the CAN_XIDFE_1 register */ +#define CAN_XIDFE_1_EFT_RANGEM_Val _UINT32_(0x0) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define CAN_XIDFE_1_EFT_DUAL_Val _UINT32_(0x1) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define CAN_XIDFE_1_EFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_XIDFE_1) Classic filter */ +#define CAN_XIDFE_1_EFT_RANGE_Val _UINT32_(0x3) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ +#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ +#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Classic filter Position */ +#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ +#define CAN_XIDFE_1_Msk _UINT32_(0xDFFFFFFF) /* (CAN_XIDFE_1) Register Mask */ + + +/* -------- CAN_CREL : (CAN Offset: 0x00) ( R/ 32) Core Release -------- */ +#define CAN_CREL_RESETVALUE _UINT32_(0x32100000) /* (CAN_CREL) Core Release Reset Value */ + +#define CAN_CREL_SUBSTEP_Pos _UINT32_(20) /* (CAN_CREL) Sub-step of Core Release Position */ +#define CAN_CREL_SUBSTEP_Msk (_UINT32_(0xF) << CAN_CREL_SUBSTEP_Pos) /* (CAN_CREL) Sub-step of Core Release Mask */ +#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & (_UINT32_(value) << CAN_CREL_SUBSTEP_Pos)) /* Assigment of value for SUBSTEP in the CAN_CREL register */ +#define CAN_CREL_STEP_Pos _UINT32_(24) /* (CAN_CREL) Step of Core Release Position */ +#define CAN_CREL_STEP_Msk (_UINT32_(0xF) << CAN_CREL_STEP_Pos) /* (CAN_CREL) Step of Core Release Mask */ +#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & (_UINT32_(value) << CAN_CREL_STEP_Pos)) /* Assigment of value for STEP in the CAN_CREL register */ +#define CAN_CREL_REL_Pos _UINT32_(28) /* (CAN_CREL) Core Release Position */ +#define CAN_CREL_REL_Msk (_UINT32_(0xF) << CAN_CREL_REL_Pos) /* (CAN_CREL) Core Release Mask */ +#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & (_UINT32_(value) << CAN_CREL_REL_Pos)) /* Assigment of value for REL in the CAN_CREL register */ +#define CAN_CREL_Msk _UINT32_(0xFFF00000) /* (CAN_CREL) Register Mask */ + + +/* -------- CAN_ENDN : (CAN Offset: 0x04) ( R/ 32) Endian -------- */ +#define CAN_ENDN_RESETVALUE _UINT32_(0x87654321) /* (CAN_ENDN) Endian Reset Value */ + +#define CAN_ENDN_ETV_Pos _UINT32_(0) /* (CAN_ENDN) Endianness Test Value Position */ +#define CAN_ENDN_ETV_Msk (_UINT32_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) /* (CAN_ENDN) Endianness Test Value Mask */ +#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & (_UINT32_(value) << CAN_ENDN_ETV_Pos)) /* Assigment of value for ETV in the CAN_ENDN register */ +#define CAN_ENDN_Msk _UINT32_(0xFFFFFFFF) /* (CAN_ENDN) Register Mask */ + + +/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ +#define CAN_MRCFG_RESETVALUE _UINT32_(0x02) /* (CAN_MRCFG) Message RAM Configuration Reset Value */ + +#define CAN_MRCFG_QOS_Pos _UINT32_(0) /* (CAN_MRCFG) Quality of Service Position */ +#define CAN_MRCFG_QOS_Msk (_UINT32_(0x3) << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Quality of Service Mask */ +#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & (_UINT32_(value) << CAN_MRCFG_QOS_Pos)) /* Assigment of value for QOS in the CAN_MRCFG register */ +#define CAN_MRCFG_QOS_DISABLE_Val _UINT32_(0x0) /* (CAN_MRCFG) Background (no sensitive operation) */ +#define CAN_MRCFG_QOS_LOW_Val _UINT32_(0x1) /* (CAN_MRCFG) Sensitive Bandwidth */ +#define CAN_MRCFG_QOS_MEDIUM_Val _UINT32_(0x2) /* (CAN_MRCFG) Sensitive Latency */ +#define CAN_MRCFG_QOS_HIGH_Val _UINT32_(0x3) /* (CAN_MRCFG) Critical Latency */ +#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Background (no sensitive operation) Position */ +#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Bandwidth Position */ +#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Latency Position */ +#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Critical Latency Position */ +#define CAN_MRCFG_Msk _UINT32_(0x00000003) /* (CAN_MRCFG) Register Mask */ + + +/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ +#define CAN_DBTP_RESETVALUE _UINT32_(0xA33) /* (CAN_DBTP) Fast Bit Timing and Prescaler Reset Value */ + +#define CAN_DBTP_DSJW_Pos _UINT32_(0) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Position */ +#define CAN_DBTP_DSJW_Msk (_UINT32_(0xF) << CAN_DBTP_DSJW_Pos) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Mask */ +#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & (_UINT32_(value) << CAN_DBTP_DSJW_Pos)) /* Assigment of value for DSJW in the CAN_DBTP register */ +#define CAN_DBTP_DTSEG2_Pos _UINT32_(4) /* (CAN_DBTP) Data time segment after sample point Position */ +#define CAN_DBTP_DTSEG2_Msk (_UINT32_(0xF) << CAN_DBTP_DTSEG2_Pos) /* (CAN_DBTP) Data time segment after sample point Mask */ +#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG2_Pos)) /* Assigment of value for DTSEG2 in the CAN_DBTP register */ +#define CAN_DBTP_DTSEG1_Pos _UINT32_(8) /* (CAN_DBTP) Data time segment before sample point Position */ +#define CAN_DBTP_DTSEG1_Msk (_UINT32_(0x1F) << CAN_DBTP_DTSEG1_Pos) /* (CAN_DBTP) Data time segment before sample point Mask */ +#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG1_Pos)) /* Assigment of value for DTSEG1 in the CAN_DBTP register */ +#define CAN_DBTP_DBRP_Pos _UINT32_(16) /* (CAN_DBTP) Data Baud Rate Prescaler Position */ +#define CAN_DBTP_DBRP_Msk (_UINT32_(0x1F) << CAN_DBTP_DBRP_Pos) /* (CAN_DBTP) Data Baud Rate Prescaler Mask */ +#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & (_UINT32_(value) << CAN_DBTP_DBRP_Pos)) /* Assigment of value for DBRP in the CAN_DBTP register */ +#define CAN_DBTP_TDC_Pos _UINT32_(23) /* (CAN_DBTP) Tranceiver Delay Compensation Position */ +#define CAN_DBTP_TDC_Msk (_UINT32_(0x1) << CAN_DBTP_TDC_Pos) /* (CAN_DBTP) Tranceiver Delay Compensation Mask */ +#define CAN_DBTP_TDC(value) (CAN_DBTP_TDC_Msk & (_UINT32_(value) << CAN_DBTP_TDC_Pos)) /* Assigment of value for TDC in the CAN_DBTP register */ +#define CAN_DBTP_Msk _UINT32_(0x009F1FFF) /* (CAN_DBTP) Register Mask */ + + +/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ +#define CAN_TEST_RESETVALUE _UINT32_(0x00) /* (CAN_TEST) Test Reset Value */ + +#define CAN_TEST_LBCK_Pos _UINT32_(4) /* (CAN_TEST) Loop Back Mode Position */ +#define CAN_TEST_LBCK_Msk (_UINT32_(0x1) << CAN_TEST_LBCK_Pos) /* (CAN_TEST) Loop Back Mode Mask */ +#define CAN_TEST_LBCK(value) (CAN_TEST_LBCK_Msk & (_UINT32_(value) << CAN_TEST_LBCK_Pos)) /* Assigment of value for LBCK in the CAN_TEST register */ +#define CAN_TEST_TX_Pos _UINT32_(5) /* (CAN_TEST) Control of Transmit Pin Position */ +#define CAN_TEST_TX_Msk (_UINT32_(0x3) << CAN_TEST_TX_Pos) /* (CAN_TEST) Control of Transmit Pin Mask */ +#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & (_UINT32_(value) << CAN_TEST_TX_Pos)) /* Assigment of value for TX in the CAN_TEST register */ +#define CAN_TEST_TX_CORE_Val _UINT32_(0x0) /* (CAN_TEST) TX controlled by CAN core */ +#define CAN_TEST_TX_SAMPLE_Val _UINT32_(0x1) /* (CAN_TEST) TX monitoring sample point */ +#define CAN_TEST_TX_DOMINANT_Val _UINT32_(0x2) /* (CAN_TEST) Dominant (0) level at pin CAN_TX */ +#define CAN_TEST_TX_RECESSIVE_Val _UINT32_(0x3) /* (CAN_TEST) Recessive (1) level at pin CAN_TX */ +#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX controlled by CAN core Position */ +#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX monitoring sample point Position */ +#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Dominant (0) level at pin CAN_TX Position */ +#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Recessive (1) level at pin CAN_TX Position */ +#define CAN_TEST_RX_Pos _UINT32_(7) /* (CAN_TEST) Receive Pin Position */ +#define CAN_TEST_RX_Msk (_UINT32_(0x1) << CAN_TEST_RX_Pos) /* (CAN_TEST) Receive Pin Mask */ +#define CAN_TEST_RX(value) (CAN_TEST_RX_Msk & (_UINT32_(value) << CAN_TEST_RX_Pos)) /* Assigment of value for RX in the CAN_TEST register */ +#define CAN_TEST_Msk _UINT32_(0x000000F0) /* (CAN_TEST) Register Mask */ + + +/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ +#define CAN_RWD_RESETVALUE _UINT32_(0x00) /* (CAN_RWD) RAM Watchdog Reset Value */ + +#define CAN_RWD_WDC_Pos _UINT32_(0) /* (CAN_RWD) Watchdog Configuration Position */ +#define CAN_RWD_WDC_Msk (_UINT32_(0xFF) << CAN_RWD_WDC_Pos) /* (CAN_RWD) Watchdog Configuration Mask */ +#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & (_UINT32_(value) << CAN_RWD_WDC_Pos)) /* Assigment of value for WDC in the CAN_RWD register */ +#define CAN_RWD_WDV_Pos _UINT32_(8) /* (CAN_RWD) Watchdog Value Position */ +#define CAN_RWD_WDV_Msk (_UINT32_(0xFF) << CAN_RWD_WDV_Pos) /* (CAN_RWD) Watchdog Value Mask */ +#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & (_UINT32_(value) << CAN_RWD_WDV_Pos)) /* Assigment of value for WDV in the CAN_RWD register */ +#define CAN_RWD_Msk _UINT32_(0x0000FFFF) /* (CAN_RWD) Register Mask */ + + +/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ +#define CAN_CCCR_RESETVALUE _UINT32_(0x01) /* (CAN_CCCR) CC Control Reset Value */ + +#define CAN_CCCR_INIT_Pos _UINT32_(0) /* (CAN_CCCR) Initialization Position */ +#define CAN_CCCR_INIT_Msk (_UINT32_(0x1) << CAN_CCCR_INIT_Pos) /* (CAN_CCCR) Initialization Mask */ +#define CAN_CCCR_INIT(value) (CAN_CCCR_INIT_Msk & (_UINT32_(value) << CAN_CCCR_INIT_Pos)) /* Assigment of value for INIT in the CAN_CCCR register */ +#define CAN_CCCR_CCE_Pos _UINT32_(1) /* (CAN_CCCR) Configuration Change Enable Position */ +#define CAN_CCCR_CCE_Msk (_UINT32_(0x1) << CAN_CCCR_CCE_Pos) /* (CAN_CCCR) Configuration Change Enable Mask */ +#define CAN_CCCR_CCE(value) (CAN_CCCR_CCE_Msk & (_UINT32_(value) << CAN_CCCR_CCE_Pos)) /* Assigment of value for CCE in the CAN_CCCR register */ +#define CAN_CCCR_ASM_Pos _UINT32_(2) /* (CAN_CCCR) ASM Restricted Operation Mode Position */ +#define CAN_CCCR_ASM_Msk (_UINT32_(0x1) << CAN_CCCR_ASM_Pos) /* (CAN_CCCR) ASM Restricted Operation Mode Mask */ +#define CAN_CCCR_ASM(value) (CAN_CCCR_ASM_Msk & (_UINT32_(value) << CAN_CCCR_ASM_Pos)) /* Assigment of value for ASM in the CAN_CCCR register */ +#define CAN_CCCR_CSA_Pos _UINT32_(3) /* (CAN_CCCR) Clock Stop Acknowledge Position */ +#define CAN_CCCR_CSA_Msk (_UINT32_(0x1) << CAN_CCCR_CSA_Pos) /* (CAN_CCCR) Clock Stop Acknowledge Mask */ +#define CAN_CCCR_CSA(value) (CAN_CCCR_CSA_Msk & (_UINT32_(value) << CAN_CCCR_CSA_Pos)) /* Assigment of value for CSA in the CAN_CCCR register */ +#define CAN_CCCR_CSR_Pos _UINT32_(4) /* (CAN_CCCR) Clock Stop Request Position */ +#define CAN_CCCR_CSR_Msk (_UINT32_(0x1) << CAN_CCCR_CSR_Pos) /* (CAN_CCCR) Clock Stop Request Mask */ +#define CAN_CCCR_CSR(value) (CAN_CCCR_CSR_Msk & (_UINT32_(value) << CAN_CCCR_CSR_Pos)) /* Assigment of value for CSR in the CAN_CCCR register */ +#define CAN_CCCR_MON_Pos _UINT32_(5) /* (CAN_CCCR) Bus Monitoring Mode Position */ +#define CAN_CCCR_MON_Msk (_UINT32_(0x1) << CAN_CCCR_MON_Pos) /* (CAN_CCCR) Bus Monitoring Mode Mask */ +#define CAN_CCCR_MON(value) (CAN_CCCR_MON_Msk & (_UINT32_(value) << CAN_CCCR_MON_Pos)) /* Assigment of value for MON in the CAN_CCCR register */ +#define CAN_CCCR_DAR_Pos _UINT32_(6) /* (CAN_CCCR) Disable Automatic Retransmission Position */ +#define CAN_CCCR_DAR_Msk (_UINT32_(0x1) << CAN_CCCR_DAR_Pos) /* (CAN_CCCR) Disable Automatic Retransmission Mask */ +#define CAN_CCCR_DAR(value) (CAN_CCCR_DAR_Msk & (_UINT32_(value) << CAN_CCCR_DAR_Pos)) /* Assigment of value for DAR in the CAN_CCCR register */ +#define CAN_CCCR_TEST_Pos _UINT32_(7) /* (CAN_CCCR) Test Mode Enable Position */ +#define CAN_CCCR_TEST_Msk (_UINT32_(0x1) << CAN_CCCR_TEST_Pos) /* (CAN_CCCR) Test Mode Enable Mask */ +#define CAN_CCCR_TEST(value) (CAN_CCCR_TEST_Msk & (_UINT32_(value) << CAN_CCCR_TEST_Pos)) /* Assigment of value for TEST in the CAN_CCCR register */ +#define CAN_CCCR_FDOE_Pos _UINT32_(8) /* (CAN_CCCR) FD Operation Enable Position */ +#define CAN_CCCR_FDOE_Msk (_UINT32_(0x1) << CAN_CCCR_FDOE_Pos) /* (CAN_CCCR) FD Operation Enable Mask */ +#define CAN_CCCR_FDOE(value) (CAN_CCCR_FDOE_Msk & (_UINT32_(value) << CAN_CCCR_FDOE_Pos)) /* Assigment of value for FDOE in the CAN_CCCR register */ +#define CAN_CCCR_BRSE_Pos _UINT32_(9) /* (CAN_CCCR) Bit Rate Switch Enable Position */ +#define CAN_CCCR_BRSE_Msk (_UINT32_(0x1) << CAN_CCCR_BRSE_Pos) /* (CAN_CCCR) Bit Rate Switch Enable Mask */ +#define CAN_CCCR_BRSE(value) (CAN_CCCR_BRSE_Msk & (_UINT32_(value) << CAN_CCCR_BRSE_Pos)) /* Assigment of value for BRSE in the CAN_CCCR register */ +#define CAN_CCCR_PXHD_Pos _UINT32_(12) /* (CAN_CCCR) Protocol Exception Handling Disable Position */ +#define CAN_CCCR_PXHD_Msk (_UINT32_(0x1) << CAN_CCCR_PXHD_Pos) /* (CAN_CCCR) Protocol Exception Handling Disable Mask */ +#define CAN_CCCR_PXHD(value) (CAN_CCCR_PXHD_Msk & (_UINT32_(value) << CAN_CCCR_PXHD_Pos)) /* Assigment of value for PXHD in the CAN_CCCR register */ +#define CAN_CCCR_EFBI_Pos _UINT32_(13) /* (CAN_CCCR) Edge Filtering during Bus Integration Position */ +#define CAN_CCCR_EFBI_Msk (_UINT32_(0x1) << CAN_CCCR_EFBI_Pos) /* (CAN_CCCR) Edge Filtering during Bus Integration Mask */ +#define CAN_CCCR_EFBI(value) (CAN_CCCR_EFBI_Msk & (_UINT32_(value) << CAN_CCCR_EFBI_Pos)) /* Assigment of value for EFBI in the CAN_CCCR register */ +#define CAN_CCCR_TXP_Pos _UINT32_(14) /* (CAN_CCCR) Transmit Pause Position */ +#define CAN_CCCR_TXP_Msk (_UINT32_(0x1) << CAN_CCCR_TXP_Pos) /* (CAN_CCCR) Transmit Pause Mask */ +#define CAN_CCCR_TXP(value) (CAN_CCCR_TXP_Msk & (_UINT32_(value) << CAN_CCCR_TXP_Pos)) /* Assigment of value for TXP in the CAN_CCCR register */ +#define CAN_CCCR_Msk _UINT32_(0x000073FF) /* (CAN_CCCR) Register Mask */ + + +/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ +#define CAN_NBTP_RESETVALUE _UINT32_(0x6000A03) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Reset Value */ + +#define CAN_NBTP_NTSEG2_Pos _UINT32_(0) /* (CAN_NBTP) Nominal Time segment after sample point Position */ +#define CAN_NBTP_NTSEG2_Msk (_UINT32_(0x7F) << CAN_NBTP_NTSEG2_Pos) /* (CAN_NBTP) Nominal Time segment after sample point Mask */ +#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG2_Pos)) /* Assigment of value for NTSEG2 in the CAN_NBTP register */ +#define CAN_NBTP_NTSEG1_Pos _UINT32_(8) /* (CAN_NBTP) Nominal Time segment before sample point Position */ +#define CAN_NBTP_NTSEG1_Msk (_UINT32_(0xFF) << CAN_NBTP_NTSEG1_Pos) /* (CAN_NBTP) Nominal Time segment before sample point Mask */ +#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG1_Pos)) /* Assigment of value for NTSEG1 in the CAN_NBTP register */ +#define CAN_NBTP_NBRP_Pos _UINT32_(16) /* (CAN_NBTP) Nominal Baud Rate Prescaler Position */ +#define CAN_NBTP_NBRP_Msk (_UINT32_(0x1FF) << CAN_NBTP_NBRP_Pos) /* (CAN_NBTP) Nominal Baud Rate Prescaler Mask */ +#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & (_UINT32_(value) << CAN_NBTP_NBRP_Pos)) /* Assigment of value for NBRP in the CAN_NBTP register */ +#define CAN_NBTP_NSJW_Pos _UINT32_(25) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Position */ +#define CAN_NBTP_NSJW_Msk (_UINT32_(0x7F) << CAN_NBTP_NSJW_Pos) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Mask */ +#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & (_UINT32_(value) << CAN_NBTP_NSJW_Pos)) /* Assigment of value for NSJW in the CAN_NBTP register */ +#define CAN_NBTP_Msk _UINT32_(0xFFFFFF7F) /* (CAN_NBTP) Register Mask */ + + +/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ +#define CAN_TSCC_RESETVALUE _UINT32_(0x00) /* (CAN_TSCC) Timestamp Counter Configuration Reset Value */ + +#define CAN_TSCC_TSS_Pos _UINT32_(0) /* (CAN_TSCC) Timestamp Select Position */ +#define CAN_TSCC_TSS_Msk (_UINT32_(0x3) << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp Select Mask */ +#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & (_UINT32_(value) << CAN_TSCC_TSS_Pos)) /* Assigment of value for TSS in the CAN_TSCC register */ +#define CAN_TSCC_TSS_ZERO_Val _UINT32_(0x0) /* (CAN_TSCC) Timestamp counter value always 0x0000 */ +#define CAN_TSCC_TSS_INC_Val _UINT32_(0x1) /* (CAN_TSCC) Timestamp counter value incremented by TCP */ +#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value always 0x0000 Position */ +#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value incremented by TCP Position */ +#define CAN_TSCC_TCP_Pos _UINT32_(16) /* (CAN_TSCC) Timestamp Counter Prescaler Position */ +#define CAN_TSCC_TCP_Msk (_UINT32_(0xF) << CAN_TSCC_TCP_Pos) /* (CAN_TSCC) Timestamp Counter Prescaler Mask */ +#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & (_UINT32_(value) << CAN_TSCC_TCP_Pos)) /* Assigment of value for TCP in the CAN_TSCC register */ +#define CAN_TSCC_Msk _UINT32_(0x000F0003) /* (CAN_TSCC) Register Mask */ + + +/* -------- CAN_TSCV : (CAN Offset: 0x24) ( R/ 32) Timestamp Counter Value -------- */ +#define CAN_TSCV_RESETVALUE _UINT32_(0x00) /* (CAN_TSCV) Timestamp Counter Value Reset Value */ + +#define CAN_TSCV_TSC_Pos _UINT32_(0) /* (CAN_TSCV) Timestamp Counter Position */ +#define CAN_TSCV_TSC_Msk (_UINT32_(0xFFFF) << CAN_TSCV_TSC_Pos) /* (CAN_TSCV) Timestamp Counter Mask */ +#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & (_UINT32_(value) << CAN_TSCV_TSC_Pos)) /* Assigment of value for TSC in the CAN_TSCV register */ +#define CAN_TSCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TSCV) Register Mask */ + + +/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ +#define CAN_TOCC_RESETVALUE _UINT32_(0xFFFF0000) /* (CAN_TOCC) Timeout Counter Configuration Reset Value */ + +#define CAN_TOCC_ETOC_Pos _UINT32_(0) /* (CAN_TOCC) Enable Timeout Counter Position */ +#define CAN_TOCC_ETOC_Msk (_UINT32_(0x1) << CAN_TOCC_ETOC_Pos) /* (CAN_TOCC) Enable Timeout Counter Mask */ +#define CAN_TOCC_ETOC(value) (CAN_TOCC_ETOC_Msk & (_UINT32_(value) << CAN_TOCC_ETOC_Pos)) /* Assigment of value for ETOC in the CAN_TOCC register */ +#define CAN_TOCC_TOS_Pos _UINT32_(1) /* (CAN_TOCC) Timeout Select Position */ +#define CAN_TOCC_TOS_Msk (_UINT32_(0x3) << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout Select Mask */ +#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & (_UINT32_(value) << CAN_TOCC_TOS_Pos)) /* Assigment of value for TOS in the CAN_TOCC register */ +#define CAN_TOCC_TOS_CONT_Val _UINT32_(0x0) /* (CAN_TOCC) Continuout operation */ +#define CAN_TOCC_TOS_TXEF_Val _UINT32_(0x1) /* (CAN_TOCC) Timeout controlled by TX Event FIFO */ +#define CAN_TOCC_TOS_RXF0_Val _UINT32_(0x2) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ +#define CAN_TOCC_TOS_RXF1_Val _UINT32_(0x3) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ +#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Continuout operation Position */ +#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by TX Event FIFO Position */ +#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 Position */ +#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 Position */ +#define CAN_TOCC_TOP_Pos _UINT32_(16) /* (CAN_TOCC) Timeout Period Position */ +#define CAN_TOCC_TOP_Msk (_UINT32_(0xFFFF) << CAN_TOCC_TOP_Pos) /* (CAN_TOCC) Timeout Period Mask */ +#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & (_UINT32_(value) << CAN_TOCC_TOP_Pos)) /* Assigment of value for TOP in the CAN_TOCC register */ +#define CAN_TOCC_Msk _UINT32_(0xFFFF0007) /* (CAN_TOCC) Register Mask */ + + +/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ +#define CAN_TOCV_RESETVALUE _UINT32_(0xFFFF) /* (CAN_TOCV) Timeout Counter Value Reset Value */ + +#define CAN_TOCV_TOC_Pos _UINT32_(0) /* (CAN_TOCV) Timeout Counter Position */ +#define CAN_TOCV_TOC_Msk (_UINT32_(0xFFFF) << CAN_TOCV_TOC_Pos) /* (CAN_TOCV) Timeout Counter Mask */ +#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & (_UINT32_(value) << CAN_TOCV_TOC_Pos)) /* Assigment of value for TOC in the CAN_TOCV register */ +#define CAN_TOCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TOCV) Register Mask */ + + +/* -------- CAN_ECR : (CAN Offset: 0x40) ( R/ 32) Error Counter -------- */ +#define CAN_ECR_RESETVALUE _UINT32_(0x00) /* (CAN_ECR) Error Counter Reset Value */ + +#define CAN_ECR_TEC_Pos _UINT32_(0) /* (CAN_ECR) Transmit Error Counter Position */ +#define CAN_ECR_TEC_Msk (_UINT32_(0xFF) << CAN_ECR_TEC_Pos) /* (CAN_ECR) Transmit Error Counter Mask */ +#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & (_UINT32_(value) << CAN_ECR_TEC_Pos)) /* Assigment of value for TEC in the CAN_ECR register */ +#define CAN_ECR_REC_Pos _UINT32_(8) /* (CAN_ECR) Receive Error Counter Position */ +#define CAN_ECR_REC_Msk (_UINT32_(0x7F) << CAN_ECR_REC_Pos) /* (CAN_ECR) Receive Error Counter Mask */ +#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & (_UINT32_(value) << CAN_ECR_REC_Pos)) /* Assigment of value for REC in the CAN_ECR register */ +#define CAN_ECR_RP_Pos _UINT32_(15) /* (CAN_ECR) Receive Error Passive Position */ +#define CAN_ECR_RP_Msk (_UINT32_(0x1) << CAN_ECR_RP_Pos) /* (CAN_ECR) Receive Error Passive Mask */ +#define CAN_ECR_RP(value) (CAN_ECR_RP_Msk & (_UINT32_(value) << CAN_ECR_RP_Pos)) /* Assigment of value for RP in the CAN_ECR register */ +#define CAN_ECR_CEL_Pos _UINT32_(16) /* (CAN_ECR) CAN Error Logging Position */ +#define CAN_ECR_CEL_Msk (_UINT32_(0xFF) << CAN_ECR_CEL_Pos) /* (CAN_ECR) CAN Error Logging Mask */ +#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & (_UINT32_(value) << CAN_ECR_CEL_Pos)) /* Assigment of value for CEL in the CAN_ECR register */ +#define CAN_ECR_Msk _UINT32_(0x00FFFFFF) /* (CAN_ECR) Register Mask */ + + +/* -------- CAN_PSR : (CAN Offset: 0x44) ( R/ 32) Protocol Status -------- */ +#define CAN_PSR_RESETVALUE _UINT32_(0x707) /* (CAN_PSR) Protocol Status Reset Value */ + +#define CAN_PSR_LEC_Pos _UINT32_(0) /* (CAN_PSR) Last Error Code Position */ +#define CAN_PSR_LEC_Msk (_UINT32_(0x7) << CAN_PSR_LEC_Pos) /* (CAN_PSR) Last Error Code Mask */ +#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & (_UINT32_(value) << CAN_PSR_LEC_Pos)) /* Assigment of value for LEC in the CAN_PSR register */ +#define CAN_PSR_LEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ +#define CAN_PSR_LEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ +#define CAN_PSR_LEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ +#define CAN_PSR_LEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ +#define CAN_PSR_LEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ +#define CAN_PSR_LEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ +#define CAN_PSR_LEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ +#define CAN_PSR_LEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ +#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Error Position */ +#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Form Error Position */ +#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Ack Error Position */ +#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) CRC Error Position */ +#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Change Position */ +#define CAN_PSR_ACT_Pos _UINT32_(3) /* (CAN_PSR) Activity Position */ +#define CAN_PSR_ACT_Msk (_UINT32_(0x3) << CAN_PSR_ACT_Pos) /* (CAN_PSR) Activity Mask */ +#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & (_UINT32_(value) << CAN_PSR_ACT_Pos)) /* Assigment of value for ACT in the CAN_PSR register */ +#define CAN_PSR_ACT_SYNC_Val _UINT32_(0x0) /* (CAN_PSR) Node is synchronizing on CAN communication */ +#define CAN_PSR_ACT_IDLE_Val _UINT32_(0x1) /* (CAN_PSR) Node is neither receiver nor transmitter */ +#define CAN_PSR_ACT_RX_Val _UINT32_(0x2) /* (CAN_PSR) Node is operating as receiver */ +#define CAN_PSR_ACT_TX_Val _UINT32_(0x3) /* (CAN_PSR) Node is operating as transmitter */ +#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is synchronizing on CAN communication Position */ +#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is neither receiver nor transmitter Position */ +#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as receiver Position */ +#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as transmitter Position */ +#define CAN_PSR_EP_Pos _UINT32_(5) /* (CAN_PSR) Error Passive Position */ +#define CAN_PSR_EP_Msk (_UINT32_(0x1) << CAN_PSR_EP_Pos) /* (CAN_PSR) Error Passive Mask */ +#define CAN_PSR_EP(value) (CAN_PSR_EP_Msk & (_UINT32_(value) << CAN_PSR_EP_Pos)) /* Assigment of value for EP in the CAN_PSR register */ +#define CAN_PSR_EW_Pos _UINT32_(6) /* (CAN_PSR) Warning Status Position */ +#define CAN_PSR_EW_Msk (_UINT32_(0x1) << CAN_PSR_EW_Pos) /* (CAN_PSR) Warning Status Mask */ +#define CAN_PSR_EW(value) (CAN_PSR_EW_Msk & (_UINT32_(value) << CAN_PSR_EW_Pos)) /* Assigment of value for EW in the CAN_PSR register */ +#define CAN_PSR_BO_Pos _UINT32_(7) /* (CAN_PSR) Bus_Off Status Position */ +#define CAN_PSR_BO_Msk (_UINT32_(0x1) << CAN_PSR_BO_Pos) /* (CAN_PSR) Bus_Off Status Mask */ +#define CAN_PSR_BO(value) (CAN_PSR_BO_Msk & (_UINT32_(value) << CAN_PSR_BO_Pos)) /* Assigment of value for BO in the CAN_PSR register */ +#define CAN_PSR_DLEC_Pos _UINT32_(8) /* (CAN_PSR) Data Phase Last Error Code Position */ +#define CAN_PSR_DLEC_Msk (_UINT32_(0x7) << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Data Phase Last Error Code Mask */ +#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & (_UINT32_(value) << CAN_PSR_DLEC_Pos)) /* Assigment of value for DLEC in the CAN_PSR register */ +#define CAN_PSR_DLEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ +#define CAN_PSR_DLEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ +#define CAN_PSR_DLEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ +#define CAN_PSR_DLEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ +#define CAN_PSR_DLEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ +#define CAN_PSR_DLEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ +#define CAN_PSR_DLEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ +#define CAN_PSR_DLEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ +#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Error Position */ +#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Stuff Error Position */ +#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Form Error Position */ +#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Ack Error Position */ +#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit1 Error Position */ +#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit0 Error Position */ +#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) CRC Error Position */ +#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Change Position */ +#define CAN_PSR_RESI_Pos _UINT32_(11) /* (CAN_PSR) ESI flag of last received CAN FD Message Position */ +#define CAN_PSR_RESI_Msk (_UINT32_(0x1) << CAN_PSR_RESI_Pos) /* (CAN_PSR) ESI flag of last received CAN FD Message Mask */ +#define CAN_PSR_RESI(value) (CAN_PSR_RESI_Msk & (_UINT32_(value) << CAN_PSR_RESI_Pos)) /* Assigment of value for RESI in the CAN_PSR register */ +#define CAN_PSR_RBRS_Pos _UINT32_(12) /* (CAN_PSR) BRS flag of last received CAN FD Message Position */ +#define CAN_PSR_RBRS_Msk (_UINT32_(0x1) << CAN_PSR_RBRS_Pos) /* (CAN_PSR) BRS flag of last received CAN FD Message Mask */ +#define CAN_PSR_RBRS(value) (CAN_PSR_RBRS_Msk & (_UINT32_(value) << CAN_PSR_RBRS_Pos)) /* Assigment of value for RBRS in the CAN_PSR register */ +#define CAN_PSR_RFDF_Pos _UINT32_(13) /* (CAN_PSR) Received a CAN FD Message Position */ +#define CAN_PSR_RFDF_Msk (_UINT32_(0x1) << CAN_PSR_RFDF_Pos) /* (CAN_PSR) Received a CAN FD Message Mask */ +#define CAN_PSR_RFDF(value) (CAN_PSR_RFDF_Msk & (_UINT32_(value) << CAN_PSR_RFDF_Pos)) /* Assigment of value for RFDF in the CAN_PSR register */ +#define CAN_PSR_PXE_Pos _UINT32_(14) /* (CAN_PSR) Protocol Exception Event Position */ +#define CAN_PSR_PXE_Msk (_UINT32_(0x1) << CAN_PSR_PXE_Pos) /* (CAN_PSR) Protocol Exception Event Mask */ +#define CAN_PSR_PXE(value) (CAN_PSR_PXE_Msk & (_UINT32_(value) << CAN_PSR_PXE_Pos)) /* Assigment of value for PXE in the CAN_PSR register */ +#define CAN_PSR_TDCV_Pos _UINT32_(16) /* (CAN_PSR) Transmitter Delay Compensation Value Position */ +#define CAN_PSR_TDCV_Msk (_UINT32_(0x7F) << CAN_PSR_TDCV_Pos) /* (CAN_PSR) Transmitter Delay Compensation Value Mask */ +#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & (_UINT32_(value) << CAN_PSR_TDCV_Pos)) /* Assigment of value for TDCV in the CAN_PSR register */ +#define CAN_PSR_Msk _UINT32_(0x007F7FFF) /* (CAN_PSR) Register Mask */ + + +/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_TDCR_RESETVALUE _UINT32_(0x00) /* (CAN_TDCR) Extended ID Filter Configuration Reset Value */ + +#define CAN_TDCR_TDCF_Pos _UINT32_(0) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Position */ +#define CAN_TDCR_TDCF_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCF_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Mask */ +#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & (_UINT32_(value) << CAN_TDCR_TDCF_Pos)) /* Assigment of value for TDCF in the CAN_TDCR register */ +#define CAN_TDCR_TDCO_Pos _UINT32_(8) /* (CAN_TDCR) Transmitter Delay Compensation Offset Position */ +#define CAN_TDCR_TDCO_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCO_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Offset Mask */ +#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & (_UINT32_(value) << CAN_TDCR_TDCO_Pos)) /* Assigment of value for TDCO in the CAN_TDCR register */ +#define CAN_TDCR_Msk _UINT32_(0x00007F7F) /* (CAN_TDCR) Register Mask */ + + +/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ +#define CAN_IR_RESETVALUE _UINT32_(0x00) /* (CAN_IR) Interrupt Reset Value */ + +#define CAN_IR_RF0N_Pos _UINT32_(0) /* (CAN_IR) Rx FIFO 0 New Message Position */ +#define CAN_IR_RF0N_Msk (_UINT32_(0x1) << CAN_IR_RF0N_Pos) /* (CAN_IR) Rx FIFO 0 New Message Mask */ +#define CAN_IR_RF0N(value) (CAN_IR_RF0N_Msk & (_UINT32_(value) << CAN_IR_RF0N_Pos)) /* Assigment of value for RF0N in the CAN_IR register */ +#define CAN_IR_RF0W_Pos _UINT32_(1) /* (CAN_IR) Rx FIFO 0 Watermark Reached Position */ +#define CAN_IR_RF0W_Msk (_UINT32_(0x1) << CAN_IR_RF0W_Pos) /* (CAN_IR) Rx FIFO 0 Watermark Reached Mask */ +#define CAN_IR_RF0W(value) (CAN_IR_RF0W_Msk & (_UINT32_(value) << CAN_IR_RF0W_Pos)) /* Assigment of value for RF0W in the CAN_IR register */ +#define CAN_IR_RF0F_Pos _UINT32_(2) /* (CAN_IR) Rx FIFO 0 Full Position */ +#define CAN_IR_RF0F_Msk (_UINT32_(0x1) << CAN_IR_RF0F_Pos) /* (CAN_IR) Rx FIFO 0 Full Mask */ +#define CAN_IR_RF0F(value) (CAN_IR_RF0F_Msk & (_UINT32_(value) << CAN_IR_RF0F_Pos)) /* Assigment of value for RF0F in the CAN_IR register */ +#define CAN_IR_RF0L_Pos _UINT32_(3) /* (CAN_IR) Rx FIFO 0 Message Lost Position */ +#define CAN_IR_RF0L_Msk (_UINT32_(0x1) << CAN_IR_RF0L_Pos) /* (CAN_IR) Rx FIFO 0 Message Lost Mask */ +#define CAN_IR_RF0L(value) (CAN_IR_RF0L_Msk & (_UINT32_(value) << CAN_IR_RF0L_Pos)) /* Assigment of value for RF0L in the CAN_IR register */ +#define CAN_IR_RF1N_Pos _UINT32_(4) /* (CAN_IR) Rx FIFO 1 New Message Position */ +#define CAN_IR_RF1N_Msk (_UINT32_(0x1) << CAN_IR_RF1N_Pos) /* (CAN_IR) Rx FIFO 1 New Message Mask */ +#define CAN_IR_RF1N(value) (CAN_IR_RF1N_Msk & (_UINT32_(value) << CAN_IR_RF1N_Pos)) /* Assigment of value for RF1N in the CAN_IR register */ +#define CAN_IR_RF1W_Pos _UINT32_(5) /* (CAN_IR) Rx FIFO 1 Watermark Reached Position */ +#define CAN_IR_RF1W_Msk (_UINT32_(0x1) << CAN_IR_RF1W_Pos) /* (CAN_IR) Rx FIFO 1 Watermark Reached Mask */ +#define CAN_IR_RF1W(value) (CAN_IR_RF1W_Msk & (_UINT32_(value) << CAN_IR_RF1W_Pos)) /* Assigment of value for RF1W in the CAN_IR register */ +#define CAN_IR_RF1F_Pos _UINT32_(6) /* (CAN_IR) Rx FIFO 1 FIFO Full Position */ +#define CAN_IR_RF1F_Msk (_UINT32_(0x1) << CAN_IR_RF1F_Pos) /* (CAN_IR) Rx FIFO 1 FIFO Full Mask */ +#define CAN_IR_RF1F(value) (CAN_IR_RF1F_Msk & (_UINT32_(value) << CAN_IR_RF1F_Pos)) /* Assigment of value for RF1F in the CAN_IR register */ +#define CAN_IR_RF1L_Pos _UINT32_(7) /* (CAN_IR) Rx FIFO 1 Message Lost Position */ +#define CAN_IR_RF1L_Msk (_UINT32_(0x1) << CAN_IR_RF1L_Pos) /* (CAN_IR) Rx FIFO 1 Message Lost Mask */ +#define CAN_IR_RF1L(value) (CAN_IR_RF1L_Msk & (_UINT32_(value) << CAN_IR_RF1L_Pos)) /* Assigment of value for RF1L in the CAN_IR register */ +#define CAN_IR_HPM_Pos _UINT32_(8) /* (CAN_IR) High Priority Message Position */ +#define CAN_IR_HPM_Msk (_UINT32_(0x1) << CAN_IR_HPM_Pos) /* (CAN_IR) High Priority Message Mask */ +#define CAN_IR_HPM(value) (CAN_IR_HPM_Msk & (_UINT32_(value) << CAN_IR_HPM_Pos)) /* Assigment of value for HPM in the CAN_IR register */ +#define CAN_IR_TC_Pos _UINT32_(9) /* (CAN_IR) Timestamp Completed Position */ +#define CAN_IR_TC_Msk (_UINT32_(0x1) << CAN_IR_TC_Pos) /* (CAN_IR) Timestamp Completed Mask */ +#define CAN_IR_TC(value) (CAN_IR_TC_Msk & (_UINT32_(value) << CAN_IR_TC_Pos)) /* Assigment of value for TC in the CAN_IR register */ +#define CAN_IR_TCF_Pos _UINT32_(10) /* (CAN_IR) Transmission Cancellation Finished Position */ +#define CAN_IR_TCF_Msk (_UINT32_(0x1) << CAN_IR_TCF_Pos) /* (CAN_IR) Transmission Cancellation Finished Mask */ +#define CAN_IR_TCF(value) (CAN_IR_TCF_Msk & (_UINT32_(value) << CAN_IR_TCF_Pos)) /* Assigment of value for TCF in the CAN_IR register */ +#define CAN_IR_TFE_Pos _UINT32_(11) /* (CAN_IR) Tx FIFO Empty Position */ +#define CAN_IR_TFE_Msk (_UINT32_(0x1) << CAN_IR_TFE_Pos) /* (CAN_IR) Tx FIFO Empty Mask */ +#define CAN_IR_TFE(value) (CAN_IR_TFE_Msk & (_UINT32_(value) << CAN_IR_TFE_Pos)) /* Assigment of value for TFE in the CAN_IR register */ +#define CAN_IR_TEFN_Pos _UINT32_(12) /* (CAN_IR) Tx Event FIFO New Entry Position */ +#define CAN_IR_TEFN_Msk (_UINT32_(0x1) << CAN_IR_TEFN_Pos) /* (CAN_IR) Tx Event FIFO New Entry Mask */ +#define CAN_IR_TEFN(value) (CAN_IR_TEFN_Msk & (_UINT32_(value) << CAN_IR_TEFN_Pos)) /* Assigment of value for TEFN in the CAN_IR register */ +#define CAN_IR_TEFW_Pos _UINT32_(13) /* (CAN_IR) Tx Event FIFO Watermark Reached Position */ +#define CAN_IR_TEFW_Msk (_UINT32_(0x1) << CAN_IR_TEFW_Pos) /* (CAN_IR) Tx Event FIFO Watermark Reached Mask */ +#define CAN_IR_TEFW(value) (CAN_IR_TEFW_Msk & (_UINT32_(value) << CAN_IR_TEFW_Pos)) /* Assigment of value for TEFW in the CAN_IR register */ +#define CAN_IR_TEFF_Pos _UINT32_(14) /* (CAN_IR) Tx Event FIFO Full Position */ +#define CAN_IR_TEFF_Msk (_UINT32_(0x1) << CAN_IR_TEFF_Pos) /* (CAN_IR) Tx Event FIFO Full Mask */ +#define CAN_IR_TEFF(value) (CAN_IR_TEFF_Msk & (_UINT32_(value) << CAN_IR_TEFF_Pos)) /* Assigment of value for TEFF in the CAN_IR register */ +#define CAN_IR_TEFL_Pos _UINT32_(15) /* (CAN_IR) Tx Event FIFO Element Lost Position */ +#define CAN_IR_TEFL_Msk (_UINT32_(0x1) << CAN_IR_TEFL_Pos) /* (CAN_IR) Tx Event FIFO Element Lost Mask */ +#define CAN_IR_TEFL(value) (CAN_IR_TEFL_Msk & (_UINT32_(value) << CAN_IR_TEFL_Pos)) /* Assigment of value for TEFL in the CAN_IR register */ +#define CAN_IR_TSW_Pos _UINT32_(16) /* (CAN_IR) Timestamp Wraparound Position */ +#define CAN_IR_TSW_Msk (_UINT32_(0x1) << CAN_IR_TSW_Pos) /* (CAN_IR) Timestamp Wraparound Mask */ +#define CAN_IR_TSW(value) (CAN_IR_TSW_Msk & (_UINT32_(value) << CAN_IR_TSW_Pos)) /* Assigment of value for TSW in the CAN_IR register */ +#define CAN_IR_MRAF_Pos _UINT32_(17) /* (CAN_IR) Message RAM Access Failure Position */ +#define CAN_IR_MRAF_Msk (_UINT32_(0x1) << CAN_IR_MRAF_Pos) /* (CAN_IR) Message RAM Access Failure Mask */ +#define CAN_IR_MRAF(value) (CAN_IR_MRAF_Msk & (_UINT32_(value) << CAN_IR_MRAF_Pos)) /* Assigment of value for MRAF in the CAN_IR register */ +#define CAN_IR_TOO_Pos _UINT32_(18) /* (CAN_IR) Timeout Occurred Position */ +#define CAN_IR_TOO_Msk (_UINT32_(0x1) << CAN_IR_TOO_Pos) /* (CAN_IR) Timeout Occurred Mask */ +#define CAN_IR_TOO(value) (CAN_IR_TOO_Msk & (_UINT32_(value) << CAN_IR_TOO_Pos)) /* Assigment of value for TOO in the CAN_IR register */ +#define CAN_IR_DRX_Pos _UINT32_(19) /* (CAN_IR) Message stored to Dedicated Rx Buffer Position */ +#define CAN_IR_DRX_Msk (_UINT32_(0x1) << CAN_IR_DRX_Pos) /* (CAN_IR) Message stored to Dedicated Rx Buffer Mask */ +#define CAN_IR_DRX(value) (CAN_IR_DRX_Msk & (_UINT32_(value) << CAN_IR_DRX_Pos)) /* Assigment of value for DRX in the CAN_IR register */ +#define CAN_IR_BEC_Pos _UINT32_(20) /* (CAN_IR) Bit Error Corrected Position */ +#define CAN_IR_BEC_Msk (_UINT32_(0x1) << CAN_IR_BEC_Pos) /* (CAN_IR) Bit Error Corrected Mask */ +#define CAN_IR_BEC(value) (CAN_IR_BEC_Msk & (_UINT32_(value) << CAN_IR_BEC_Pos)) /* Assigment of value for BEC in the CAN_IR register */ +#define CAN_IR_BEU_Pos _UINT32_(21) /* (CAN_IR) Bit Error Uncorrected Position */ +#define CAN_IR_BEU_Msk (_UINT32_(0x1) << CAN_IR_BEU_Pos) /* (CAN_IR) Bit Error Uncorrected Mask */ +#define CAN_IR_BEU(value) (CAN_IR_BEU_Msk & (_UINT32_(value) << CAN_IR_BEU_Pos)) /* Assigment of value for BEU in the CAN_IR register */ +#define CAN_IR_ELO_Pos _UINT32_(22) /* (CAN_IR) Error Logging Overflow Position */ +#define CAN_IR_ELO_Msk (_UINT32_(0x1) << CAN_IR_ELO_Pos) /* (CAN_IR) Error Logging Overflow Mask */ +#define CAN_IR_ELO(value) (CAN_IR_ELO_Msk & (_UINT32_(value) << CAN_IR_ELO_Pos)) /* Assigment of value for ELO in the CAN_IR register */ +#define CAN_IR_EP_Pos _UINT32_(23) /* (CAN_IR) Error Passive Position */ +#define CAN_IR_EP_Msk (_UINT32_(0x1) << CAN_IR_EP_Pos) /* (CAN_IR) Error Passive Mask */ +#define CAN_IR_EP(value) (CAN_IR_EP_Msk & (_UINT32_(value) << CAN_IR_EP_Pos)) /* Assigment of value for EP in the CAN_IR register */ +#define CAN_IR_EW_Pos _UINT32_(24) /* (CAN_IR) Warning Status Position */ +#define CAN_IR_EW_Msk (_UINT32_(0x1) << CAN_IR_EW_Pos) /* (CAN_IR) Warning Status Mask */ +#define CAN_IR_EW(value) (CAN_IR_EW_Msk & (_UINT32_(value) << CAN_IR_EW_Pos)) /* Assigment of value for EW in the CAN_IR register */ +#define CAN_IR_BO_Pos _UINT32_(25) /* (CAN_IR) Bus_Off Status Position */ +#define CAN_IR_BO_Msk (_UINT32_(0x1) << CAN_IR_BO_Pos) /* (CAN_IR) Bus_Off Status Mask */ +#define CAN_IR_BO(value) (CAN_IR_BO_Msk & (_UINT32_(value) << CAN_IR_BO_Pos)) /* Assigment of value for BO in the CAN_IR register */ +#define CAN_IR_WDI_Pos _UINT32_(26) /* (CAN_IR) Watchdog Interrupt Position */ +#define CAN_IR_WDI_Msk (_UINT32_(0x1) << CAN_IR_WDI_Pos) /* (CAN_IR) Watchdog Interrupt Mask */ +#define CAN_IR_WDI(value) (CAN_IR_WDI_Msk & (_UINT32_(value) << CAN_IR_WDI_Pos)) /* Assigment of value for WDI in the CAN_IR register */ +#define CAN_IR_PEA_Pos _UINT32_(27) /* (CAN_IR) Protocol Error in Arbitration Phase Position */ +#define CAN_IR_PEA_Msk (_UINT32_(0x1) << CAN_IR_PEA_Pos) /* (CAN_IR) Protocol Error in Arbitration Phase Mask */ +#define CAN_IR_PEA(value) (CAN_IR_PEA_Msk & (_UINT32_(value) << CAN_IR_PEA_Pos)) /* Assigment of value for PEA in the CAN_IR register */ +#define CAN_IR_PED_Pos _UINT32_(28) /* (CAN_IR) Protocol Error in Data Phase Position */ +#define CAN_IR_PED_Msk (_UINT32_(0x1) << CAN_IR_PED_Pos) /* (CAN_IR) Protocol Error in Data Phase Mask */ +#define CAN_IR_PED(value) (CAN_IR_PED_Msk & (_UINT32_(value) << CAN_IR_PED_Pos)) /* Assigment of value for PED in the CAN_IR register */ +#define CAN_IR_ARA_Pos _UINT32_(29) /* (CAN_IR) Access to Reserved Address Position */ +#define CAN_IR_ARA_Msk (_UINT32_(0x1) << CAN_IR_ARA_Pos) /* (CAN_IR) Access to Reserved Address Mask */ +#define CAN_IR_ARA(value) (CAN_IR_ARA_Msk & (_UINT32_(value) << CAN_IR_ARA_Pos)) /* Assigment of value for ARA in the CAN_IR register */ +#define CAN_IR_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IR) Register Mask */ + + +/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ +#define CAN_IE_RESETVALUE _UINT32_(0x00) /* (CAN_IE) Interrupt Enable Reset Value */ + +#define CAN_IE_RF0NE_Pos _UINT32_(0) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Position */ +#define CAN_IE_RF0NE_Msk (_UINT32_(0x1) << CAN_IE_RF0NE_Pos) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Mask */ +#define CAN_IE_RF0NE(value) (CAN_IE_RF0NE_Msk & (_UINT32_(value) << CAN_IE_RF0NE_Pos)) /* Assigment of value for RF0NE in the CAN_IE register */ +#define CAN_IE_RF0WE_Pos _UINT32_(1) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF0WE_Msk (_UINT32_(0x1) << CAN_IE_RF0WE_Pos) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF0WE(value) (CAN_IE_RF0WE_Msk & (_UINT32_(value) << CAN_IE_RF0WE_Pos)) /* Assigment of value for RF0WE in the CAN_IE register */ +#define CAN_IE_RF0FE_Pos _UINT32_(2) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Position */ +#define CAN_IE_RF0FE_Msk (_UINT32_(0x1) << CAN_IE_RF0FE_Pos) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Mask */ +#define CAN_IE_RF0FE(value) (CAN_IE_RF0FE_Msk & (_UINT32_(value) << CAN_IE_RF0FE_Pos)) /* Assigment of value for RF0FE in the CAN_IE register */ +#define CAN_IE_RF0LE_Pos _UINT32_(3) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF0LE_Msk (_UINT32_(0x1) << CAN_IE_RF0LE_Pos) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF0LE(value) (CAN_IE_RF0LE_Msk & (_UINT32_(value) << CAN_IE_RF0LE_Pos)) /* Assigment of value for RF0LE in the CAN_IE register */ +#define CAN_IE_RF1NE_Pos _UINT32_(4) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Position */ +#define CAN_IE_RF1NE_Msk (_UINT32_(0x1) << CAN_IE_RF1NE_Pos) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Mask */ +#define CAN_IE_RF1NE(value) (CAN_IE_RF1NE_Msk & (_UINT32_(value) << CAN_IE_RF1NE_Pos)) /* Assigment of value for RF1NE in the CAN_IE register */ +#define CAN_IE_RF1WE_Pos _UINT32_(5) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Position */ +#define CAN_IE_RF1WE_Msk (_UINT32_(0x1) << CAN_IE_RF1WE_Pos) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_RF1WE(value) (CAN_IE_RF1WE_Msk & (_UINT32_(value) << CAN_IE_RF1WE_Pos)) /* Assigment of value for RF1WE in the CAN_IE register */ +#define CAN_IE_RF1FE_Pos _UINT32_(6) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Position */ +#define CAN_IE_RF1FE_Msk (_UINT32_(0x1) << CAN_IE_RF1FE_Pos) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Mask */ +#define CAN_IE_RF1FE(value) (CAN_IE_RF1FE_Msk & (_UINT32_(value) << CAN_IE_RF1FE_Pos)) /* Assigment of value for RF1FE in the CAN_IE register */ +#define CAN_IE_RF1LE_Pos _UINT32_(7) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Position */ +#define CAN_IE_RF1LE_Msk (_UINT32_(0x1) << CAN_IE_RF1LE_Pos) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Mask */ +#define CAN_IE_RF1LE(value) (CAN_IE_RF1LE_Msk & (_UINT32_(value) << CAN_IE_RF1LE_Pos)) /* Assigment of value for RF1LE in the CAN_IE register */ +#define CAN_IE_HPME_Pos _UINT32_(8) /* (CAN_IE) High Priority Message Interrupt Enable Position */ +#define CAN_IE_HPME_Msk (_UINT32_(0x1) << CAN_IE_HPME_Pos) /* (CAN_IE) High Priority Message Interrupt Enable Mask */ +#define CAN_IE_HPME(value) (CAN_IE_HPME_Msk & (_UINT32_(value) << CAN_IE_HPME_Pos)) /* Assigment of value for HPME in the CAN_IE register */ +#define CAN_IE_TCE_Pos _UINT32_(9) /* (CAN_IE) Timestamp Completed Interrupt Enable Position */ +#define CAN_IE_TCE_Msk (_UINT32_(0x1) << CAN_IE_TCE_Pos) /* (CAN_IE) Timestamp Completed Interrupt Enable Mask */ +#define CAN_IE_TCE(value) (CAN_IE_TCE_Msk & (_UINT32_(value) << CAN_IE_TCE_Pos)) /* Assigment of value for TCE in the CAN_IE register */ +#define CAN_IE_TCFE_Pos _UINT32_(10) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ +#define CAN_IE_TCFE_Msk (_UINT32_(0x1) << CAN_IE_TCFE_Pos) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ +#define CAN_IE_TCFE(value) (CAN_IE_TCFE_Msk & (_UINT32_(value) << CAN_IE_TCFE_Pos)) /* Assigment of value for TCFE in the CAN_IE register */ +#define CAN_IE_TFEE_Pos _UINT32_(11) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Position */ +#define CAN_IE_TFEE_Msk (_UINT32_(0x1) << CAN_IE_TFEE_Pos) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Mask */ +#define CAN_IE_TFEE(value) (CAN_IE_TFEE_Msk & (_UINT32_(value) << CAN_IE_TFEE_Pos)) /* Assigment of value for TFEE in the CAN_IE register */ +#define CAN_IE_TEFNE_Pos _UINT32_(12) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ +#define CAN_IE_TEFNE_Msk (_UINT32_(0x1) << CAN_IE_TEFNE_Pos) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ +#define CAN_IE_TEFNE(value) (CAN_IE_TEFNE_Msk & (_UINT32_(value) << CAN_IE_TEFNE_Pos)) /* Assigment of value for TEFNE in the CAN_IE register */ +#define CAN_IE_TEFWE_Pos _UINT32_(13) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ +#define CAN_IE_TEFWE_Msk (_UINT32_(0x1) << CAN_IE_TEFWE_Pos) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ +#define CAN_IE_TEFWE(value) (CAN_IE_TEFWE_Msk & (_UINT32_(value) << CAN_IE_TEFWE_Pos)) /* Assigment of value for TEFWE in the CAN_IE register */ +#define CAN_IE_TEFFE_Pos _UINT32_(14) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Position */ +#define CAN_IE_TEFFE_Msk (_UINT32_(0x1) << CAN_IE_TEFFE_Pos) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ +#define CAN_IE_TEFFE(value) (CAN_IE_TEFFE_Msk & (_UINT32_(value) << CAN_IE_TEFFE_Pos)) /* Assigment of value for TEFFE in the CAN_IE register */ +#define CAN_IE_TEFLE_Pos _UINT32_(15) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Position */ +#define CAN_IE_TEFLE_Msk (_UINT32_(0x1) << CAN_IE_TEFLE_Pos) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Mask */ +#define CAN_IE_TEFLE(value) (CAN_IE_TEFLE_Msk & (_UINT32_(value) << CAN_IE_TEFLE_Pos)) /* Assigment of value for TEFLE in the CAN_IE register */ +#define CAN_IE_TSWE_Pos _UINT32_(16) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Position */ +#define CAN_IE_TSWE_Msk (_UINT32_(0x1) << CAN_IE_TSWE_Pos) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Mask */ +#define CAN_IE_TSWE(value) (CAN_IE_TSWE_Msk & (_UINT32_(value) << CAN_IE_TSWE_Pos)) /* Assigment of value for TSWE in the CAN_IE register */ +#define CAN_IE_MRAFE_Pos _UINT32_(17) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Position */ +#define CAN_IE_MRAFE_Msk (_UINT32_(0x1) << CAN_IE_MRAFE_Pos) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Mask */ +#define CAN_IE_MRAFE(value) (CAN_IE_MRAFE_Msk & (_UINT32_(value) << CAN_IE_MRAFE_Pos)) /* Assigment of value for MRAFE in the CAN_IE register */ +#define CAN_IE_TOOE_Pos _UINT32_(18) /* (CAN_IE) Timeout Occurred Interrupt Enable Position */ +#define CAN_IE_TOOE_Msk (_UINT32_(0x1) << CAN_IE_TOOE_Pos) /* (CAN_IE) Timeout Occurred Interrupt Enable Mask */ +#define CAN_IE_TOOE(value) (CAN_IE_TOOE_Msk & (_UINT32_(value) << CAN_IE_TOOE_Pos)) /* Assigment of value for TOOE in the CAN_IE register */ +#define CAN_IE_DRXE_Pos _UINT32_(19) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Position */ +#define CAN_IE_DRXE_Msk (_UINT32_(0x1) << CAN_IE_DRXE_Pos) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Mask */ +#define CAN_IE_DRXE(value) (CAN_IE_DRXE_Msk & (_UINT32_(value) << CAN_IE_DRXE_Pos)) /* Assigment of value for DRXE in the CAN_IE register */ +#define CAN_IE_BECE_Pos _UINT32_(20) /* (CAN_IE) Bit Error Corrected Interrupt Enable Position */ +#define CAN_IE_BECE_Msk (_UINT32_(0x1) << CAN_IE_BECE_Pos) /* (CAN_IE) Bit Error Corrected Interrupt Enable Mask */ +#define CAN_IE_BECE(value) (CAN_IE_BECE_Msk & (_UINT32_(value) << CAN_IE_BECE_Pos)) /* Assigment of value for BECE in the CAN_IE register */ +#define CAN_IE_BEUE_Pos _UINT32_(21) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Position */ +#define CAN_IE_BEUE_Msk (_UINT32_(0x1) << CAN_IE_BEUE_Pos) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Mask */ +#define CAN_IE_BEUE(value) (CAN_IE_BEUE_Msk & (_UINT32_(value) << CAN_IE_BEUE_Pos)) /* Assigment of value for BEUE in the CAN_IE register */ +#define CAN_IE_ELOE_Pos _UINT32_(22) /* (CAN_IE) Error Logging Overflow Interrupt Enable Position */ +#define CAN_IE_ELOE_Msk (_UINT32_(0x1) << CAN_IE_ELOE_Pos) /* (CAN_IE) Error Logging Overflow Interrupt Enable Mask */ +#define CAN_IE_ELOE(value) (CAN_IE_ELOE_Msk & (_UINT32_(value) << CAN_IE_ELOE_Pos)) /* Assigment of value for ELOE in the CAN_IE register */ +#define CAN_IE_EPE_Pos _UINT32_(23) /* (CAN_IE) Error Passive Interrupt Enable Position */ +#define CAN_IE_EPE_Msk (_UINT32_(0x1) << CAN_IE_EPE_Pos) /* (CAN_IE) Error Passive Interrupt Enable Mask */ +#define CAN_IE_EPE(value) (CAN_IE_EPE_Msk & (_UINT32_(value) << CAN_IE_EPE_Pos)) /* Assigment of value for EPE in the CAN_IE register */ +#define CAN_IE_EWE_Pos _UINT32_(24) /* (CAN_IE) Warning Status Interrupt Enable Position */ +#define CAN_IE_EWE_Msk (_UINT32_(0x1) << CAN_IE_EWE_Pos) /* (CAN_IE) Warning Status Interrupt Enable Mask */ +#define CAN_IE_EWE(value) (CAN_IE_EWE_Msk & (_UINT32_(value) << CAN_IE_EWE_Pos)) /* Assigment of value for EWE in the CAN_IE register */ +#define CAN_IE_BOE_Pos _UINT32_(25) /* (CAN_IE) Bus_Off Status Interrupt Enable Position */ +#define CAN_IE_BOE_Msk (_UINT32_(0x1) << CAN_IE_BOE_Pos) /* (CAN_IE) Bus_Off Status Interrupt Enable Mask */ +#define CAN_IE_BOE(value) (CAN_IE_BOE_Msk & (_UINT32_(value) << CAN_IE_BOE_Pos)) /* Assigment of value for BOE in the CAN_IE register */ +#define CAN_IE_WDIE_Pos _UINT32_(26) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Position */ +#define CAN_IE_WDIE_Msk (_UINT32_(0x1) << CAN_IE_WDIE_Pos) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Mask */ +#define CAN_IE_WDIE(value) (CAN_IE_WDIE_Msk & (_UINT32_(value) << CAN_IE_WDIE_Pos)) /* Assigment of value for WDIE in the CAN_IE register */ +#define CAN_IE_PEAE_Pos _UINT32_(27) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Position */ +#define CAN_IE_PEAE_Msk (_UINT32_(0x1) << CAN_IE_PEAE_Pos) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Mask */ +#define CAN_IE_PEAE(value) (CAN_IE_PEAE_Msk & (_UINT32_(value) << CAN_IE_PEAE_Pos)) /* Assigment of value for PEAE in the CAN_IE register */ +#define CAN_IE_PEDE_Pos _UINT32_(28) /* (CAN_IE) Protocol Error in Data Phase Enable Position */ +#define CAN_IE_PEDE_Msk (_UINT32_(0x1) << CAN_IE_PEDE_Pos) /* (CAN_IE) Protocol Error in Data Phase Enable Mask */ +#define CAN_IE_PEDE(value) (CAN_IE_PEDE_Msk & (_UINT32_(value) << CAN_IE_PEDE_Pos)) /* Assigment of value for PEDE in the CAN_IE register */ +#define CAN_IE_ARAE_Pos _UINT32_(29) /* (CAN_IE) Access to Reserved Address Enable Position */ +#define CAN_IE_ARAE_Msk (_UINT32_(0x1) << CAN_IE_ARAE_Pos) /* (CAN_IE) Access to Reserved Address Enable Mask */ +#define CAN_IE_ARAE(value) (CAN_IE_ARAE_Msk & (_UINT32_(value) << CAN_IE_ARAE_Pos)) /* Assigment of value for ARAE in the CAN_IE register */ +#define CAN_IE_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IE) Register Mask */ + + +/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ +#define CAN_ILS_RESETVALUE _UINT32_(0x00) /* (CAN_ILS) Interrupt Line Select Reset Value */ + +#define CAN_ILS_RF0NL_Pos _UINT32_(0) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Position */ +#define CAN_ILS_RF0NL_Msk (_UINT32_(0x1) << CAN_ILS_RF0NL_Pos) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Mask */ +#define CAN_ILS_RF0NL(value) (CAN_ILS_RF0NL_Msk & (_UINT32_(value) << CAN_ILS_RF0NL_Pos)) /* Assigment of value for RF0NL in the CAN_ILS register */ +#define CAN_ILS_RF0WL_Pos _UINT32_(1) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF0WL_Msk (_UINT32_(0x1) << CAN_ILS_RF0WL_Pos) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF0WL(value) (CAN_ILS_RF0WL_Msk & (_UINT32_(value) << CAN_ILS_RF0WL_Pos)) /* Assigment of value for RF0WL in the CAN_ILS register */ +#define CAN_ILS_RF0FL_Pos _UINT32_(2) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Position */ +#define CAN_ILS_RF0FL_Msk (_UINT32_(0x1) << CAN_ILS_RF0FL_Pos) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Mask */ +#define CAN_ILS_RF0FL(value) (CAN_ILS_RF0FL_Msk & (_UINT32_(value) << CAN_ILS_RF0FL_Pos)) /* Assigment of value for RF0FL in the CAN_ILS register */ +#define CAN_ILS_RF0LL_Pos _UINT32_(3) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF0LL_Msk (_UINT32_(0x1) << CAN_ILS_RF0LL_Pos) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF0LL(value) (CAN_ILS_RF0LL_Msk & (_UINT32_(value) << CAN_ILS_RF0LL_Pos)) /* Assigment of value for RF0LL in the CAN_ILS register */ +#define CAN_ILS_RF1NL_Pos _UINT32_(4) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Position */ +#define CAN_ILS_RF1NL_Msk (_UINT32_(0x1) << CAN_ILS_RF1NL_Pos) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Mask */ +#define CAN_ILS_RF1NL(value) (CAN_ILS_RF1NL_Msk & (_UINT32_(value) << CAN_ILS_RF1NL_Pos)) /* Assigment of value for RF1NL in the CAN_ILS register */ +#define CAN_ILS_RF1WL_Pos _UINT32_(5) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Position */ +#define CAN_ILS_RF1WL_Msk (_UINT32_(0x1) << CAN_ILS_RF1WL_Pos) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_RF1WL(value) (CAN_ILS_RF1WL_Msk & (_UINT32_(value) << CAN_ILS_RF1WL_Pos)) /* Assigment of value for RF1WL in the CAN_ILS register */ +#define CAN_ILS_RF1FL_Pos _UINT32_(6) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Position */ +#define CAN_ILS_RF1FL_Msk (_UINT32_(0x1) << CAN_ILS_RF1FL_Pos) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Mask */ +#define CAN_ILS_RF1FL(value) (CAN_ILS_RF1FL_Msk & (_UINT32_(value) << CAN_ILS_RF1FL_Pos)) /* Assigment of value for RF1FL in the CAN_ILS register */ +#define CAN_ILS_RF1LL_Pos _UINT32_(7) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Position */ +#define CAN_ILS_RF1LL_Msk (_UINT32_(0x1) << CAN_ILS_RF1LL_Pos) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Mask */ +#define CAN_ILS_RF1LL(value) (CAN_ILS_RF1LL_Msk & (_UINT32_(value) << CAN_ILS_RF1LL_Pos)) /* Assigment of value for RF1LL in the CAN_ILS register */ +#define CAN_ILS_HPML_Pos _UINT32_(8) /* (CAN_ILS) High Priority Message Interrupt Line Position */ +#define CAN_ILS_HPML_Msk (_UINT32_(0x1) << CAN_ILS_HPML_Pos) /* (CAN_ILS) High Priority Message Interrupt Line Mask */ +#define CAN_ILS_HPML(value) (CAN_ILS_HPML_Msk & (_UINT32_(value) << CAN_ILS_HPML_Pos)) /* Assigment of value for HPML in the CAN_ILS register */ +#define CAN_ILS_TCL_Pos _UINT32_(9) /* (CAN_ILS) Timestamp Completed Interrupt Line Position */ +#define CAN_ILS_TCL_Msk (_UINT32_(0x1) << CAN_ILS_TCL_Pos) /* (CAN_ILS) Timestamp Completed Interrupt Line Mask */ +#define CAN_ILS_TCL(value) (CAN_ILS_TCL_Msk & (_UINT32_(value) << CAN_ILS_TCL_Pos)) /* Assigment of value for TCL in the CAN_ILS register */ +#define CAN_ILS_TCFL_Pos _UINT32_(10) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ +#define CAN_ILS_TCFL_Msk (_UINT32_(0x1) << CAN_ILS_TCFL_Pos) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ +#define CAN_ILS_TCFL(value) (CAN_ILS_TCFL_Msk & (_UINT32_(value) << CAN_ILS_TCFL_Pos)) /* Assigment of value for TCFL in the CAN_ILS register */ +#define CAN_ILS_TFEL_Pos _UINT32_(11) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Position */ +#define CAN_ILS_TFEL_Msk (_UINT32_(0x1) << CAN_ILS_TFEL_Pos) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Mask */ +#define CAN_ILS_TFEL(value) (CAN_ILS_TFEL_Msk & (_UINT32_(value) << CAN_ILS_TFEL_Pos)) /* Assigment of value for TFEL in the CAN_ILS register */ +#define CAN_ILS_TEFNL_Pos _UINT32_(12) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ +#define CAN_ILS_TEFNL_Msk (_UINT32_(0x1) << CAN_ILS_TEFNL_Pos) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ +#define CAN_ILS_TEFNL(value) (CAN_ILS_TEFNL_Msk & (_UINT32_(value) << CAN_ILS_TEFNL_Pos)) /* Assigment of value for TEFNL in the CAN_ILS register */ +#define CAN_ILS_TEFWL_Pos _UINT32_(13) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ +#define CAN_ILS_TEFWL_Msk (_UINT32_(0x1) << CAN_ILS_TEFWL_Pos) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ +#define CAN_ILS_TEFWL(value) (CAN_ILS_TEFWL_Msk & (_UINT32_(value) << CAN_ILS_TEFWL_Pos)) /* Assigment of value for TEFWL in the CAN_ILS register */ +#define CAN_ILS_TEFFL_Pos _UINT32_(14) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Position */ +#define CAN_ILS_TEFFL_Msk (_UINT32_(0x1) << CAN_ILS_TEFFL_Pos) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ +#define CAN_ILS_TEFFL(value) (CAN_ILS_TEFFL_Msk & (_UINT32_(value) << CAN_ILS_TEFFL_Pos)) /* Assigment of value for TEFFL in the CAN_ILS register */ +#define CAN_ILS_TEFLL_Pos _UINT32_(15) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Position */ +#define CAN_ILS_TEFLL_Msk (_UINT32_(0x1) << CAN_ILS_TEFLL_Pos) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Mask */ +#define CAN_ILS_TEFLL(value) (CAN_ILS_TEFLL_Msk & (_UINT32_(value) << CAN_ILS_TEFLL_Pos)) /* Assigment of value for TEFLL in the CAN_ILS register */ +#define CAN_ILS_TSWL_Pos _UINT32_(16) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Position */ +#define CAN_ILS_TSWL_Msk (_UINT32_(0x1) << CAN_ILS_TSWL_Pos) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Mask */ +#define CAN_ILS_TSWL(value) (CAN_ILS_TSWL_Msk & (_UINT32_(value) << CAN_ILS_TSWL_Pos)) /* Assigment of value for TSWL in the CAN_ILS register */ +#define CAN_ILS_MRAFL_Pos _UINT32_(17) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Position */ +#define CAN_ILS_MRAFL_Msk (_UINT32_(0x1) << CAN_ILS_MRAFL_Pos) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Mask */ +#define CAN_ILS_MRAFL(value) (CAN_ILS_MRAFL_Msk & (_UINT32_(value) << CAN_ILS_MRAFL_Pos)) /* Assigment of value for MRAFL in the CAN_ILS register */ +#define CAN_ILS_TOOL_Pos _UINT32_(18) /* (CAN_ILS) Timeout Occurred Interrupt Line Position */ +#define CAN_ILS_TOOL_Msk (_UINT32_(0x1) << CAN_ILS_TOOL_Pos) /* (CAN_ILS) Timeout Occurred Interrupt Line Mask */ +#define CAN_ILS_TOOL(value) (CAN_ILS_TOOL_Msk & (_UINT32_(value) << CAN_ILS_TOOL_Pos)) /* Assigment of value for TOOL in the CAN_ILS register */ +#define CAN_ILS_DRXL_Pos _UINT32_(19) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Position */ +#define CAN_ILS_DRXL_Msk (_UINT32_(0x1) << CAN_ILS_DRXL_Pos) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Mask */ +#define CAN_ILS_DRXL(value) (CAN_ILS_DRXL_Msk & (_UINT32_(value) << CAN_ILS_DRXL_Pos)) /* Assigment of value for DRXL in the CAN_ILS register */ +#define CAN_ILS_BECL_Pos _UINT32_(20) /* (CAN_ILS) Bit Error Corrected Interrupt Line Position */ +#define CAN_ILS_BECL_Msk (_UINT32_(0x1) << CAN_ILS_BECL_Pos) /* (CAN_ILS) Bit Error Corrected Interrupt Line Mask */ +#define CAN_ILS_BECL(value) (CAN_ILS_BECL_Msk & (_UINT32_(value) << CAN_ILS_BECL_Pos)) /* Assigment of value for BECL in the CAN_ILS register */ +#define CAN_ILS_BEUL_Pos _UINT32_(21) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Position */ +#define CAN_ILS_BEUL_Msk (_UINT32_(0x1) << CAN_ILS_BEUL_Pos) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Mask */ +#define CAN_ILS_BEUL(value) (CAN_ILS_BEUL_Msk & (_UINT32_(value) << CAN_ILS_BEUL_Pos)) /* Assigment of value for BEUL in the CAN_ILS register */ +#define CAN_ILS_ELOL_Pos _UINT32_(22) /* (CAN_ILS) Error Logging Overflow Interrupt Line Position */ +#define CAN_ILS_ELOL_Msk (_UINT32_(0x1) << CAN_ILS_ELOL_Pos) /* (CAN_ILS) Error Logging Overflow Interrupt Line Mask */ +#define CAN_ILS_ELOL(value) (CAN_ILS_ELOL_Msk & (_UINT32_(value) << CAN_ILS_ELOL_Pos)) /* Assigment of value for ELOL in the CAN_ILS register */ +#define CAN_ILS_EPL_Pos _UINT32_(23) /* (CAN_ILS) Error Passive Interrupt Line Position */ +#define CAN_ILS_EPL_Msk (_UINT32_(0x1) << CAN_ILS_EPL_Pos) /* (CAN_ILS) Error Passive Interrupt Line Mask */ +#define CAN_ILS_EPL(value) (CAN_ILS_EPL_Msk & (_UINT32_(value) << CAN_ILS_EPL_Pos)) /* Assigment of value for EPL in the CAN_ILS register */ +#define CAN_ILS_EWL_Pos _UINT32_(24) /* (CAN_ILS) Warning Status Interrupt Line Position */ +#define CAN_ILS_EWL_Msk (_UINT32_(0x1) << CAN_ILS_EWL_Pos) /* (CAN_ILS) Warning Status Interrupt Line Mask */ +#define CAN_ILS_EWL(value) (CAN_ILS_EWL_Msk & (_UINT32_(value) << CAN_ILS_EWL_Pos)) /* Assigment of value for EWL in the CAN_ILS register */ +#define CAN_ILS_BOL_Pos _UINT32_(25) /* (CAN_ILS) Bus_Off Status Interrupt Line Position */ +#define CAN_ILS_BOL_Msk (_UINT32_(0x1) << CAN_ILS_BOL_Pos) /* (CAN_ILS) Bus_Off Status Interrupt Line Mask */ +#define CAN_ILS_BOL(value) (CAN_ILS_BOL_Msk & (_UINT32_(value) << CAN_ILS_BOL_Pos)) /* Assigment of value for BOL in the CAN_ILS register */ +#define CAN_ILS_WDIL_Pos _UINT32_(26) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Position */ +#define CAN_ILS_WDIL_Msk (_UINT32_(0x1) << CAN_ILS_WDIL_Pos) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Mask */ +#define CAN_ILS_WDIL(value) (CAN_ILS_WDIL_Msk & (_UINT32_(value) << CAN_ILS_WDIL_Pos)) /* Assigment of value for WDIL in the CAN_ILS register */ +#define CAN_ILS_PEAL_Pos _UINT32_(27) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Position */ +#define CAN_ILS_PEAL_Msk (_UINT32_(0x1) << CAN_ILS_PEAL_Pos) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Mask */ +#define CAN_ILS_PEAL(value) (CAN_ILS_PEAL_Msk & (_UINT32_(value) << CAN_ILS_PEAL_Pos)) /* Assigment of value for PEAL in the CAN_ILS register */ +#define CAN_ILS_PEDL_Pos _UINT32_(28) /* (CAN_ILS) Protocol Error in Data Phase Line Position */ +#define CAN_ILS_PEDL_Msk (_UINT32_(0x1) << CAN_ILS_PEDL_Pos) /* (CAN_ILS) Protocol Error in Data Phase Line Mask */ +#define CAN_ILS_PEDL(value) (CAN_ILS_PEDL_Msk & (_UINT32_(value) << CAN_ILS_PEDL_Pos)) /* Assigment of value for PEDL in the CAN_ILS register */ +#define CAN_ILS_ARAL_Pos _UINT32_(29) /* (CAN_ILS) Access to Reserved Address Line Position */ +#define CAN_ILS_ARAL_Msk (_UINT32_(0x1) << CAN_ILS_ARAL_Pos) /* (CAN_ILS) Access to Reserved Address Line Mask */ +#define CAN_ILS_ARAL(value) (CAN_ILS_ARAL_Msk & (_UINT32_(value) << CAN_ILS_ARAL_Pos)) /* Assigment of value for ARAL in the CAN_ILS register */ +#define CAN_ILS_Msk _UINT32_(0x3FFFFFFF) /* (CAN_ILS) Register Mask */ + + +/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ +#define CAN_ILE_RESETVALUE _UINT32_(0x00) /* (CAN_ILE) Interrupt Line Enable Reset Value */ + +#define CAN_ILE_EINT0_Pos _UINT32_(0) /* (CAN_ILE) Enable Interrupt Line 0 Position */ +#define CAN_ILE_EINT0_Msk (_UINT32_(0x1) << CAN_ILE_EINT0_Pos) /* (CAN_ILE) Enable Interrupt Line 0 Mask */ +#define CAN_ILE_EINT0(value) (CAN_ILE_EINT0_Msk & (_UINT32_(value) << CAN_ILE_EINT0_Pos)) /* Assigment of value for EINT0 in the CAN_ILE register */ +#define CAN_ILE_EINT1_Pos _UINT32_(1) /* (CAN_ILE) Enable Interrupt Line 1 Position */ +#define CAN_ILE_EINT1_Msk (_UINT32_(0x1) << CAN_ILE_EINT1_Pos) /* (CAN_ILE) Enable Interrupt Line 1 Mask */ +#define CAN_ILE_EINT1(value) (CAN_ILE_EINT1_Msk & (_UINT32_(value) << CAN_ILE_EINT1_Pos)) /* Assigment of value for EINT1 in the CAN_ILE register */ +#define CAN_ILE_Msk _UINT32_(0x00000003) /* (CAN_ILE) Register Mask */ + +#define CAN_ILE_EINT_Pos _UINT32_(0) /* (CAN_ILE Position) Enable Interrupt Line x */ +#define CAN_ILE_EINT_Msk (_UINT32_(0x3) << CAN_ILE_EINT_Pos) /* (CAN_ILE Mask) EINT */ +#define CAN_ILE_EINT(value) (CAN_ILE_EINT_Msk & (_UINT32_(value) << CAN_ILE_EINT_Pos)) + +/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ +#define CAN_GFC_RESETVALUE _UINT32_(0x00) /* (CAN_GFC) Global Filter Configuration Reset Value */ + +#define CAN_GFC_RRFE_Pos _UINT32_(0) /* (CAN_GFC) Reject Remote Frames Extended Position */ +#define CAN_GFC_RRFE_Msk (_UINT32_(0x1) << CAN_GFC_RRFE_Pos) /* (CAN_GFC) Reject Remote Frames Extended Mask */ +#define CAN_GFC_RRFE(value) (CAN_GFC_RRFE_Msk & (_UINT32_(value) << CAN_GFC_RRFE_Pos)) /* Assigment of value for RRFE in the CAN_GFC register */ +#define CAN_GFC_RRFS_Pos _UINT32_(1) /* (CAN_GFC) Reject Remote Frames Standard Position */ +#define CAN_GFC_RRFS_Msk (_UINT32_(0x1) << CAN_GFC_RRFS_Pos) /* (CAN_GFC) Reject Remote Frames Standard Mask */ +#define CAN_GFC_RRFS(value) (CAN_GFC_RRFS_Msk & (_UINT32_(value) << CAN_GFC_RRFS_Pos)) /* Assigment of value for RRFS in the CAN_GFC register */ +#define CAN_GFC_ANFE_Pos _UINT32_(2) /* (CAN_GFC) Accept Non-matching Frames Extended Position */ +#define CAN_GFC_ANFE_Msk (_UINT32_(0x3) << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept Non-matching Frames Extended Mask */ +#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & (_UINT32_(value) << CAN_GFC_ANFE_Pos)) /* Assigment of value for ANFE in the CAN_GFC register */ +#define CAN_GFC_ANFE_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFE_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFE_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ +#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Reject Position */ +#define CAN_GFC_ANFS_Pos _UINT32_(4) /* (CAN_GFC) Accept Non-matching Frames Standard Position */ +#define CAN_GFC_ANFS_Msk (_UINT32_(0x3) << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept Non-matching Frames Standard Mask */ +#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & (_UINT32_(value) << CAN_GFC_ANFS_Pos)) /* Assigment of value for ANFS in the CAN_GFC register */ +#define CAN_GFC_ANFS_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFS_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFS_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ +#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ +#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ +#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Reject Position */ +#define CAN_GFC_Msk _UINT32_(0x0000003F) /* (CAN_GFC) Register Mask */ + + +/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ +#define CAN_SIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_SIDFC) Standard ID Filter Configuration Reset Value */ + +#define CAN_SIDFC_FLSSA_Pos _UINT32_(0) /* (CAN_SIDFC) Filter List Standard Start Address Position */ +#define CAN_SIDFC_FLSSA_Msk (_UINT32_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) /* (CAN_SIDFC) Filter List Standard Start Address Mask */ +#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & (_UINT32_(value) << CAN_SIDFC_FLSSA_Pos)) /* Assigment of value for FLSSA in the CAN_SIDFC register */ +#define CAN_SIDFC_LSS_Pos _UINT32_(16) /* (CAN_SIDFC) List Size Standard Position */ +#define CAN_SIDFC_LSS_Msk (_UINT32_(0xFF) << CAN_SIDFC_LSS_Pos) /* (CAN_SIDFC) List Size Standard Mask */ +#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & (_UINT32_(value) << CAN_SIDFC_LSS_Pos)) /* Assigment of value for LSS in the CAN_SIDFC register */ +#define CAN_SIDFC_Msk _UINT32_(0x00FFFFFF) /* (CAN_SIDFC) Register Mask */ + + +/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ +#define CAN_XIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_XIDFC) Extended ID Filter Configuration Reset Value */ + +#define CAN_XIDFC_FLESA_Pos _UINT32_(0) /* (CAN_XIDFC) Filter List Extended Start Address Position */ +#define CAN_XIDFC_FLESA_Msk (_UINT32_(0xFFFF) << CAN_XIDFC_FLESA_Pos) /* (CAN_XIDFC) Filter List Extended Start Address Mask */ +#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & (_UINT32_(value) << CAN_XIDFC_FLESA_Pos)) /* Assigment of value for FLESA in the CAN_XIDFC register */ +#define CAN_XIDFC_LSE_Pos _UINT32_(16) /* (CAN_XIDFC) List Size Extended Position */ +#define CAN_XIDFC_LSE_Msk (_UINT32_(0x7F) << CAN_XIDFC_LSE_Pos) /* (CAN_XIDFC) List Size Extended Mask */ +#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & (_UINT32_(value) << CAN_XIDFC_LSE_Pos)) /* Assigment of value for LSE in the CAN_XIDFC register */ +#define CAN_XIDFC_Msk _UINT32_(0x007FFFFF) /* (CAN_XIDFC) Register Mask */ + + +/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ +#define CAN_XIDAM_RESETVALUE _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Extended ID AND Mask Reset Value */ + +#define CAN_XIDAM_EIDM_Pos _UINT32_(0) /* (CAN_XIDAM) Extended ID Mask Position */ +#define CAN_XIDAM_EIDM_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) /* (CAN_XIDAM) Extended ID Mask Mask */ +#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & (_UINT32_(value) << CAN_XIDAM_EIDM_Pos)) /* Assigment of value for EIDM in the CAN_XIDAM register */ +#define CAN_XIDAM_Msk _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Register Mask */ + + +/* -------- CAN_HPMS : (CAN Offset: 0x94) ( R/ 32) High Priority Message Status -------- */ +#define CAN_HPMS_RESETVALUE _UINT32_(0x00) /* (CAN_HPMS) High Priority Message Status Reset Value */ + +#define CAN_HPMS_BIDX_Pos _UINT32_(0) /* (CAN_HPMS) Buffer Index Position */ +#define CAN_HPMS_BIDX_Msk (_UINT32_(0x3F) << CAN_HPMS_BIDX_Pos) /* (CAN_HPMS) Buffer Index Mask */ +#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & (_UINT32_(value) << CAN_HPMS_BIDX_Pos)) /* Assigment of value for BIDX in the CAN_HPMS register */ +#define CAN_HPMS_MSI_Pos _UINT32_(6) /* (CAN_HPMS) Message Storage Indicator Position */ +#define CAN_HPMS_MSI_Msk (_UINT32_(0x3) << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message Storage Indicator Mask */ +#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & (_UINT32_(value) << CAN_HPMS_MSI_Pos)) /* Assigment of value for MSI in the CAN_HPMS register */ +#define CAN_HPMS_MSI_NONE_Val _UINT32_(0x0) /* (CAN_HPMS) No FIFO selected */ +#define CAN_HPMS_MSI_LOST_Val _UINT32_(0x1) /* (CAN_HPMS) FIFO message lost */ +#define CAN_HPMS_MSI_FIFO0_Val _UINT32_(0x2) /* (CAN_HPMS) Message stored in FIFO 0 */ +#define CAN_HPMS_MSI_FIFO1_Val _UINT32_(0x3) /* (CAN_HPMS) Message stored in FIFO 1 */ +#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) No FIFO selected Position */ +#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) FIFO message lost Position */ +#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 0 Position */ +#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 1 Position */ +#define CAN_HPMS_FIDX_Pos _UINT32_(8) /* (CAN_HPMS) Filter Index Position */ +#define CAN_HPMS_FIDX_Msk (_UINT32_(0x7F) << CAN_HPMS_FIDX_Pos) /* (CAN_HPMS) Filter Index Mask */ +#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & (_UINT32_(value) << CAN_HPMS_FIDX_Pos)) /* Assigment of value for FIDX in the CAN_HPMS register */ +#define CAN_HPMS_FLST_Pos _UINT32_(15) /* (CAN_HPMS) Filter List Position */ +#define CAN_HPMS_FLST_Msk (_UINT32_(0x1) << CAN_HPMS_FLST_Pos) /* (CAN_HPMS) Filter List Mask */ +#define CAN_HPMS_FLST(value) (CAN_HPMS_FLST_Msk & (_UINT32_(value) << CAN_HPMS_FLST_Pos)) /* Assigment of value for FLST in the CAN_HPMS register */ +#define CAN_HPMS_Msk _UINT32_(0x0000FFFF) /* (CAN_HPMS) Register Mask */ + + +/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ +#define CAN_NDAT1_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT1) New Data 1 Reset Value */ + +#define CAN_NDAT1_ND0_Pos _UINT32_(0) /* (CAN_NDAT1) New Data 0 Position */ +#define CAN_NDAT1_ND0_Msk (_UINT32_(0x1) << CAN_NDAT1_ND0_Pos) /* (CAN_NDAT1) New Data 0 Mask */ +#define CAN_NDAT1_ND0(value) (CAN_NDAT1_ND0_Msk & (_UINT32_(value) << CAN_NDAT1_ND0_Pos)) /* Assigment of value for ND0 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND1_Pos _UINT32_(1) /* (CAN_NDAT1) New Data 1 Position */ +#define CAN_NDAT1_ND1_Msk (_UINT32_(0x1) << CAN_NDAT1_ND1_Pos) /* (CAN_NDAT1) New Data 1 Mask */ +#define CAN_NDAT1_ND1(value) (CAN_NDAT1_ND1_Msk & (_UINT32_(value) << CAN_NDAT1_ND1_Pos)) /* Assigment of value for ND1 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND2_Pos _UINT32_(2) /* (CAN_NDAT1) New Data 2 Position */ +#define CAN_NDAT1_ND2_Msk (_UINT32_(0x1) << CAN_NDAT1_ND2_Pos) /* (CAN_NDAT1) New Data 2 Mask */ +#define CAN_NDAT1_ND2(value) (CAN_NDAT1_ND2_Msk & (_UINT32_(value) << CAN_NDAT1_ND2_Pos)) /* Assigment of value for ND2 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND3_Pos _UINT32_(3) /* (CAN_NDAT1) New Data 3 Position */ +#define CAN_NDAT1_ND3_Msk (_UINT32_(0x1) << CAN_NDAT1_ND3_Pos) /* (CAN_NDAT1) New Data 3 Mask */ +#define CAN_NDAT1_ND3(value) (CAN_NDAT1_ND3_Msk & (_UINT32_(value) << CAN_NDAT1_ND3_Pos)) /* Assigment of value for ND3 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND4_Pos _UINT32_(4) /* (CAN_NDAT1) New Data 4 Position */ +#define CAN_NDAT1_ND4_Msk (_UINT32_(0x1) << CAN_NDAT1_ND4_Pos) /* (CAN_NDAT1) New Data 4 Mask */ +#define CAN_NDAT1_ND4(value) (CAN_NDAT1_ND4_Msk & (_UINT32_(value) << CAN_NDAT1_ND4_Pos)) /* Assigment of value for ND4 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND5_Pos _UINT32_(5) /* (CAN_NDAT1) New Data 5 Position */ +#define CAN_NDAT1_ND5_Msk (_UINT32_(0x1) << CAN_NDAT1_ND5_Pos) /* (CAN_NDAT1) New Data 5 Mask */ +#define CAN_NDAT1_ND5(value) (CAN_NDAT1_ND5_Msk & (_UINT32_(value) << CAN_NDAT1_ND5_Pos)) /* Assigment of value for ND5 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND6_Pos _UINT32_(6) /* (CAN_NDAT1) New Data 6 Position */ +#define CAN_NDAT1_ND6_Msk (_UINT32_(0x1) << CAN_NDAT1_ND6_Pos) /* (CAN_NDAT1) New Data 6 Mask */ +#define CAN_NDAT1_ND6(value) (CAN_NDAT1_ND6_Msk & (_UINT32_(value) << CAN_NDAT1_ND6_Pos)) /* Assigment of value for ND6 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND7_Pos _UINT32_(7) /* (CAN_NDAT1) New Data 7 Position */ +#define CAN_NDAT1_ND7_Msk (_UINT32_(0x1) << CAN_NDAT1_ND7_Pos) /* (CAN_NDAT1) New Data 7 Mask */ +#define CAN_NDAT1_ND7(value) (CAN_NDAT1_ND7_Msk & (_UINT32_(value) << CAN_NDAT1_ND7_Pos)) /* Assigment of value for ND7 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND8_Pos _UINT32_(8) /* (CAN_NDAT1) New Data 8 Position */ +#define CAN_NDAT1_ND8_Msk (_UINT32_(0x1) << CAN_NDAT1_ND8_Pos) /* (CAN_NDAT1) New Data 8 Mask */ +#define CAN_NDAT1_ND8(value) (CAN_NDAT1_ND8_Msk & (_UINT32_(value) << CAN_NDAT1_ND8_Pos)) /* Assigment of value for ND8 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND9_Pos _UINT32_(9) /* (CAN_NDAT1) New Data 9 Position */ +#define CAN_NDAT1_ND9_Msk (_UINT32_(0x1) << CAN_NDAT1_ND9_Pos) /* (CAN_NDAT1) New Data 9 Mask */ +#define CAN_NDAT1_ND9(value) (CAN_NDAT1_ND9_Msk & (_UINT32_(value) << CAN_NDAT1_ND9_Pos)) /* Assigment of value for ND9 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND10_Pos _UINT32_(10) /* (CAN_NDAT1) New Data 10 Position */ +#define CAN_NDAT1_ND10_Msk (_UINT32_(0x1) << CAN_NDAT1_ND10_Pos) /* (CAN_NDAT1) New Data 10 Mask */ +#define CAN_NDAT1_ND10(value) (CAN_NDAT1_ND10_Msk & (_UINT32_(value) << CAN_NDAT1_ND10_Pos)) /* Assigment of value for ND10 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND11_Pos _UINT32_(11) /* (CAN_NDAT1) New Data 11 Position */ +#define CAN_NDAT1_ND11_Msk (_UINT32_(0x1) << CAN_NDAT1_ND11_Pos) /* (CAN_NDAT1) New Data 11 Mask */ +#define CAN_NDAT1_ND11(value) (CAN_NDAT1_ND11_Msk & (_UINT32_(value) << CAN_NDAT1_ND11_Pos)) /* Assigment of value for ND11 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND12_Pos _UINT32_(12) /* (CAN_NDAT1) New Data 12 Position */ +#define CAN_NDAT1_ND12_Msk (_UINT32_(0x1) << CAN_NDAT1_ND12_Pos) /* (CAN_NDAT1) New Data 12 Mask */ +#define CAN_NDAT1_ND12(value) (CAN_NDAT1_ND12_Msk & (_UINT32_(value) << CAN_NDAT1_ND12_Pos)) /* Assigment of value for ND12 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND13_Pos _UINT32_(13) /* (CAN_NDAT1) New Data 13 Position */ +#define CAN_NDAT1_ND13_Msk (_UINT32_(0x1) << CAN_NDAT1_ND13_Pos) /* (CAN_NDAT1) New Data 13 Mask */ +#define CAN_NDAT1_ND13(value) (CAN_NDAT1_ND13_Msk & (_UINT32_(value) << CAN_NDAT1_ND13_Pos)) /* Assigment of value for ND13 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND14_Pos _UINT32_(14) /* (CAN_NDAT1) New Data 14 Position */ +#define CAN_NDAT1_ND14_Msk (_UINT32_(0x1) << CAN_NDAT1_ND14_Pos) /* (CAN_NDAT1) New Data 14 Mask */ +#define CAN_NDAT1_ND14(value) (CAN_NDAT1_ND14_Msk & (_UINT32_(value) << CAN_NDAT1_ND14_Pos)) /* Assigment of value for ND14 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND15_Pos _UINT32_(15) /* (CAN_NDAT1) New Data 15 Position */ +#define CAN_NDAT1_ND15_Msk (_UINT32_(0x1) << CAN_NDAT1_ND15_Pos) /* (CAN_NDAT1) New Data 15 Mask */ +#define CAN_NDAT1_ND15(value) (CAN_NDAT1_ND15_Msk & (_UINT32_(value) << CAN_NDAT1_ND15_Pos)) /* Assigment of value for ND15 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND16_Pos _UINT32_(16) /* (CAN_NDAT1) New Data 16 Position */ +#define CAN_NDAT1_ND16_Msk (_UINT32_(0x1) << CAN_NDAT1_ND16_Pos) /* (CAN_NDAT1) New Data 16 Mask */ +#define CAN_NDAT1_ND16(value) (CAN_NDAT1_ND16_Msk & (_UINT32_(value) << CAN_NDAT1_ND16_Pos)) /* Assigment of value for ND16 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND17_Pos _UINT32_(17) /* (CAN_NDAT1) New Data 17 Position */ +#define CAN_NDAT1_ND17_Msk (_UINT32_(0x1) << CAN_NDAT1_ND17_Pos) /* (CAN_NDAT1) New Data 17 Mask */ +#define CAN_NDAT1_ND17(value) (CAN_NDAT1_ND17_Msk & (_UINT32_(value) << CAN_NDAT1_ND17_Pos)) /* Assigment of value for ND17 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND18_Pos _UINT32_(18) /* (CAN_NDAT1) New Data 18 Position */ +#define CAN_NDAT1_ND18_Msk (_UINT32_(0x1) << CAN_NDAT1_ND18_Pos) /* (CAN_NDAT1) New Data 18 Mask */ +#define CAN_NDAT1_ND18(value) (CAN_NDAT1_ND18_Msk & (_UINT32_(value) << CAN_NDAT1_ND18_Pos)) /* Assigment of value for ND18 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND19_Pos _UINT32_(19) /* (CAN_NDAT1) New Data 19 Position */ +#define CAN_NDAT1_ND19_Msk (_UINT32_(0x1) << CAN_NDAT1_ND19_Pos) /* (CAN_NDAT1) New Data 19 Mask */ +#define CAN_NDAT1_ND19(value) (CAN_NDAT1_ND19_Msk & (_UINT32_(value) << CAN_NDAT1_ND19_Pos)) /* Assigment of value for ND19 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND20_Pos _UINT32_(20) /* (CAN_NDAT1) New Data 20 Position */ +#define CAN_NDAT1_ND20_Msk (_UINT32_(0x1) << CAN_NDAT1_ND20_Pos) /* (CAN_NDAT1) New Data 20 Mask */ +#define CAN_NDAT1_ND20(value) (CAN_NDAT1_ND20_Msk & (_UINT32_(value) << CAN_NDAT1_ND20_Pos)) /* Assigment of value for ND20 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND21_Pos _UINT32_(21) /* (CAN_NDAT1) New Data 21 Position */ +#define CAN_NDAT1_ND21_Msk (_UINT32_(0x1) << CAN_NDAT1_ND21_Pos) /* (CAN_NDAT1) New Data 21 Mask */ +#define CAN_NDAT1_ND21(value) (CAN_NDAT1_ND21_Msk & (_UINT32_(value) << CAN_NDAT1_ND21_Pos)) /* Assigment of value for ND21 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND22_Pos _UINT32_(22) /* (CAN_NDAT1) New Data 22 Position */ +#define CAN_NDAT1_ND22_Msk (_UINT32_(0x1) << CAN_NDAT1_ND22_Pos) /* (CAN_NDAT1) New Data 22 Mask */ +#define CAN_NDAT1_ND22(value) (CAN_NDAT1_ND22_Msk & (_UINT32_(value) << CAN_NDAT1_ND22_Pos)) /* Assigment of value for ND22 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND23_Pos _UINT32_(23) /* (CAN_NDAT1) New Data 23 Position */ +#define CAN_NDAT1_ND23_Msk (_UINT32_(0x1) << CAN_NDAT1_ND23_Pos) /* (CAN_NDAT1) New Data 23 Mask */ +#define CAN_NDAT1_ND23(value) (CAN_NDAT1_ND23_Msk & (_UINT32_(value) << CAN_NDAT1_ND23_Pos)) /* Assigment of value for ND23 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND24_Pos _UINT32_(24) /* (CAN_NDAT1) New Data 24 Position */ +#define CAN_NDAT1_ND24_Msk (_UINT32_(0x1) << CAN_NDAT1_ND24_Pos) /* (CAN_NDAT1) New Data 24 Mask */ +#define CAN_NDAT1_ND24(value) (CAN_NDAT1_ND24_Msk & (_UINT32_(value) << CAN_NDAT1_ND24_Pos)) /* Assigment of value for ND24 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND25_Pos _UINT32_(25) /* (CAN_NDAT1) New Data 25 Position */ +#define CAN_NDAT1_ND25_Msk (_UINT32_(0x1) << CAN_NDAT1_ND25_Pos) /* (CAN_NDAT1) New Data 25 Mask */ +#define CAN_NDAT1_ND25(value) (CAN_NDAT1_ND25_Msk & (_UINT32_(value) << CAN_NDAT1_ND25_Pos)) /* Assigment of value for ND25 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND26_Pos _UINT32_(26) /* (CAN_NDAT1) New Data 26 Position */ +#define CAN_NDAT1_ND26_Msk (_UINT32_(0x1) << CAN_NDAT1_ND26_Pos) /* (CAN_NDAT1) New Data 26 Mask */ +#define CAN_NDAT1_ND26(value) (CAN_NDAT1_ND26_Msk & (_UINT32_(value) << CAN_NDAT1_ND26_Pos)) /* Assigment of value for ND26 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND27_Pos _UINT32_(27) /* (CAN_NDAT1) New Data 27 Position */ +#define CAN_NDAT1_ND27_Msk (_UINT32_(0x1) << CAN_NDAT1_ND27_Pos) /* (CAN_NDAT1) New Data 27 Mask */ +#define CAN_NDAT1_ND27(value) (CAN_NDAT1_ND27_Msk & (_UINT32_(value) << CAN_NDAT1_ND27_Pos)) /* Assigment of value for ND27 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND28_Pos _UINT32_(28) /* (CAN_NDAT1) New Data 28 Position */ +#define CAN_NDAT1_ND28_Msk (_UINT32_(0x1) << CAN_NDAT1_ND28_Pos) /* (CAN_NDAT1) New Data 28 Mask */ +#define CAN_NDAT1_ND28(value) (CAN_NDAT1_ND28_Msk & (_UINT32_(value) << CAN_NDAT1_ND28_Pos)) /* Assigment of value for ND28 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND29_Pos _UINT32_(29) /* (CAN_NDAT1) New Data 29 Position */ +#define CAN_NDAT1_ND29_Msk (_UINT32_(0x1) << CAN_NDAT1_ND29_Pos) /* (CAN_NDAT1) New Data 29 Mask */ +#define CAN_NDAT1_ND29(value) (CAN_NDAT1_ND29_Msk & (_UINT32_(value) << CAN_NDAT1_ND29_Pos)) /* Assigment of value for ND29 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND30_Pos _UINT32_(30) /* (CAN_NDAT1) New Data 30 Position */ +#define CAN_NDAT1_ND30_Msk (_UINT32_(0x1) << CAN_NDAT1_ND30_Pos) /* (CAN_NDAT1) New Data 30 Mask */ +#define CAN_NDAT1_ND30(value) (CAN_NDAT1_ND30_Msk & (_UINT32_(value) << CAN_NDAT1_ND30_Pos)) /* Assigment of value for ND30 in the CAN_NDAT1 register */ +#define CAN_NDAT1_ND31_Pos _UINT32_(31) /* (CAN_NDAT1) New Data 31 Position */ +#define CAN_NDAT1_ND31_Msk (_UINT32_(0x1) << CAN_NDAT1_ND31_Pos) /* (CAN_NDAT1) New Data 31 Mask */ +#define CAN_NDAT1_ND31(value) (CAN_NDAT1_ND31_Msk & (_UINT32_(value) << CAN_NDAT1_ND31_Pos)) /* Assigment of value for ND31 in the CAN_NDAT1 register */ +#define CAN_NDAT1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT1) Register Mask */ + +#define CAN_NDAT1_ND_Pos _UINT32_(0) /* (CAN_NDAT1 Position) New Data 3x */ +#define CAN_NDAT1_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT1_ND_Pos) /* (CAN_NDAT1 Mask) ND */ +#define CAN_NDAT1_ND(value) (CAN_NDAT1_ND_Msk & (_UINT32_(value) << CAN_NDAT1_ND_Pos)) + +/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ +#define CAN_NDAT2_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT2) New Data 2 Reset Value */ + +#define CAN_NDAT2_ND32_Pos _UINT32_(0) /* (CAN_NDAT2) New Data 32 Position */ +#define CAN_NDAT2_ND32_Msk (_UINT32_(0x1) << CAN_NDAT2_ND32_Pos) /* (CAN_NDAT2) New Data 32 Mask */ +#define CAN_NDAT2_ND32(value) (CAN_NDAT2_ND32_Msk & (_UINT32_(value) << CAN_NDAT2_ND32_Pos)) /* Assigment of value for ND32 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND33_Pos _UINT32_(1) /* (CAN_NDAT2) New Data 33 Position */ +#define CAN_NDAT2_ND33_Msk (_UINT32_(0x1) << CAN_NDAT2_ND33_Pos) /* (CAN_NDAT2) New Data 33 Mask */ +#define CAN_NDAT2_ND33(value) (CAN_NDAT2_ND33_Msk & (_UINT32_(value) << CAN_NDAT2_ND33_Pos)) /* Assigment of value for ND33 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND34_Pos _UINT32_(2) /* (CAN_NDAT2) New Data 34 Position */ +#define CAN_NDAT2_ND34_Msk (_UINT32_(0x1) << CAN_NDAT2_ND34_Pos) /* (CAN_NDAT2) New Data 34 Mask */ +#define CAN_NDAT2_ND34(value) (CAN_NDAT2_ND34_Msk & (_UINT32_(value) << CAN_NDAT2_ND34_Pos)) /* Assigment of value for ND34 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND35_Pos _UINT32_(3) /* (CAN_NDAT2) New Data 35 Position */ +#define CAN_NDAT2_ND35_Msk (_UINT32_(0x1) << CAN_NDAT2_ND35_Pos) /* (CAN_NDAT2) New Data 35 Mask */ +#define CAN_NDAT2_ND35(value) (CAN_NDAT2_ND35_Msk & (_UINT32_(value) << CAN_NDAT2_ND35_Pos)) /* Assigment of value for ND35 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND36_Pos _UINT32_(4) /* (CAN_NDAT2) New Data 36 Position */ +#define CAN_NDAT2_ND36_Msk (_UINT32_(0x1) << CAN_NDAT2_ND36_Pos) /* (CAN_NDAT2) New Data 36 Mask */ +#define CAN_NDAT2_ND36(value) (CAN_NDAT2_ND36_Msk & (_UINT32_(value) << CAN_NDAT2_ND36_Pos)) /* Assigment of value for ND36 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND37_Pos _UINT32_(5) /* (CAN_NDAT2) New Data 37 Position */ +#define CAN_NDAT2_ND37_Msk (_UINT32_(0x1) << CAN_NDAT2_ND37_Pos) /* (CAN_NDAT2) New Data 37 Mask */ +#define CAN_NDAT2_ND37(value) (CAN_NDAT2_ND37_Msk & (_UINT32_(value) << CAN_NDAT2_ND37_Pos)) /* Assigment of value for ND37 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND38_Pos _UINT32_(6) /* (CAN_NDAT2) New Data 38 Position */ +#define CAN_NDAT2_ND38_Msk (_UINT32_(0x1) << CAN_NDAT2_ND38_Pos) /* (CAN_NDAT2) New Data 38 Mask */ +#define CAN_NDAT2_ND38(value) (CAN_NDAT2_ND38_Msk & (_UINT32_(value) << CAN_NDAT2_ND38_Pos)) /* Assigment of value for ND38 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND39_Pos _UINT32_(7) /* (CAN_NDAT2) New Data 39 Position */ +#define CAN_NDAT2_ND39_Msk (_UINT32_(0x1) << CAN_NDAT2_ND39_Pos) /* (CAN_NDAT2) New Data 39 Mask */ +#define CAN_NDAT2_ND39(value) (CAN_NDAT2_ND39_Msk & (_UINT32_(value) << CAN_NDAT2_ND39_Pos)) /* Assigment of value for ND39 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND40_Pos _UINT32_(8) /* (CAN_NDAT2) New Data 40 Position */ +#define CAN_NDAT2_ND40_Msk (_UINT32_(0x1) << CAN_NDAT2_ND40_Pos) /* (CAN_NDAT2) New Data 40 Mask */ +#define CAN_NDAT2_ND40(value) (CAN_NDAT2_ND40_Msk & (_UINT32_(value) << CAN_NDAT2_ND40_Pos)) /* Assigment of value for ND40 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND41_Pos _UINT32_(9) /* (CAN_NDAT2) New Data 41 Position */ +#define CAN_NDAT2_ND41_Msk (_UINT32_(0x1) << CAN_NDAT2_ND41_Pos) /* (CAN_NDAT2) New Data 41 Mask */ +#define CAN_NDAT2_ND41(value) (CAN_NDAT2_ND41_Msk & (_UINT32_(value) << CAN_NDAT2_ND41_Pos)) /* Assigment of value for ND41 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND42_Pos _UINT32_(10) /* (CAN_NDAT2) New Data 42 Position */ +#define CAN_NDAT2_ND42_Msk (_UINT32_(0x1) << CAN_NDAT2_ND42_Pos) /* (CAN_NDAT2) New Data 42 Mask */ +#define CAN_NDAT2_ND42(value) (CAN_NDAT2_ND42_Msk & (_UINT32_(value) << CAN_NDAT2_ND42_Pos)) /* Assigment of value for ND42 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND43_Pos _UINT32_(11) /* (CAN_NDAT2) New Data 43 Position */ +#define CAN_NDAT2_ND43_Msk (_UINT32_(0x1) << CAN_NDAT2_ND43_Pos) /* (CAN_NDAT2) New Data 43 Mask */ +#define CAN_NDAT2_ND43(value) (CAN_NDAT2_ND43_Msk & (_UINT32_(value) << CAN_NDAT2_ND43_Pos)) /* Assigment of value for ND43 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND44_Pos _UINT32_(12) /* (CAN_NDAT2) New Data 44 Position */ +#define CAN_NDAT2_ND44_Msk (_UINT32_(0x1) << CAN_NDAT2_ND44_Pos) /* (CAN_NDAT2) New Data 44 Mask */ +#define CAN_NDAT2_ND44(value) (CAN_NDAT2_ND44_Msk & (_UINT32_(value) << CAN_NDAT2_ND44_Pos)) /* Assigment of value for ND44 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND45_Pos _UINT32_(13) /* (CAN_NDAT2) New Data 45 Position */ +#define CAN_NDAT2_ND45_Msk (_UINT32_(0x1) << CAN_NDAT2_ND45_Pos) /* (CAN_NDAT2) New Data 45 Mask */ +#define CAN_NDAT2_ND45(value) (CAN_NDAT2_ND45_Msk & (_UINT32_(value) << CAN_NDAT2_ND45_Pos)) /* Assigment of value for ND45 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND46_Pos _UINT32_(14) /* (CAN_NDAT2) New Data 46 Position */ +#define CAN_NDAT2_ND46_Msk (_UINT32_(0x1) << CAN_NDAT2_ND46_Pos) /* (CAN_NDAT2) New Data 46 Mask */ +#define CAN_NDAT2_ND46(value) (CAN_NDAT2_ND46_Msk & (_UINT32_(value) << CAN_NDAT2_ND46_Pos)) /* Assigment of value for ND46 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND47_Pos _UINT32_(15) /* (CAN_NDAT2) New Data 47 Position */ +#define CAN_NDAT2_ND47_Msk (_UINT32_(0x1) << CAN_NDAT2_ND47_Pos) /* (CAN_NDAT2) New Data 47 Mask */ +#define CAN_NDAT2_ND47(value) (CAN_NDAT2_ND47_Msk & (_UINT32_(value) << CAN_NDAT2_ND47_Pos)) /* Assigment of value for ND47 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND48_Pos _UINT32_(16) /* (CAN_NDAT2) New Data 48 Position */ +#define CAN_NDAT2_ND48_Msk (_UINT32_(0x1) << CAN_NDAT2_ND48_Pos) /* (CAN_NDAT2) New Data 48 Mask */ +#define CAN_NDAT2_ND48(value) (CAN_NDAT2_ND48_Msk & (_UINT32_(value) << CAN_NDAT2_ND48_Pos)) /* Assigment of value for ND48 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND49_Pos _UINT32_(17) /* (CAN_NDAT2) New Data 49 Position */ +#define CAN_NDAT2_ND49_Msk (_UINT32_(0x1) << CAN_NDAT2_ND49_Pos) /* (CAN_NDAT2) New Data 49 Mask */ +#define CAN_NDAT2_ND49(value) (CAN_NDAT2_ND49_Msk & (_UINT32_(value) << CAN_NDAT2_ND49_Pos)) /* Assigment of value for ND49 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND50_Pos _UINT32_(18) /* (CAN_NDAT2) New Data 50 Position */ +#define CAN_NDAT2_ND50_Msk (_UINT32_(0x1) << CAN_NDAT2_ND50_Pos) /* (CAN_NDAT2) New Data 50 Mask */ +#define CAN_NDAT2_ND50(value) (CAN_NDAT2_ND50_Msk & (_UINT32_(value) << CAN_NDAT2_ND50_Pos)) /* Assigment of value for ND50 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND51_Pos _UINT32_(19) /* (CAN_NDAT2) New Data 51 Position */ +#define CAN_NDAT2_ND51_Msk (_UINT32_(0x1) << CAN_NDAT2_ND51_Pos) /* (CAN_NDAT2) New Data 51 Mask */ +#define CAN_NDAT2_ND51(value) (CAN_NDAT2_ND51_Msk & (_UINT32_(value) << CAN_NDAT2_ND51_Pos)) /* Assigment of value for ND51 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND52_Pos _UINT32_(20) /* (CAN_NDAT2) New Data 52 Position */ +#define CAN_NDAT2_ND52_Msk (_UINT32_(0x1) << CAN_NDAT2_ND52_Pos) /* (CAN_NDAT2) New Data 52 Mask */ +#define CAN_NDAT2_ND52(value) (CAN_NDAT2_ND52_Msk & (_UINT32_(value) << CAN_NDAT2_ND52_Pos)) /* Assigment of value for ND52 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND53_Pos _UINT32_(21) /* (CAN_NDAT2) New Data 53 Position */ +#define CAN_NDAT2_ND53_Msk (_UINT32_(0x1) << CAN_NDAT2_ND53_Pos) /* (CAN_NDAT2) New Data 53 Mask */ +#define CAN_NDAT2_ND53(value) (CAN_NDAT2_ND53_Msk & (_UINT32_(value) << CAN_NDAT2_ND53_Pos)) /* Assigment of value for ND53 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND54_Pos _UINT32_(22) /* (CAN_NDAT2) New Data 54 Position */ +#define CAN_NDAT2_ND54_Msk (_UINT32_(0x1) << CAN_NDAT2_ND54_Pos) /* (CAN_NDAT2) New Data 54 Mask */ +#define CAN_NDAT2_ND54(value) (CAN_NDAT2_ND54_Msk & (_UINT32_(value) << CAN_NDAT2_ND54_Pos)) /* Assigment of value for ND54 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND55_Pos _UINT32_(23) /* (CAN_NDAT2) New Data 55 Position */ +#define CAN_NDAT2_ND55_Msk (_UINT32_(0x1) << CAN_NDAT2_ND55_Pos) /* (CAN_NDAT2) New Data 55 Mask */ +#define CAN_NDAT2_ND55(value) (CAN_NDAT2_ND55_Msk & (_UINT32_(value) << CAN_NDAT2_ND55_Pos)) /* Assigment of value for ND55 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND56_Pos _UINT32_(24) /* (CAN_NDAT2) New Data 56 Position */ +#define CAN_NDAT2_ND56_Msk (_UINT32_(0x1) << CAN_NDAT2_ND56_Pos) /* (CAN_NDAT2) New Data 56 Mask */ +#define CAN_NDAT2_ND56(value) (CAN_NDAT2_ND56_Msk & (_UINT32_(value) << CAN_NDAT2_ND56_Pos)) /* Assigment of value for ND56 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND57_Pos _UINT32_(25) /* (CAN_NDAT2) New Data 57 Position */ +#define CAN_NDAT2_ND57_Msk (_UINT32_(0x1) << CAN_NDAT2_ND57_Pos) /* (CAN_NDAT2) New Data 57 Mask */ +#define CAN_NDAT2_ND57(value) (CAN_NDAT2_ND57_Msk & (_UINT32_(value) << CAN_NDAT2_ND57_Pos)) /* Assigment of value for ND57 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND58_Pos _UINT32_(26) /* (CAN_NDAT2) New Data 58 Position */ +#define CAN_NDAT2_ND58_Msk (_UINT32_(0x1) << CAN_NDAT2_ND58_Pos) /* (CAN_NDAT2) New Data 58 Mask */ +#define CAN_NDAT2_ND58(value) (CAN_NDAT2_ND58_Msk & (_UINT32_(value) << CAN_NDAT2_ND58_Pos)) /* Assigment of value for ND58 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND59_Pos _UINT32_(27) /* (CAN_NDAT2) New Data 59 Position */ +#define CAN_NDAT2_ND59_Msk (_UINT32_(0x1) << CAN_NDAT2_ND59_Pos) /* (CAN_NDAT2) New Data 59 Mask */ +#define CAN_NDAT2_ND59(value) (CAN_NDAT2_ND59_Msk & (_UINT32_(value) << CAN_NDAT2_ND59_Pos)) /* Assigment of value for ND59 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND60_Pos _UINT32_(28) /* (CAN_NDAT2) New Data 60 Position */ +#define CAN_NDAT2_ND60_Msk (_UINT32_(0x1) << CAN_NDAT2_ND60_Pos) /* (CAN_NDAT2) New Data 60 Mask */ +#define CAN_NDAT2_ND60(value) (CAN_NDAT2_ND60_Msk & (_UINT32_(value) << CAN_NDAT2_ND60_Pos)) /* Assigment of value for ND60 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND61_Pos _UINT32_(29) /* (CAN_NDAT2) New Data 61 Position */ +#define CAN_NDAT2_ND61_Msk (_UINT32_(0x1) << CAN_NDAT2_ND61_Pos) /* (CAN_NDAT2) New Data 61 Mask */ +#define CAN_NDAT2_ND61(value) (CAN_NDAT2_ND61_Msk & (_UINT32_(value) << CAN_NDAT2_ND61_Pos)) /* Assigment of value for ND61 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND62_Pos _UINT32_(30) /* (CAN_NDAT2) New Data 62 Position */ +#define CAN_NDAT2_ND62_Msk (_UINT32_(0x1) << CAN_NDAT2_ND62_Pos) /* (CAN_NDAT2) New Data 62 Mask */ +#define CAN_NDAT2_ND62(value) (CAN_NDAT2_ND62_Msk & (_UINT32_(value) << CAN_NDAT2_ND62_Pos)) /* Assigment of value for ND62 in the CAN_NDAT2 register */ +#define CAN_NDAT2_ND63_Pos _UINT32_(31) /* (CAN_NDAT2) New Data 63 Position */ +#define CAN_NDAT2_ND63_Msk (_UINT32_(0x1) << CAN_NDAT2_ND63_Pos) /* (CAN_NDAT2) New Data 63 Mask */ +#define CAN_NDAT2_ND63(value) (CAN_NDAT2_ND63_Msk & (_UINT32_(value) << CAN_NDAT2_ND63_Pos)) /* Assigment of value for ND63 in the CAN_NDAT2 register */ +#define CAN_NDAT2_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT2) Register Mask */ + +#define CAN_NDAT2_ND_Pos _UINT32_(0) /* (CAN_NDAT2 Position) New Data 63 */ +#define CAN_NDAT2_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT2_ND_Pos) /* (CAN_NDAT2 Mask) ND */ +#define CAN_NDAT2_ND(value) (CAN_NDAT2_ND_Msk & (_UINT32_(value) << CAN_NDAT2_ND_Pos)) + +/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ +#define CAN_RXF0C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0C) Rx FIFO 0 Configuration Reset Value */ + +#define CAN_RXF0C_F0SA_Pos _UINT32_(0) /* (CAN_RXF0C) Rx FIFO 0 Start Address Position */ +#define CAN_RXF0C_F0SA_Msk (_UINT32_(0xFFFF) << CAN_RXF0C_F0SA_Pos) /* (CAN_RXF0C) Rx FIFO 0 Start Address Mask */ +#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & (_UINT32_(value) << CAN_RXF0C_F0SA_Pos)) /* Assigment of value for F0SA in the CAN_RXF0C register */ +#define CAN_RXF0C_F0S_Pos _UINT32_(16) /* (CAN_RXF0C) Rx FIFO 0 Size Position */ +#define CAN_RXF0C_F0S_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0S_Pos) /* (CAN_RXF0C) Rx FIFO 0 Size Mask */ +#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & (_UINT32_(value) << CAN_RXF0C_F0S_Pos)) /* Assigment of value for F0S in the CAN_RXF0C register */ +#define CAN_RXF0C_F0WM_Pos _UINT32_(24) /* (CAN_RXF0C) Rx FIFO 0 Watermark Position */ +#define CAN_RXF0C_F0WM_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0WM_Pos) /* (CAN_RXF0C) Rx FIFO 0 Watermark Mask */ +#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & (_UINT32_(value) << CAN_RXF0C_F0WM_Pos)) /* Assigment of value for F0WM in the CAN_RXF0C register */ +#define CAN_RXF0C_F0OM_Pos _UINT32_(31) /* (CAN_RXF0C) FIFO 0 Operation Mode Position */ +#define CAN_RXF0C_F0OM_Msk (_UINT32_(0x1) << CAN_RXF0C_F0OM_Pos) /* (CAN_RXF0C) FIFO 0 Operation Mode Mask */ +#define CAN_RXF0C_F0OM(value) (CAN_RXF0C_F0OM_Msk & (_UINT32_(value) << CAN_RXF0C_F0OM_Pos)) /* Assigment of value for F0OM in the CAN_RXF0C register */ +#define CAN_RXF0C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF0C) Register Mask */ + + +/* -------- CAN_RXF0S : (CAN Offset: 0xA4) ( R/ 32) Rx FIFO 0 Status -------- */ +#define CAN_RXF0S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0S) Rx FIFO 0 Status Reset Value */ + +#define CAN_RXF0S_F0FL_Pos _UINT32_(0) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Position */ +#define CAN_RXF0S_F0FL_Msk (_UINT32_(0x7F) << CAN_RXF0S_F0FL_Pos) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Mask */ +#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & (_UINT32_(value) << CAN_RXF0S_F0FL_Pos)) /* Assigment of value for F0FL in the CAN_RXF0S register */ +#define CAN_RXF0S_F0GI_Pos _UINT32_(8) /* (CAN_RXF0S) Rx FIFO 0 Get Index Position */ +#define CAN_RXF0S_F0GI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0GI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Get Index Mask */ +#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & (_UINT32_(value) << CAN_RXF0S_F0GI_Pos)) /* Assigment of value for F0GI in the CAN_RXF0S register */ +#define CAN_RXF0S_F0PI_Pos _UINT32_(16) /* (CAN_RXF0S) Rx FIFO 0 Put Index Position */ +#define CAN_RXF0S_F0PI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0PI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Put Index Mask */ +#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & (_UINT32_(value) << CAN_RXF0S_F0PI_Pos)) /* Assigment of value for F0PI in the CAN_RXF0S register */ +#define CAN_RXF0S_F0F_Pos _UINT32_(24) /* (CAN_RXF0S) Rx FIFO 0 Full Position */ +#define CAN_RXF0S_F0F_Msk (_UINT32_(0x1) << CAN_RXF0S_F0F_Pos) /* (CAN_RXF0S) Rx FIFO 0 Full Mask */ +#define CAN_RXF0S_F0F(value) (CAN_RXF0S_F0F_Msk & (_UINT32_(value) << CAN_RXF0S_F0F_Pos)) /* Assigment of value for F0F in the CAN_RXF0S register */ +#define CAN_RXF0S_RF0L_Pos _UINT32_(25) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Position */ +#define CAN_RXF0S_RF0L_Msk (_UINT32_(0x1) << CAN_RXF0S_RF0L_Pos) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Mask */ +#define CAN_RXF0S_RF0L(value) (CAN_RXF0S_RF0L_Msk & (_UINT32_(value) << CAN_RXF0S_RF0L_Pos)) /* Assigment of value for RF0L in the CAN_RXF0S register */ +#define CAN_RXF0S_Msk _UINT32_(0x033F3F7F) /* (CAN_RXF0S) Register Mask */ + + +/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ +#define CAN_RXF0A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Reset Value */ + +#define CAN_RXF0A_F0AI_Pos _UINT32_(0) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Position */ +#define CAN_RXF0A_F0AI_Msk (_UINT32_(0x3F) << CAN_RXF0A_F0AI_Pos) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Mask */ +#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & (_UINT32_(value) << CAN_RXF0A_F0AI_Pos)) /* Assigment of value for F0AI in the CAN_RXF0A register */ +#define CAN_RXF0A_Msk _UINT32_(0x0000003F) /* (CAN_RXF0A) Register Mask */ + + +/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ +#define CAN_RXBC_RESETVALUE _UINT32_(0x00) /* (CAN_RXBC) Rx Buffer Configuration Reset Value */ + +#define CAN_RXBC_RBSA_Pos _UINT32_(0) /* (CAN_RXBC) Rx Buffer Start Address Position */ +#define CAN_RXBC_RBSA_Msk (_UINT32_(0xFFFF) << CAN_RXBC_RBSA_Pos) /* (CAN_RXBC) Rx Buffer Start Address Mask */ +#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & (_UINT32_(value) << CAN_RXBC_RBSA_Pos)) /* Assigment of value for RBSA in the CAN_RXBC register */ +#define CAN_RXBC_Msk _UINT32_(0x0000FFFF) /* (CAN_RXBC) Register Mask */ + + +/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ +#define CAN_RXF1C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1C) Rx FIFO 1 Configuration Reset Value */ + +#define CAN_RXF1C_F1SA_Pos _UINT32_(0) /* (CAN_RXF1C) Rx FIFO 1 Start Address Position */ +#define CAN_RXF1C_F1SA_Msk (_UINT32_(0xFFFF) << CAN_RXF1C_F1SA_Pos) /* (CAN_RXF1C) Rx FIFO 1 Start Address Mask */ +#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & (_UINT32_(value) << CAN_RXF1C_F1SA_Pos)) /* Assigment of value for F1SA in the CAN_RXF1C register */ +#define CAN_RXF1C_F1S_Pos _UINT32_(16) /* (CAN_RXF1C) Rx FIFO 1 Size Position */ +#define CAN_RXF1C_F1S_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1S_Pos) /* (CAN_RXF1C) Rx FIFO 1 Size Mask */ +#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & (_UINT32_(value) << CAN_RXF1C_F1S_Pos)) /* Assigment of value for F1S in the CAN_RXF1C register */ +#define CAN_RXF1C_F1WM_Pos _UINT32_(24) /* (CAN_RXF1C) Rx FIFO 1 Watermark Position */ +#define CAN_RXF1C_F1WM_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1WM_Pos) /* (CAN_RXF1C) Rx FIFO 1 Watermark Mask */ +#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & (_UINT32_(value) << CAN_RXF1C_F1WM_Pos)) /* Assigment of value for F1WM in the CAN_RXF1C register */ +#define CAN_RXF1C_F1OM_Pos _UINT32_(31) /* (CAN_RXF1C) FIFO 1 Operation Mode Position */ +#define CAN_RXF1C_F1OM_Msk (_UINT32_(0x1) << CAN_RXF1C_F1OM_Pos) /* (CAN_RXF1C) FIFO 1 Operation Mode Mask */ +#define CAN_RXF1C_F1OM(value) (CAN_RXF1C_F1OM_Msk & (_UINT32_(value) << CAN_RXF1C_F1OM_Pos)) /* Assigment of value for F1OM in the CAN_RXF1C register */ +#define CAN_RXF1C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF1C) Register Mask */ + + +/* -------- CAN_RXF1S : (CAN Offset: 0xB4) ( R/ 32) Rx FIFO 1 Status -------- */ +#define CAN_RXF1S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1S) Rx FIFO 1 Status Reset Value */ + +#define CAN_RXF1S_F1FL_Pos _UINT32_(0) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Position */ +#define CAN_RXF1S_F1FL_Msk (_UINT32_(0x7F) << CAN_RXF1S_F1FL_Pos) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Mask */ +#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & (_UINT32_(value) << CAN_RXF1S_F1FL_Pos)) /* Assigment of value for F1FL in the CAN_RXF1S register */ +#define CAN_RXF1S_F1GI_Pos _UINT32_(8) /* (CAN_RXF1S) Rx FIFO 1 Get Index Position */ +#define CAN_RXF1S_F1GI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1GI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Get Index Mask */ +#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & (_UINT32_(value) << CAN_RXF1S_F1GI_Pos)) /* Assigment of value for F1GI in the CAN_RXF1S register */ +#define CAN_RXF1S_F1PI_Pos _UINT32_(16) /* (CAN_RXF1S) Rx FIFO 1 Put Index Position */ +#define CAN_RXF1S_F1PI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1PI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Put Index Mask */ +#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & (_UINT32_(value) << CAN_RXF1S_F1PI_Pos)) /* Assigment of value for F1PI in the CAN_RXF1S register */ +#define CAN_RXF1S_F1F_Pos _UINT32_(24) /* (CAN_RXF1S) Rx FIFO 1 Full Position */ +#define CAN_RXF1S_F1F_Msk (_UINT32_(0x1) << CAN_RXF1S_F1F_Pos) /* (CAN_RXF1S) Rx FIFO 1 Full Mask */ +#define CAN_RXF1S_F1F(value) (CAN_RXF1S_F1F_Msk & (_UINT32_(value) << CAN_RXF1S_F1F_Pos)) /* Assigment of value for F1F in the CAN_RXF1S register */ +#define CAN_RXF1S_RF1L_Pos _UINT32_(25) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Position */ +#define CAN_RXF1S_RF1L_Msk (_UINT32_(0x1) << CAN_RXF1S_RF1L_Pos) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Mask */ +#define CAN_RXF1S_RF1L(value) (CAN_RXF1S_RF1L_Msk & (_UINT32_(value) << CAN_RXF1S_RF1L_Pos)) /* Assigment of value for RF1L in the CAN_RXF1S register */ +#define CAN_RXF1S_DMS_Pos _UINT32_(30) /* (CAN_RXF1S) Debug Message Status Position */ +#define CAN_RXF1S_DMS_Msk (_UINT32_(0x3) << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug Message Status Mask */ +#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & (_UINT32_(value) << CAN_RXF1S_DMS_Pos)) /* Assigment of value for DMS in the CAN_RXF1S register */ +#define CAN_RXF1S_DMS_IDLE_Val _UINT32_(0x0) /* (CAN_RXF1S) Idle state */ +#define CAN_RXF1S_DMS_DBGA_Val _UINT32_(0x1) /* (CAN_RXF1S) Debug message A received */ +#define CAN_RXF1S_DMS_DBGB_Val _UINT32_(0x2) /* (CAN_RXF1S) Debug message A/B received */ +#define CAN_RXF1S_DMS_DBGC_Val _UINT32_(0x3) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set */ +#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Idle state Position */ +#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A received Position */ +#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B received Position */ +#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set Position */ +#define CAN_RXF1S_Msk _UINT32_(0xC33F3F7F) /* (CAN_RXF1S) Register Mask */ + + +/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ +#define CAN_RXF1A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Reset Value */ + +#define CAN_RXF1A_F1AI_Pos _UINT32_(0) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Position */ +#define CAN_RXF1A_F1AI_Msk (_UINT32_(0x3F) << CAN_RXF1A_F1AI_Pos) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Mask */ +#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & (_UINT32_(value) << CAN_RXF1A_F1AI_Pos)) /* Assigment of value for F1AI in the CAN_RXF1A register */ +#define CAN_RXF1A_Msk _UINT32_(0x0000003F) /* (CAN_RXF1A) Register Mask */ + + +/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ +#define CAN_RXESC_RESETVALUE _UINT32_(0x00) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Reset Value */ + +#define CAN_RXESC_F0DS_Pos _UINT32_(0) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Position */ +#define CAN_RXESC_F0DS_Msk (_UINT32_(0x7) << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Mask */ +#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & (_UINT32_(value) << CAN_RXESC_F0DS_Pos)) /* Assigment of value for F0DS in the CAN_RXESC register */ +#define CAN_RXESC_F0DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F0DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F0DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F0DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F0DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F0DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F0DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F0DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_F1DS_Pos _UINT32_(4) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Position */ +#define CAN_RXESC_F1DS_Msk (_UINT32_(0x7) << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Mask */ +#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & (_UINT32_(value) << CAN_RXESC_F1DS_Pos)) /* Assigment of value for F1DS in the CAN_RXESC register */ +#define CAN_RXESC_F1DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F1DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F1DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F1DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F1DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F1DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F1DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F1DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_RBDS_Pos _UINT32_(8) /* (CAN_RXESC) Rx Buffer Data Field Size Position */ +#define CAN_RXESC_RBDS_Msk (_UINT32_(0x7) << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) Rx Buffer Data Field Size Mask */ +#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & (_UINT32_(value) << CAN_RXESC_RBDS_Pos)) /* Assigment of value for RBDS in the CAN_RXESC register */ +#define CAN_RXESC_RBDS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_RBDS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_RBDS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_RBDS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_RBDS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_RBDS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_RBDS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_RBDS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 8 byte data field Position */ +#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 12 byte data field Position */ +#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 16 byte data field Position */ +#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 20 byte data field Position */ +#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 24 byte data field Position */ +#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 32 byte data field Position */ +#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 48 byte data field Position */ +#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 64 byte data field Position */ +#define CAN_RXESC_Msk _UINT32_(0x00000777) /* (CAN_RXESC) Register Mask */ + + +/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ +#define CAN_TXBC_RESETVALUE _UINT32_(0x00) /* (CAN_TXBC) Tx Buffer Configuration Reset Value */ + +#define CAN_TXBC_TBSA_Pos _UINT32_(0) /* (CAN_TXBC) Tx Buffers Start Address Position */ +#define CAN_TXBC_TBSA_Msk (_UINT32_(0xFFFF) << CAN_TXBC_TBSA_Pos) /* (CAN_TXBC) Tx Buffers Start Address Mask */ +#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & (_UINT32_(value) << CAN_TXBC_TBSA_Pos)) /* Assigment of value for TBSA in the CAN_TXBC register */ +#define CAN_TXBC_NDTB_Pos _UINT32_(16) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Position */ +#define CAN_TXBC_NDTB_Msk (_UINT32_(0x3F) << CAN_TXBC_NDTB_Pos) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Mask */ +#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & (_UINT32_(value) << CAN_TXBC_NDTB_Pos)) /* Assigment of value for NDTB in the CAN_TXBC register */ +#define CAN_TXBC_TFQS_Pos _UINT32_(24) /* (CAN_TXBC) Transmit FIFO/Queue Size Position */ +#define CAN_TXBC_TFQS_Msk (_UINT32_(0x3F) << CAN_TXBC_TFQS_Pos) /* (CAN_TXBC) Transmit FIFO/Queue Size Mask */ +#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & (_UINT32_(value) << CAN_TXBC_TFQS_Pos)) /* Assigment of value for TFQS in the CAN_TXBC register */ +#define CAN_TXBC_TFQM_Pos _UINT32_(30) /* (CAN_TXBC) Tx FIFO/Queue Mode Position */ +#define CAN_TXBC_TFQM_Msk (_UINT32_(0x1) << CAN_TXBC_TFQM_Pos) /* (CAN_TXBC) Tx FIFO/Queue Mode Mask */ +#define CAN_TXBC_TFQM(value) (CAN_TXBC_TFQM_Msk & (_UINT32_(value) << CAN_TXBC_TFQM_Pos)) /* Assigment of value for TFQM in the CAN_TXBC register */ +#define CAN_TXBC_Msk _UINT32_(0x7F3FFFFF) /* (CAN_TXBC) Register Mask */ + + +/* -------- CAN_TXFQS : (CAN Offset: 0xC4) ( R/ 32) Tx FIFO / Queue Status -------- */ +#define CAN_TXFQS_RESETVALUE _UINT32_(0x00) /* (CAN_TXFQS) Tx FIFO / Queue Status Reset Value */ + +#define CAN_TXFQS_TFFL_Pos _UINT32_(0) /* (CAN_TXFQS) Tx FIFO Free Level Position */ +#define CAN_TXFQS_TFFL_Msk (_UINT32_(0x3F) << CAN_TXFQS_TFFL_Pos) /* (CAN_TXFQS) Tx FIFO Free Level Mask */ +#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & (_UINT32_(value) << CAN_TXFQS_TFFL_Pos)) /* Assigment of value for TFFL in the CAN_TXFQS register */ +#define CAN_TXFQS_TFGI_Pos _UINT32_(8) /* (CAN_TXFQS) Tx FIFO Get Index Position */ +#define CAN_TXFQS_TFGI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFGI_Pos) /* (CAN_TXFQS) Tx FIFO Get Index Mask */ +#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & (_UINT32_(value) << CAN_TXFQS_TFGI_Pos)) /* Assigment of value for TFGI in the CAN_TXFQS register */ +#define CAN_TXFQS_TFQPI_Pos _UINT32_(16) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Position */ +#define CAN_TXFQS_TFQPI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFQPI_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Mask */ +#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & (_UINT32_(value) << CAN_TXFQS_TFQPI_Pos)) /* Assigment of value for TFQPI in the CAN_TXFQS register */ +#define CAN_TXFQS_TFQF_Pos _UINT32_(21) /* (CAN_TXFQS) Tx FIFO/Queue Full Position */ +#define CAN_TXFQS_TFQF_Msk (_UINT32_(0x1) << CAN_TXFQS_TFQF_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Full Mask */ +#define CAN_TXFQS_TFQF(value) (CAN_TXFQS_TFQF_Msk & (_UINT32_(value) << CAN_TXFQS_TFQF_Pos)) /* Assigment of value for TFQF in the CAN_TXFQS register */ +#define CAN_TXFQS_Msk _UINT32_(0x003F1F3F) /* (CAN_TXFQS) Register Mask */ + + +/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ +#define CAN_TXESC_RESETVALUE _UINT32_(0x00) /* (CAN_TXESC) Tx Buffer Element Size Configuration Reset Value */ + +#define CAN_TXESC_TBDS_Pos _UINT32_(0) /* (CAN_TXESC) Tx Buffer Data Field Size Position */ +#define CAN_TXESC_TBDS_Msk (_UINT32_(0x7) << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) Tx Buffer Data Field Size Mask */ +#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & (_UINT32_(value) << CAN_TXESC_TBDS_Pos)) /* Assigment of value for TBDS in the CAN_TXESC register */ +#define CAN_TXESC_TBDS_DATA8_Val _UINT32_(0x0) /* (CAN_TXESC) 8 byte data field */ +#define CAN_TXESC_TBDS_DATA12_Val _UINT32_(0x1) /* (CAN_TXESC) 12 byte data field */ +#define CAN_TXESC_TBDS_DATA16_Val _UINT32_(0x2) /* (CAN_TXESC) 16 byte data field */ +#define CAN_TXESC_TBDS_DATA20_Val _UINT32_(0x3) /* (CAN_TXESC) 20 byte data field */ +#define CAN_TXESC_TBDS_DATA24_Val _UINT32_(0x4) /* (CAN_TXESC) 24 byte data field */ +#define CAN_TXESC_TBDS_DATA32_Val _UINT32_(0x5) /* (CAN_TXESC) 32 byte data field */ +#define CAN_TXESC_TBDS_DATA48_Val _UINT32_(0x6) /* (CAN_TXESC) 48 byte data field */ +#define CAN_TXESC_TBDS_DATA64_Val _UINT32_(0x7) /* (CAN_TXESC) 64 byte data field */ +#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 8 byte data field Position */ +#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 12 byte data field Position */ +#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 16 byte data field Position */ +#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 20 byte data field Position */ +#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 24 byte data field Position */ +#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 32 byte data field Position */ +#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 48 byte data field Position */ +#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 64 byte data field Position */ +#define CAN_TXESC_Msk _UINT32_(0x00000007) /* (CAN_TXESC) Register Mask */ + + +/* -------- CAN_TXBRP : (CAN Offset: 0xCC) ( R/ 32) Tx Buffer Request Pending -------- */ +#define CAN_TXBRP_RESETVALUE _UINT32_(0x00) /* (CAN_TXBRP) Tx Buffer Request Pending Reset Value */ + +#define CAN_TXBRP_TRP0_Pos _UINT32_(0) /* (CAN_TXBRP) Transmission Request Pending 0 Position */ +#define CAN_TXBRP_TRP0_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP0_Pos) /* (CAN_TXBRP) Transmission Request Pending 0 Mask */ +#define CAN_TXBRP_TRP0(value) (CAN_TXBRP_TRP0_Msk & (_UINT32_(value) << CAN_TXBRP_TRP0_Pos)) /* Assigment of value for TRP0 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP1_Pos _UINT32_(1) /* (CAN_TXBRP) Transmission Request Pending 1 Position */ +#define CAN_TXBRP_TRP1_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP1_Pos) /* (CAN_TXBRP) Transmission Request Pending 1 Mask */ +#define CAN_TXBRP_TRP1(value) (CAN_TXBRP_TRP1_Msk & (_UINT32_(value) << CAN_TXBRP_TRP1_Pos)) /* Assigment of value for TRP1 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP2_Pos _UINT32_(2) /* (CAN_TXBRP) Transmission Request Pending 2 Position */ +#define CAN_TXBRP_TRP2_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP2_Pos) /* (CAN_TXBRP) Transmission Request Pending 2 Mask */ +#define CAN_TXBRP_TRP2(value) (CAN_TXBRP_TRP2_Msk & (_UINT32_(value) << CAN_TXBRP_TRP2_Pos)) /* Assigment of value for TRP2 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP3_Pos _UINT32_(3) /* (CAN_TXBRP) Transmission Request Pending 3 Position */ +#define CAN_TXBRP_TRP3_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP3_Pos) /* (CAN_TXBRP) Transmission Request Pending 3 Mask */ +#define CAN_TXBRP_TRP3(value) (CAN_TXBRP_TRP3_Msk & (_UINT32_(value) << CAN_TXBRP_TRP3_Pos)) /* Assigment of value for TRP3 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP4_Pos _UINT32_(4) /* (CAN_TXBRP) Transmission Request Pending 4 Position */ +#define CAN_TXBRP_TRP4_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP4_Pos) /* (CAN_TXBRP) Transmission Request Pending 4 Mask */ +#define CAN_TXBRP_TRP4(value) (CAN_TXBRP_TRP4_Msk & (_UINT32_(value) << CAN_TXBRP_TRP4_Pos)) /* Assigment of value for TRP4 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP5_Pos _UINT32_(5) /* (CAN_TXBRP) Transmission Request Pending 5 Position */ +#define CAN_TXBRP_TRP5_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP5_Pos) /* (CAN_TXBRP) Transmission Request Pending 5 Mask */ +#define CAN_TXBRP_TRP5(value) (CAN_TXBRP_TRP5_Msk & (_UINT32_(value) << CAN_TXBRP_TRP5_Pos)) /* Assigment of value for TRP5 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP6_Pos _UINT32_(6) /* (CAN_TXBRP) Transmission Request Pending 6 Position */ +#define CAN_TXBRP_TRP6_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP6_Pos) /* (CAN_TXBRP) Transmission Request Pending 6 Mask */ +#define CAN_TXBRP_TRP6(value) (CAN_TXBRP_TRP6_Msk & (_UINT32_(value) << CAN_TXBRP_TRP6_Pos)) /* Assigment of value for TRP6 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP7_Pos _UINT32_(7) /* (CAN_TXBRP) Transmission Request Pending 7 Position */ +#define CAN_TXBRP_TRP7_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP7_Pos) /* (CAN_TXBRP) Transmission Request Pending 7 Mask */ +#define CAN_TXBRP_TRP7(value) (CAN_TXBRP_TRP7_Msk & (_UINT32_(value) << CAN_TXBRP_TRP7_Pos)) /* Assigment of value for TRP7 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP8_Pos _UINT32_(8) /* (CAN_TXBRP) Transmission Request Pending 8 Position */ +#define CAN_TXBRP_TRP8_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP8_Pos) /* (CAN_TXBRP) Transmission Request Pending 8 Mask */ +#define CAN_TXBRP_TRP8(value) (CAN_TXBRP_TRP8_Msk & (_UINT32_(value) << CAN_TXBRP_TRP8_Pos)) /* Assigment of value for TRP8 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP9_Pos _UINT32_(9) /* (CAN_TXBRP) Transmission Request Pending 9 Position */ +#define CAN_TXBRP_TRP9_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP9_Pos) /* (CAN_TXBRP) Transmission Request Pending 9 Mask */ +#define CAN_TXBRP_TRP9(value) (CAN_TXBRP_TRP9_Msk & (_UINT32_(value) << CAN_TXBRP_TRP9_Pos)) /* Assigment of value for TRP9 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP10_Pos _UINT32_(10) /* (CAN_TXBRP) Transmission Request Pending 10 Position */ +#define CAN_TXBRP_TRP10_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP10_Pos) /* (CAN_TXBRP) Transmission Request Pending 10 Mask */ +#define CAN_TXBRP_TRP10(value) (CAN_TXBRP_TRP10_Msk & (_UINT32_(value) << CAN_TXBRP_TRP10_Pos)) /* Assigment of value for TRP10 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP11_Pos _UINT32_(11) /* (CAN_TXBRP) Transmission Request Pending 11 Position */ +#define CAN_TXBRP_TRP11_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP11_Pos) /* (CAN_TXBRP) Transmission Request Pending 11 Mask */ +#define CAN_TXBRP_TRP11(value) (CAN_TXBRP_TRP11_Msk & (_UINT32_(value) << CAN_TXBRP_TRP11_Pos)) /* Assigment of value for TRP11 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP12_Pos _UINT32_(12) /* (CAN_TXBRP) Transmission Request Pending 12 Position */ +#define CAN_TXBRP_TRP12_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP12_Pos) /* (CAN_TXBRP) Transmission Request Pending 12 Mask */ +#define CAN_TXBRP_TRP12(value) (CAN_TXBRP_TRP12_Msk & (_UINT32_(value) << CAN_TXBRP_TRP12_Pos)) /* Assigment of value for TRP12 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP13_Pos _UINT32_(13) /* (CAN_TXBRP) Transmission Request Pending 13 Position */ +#define CAN_TXBRP_TRP13_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP13_Pos) /* (CAN_TXBRP) Transmission Request Pending 13 Mask */ +#define CAN_TXBRP_TRP13(value) (CAN_TXBRP_TRP13_Msk & (_UINT32_(value) << CAN_TXBRP_TRP13_Pos)) /* Assigment of value for TRP13 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP14_Pos _UINT32_(14) /* (CAN_TXBRP) Transmission Request Pending 14 Position */ +#define CAN_TXBRP_TRP14_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP14_Pos) /* (CAN_TXBRP) Transmission Request Pending 14 Mask */ +#define CAN_TXBRP_TRP14(value) (CAN_TXBRP_TRP14_Msk & (_UINT32_(value) << CAN_TXBRP_TRP14_Pos)) /* Assigment of value for TRP14 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP15_Pos _UINT32_(15) /* (CAN_TXBRP) Transmission Request Pending 15 Position */ +#define CAN_TXBRP_TRP15_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP15_Pos) /* (CAN_TXBRP) Transmission Request Pending 15 Mask */ +#define CAN_TXBRP_TRP15(value) (CAN_TXBRP_TRP15_Msk & (_UINT32_(value) << CAN_TXBRP_TRP15_Pos)) /* Assigment of value for TRP15 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP16_Pos _UINT32_(16) /* (CAN_TXBRP) Transmission Request Pending 16 Position */ +#define CAN_TXBRP_TRP16_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP16_Pos) /* (CAN_TXBRP) Transmission Request Pending 16 Mask */ +#define CAN_TXBRP_TRP16(value) (CAN_TXBRP_TRP16_Msk & (_UINT32_(value) << CAN_TXBRP_TRP16_Pos)) /* Assigment of value for TRP16 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP17_Pos _UINT32_(17) /* (CAN_TXBRP) Transmission Request Pending 17 Position */ +#define CAN_TXBRP_TRP17_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP17_Pos) /* (CAN_TXBRP) Transmission Request Pending 17 Mask */ +#define CAN_TXBRP_TRP17(value) (CAN_TXBRP_TRP17_Msk & (_UINT32_(value) << CAN_TXBRP_TRP17_Pos)) /* Assigment of value for TRP17 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP18_Pos _UINT32_(18) /* (CAN_TXBRP) Transmission Request Pending 18 Position */ +#define CAN_TXBRP_TRP18_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP18_Pos) /* (CAN_TXBRP) Transmission Request Pending 18 Mask */ +#define CAN_TXBRP_TRP18(value) (CAN_TXBRP_TRP18_Msk & (_UINT32_(value) << CAN_TXBRP_TRP18_Pos)) /* Assigment of value for TRP18 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP19_Pos _UINT32_(19) /* (CAN_TXBRP) Transmission Request Pending 19 Position */ +#define CAN_TXBRP_TRP19_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP19_Pos) /* (CAN_TXBRP) Transmission Request Pending 19 Mask */ +#define CAN_TXBRP_TRP19(value) (CAN_TXBRP_TRP19_Msk & (_UINT32_(value) << CAN_TXBRP_TRP19_Pos)) /* Assigment of value for TRP19 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP20_Pos _UINT32_(20) /* (CAN_TXBRP) Transmission Request Pending 20 Position */ +#define CAN_TXBRP_TRP20_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP20_Pos) /* (CAN_TXBRP) Transmission Request Pending 20 Mask */ +#define CAN_TXBRP_TRP20(value) (CAN_TXBRP_TRP20_Msk & (_UINT32_(value) << CAN_TXBRP_TRP20_Pos)) /* Assigment of value for TRP20 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP21_Pos _UINT32_(21) /* (CAN_TXBRP) Transmission Request Pending 21 Position */ +#define CAN_TXBRP_TRP21_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP21_Pos) /* (CAN_TXBRP) Transmission Request Pending 21 Mask */ +#define CAN_TXBRP_TRP21(value) (CAN_TXBRP_TRP21_Msk & (_UINT32_(value) << CAN_TXBRP_TRP21_Pos)) /* Assigment of value for TRP21 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP22_Pos _UINT32_(22) /* (CAN_TXBRP) Transmission Request Pending 22 Position */ +#define CAN_TXBRP_TRP22_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP22_Pos) /* (CAN_TXBRP) Transmission Request Pending 22 Mask */ +#define CAN_TXBRP_TRP22(value) (CAN_TXBRP_TRP22_Msk & (_UINT32_(value) << CAN_TXBRP_TRP22_Pos)) /* Assigment of value for TRP22 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP23_Pos _UINT32_(23) /* (CAN_TXBRP) Transmission Request Pending 23 Position */ +#define CAN_TXBRP_TRP23_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP23_Pos) /* (CAN_TXBRP) Transmission Request Pending 23 Mask */ +#define CAN_TXBRP_TRP23(value) (CAN_TXBRP_TRP23_Msk & (_UINT32_(value) << CAN_TXBRP_TRP23_Pos)) /* Assigment of value for TRP23 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP24_Pos _UINT32_(24) /* (CAN_TXBRP) Transmission Request Pending 24 Position */ +#define CAN_TXBRP_TRP24_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP24_Pos) /* (CAN_TXBRP) Transmission Request Pending 24 Mask */ +#define CAN_TXBRP_TRP24(value) (CAN_TXBRP_TRP24_Msk & (_UINT32_(value) << CAN_TXBRP_TRP24_Pos)) /* Assigment of value for TRP24 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP25_Pos _UINT32_(25) /* (CAN_TXBRP) Transmission Request Pending 25 Position */ +#define CAN_TXBRP_TRP25_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP25_Pos) /* (CAN_TXBRP) Transmission Request Pending 25 Mask */ +#define CAN_TXBRP_TRP25(value) (CAN_TXBRP_TRP25_Msk & (_UINT32_(value) << CAN_TXBRP_TRP25_Pos)) /* Assigment of value for TRP25 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP26_Pos _UINT32_(26) /* (CAN_TXBRP) Transmission Request Pending 26 Position */ +#define CAN_TXBRP_TRP26_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP26_Pos) /* (CAN_TXBRP) Transmission Request Pending 26 Mask */ +#define CAN_TXBRP_TRP26(value) (CAN_TXBRP_TRP26_Msk & (_UINT32_(value) << CAN_TXBRP_TRP26_Pos)) /* Assigment of value for TRP26 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP27_Pos _UINT32_(27) /* (CAN_TXBRP) Transmission Request Pending 27 Position */ +#define CAN_TXBRP_TRP27_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP27_Pos) /* (CAN_TXBRP) Transmission Request Pending 27 Mask */ +#define CAN_TXBRP_TRP27(value) (CAN_TXBRP_TRP27_Msk & (_UINT32_(value) << CAN_TXBRP_TRP27_Pos)) /* Assigment of value for TRP27 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP28_Pos _UINT32_(28) /* (CAN_TXBRP) Transmission Request Pending 28 Position */ +#define CAN_TXBRP_TRP28_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP28_Pos) /* (CAN_TXBRP) Transmission Request Pending 28 Mask */ +#define CAN_TXBRP_TRP28(value) (CAN_TXBRP_TRP28_Msk & (_UINT32_(value) << CAN_TXBRP_TRP28_Pos)) /* Assigment of value for TRP28 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP29_Pos _UINT32_(29) /* (CAN_TXBRP) Transmission Request Pending 29 Position */ +#define CAN_TXBRP_TRP29_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP29_Pos) /* (CAN_TXBRP) Transmission Request Pending 29 Mask */ +#define CAN_TXBRP_TRP29(value) (CAN_TXBRP_TRP29_Msk & (_UINT32_(value) << CAN_TXBRP_TRP29_Pos)) /* Assigment of value for TRP29 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP30_Pos _UINT32_(30) /* (CAN_TXBRP) Transmission Request Pending 30 Position */ +#define CAN_TXBRP_TRP30_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP30_Pos) /* (CAN_TXBRP) Transmission Request Pending 30 Mask */ +#define CAN_TXBRP_TRP30(value) (CAN_TXBRP_TRP30_Msk & (_UINT32_(value) << CAN_TXBRP_TRP30_Pos)) /* Assigment of value for TRP30 in the CAN_TXBRP register */ +#define CAN_TXBRP_TRP31_Pos _UINT32_(31) /* (CAN_TXBRP) Transmission Request Pending 31 Position */ +#define CAN_TXBRP_TRP31_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP31_Pos) /* (CAN_TXBRP) Transmission Request Pending 31 Mask */ +#define CAN_TXBRP_TRP31(value) (CAN_TXBRP_TRP31_Msk & (_UINT32_(value) << CAN_TXBRP_TRP31_Pos)) /* Assigment of value for TRP31 in the CAN_TXBRP register */ +#define CAN_TXBRP_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBRP) Register Mask */ + +#define CAN_TXBRP_TRP_Pos _UINT32_(0) /* (CAN_TXBRP Position) Transmission Request Pending 3x */ +#define CAN_TXBRP_TRP_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBRP_TRP_Pos) /* (CAN_TXBRP Mask) TRP */ +#define CAN_TXBRP_TRP(value) (CAN_TXBRP_TRP_Msk & (_UINT32_(value) << CAN_TXBRP_TRP_Pos)) + +/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ +#define CAN_TXBAR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBAR) Tx Buffer Add Request Reset Value */ + +#define CAN_TXBAR_AR0_Pos _UINT32_(0) /* (CAN_TXBAR) Add Request 0 Position */ +#define CAN_TXBAR_AR0_Msk (_UINT32_(0x1) << CAN_TXBAR_AR0_Pos) /* (CAN_TXBAR) Add Request 0 Mask */ +#define CAN_TXBAR_AR0(value) (CAN_TXBAR_AR0_Msk & (_UINT32_(value) << CAN_TXBAR_AR0_Pos)) /* Assigment of value for AR0 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR1_Pos _UINT32_(1) /* (CAN_TXBAR) Add Request 1 Position */ +#define CAN_TXBAR_AR1_Msk (_UINT32_(0x1) << CAN_TXBAR_AR1_Pos) /* (CAN_TXBAR) Add Request 1 Mask */ +#define CAN_TXBAR_AR1(value) (CAN_TXBAR_AR1_Msk & (_UINT32_(value) << CAN_TXBAR_AR1_Pos)) /* Assigment of value for AR1 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR2_Pos _UINT32_(2) /* (CAN_TXBAR) Add Request 2 Position */ +#define CAN_TXBAR_AR2_Msk (_UINT32_(0x1) << CAN_TXBAR_AR2_Pos) /* (CAN_TXBAR) Add Request 2 Mask */ +#define CAN_TXBAR_AR2(value) (CAN_TXBAR_AR2_Msk & (_UINT32_(value) << CAN_TXBAR_AR2_Pos)) /* Assigment of value for AR2 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR3_Pos _UINT32_(3) /* (CAN_TXBAR) Add Request 3 Position */ +#define CAN_TXBAR_AR3_Msk (_UINT32_(0x1) << CAN_TXBAR_AR3_Pos) /* (CAN_TXBAR) Add Request 3 Mask */ +#define CAN_TXBAR_AR3(value) (CAN_TXBAR_AR3_Msk & (_UINT32_(value) << CAN_TXBAR_AR3_Pos)) /* Assigment of value for AR3 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR4_Pos _UINT32_(4) /* (CAN_TXBAR) Add Request 4 Position */ +#define CAN_TXBAR_AR4_Msk (_UINT32_(0x1) << CAN_TXBAR_AR4_Pos) /* (CAN_TXBAR) Add Request 4 Mask */ +#define CAN_TXBAR_AR4(value) (CAN_TXBAR_AR4_Msk & (_UINT32_(value) << CAN_TXBAR_AR4_Pos)) /* Assigment of value for AR4 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR5_Pos _UINT32_(5) /* (CAN_TXBAR) Add Request 5 Position */ +#define CAN_TXBAR_AR5_Msk (_UINT32_(0x1) << CAN_TXBAR_AR5_Pos) /* (CAN_TXBAR) Add Request 5 Mask */ +#define CAN_TXBAR_AR5(value) (CAN_TXBAR_AR5_Msk & (_UINT32_(value) << CAN_TXBAR_AR5_Pos)) /* Assigment of value for AR5 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR6_Pos _UINT32_(6) /* (CAN_TXBAR) Add Request 6 Position */ +#define CAN_TXBAR_AR6_Msk (_UINT32_(0x1) << CAN_TXBAR_AR6_Pos) /* (CAN_TXBAR) Add Request 6 Mask */ +#define CAN_TXBAR_AR6(value) (CAN_TXBAR_AR6_Msk & (_UINT32_(value) << CAN_TXBAR_AR6_Pos)) /* Assigment of value for AR6 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR7_Pos _UINT32_(7) /* (CAN_TXBAR) Add Request 7 Position */ +#define CAN_TXBAR_AR7_Msk (_UINT32_(0x1) << CAN_TXBAR_AR7_Pos) /* (CAN_TXBAR) Add Request 7 Mask */ +#define CAN_TXBAR_AR7(value) (CAN_TXBAR_AR7_Msk & (_UINT32_(value) << CAN_TXBAR_AR7_Pos)) /* Assigment of value for AR7 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR8_Pos _UINT32_(8) /* (CAN_TXBAR) Add Request 8 Position */ +#define CAN_TXBAR_AR8_Msk (_UINT32_(0x1) << CAN_TXBAR_AR8_Pos) /* (CAN_TXBAR) Add Request 8 Mask */ +#define CAN_TXBAR_AR8(value) (CAN_TXBAR_AR8_Msk & (_UINT32_(value) << CAN_TXBAR_AR8_Pos)) /* Assigment of value for AR8 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR9_Pos _UINT32_(9) /* (CAN_TXBAR) Add Request 9 Position */ +#define CAN_TXBAR_AR9_Msk (_UINT32_(0x1) << CAN_TXBAR_AR9_Pos) /* (CAN_TXBAR) Add Request 9 Mask */ +#define CAN_TXBAR_AR9(value) (CAN_TXBAR_AR9_Msk & (_UINT32_(value) << CAN_TXBAR_AR9_Pos)) /* Assigment of value for AR9 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR10_Pos _UINT32_(10) /* (CAN_TXBAR) Add Request 10 Position */ +#define CAN_TXBAR_AR10_Msk (_UINT32_(0x1) << CAN_TXBAR_AR10_Pos) /* (CAN_TXBAR) Add Request 10 Mask */ +#define CAN_TXBAR_AR10(value) (CAN_TXBAR_AR10_Msk & (_UINT32_(value) << CAN_TXBAR_AR10_Pos)) /* Assigment of value for AR10 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR11_Pos _UINT32_(11) /* (CAN_TXBAR) Add Request 11 Position */ +#define CAN_TXBAR_AR11_Msk (_UINT32_(0x1) << CAN_TXBAR_AR11_Pos) /* (CAN_TXBAR) Add Request 11 Mask */ +#define CAN_TXBAR_AR11(value) (CAN_TXBAR_AR11_Msk & (_UINT32_(value) << CAN_TXBAR_AR11_Pos)) /* Assigment of value for AR11 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR12_Pos _UINT32_(12) /* (CAN_TXBAR) Add Request 12 Position */ +#define CAN_TXBAR_AR12_Msk (_UINT32_(0x1) << CAN_TXBAR_AR12_Pos) /* (CAN_TXBAR) Add Request 12 Mask */ +#define CAN_TXBAR_AR12(value) (CAN_TXBAR_AR12_Msk & (_UINT32_(value) << CAN_TXBAR_AR12_Pos)) /* Assigment of value for AR12 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR13_Pos _UINT32_(13) /* (CAN_TXBAR) Add Request 13 Position */ +#define CAN_TXBAR_AR13_Msk (_UINT32_(0x1) << CAN_TXBAR_AR13_Pos) /* (CAN_TXBAR) Add Request 13 Mask */ +#define CAN_TXBAR_AR13(value) (CAN_TXBAR_AR13_Msk & (_UINT32_(value) << CAN_TXBAR_AR13_Pos)) /* Assigment of value for AR13 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR14_Pos _UINT32_(14) /* (CAN_TXBAR) Add Request 14 Position */ +#define CAN_TXBAR_AR14_Msk (_UINT32_(0x1) << CAN_TXBAR_AR14_Pos) /* (CAN_TXBAR) Add Request 14 Mask */ +#define CAN_TXBAR_AR14(value) (CAN_TXBAR_AR14_Msk & (_UINT32_(value) << CAN_TXBAR_AR14_Pos)) /* Assigment of value for AR14 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR15_Pos _UINT32_(15) /* (CAN_TXBAR) Add Request 15 Position */ +#define CAN_TXBAR_AR15_Msk (_UINT32_(0x1) << CAN_TXBAR_AR15_Pos) /* (CAN_TXBAR) Add Request 15 Mask */ +#define CAN_TXBAR_AR15(value) (CAN_TXBAR_AR15_Msk & (_UINT32_(value) << CAN_TXBAR_AR15_Pos)) /* Assigment of value for AR15 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR16_Pos _UINT32_(16) /* (CAN_TXBAR) Add Request 16 Position */ +#define CAN_TXBAR_AR16_Msk (_UINT32_(0x1) << CAN_TXBAR_AR16_Pos) /* (CAN_TXBAR) Add Request 16 Mask */ +#define CAN_TXBAR_AR16(value) (CAN_TXBAR_AR16_Msk & (_UINT32_(value) << CAN_TXBAR_AR16_Pos)) /* Assigment of value for AR16 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR17_Pos _UINT32_(17) /* (CAN_TXBAR) Add Request 17 Position */ +#define CAN_TXBAR_AR17_Msk (_UINT32_(0x1) << CAN_TXBAR_AR17_Pos) /* (CAN_TXBAR) Add Request 17 Mask */ +#define CAN_TXBAR_AR17(value) (CAN_TXBAR_AR17_Msk & (_UINT32_(value) << CAN_TXBAR_AR17_Pos)) /* Assigment of value for AR17 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR18_Pos _UINT32_(18) /* (CAN_TXBAR) Add Request 18 Position */ +#define CAN_TXBAR_AR18_Msk (_UINT32_(0x1) << CAN_TXBAR_AR18_Pos) /* (CAN_TXBAR) Add Request 18 Mask */ +#define CAN_TXBAR_AR18(value) (CAN_TXBAR_AR18_Msk & (_UINT32_(value) << CAN_TXBAR_AR18_Pos)) /* Assigment of value for AR18 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR19_Pos _UINT32_(19) /* (CAN_TXBAR) Add Request 19 Position */ +#define CAN_TXBAR_AR19_Msk (_UINT32_(0x1) << CAN_TXBAR_AR19_Pos) /* (CAN_TXBAR) Add Request 19 Mask */ +#define CAN_TXBAR_AR19(value) (CAN_TXBAR_AR19_Msk & (_UINT32_(value) << CAN_TXBAR_AR19_Pos)) /* Assigment of value for AR19 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR20_Pos _UINT32_(20) /* (CAN_TXBAR) Add Request 20 Position */ +#define CAN_TXBAR_AR20_Msk (_UINT32_(0x1) << CAN_TXBAR_AR20_Pos) /* (CAN_TXBAR) Add Request 20 Mask */ +#define CAN_TXBAR_AR20(value) (CAN_TXBAR_AR20_Msk & (_UINT32_(value) << CAN_TXBAR_AR20_Pos)) /* Assigment of value for AR20 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR21_Pos _UINT32_(21) /* (CAN_TXBAR) Add Request 21 Position */ +#define CAN_TXBAR_AR21_Msk (_UINT32_(0x1) << CAN_TXBAR_AR21_Pos) /* (CAN_TXBAR) Add Request 21 Mask */ +#define CAN_TXBAR_AR21(value) (CAN_TXBAR_AR21_Msk & (_UINT32_(value) << CAN_TXBAR_AR21_Pos)) /* Assigment of value for AR21 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR22_Pos _UINT32_(22) /* (CAN_TXBAR) Add Request 22 Position */ +#define CAN_TXBAR_AR22_Msk (_UINT32_(0x1) << CAN_TXBAR_AR22_Pos) /* (CAN_TXBAR) Add Request 22 Mask */ +#define CAN_TXBAR_AR22(value) (CAN_TXBAR_AR22_Msk & (_UINT32_(value) << CAN_TXBAR_AR22_Pos)) /* Assigment of value for AR22 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR23_Pos _UINT32_(23) /* (CAN_TXBAR) Add Request 23 Position */ +#define CAN_TXBAR_AR23_Msk (_UINT32_(0x1) << CAN_TXBAR_AR23_Pos) /* (CAN_TXBAR) Add Request 23 Mask */ +#define CAN_TXBAR_AR23(value) (CAN_TXBAR_AR23_Msk & (_UINT32_(value) << CAN_TXBAR_AR23_Pos)) /* Assigment of value for AR23 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR24_Pos _UINT32_(24) /* (CAN_TXBAR) Add Request 24 Position */ +#define CAN_TXBAR_AR24_Msk (_UINT32_(0x1) << CAN_TXBAR_AR24_Pos) /* (CAN_TXBAR) Add Request 24 Mask */ +#define CAN_TXBAR_AR24(value) (CAN_TXBAR_AR24_Msk & (_UINT32_(value) << CAN_TXBAR_AR24_Pos)) /* Assigment of value for AR24 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR25_Pos _UINT32_(25) /* (CAN_TXBAR) Add Request 25 Position */ +#define CAN_TXBAR_AR25_Msk (_UINT32_(0x1) << CAN_TXBAR_AR25_Pos) /* (CAN_TXBAR) Add Request 25 Mask */ +#define CAN_TXBAR_AR25(value) (CAN_TXBAR_AR25_Msk & (_UINT32_(value) << CAN_TXBAR_AR25_Pos)) /* Assigment of value for AR25 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR26_Pos _UINT32_(26) /* (CAN_TXBAR) Add Request 26 Position */ +#define CAN_TXBAR_AR26_Msk (_UINT32_(0x1) << CAN_TXBAR_AR26_Pos) /* (CAN_TXBAR) Add Request 26 Mask */ +#define CAN_TXBAR_AR26(value) (CAN_TXBAR_AR26_Msk & (_UINT32_(value) << CAN_TXBAR_AR26_Pos)) /* Assigment of value for AR26 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR27_Pos _UINT32_(27) /* (CAN_TXBAR) Add Request 27 Position */ +#define CAN_TXBAR_AR27_Msk (_UINT32_(0x1) << CAN_TXBAR_AR27_Pos) /* (CAN_TXBAR) Add Request 27 Mask */ +#define CAN_TXBAR_AR27(value) (CAN_TXBAR_AR27_Msk & (_UINT32_(value) << CAN_TXBAR_AR27_Pos)) /* Assigment of value for AR27 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR28_Pos _UINT32_(28) /* (CAN_TXBAR) Add Request 28 Position */ +#define CAN_TXBAR_AR28_Msk (_UINT32_(0x1) << CAN_TXBAR_AR28_Pos) /* (CAN_TXBAR) Add Request 28 Mask */ +#define CAN_TXBAR_AR28(value) (CAN_TXBAR_AR28_Msk & (_UINT32_(value) << CAN_TXBAR_AR28_Pos)) /* Assigment of value for AR28 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR29_Pos _UINT32_(29) /* (CAN_TXBAR) Add Request 29 Position */ +#define CAN_TXBAR_AR29_Msk (_UINT32_(0x1) << CAN_TXBAR_AR29_Pos) /* (CAN_TXBAR) Add Request 29 Mask */ +#define CAN_TXBAR_AR29(value) (CAN_TXBAR_AR29_Msk & (_UINT32_(value) << CAN_TXBAR_AR29_Pos)) /* Assigment of value for AR29 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR30_Pos _UINT32_(30) /* (CAN_TXBAR) Add Request 30 Position */ +#define CAN_TXBAR_AR30_Msk (_UINT32_(0x1) << CAN_TXBAR_AR30_Pos) /* (CAN_TXBAR) Add Request 30 Mask */ +#define CAN_TXBAR_AR30(value) (CAN_TXBAR_AR30_Msk & (_UINT32_(value) << CAN_TXBAR_AR30_Pos)) /* Assigment of value for AR30 in the CAN_TXBAR register */ +#define CAN_TXBAR_AR31_Pos _UINT32_(31) /* (CAN_TXBAR) Add Request 31 Position */ +#define CAN_TXBAR_AR31_Msk (_UINT32_(0x1) << CAN_TXBAR_AR31_Pos) /* (CAN_TXBAR) Add Request 31 Mask */ +#define CAN_TXBAR_AR31(value) (CAN_TXBAR_AR31_Msk & (_UINT32_(value) << CAN_TXBAR_AR31_Pos)) /* Assigment of value for AR31 in the CAN_TXBAR register */ +#define CAN_TXBAR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBAR) Register Mask */ + +#define CAN_TXBAR_AR_Pos _UINT32_(0) /* (CAN_TXBAR Position) Add Request 3x */ +#define CAN_TXBAR_AR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBAR_AR_Pos) /* (CAN_TXBAR Mask) AR */ +#define CAN_TXBAR_AR(value) (CAN_TXBAR_AR_Msk & (_UINT32_(value) << CAN_TXBAR_AR_Pos)) + +/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ +#define CAN_TXBCR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCR) Tx Buffer Cancellation Request Reset Value */ + +#define CAN_TXBCR_CR0_Pos _UINT32_(0) /* (CAN_TXBCR) Cancellation Request 0 Position */ +#define CAN_TXBCR_CR0_Msk (_UINT32_(0x1) << CAN_TXBCR_CR0_Pos) /* (CAN_TXBCR) Cancellation Request 0 Mask */ +#define CAN_TXBCR_CR0(value) (CAN_TXBCR_CR0_Msk & (_UINT32_(value) << CAN_TXBCR_CR0_Pos)) /* Assigment of value for CR0 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR1_Pos _UINT32_(1) /* (CAN_TXBCR) Cancellation Request 1 Position */ +#define CAN_TXBCR_CR1_Msk (_UINT32_(0x1) << CAN_TXBCR_CR1_Pos) /* (CAN_TXBCR) Cancellation Request 1 Mask */ +#define CAN_TXBCR_CR1(value) (CAN_TXBCR_CR1_Msk & (_UINT32_(value) << CAN_TXBCR_CR1_Pos)) /* Assigment of value for CR1 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR2_Pos _UINT32_(2) /* (CAN_TXBCR) Cancellation Request 2 Position */ +#define CAN_TXBCR_CR2_Msk (_UINT32_(0x1) << CAN_TXBCR_CR2_Pos) /* (CAN_TXBCR) Cancellation Request 2 Mask */ +#define CAN_TXBCR_CR2(value) (CAN_TXBCR_CR2_Msk & (_UINT32_(value) << CAN_TXBCR_CR2_Pos)) /* Assigment of value for CR2 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR3_Pos _UINT32_(3) /* (CAN_TXBCR) Cancellation Request 3 Position */ +#define CAN_TXBCR_CR3_Msk (_UINT32_(0x1) << CAN_TXBCR_CR3_Pos) /* (CAN_TXBCR) Cancellation Request 3 Mask */ +#define CAN_TXBCR_CR3(value) (CAN_TXBCR_CR3_Msk & (_UINT32_(value) << CAN_TXBCR_CR3_Pos)) /* Assigment of value for CR3 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR4_Pos _UINT32_(4) /* (CAN_TXBCR) Cancellation Request 4 Position */ +#define CAN_TXBCR_CR4_Msk (_UINT32_(0x1) << CAN_TXBCR_CR4_Pos) /* (CAN_TXBCR) Cancellation Request 4 Mask */ +#define CAN_TXBCR_CR4(value) (CAN_TXBCR_CR4_Msk & (_UINT32_(value) << CAN_TXBCR_CR4_Pos)) /* Assigment of value for CR4 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR5_Pos _UINT32_(5) /* (CAN_TXBCR) Cancellation Request 5 Position */ +#define CAN_TXBCR_CR5_Msk (_UINT32_(0x1) << CAN_TXBCR_CR5_Pos) /* (CAN_TXBCR) Cancellation Request 5 Mask */ +#define CAN_TXBCR_CR5(value) (CAN_TXBCR_CR5_Msk & (_UINT32_(value) << CAN_TXBCR_CR5_Pos)) /* Assigment of value for CR5 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR6_Pos _UINT32_(6) /* (CAN_TXBCR) Cancellation Request 6 Position */ +#define CAN_TXBCR_CR6_Msk (_UINT32_(0x1) << CAN_TXBCR_CR6_Pos) /* (CAN_TXBCR) Cancellation Request 6 Mask */ +#define CAN_TXBCR_CR6(value) (CAN_TXBCR_CR6_Msk & (_UINT32_(value) << CAN_TXBCR_CR6_Pos)) /* Assigment of value for CR6 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR7_Pos _UINT32_(7) /* (CAN_TXBCR) Cancellation Request 7 Position */ +#define CAN_TXBCR_CR7_Msk (_UINT32_(0x1) << CAN_TXBCR_CR7_Pos) /* (CAN_TXBCR) Cancellation Request 7 Mask */ +#define CAN_TXBCR_CR7(value) (CAN_TXBCR_CR7_Msk & (_UINT32_(value) << CAN_TXBCR_CR7_Pos)) /* Assigment of value for CR7 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR8_Pos _UINT32_(8) /* (CAN_TXBCR) Cancellation Request 8 Position */ +#define CAN_TXBCR_CR8_Msk (_UINT32_(0x1) << CAN_TXBCR_CR8_Pos) /* (CAN_TXBCR) Cancellation Request 8 Mask */ +#define CAN_TXBCR_CR8(value) (CAN_TXBCR_CR8_Msk & (_UINT32_(value) << CAN_TXBCR_CR8_Pos)) /* Assigment of value for CR8 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR9_Pos _UINT32_(9) /* (CAN_TXBCR) Cancellation Request 9 Position */ +#define CAN_TXBCR_CR9_Msk (_UINT32_(0x1) << CAN_TXBCR_CR9_Pos) /* (CAN_TXBCR) Cancellation Request 9 Mask */ +#define CAN_TXBCR_CR9(value) (CAN_TXBCR_CR9_Msk & (_UINT32_(value) << CAN_TXBCR_CR9_Pos)) /* Assigment of value for CR9 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR10_Pos _UINT32_(10) /* (CAN_TXBCR) Cancellation Request 10 Position */ +#define CAN_TXBCR_CR10_Msk (_UINT32_(0x1) << CAN_TXBCR_CR10_Pos) /* (CAN_TXBCR) Cancellation Request 10 Mask */ +#define CAN_TXBCR_CR10(value) (CAN_TXBCR_CR10_Msk & (_UINT32_(value) << CAN_TXBCR_CR10_Pos)) /* Assigment of value for CR10 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR11_Pos _UINT32_(11) /* (CAN_TXBCR) Cancellation Request 11 Position */ +#define CAN_TXBCR_CR11_Msk (_UINT32_(0x1) << CAN_TXBCR_CR11_Pos) /* (CAN_TXBCR) Cancellation Request 11 Mask */ +#define CAN_TXBCR_CR11(value) (CAN_TXBCR_CR11_Msk & (_UINT32_(value) << CAN_TXBCR_CR11_Pos)) /* Assigment of value for CR11 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR12_Pos _UINT32_(12) /* (CAN_TXBCR) Cancellation Request 12 Position */ +#define CAN_TXBCR_CR12_Msk (_UINT32_(0x1) << CAN_TXBCR_CR12_Pos) /* (CAN_TXBCR) Cancellation Request 12 Mask */ +#define CAN_TXBCR_CR12(value) (CAN_TXBCR_CR12_Msk & (_UINT32_(value) << CAN_TXBCR_CR12_Pos)) /* Assigment of value for CR12 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR13_Pos _UINT32_(13) /* (CAN_TXBCR) Cancellation Request 13 Position */ +#define CAN_TXBCR_CR13_Msk (_UINT32_(0x1) << CAN_TXBCR_CR13_Pos) /* (CAN_TXBCR) Cancellation Request 13 Mask */ +#define CAN_TXBCR_CR13(value) (CAN_TXBCR_CR13_Msk & (_UINT32_(value) << CAN_TXBCR_CR13_Pos)) /* Assigment of value for CR13 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR14_Pos _UINT32_(14) /* (CAN_TXBCR) Cancellation Request 14 Position */ +#define CAN_TXBCR_CR14_Msk (_UINT32_(0x1) << CAN_TXBCR_CR14_Pos) /* (CAN_TXBCR) Cancellation Request 14 Mask */ +#define CAN_TXBCR_CR14(value) (CAN_TXBCR_CR14_Msk & (_UINT32_(value) << CAN_TXBCR_CR14_Pos)) /* Assigment of value for CR14 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR15_Pos _UINT32_(15) /* (CAN_TXBCR) Cancellation Request 15 Position */ +#define CAN_TXBCR_CR15_Msk (_UINT32_(0x1) << CAN_TXBCR_CR15_Pos) /* (CAN_TXBCR) Cancellation Request 15 Mask */ +#define CAN_TXBCR_CR15(value) (CAN_TXBCR_CR15_Msk & (_UINT32_(value) << CAN_TXBCR_CR15_Pos)) /* Assigment of value for CR15 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR16_Pos _UINT32_(16) /* (CAN_TXBCR) Cancellation Request 16 Position */ +#define CAN_TXBCR_CR16_Msk (_UINT32_(0x1) << CAN_TXBCR_CR16_Pos) /* (CAN_TXBCR) Cancellation Request 16 Mask */ +#define CAN_TXBCR_CR16(value) (CAN_TXBCR_CR16_Msk & (_UINT32_(value) << CAN_TXBCR_CR16_Pos)) /* Assigment of value for CR16 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR17_Pos _UINT32_(17) /* (CAN_TXBCR) Cancellation Request 17 Position */ +#define CAN_TXBCR_CR17_Msk (_UINT32_(0x1) << CAN_TXBCR_CR17_Pos) /* (CAN_TXBCR) Cancellation Request 17 Mask */ +#define CAN_TXBCR_CR17(value) (CAN_TXBCR_CR17_Msk & (_UINT32_(value) << CAN_TXBCR_CR17_Pos)) /* Assigment of value for CR17 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR18_Pos _UINT32_(18) /* (CAN_TXBCR) Cancellation Request 18 Position */ +#define CAN_TXBCR_CR18_Msk (_UINT32_(0x1) << CAN_TXBCR_CR18_Pos) /* (CAN_TXBCR) Cancellation Request 18 Mask */ +#define CAN_TXBCR_CR18(value) (CAN_TXBCR_CR18_Msk & (_UINT32_(value) << CAN_TXBCR_CR18_Pos)) /* Assigment of value for CR18 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR19_Pos _UINT32_(19) /* (CAN_TXBCR) Cancellation Request 19 Position */ +#define CAN_TXBCR_CR19_Msk (_UINT32_(0x1) << CAN_TXBCR_CR19_Pos) /* (CAN_TXBCR) Cancellation Request 19 Mask */ +#define CAN_TXBCR_CR19(value) (CAN_TXBCR_CR19_Msk & (_UINT32_(value) << CAN_TXBCR_CR19_Pos)) /* Assigment of value for CR19 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR20_Pos _UINT32_(20) /* (CAN_TXBCR) Cancellation Request 20 Position */ +#define CAN_TXBCR_CR20_Msk (_UINT32_(0x1) << CAN_TXBCR_CR20_Pos) /* (CAN_TXBCR) Cancellation Request 20 Mask */ +#define CAN_TXBCR_CR20(value) (CAN_TXBCR_CR20_Msk & (_UINT32_(value) << CAN_TXBCR_CR20_Pos)) /* Assigment of value for CR20 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR21_Pos _UINT32_(21) /* (CAN_TXBCR) Cancellation Request 21 Position */ +#define CAN_TXBCR_CR21_Msk (_UINT32_(0x1) << CAN_TXBCR_CR21_Pos) /* (CAN_TXBCR) Cancellation Request 21 Mask */ +#define CAN_TXBCR_CR21(value) (CAN_TXBCR_CR21_Msk & (_UINT32_(value) << CAN_TXBCR_CR21_Pos)) /* Assigment of value for CR21 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR22_Pos _UINT32_(22) /* (CAN_TXBCR) Cancellation Request 22 Position */ +#define CAN_TXBCR_CR22_Msk (_UINT32_(0x1) << CAN_TXBCR_CR22_Pos) /* (CAN_TXBCR) Cancellation Request 22 Mask */ +#define CAN_TXBCR_CR22(value) (CAN_TXBCR_CR22_Msk & (_UINT32_(value) << CAN_TXBCR_CR22_Pos)) /* Assigment of value for CR22 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR23_Pos _UINT32_(23) /* (CAN_TXBCR) Cancellation Request 23 Position */ +#define CAN_TXBCR_CR23_Msk (_UINT32_(0x1) << CAN_TXBCR_CR23_Pos) /* (CAN_TXBCR) Cancellation Request 23 Mask */ +#define CAN_TXBCR_CR23(value) (CAN_TXBCR_CR23_Msk & (_UINT32_(value) << CAN_TXBCR_CR23_Pos)) /* Assigment of value for CR23 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR24_Pos _UINT32_(24) /* (CAN_TXBCR) Cancellation Request 24 Position */ +#define CAN_TXBCR_CR24_Msk (_UINT32_(0x1) << CAN_TXBCR_CR24_Pos) /* (CAN_TXBCR) Cancellation Request 24 Mask */ +#define CAN_TXBCR_CR24(value) (CAN_TXBCR_CR24_Msk & (_UINT32_(value) << CAN_TXBCR_CR24_Pos)) /* Assigment of value for CR24 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR25_Pos _UINT32_(25) /* (CAN_TXBCR) Cancellation Request 25 Position */ +#define CAN_TXBCR_CR25_Msk (_UINT32_(0x1) << CAN_TXBCR_CR25_Pos) /* (CAN_TXBCR) Cancellation Request 25 Mask */ +#define CAN_TXBCR_CR25(value) (CAN_TXBCR_CR25_Msk & (_UINT32_(value) << CAN_TXBCR_CR25_Pos)) /* Assigment of value for CR25 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR26_Pos _UINT32_(26) /* (CAN_TXBCR) Cancellation Request 26 Position */ +#define CAN_TXBCR_CR26_Msk (_UINT32_(0x1) << CAN_TXBCR_CR26_Pos) /* (CAN_TXBCR) Cancellation Request 26 Mask */ +#define CAN_TXBCR_CR26(value) (CAN_TXBCR_CR26_Msk & (_UINT32_(value) << CAN_TXBCR_CR26_Pos)) /* Assigment of value for CR26 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR27_Pos _UINT32_(27) /* (CAN_TXBCR) Cancellation Request 27 Position */ +#define CAN_TXBCR_CR27_Msk (_UINT32_(0x1) << CAN_TXBCR_CR27_Pos) /* (CAN_TXBCR) Cancellation Request 27 Mask */ +#define CAN_TXBCR_CR27(value) (CAN_TXBCR_CR27_Msk & (_UINT32_(value) << CAN_TXBCR_CR27_Pos)) /* Assigment of value for CR27 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR28_Pos _UINT32_(28) /* (CAN_TXBCR) Cancellation Request 28 Position */ +#define CAN_TXBCR_CR28_Msk (_UINT32_(0x1) << CAN_TXBCR_CR28_Pos) /* (CAN_TXBCR) Cancellation Request 28 Mask */ +#define CAN_TXBCR_CR28(value) (CAN_TXBCR_CR28_Msk & (_UINT32_(value) << CAN_TXBCR_CR28_Pos)) /* Assigment of value for CR28 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR29_Pos _UINT32_(29) /* (CAN_TXBCR) Cancellation Request 29 Position */ +#define CAN_TXBCR_CR29_Msk (_UINT32_(0x1) << CAN_TXBCR_CR29_Pos) /* (CAN_TXBCR) Cancellation Request 29 Mask */ +#define CAN_TXBCR_CR29(value) (CAN_TXBCR_CR29_Msk & (_UINT32_(value) << CAN_TXBCR_CR29_Pos)) /* Assigment of value for CR29 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR30_Pos _UINT32_(30) /* (CAN_TXBCR) Cancellation Request 30 Position */ +#define CAN_TXBCR_CR30_Msk (_UINT32_(0x1) << CAN_TXBCR_CR30_Pos) /* (CAN_TXBCR) Cancellation Request 30 Mask */ +#define CAN_TXBCR_CR30(value) (CAN_TXBCR_CR30_Msk & (_UINT32_(value) << CAN_TXBCR_CR30_Pos)) /* Assigment of value for CR30 in the CAN_TXBCR register */ +#define CAN_TXBCR_CR31_Pos _UINT32_(31) /* (CAN_TXBCR) Cancellation Request 31 Position */ +#define CAN_TXBCR_CR31_Msk (_UINT32_(0x1) << CAN_TXBCR_CR31_Pos) /* (CAN_TXBCR) Cancellation Request 31 Mask */ +#define CAN_TXBCR_CR31(value) (CAN_TXBCR_CR31_Msk & (_UINT32_(value) << CAN_TXBCR_CR31_Pos)) /* Assigment of value for CR31 in the CAN_TXBCR register */ +#define CAN_TXBCR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCR) Register Mask */ + +#define CAN_TXBCR_CR_Pos _UINT32_(0) /* (CAN_TXBCR Position) Cancellation Request 3x */ +#define CAN_TXBCR_CR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCR_CR_Pos) /* (CAN_TXBCR Mask) CR */ +#define CAN_TXBCR_CR(value) (CAN_TXBCR_CR_Msk & (_UINT32_(value) << CAN_TXBCR_CR_Pos)) + +/* -------- CAN_TXBTO : (CAN Offset: 0xD8) ( R/ 32) Tx Buffer Transmission Occurred -------- */ +#define CAN_TXBTO_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Reset Value */ + +#define CAN_TXBTO_TO0_Pos _UINT32_(0) /* (CAN_TXBTO) Transmission Occurred 0 Position */ +#define CAN_TXBTO_TO0_Msk (_UINT32_(0x1) << CAN_TXBTO_TO0_Pos) /* (CAN_TXBTO) Transmission Occurred 0 Mask */ +#define CAN_TXBTO_TO0(value) (CAN_TXBTO_TO0_Msk & (_UINT32_(value) << CAN_TXBTO_TO0_Pos)) /* Assigment of value for TO0 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO1_Pos _UINT32_(1) /* (CAN_TXBTO) Transmission Occurred 1 Position */ +#define CAN_TXBTO_TO1_Msk (_UINT32_(0x1) << CAN_TXBTO_TO1_Pos) /* (CAN_TXBTO) Transmission Occurred 1 Mask */ +#define CAN_TXBTO_TO1(value) (CAN_TXBTO_TO1_Msk & (_UINT32_(value) << CAN_TXBTO_TO1_Pos)) /* Assigment of value for TO1 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO2_Pos _UINT32_(2) /* (CAN_TXBTO) Transmission Occurred 2 Position */ +#define CAN_TXBTO_TO2_Msk (_UINT32_(0x1) << CAN_TXBTO_TO2_Pos) /* (CAN_TXBTO) Transmission Occurred 2 Mask */ +#define CAN_TXBTO_TO2(value) (CAN_TXBTO_TO2_Msk & (_UINT32_(value) << CAN_TXBTO_TO2_Pos)) /* Assigment of value for TO2 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO3_Pos _UINT32_(3) /* (CAN_TXBTO) Transmission Occurred 3 Position */ +#define CAN_TXBTO_TO3_Msk (_UINT32_(0x1) << CAN_TXBTO_TO3_Pos) /* (CAN_TXBTO) Transmission Occurred 3 Mask */ +#define CAN_TXBTO_TO3(value) (CAN_TXBTO_TO3_Msk & (_UINT32_(value) << CAN_TXBTO_TO3_Pos)) /* Assigment of value for TO3 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO4_Pos _UINT32_(4) /* (CAN_TXBTO) Transmission Occurred 4 Position */ +#define CAN_TXBTO_TO4_Msk (_UINT32_(0x1) << CAN_TXBTO_TO4_Pos) /* (CAN_TXBTO) Transmission Occurred 4 Mask */ +#define CAN_TXBTO_TO4(value) (CAN_TXBTO_TO4_Msk & (_UINT32_(value) << CAN_TXBTO_TO4_Pos)) /* Assigment of value for TO4 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO5_Pos _UINT32_(5) /* (CAN_TXBTO) Transmission Occurred 5 Position */ +#define CAN_TXBTO_TO5_Msk (_UINT32_(0x1) << CAN_TXBTO_TO5_Pos) /* (CAN_TXBTO) Transmission Occurred 5 Mask */ +#define CAN_TXBTO_TO5(value) (CAN_TXBTO_TO5_Msk & (_UINT32_(value) << CAN_TXBTO_TO5_Pos)) /* Assigment of value for TO5 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO6_Pos _UINT32_(6) /* (CAN_TXBTO) Transmission Occurred 6 Position */ +#define CAN_TXBTO_TO6_Msk (_UINT32_(0x1) << CAN_TXBTO_TO6_Pos) /* (CAN_TXBTO) Transmission Occurred 6 Mask */ +#define CAN_TXBTO_TO6(value) (CAN_TXBTO_TO6_Msk & (_UINT32_(value) << CAN_TXBTO_TO6_Pos)) /* Assigment of value for TO6 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO7_Pos _UINT32_(7) /* (CAN_TXBTO) Transmission Occurred 7 Position */ +#define CAN_TXBTO_TO7_Msk (_UINT32_(0x1) << CAN_TXBTO_TO7_Pos) /* (CAN_TXBTO) Transmission Occurred 7 Mask */ +#define CAN_TXBTO_TO7(value) (CAN_TXBTO_TO7_Msk & (_UINT32_(value) << CAN_TXBTO_TO7_Pos)) /* Assigment of value for TO7 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO8_Pos _UINT32_(8) /* (CAN_TXBTO) Transmission Occurred 8 Position */ +#define CAN_TXBTO_TO8_Msk (_UINT32_(0x1) << CAN_TXBTO_TO8_Pos) /* (CAN_TXBTO) Transmission Occurred 8 Mask */ +#define CAN_TXBTO_TO8(value) (CAN_TXBTO_TO8_Msk & (_UINT32_(value) << CAN_TXBTO_TO8_Pos)) /* Assigment of value for TO8 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO9_Pos _UINT32_(9) /* (CAN_TXBTO) Transmission Occurred 9 Position */ +#define CAN_TXBTO_TO9_Msk (_UINT32_(0x1) << CAN_TXBTO_TO9_Pos) /* (CAN_TXBTO) Transmission Occurred 9 Mask */ +#define CAN_TXBTO_TO9(value) (CAN_TXBTO_TO9_Msk & (_UINT32_(value) << CAN_TXBTO_TO9_Pos)) /* Assigment of value for TO9 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO10_Pos _UINT32_(10) /* (CAN_TXBTO) Transmission Occurred 10 Position */ +#define CAN_TXBTO_TO10_Msk (_UINT32_(0x1) << CAN_TXBTO_TO10_Pos) /* (CAN_TXBTO) Transmission Occurred 10 Mask */ +#define CAN_TXBTO_TO10(value) (CAN_TXBTO_TO10_Msk & (_UINT32_(value) << CAN_TXBTO_TO10_Pos)) /* Assigment of value for TO10 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO11_Pos _UINT32_(11) /* (CAN_TXBTO) Transmission Occurred 11 Position */ +#define CAN_TXBTO_TO11_Msk (_UINT32_(0x1) << CAN_TXBTO_TO11_Pos) /* (CAN_TXBTO) Transmission Occurred 11 Mask */ +#define CAN_TXBTO_TO11(value) (CAN_TXBTO_TO11_Msk & (_UINT32_(value) << CAN_TXBTO_TO11_Pos)) /* Assigment of value for TO11 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO12_Pos _UINT32_(12) /* (CAN_TXBTO) Transmission Occurred 12 Position */ +#define CAN_TXBTO_TO12_Msk (_UINT32_(0x1) << CAN_TXBTO_TO12_Pos) /* (CAN_TXBTO) Transmission Occurred 12 Mask */ +#define CAN_TXBTO_TO12(value) (CAN_TXBTO_TO12_Msk & (_UINT32_(value) << CAN_TXBTO_TO12_Pos)) /* Assigment of value for TO12 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO13_Pos _UINT32_(13) /* (CAN_TXBTO) Transmission Occurred 13 Position */ +#define CAN_TXBTO_TO13_Msk (_UINT32_(0x1) << CAN_TXBTO_TO13_Pos) /* (CAN_TXBTO) Transmission Occurred 13 Mask */ +#define CAN_TXBTO_TO13(value) (CAN_TXBTO_TO13_Msk & (_UINT32_(value) << CAN_TXBTO_TO13_Pos)) /* Assigment of value for TO13 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO14_Pos _UINT32_(14) /* (CAN_TXBTO) Transmission Occurred 14 Position */ +#define CAN_TXBTO_TO14_Msk (_UINT32_(0x1) << CAN_TXBTO_TO14_Pos) /* (CAN_TXBTO) Transmission Occurred 14 Mask */ +#define CAN_TXBTO_TO14(value) (CAN_TXBTO_TO14_Msk & (_UINT32_(value) << CAN_TXBTO_TO14_Pos)) /* Assigment of value for TO14 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO15_Pos _UINT32_(15) /* (CAN_TXBTO) Transmission Occurred 15 Position */ +#define CAN_TXBTO_TO15_Msk (_UINT32_(0x1) << CAN_TXBTO_TO15_Pos) /* (CAN_TXBTO) Transmission Occurred 15 Mask */ +#define CAN_TXBTO_TO15(value) (CAN_TXBTO_TO15_Msk & (_UINT32_(value) << CAN_TXBTO_TO15_Pos)) /* Assigment of value for TO15 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO16_Pos _UINT32_(16) /* (CAN_TXBTO) Transmission Occurred 16 Position */ +#define CAN_TXBTO_TO16_Msk (_UINT32_(0x1) << CAN_TXBTO_TO16_Pos) /* (CAN_TXBTO) Transmission Occurred 16 Mask */ +#define CAN_TXBTO_TO16(value) (CAN_TXBTO_TO16_Msk & (_UINT32_(value) << CAN_TXBTO_TO16_Pos)) /* Assigment of value for TO16 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO17_Pos _UINT32_(17) /* (CAN_TXBTO) Transmission Occurred 17 Position */ +#define CAN_TXBTO_TO17_Msk (_UINT32_(0x1) << CAN_TXBTO_TO17_Pos) /* (CAN_TXBTO) Transmission Occurred 17 Mask */ +#define CAN_TXBTO_TO17(value) (CAN_TXBTO_TO17_Msk & (_UINT32_(value) << CAN_TXBTO_TO17_Pos)) /* Assigment of value for TO17 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO18_Pos _UINT32_(18) /* (CAN_TXBTO) Transmission Occurred 18 Position */ +#define CAN_TXBTO_TO18_Msk (_UINT32_(0x1) << CAN_TXBTO_TO18_Pos) /* (CAN_TXBTO) Transmission Occurred 18 Mask */ +#define CAN_TXBTO_TO18(value) (CAN_TXBTO_TO18_Msk & (_UINT32_(value) << CAN_TXBTO_TO18_Pos)) /* Assigment of value for TO18 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO19_Pos _UINT32_(19) /* (CAN_TXBTO) Transmission Occurred 19 Position */ +#define CAN_TXBTO_TO19_Msk (_UINT32_(0x1) << CAN_TXBTO_TO19_Pos) /* (CAN_TXBTO) Transmission Occurred 19 Mask */ +#define CAN_TXBTO_TO19(value) (CAN_TXBTO_TO19_Msk & (_UINT32_(value) << CAN_TXBTO_TO19_Pos)) /* Assigment of value for TO19 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO20_Pos _UINT32_(20) /* (CAN_TXBTO) Transmission Occurred 20 Position */ +#define CAN_TXBTO_TO20_Msk (_UINT32_(0x1) << CAN_TXBTO_TO20_Pos) /* (CAN_TXBTO) Transmission Occurred 20 Mask */ +#define CAN_TXBTO_TO20(value) (CAN_TXBTO_TO20_Msk & (_UINT32_(value) << CAN_TXBTO_TO20_Pos)) /* Assigment of value for TO20 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO21_Pos _UINT32_(21) /* (CAN_TXBTO) Transmission Occurred 21 Position */ +#define CAN_TXBTO_TO21_Msk (_UINT32_(0x1) << CAN_TXBTO_TO21_Pos) /* (CAN_TXBTO) Transmission Occurred 21 Mask */ +#define CAN_TXBTO_TO21(value) (CAN_TXBTO_TO21_Msk & (_UINT32_(value) << CAN_TXBTO_TO21_Pos)) /* Assigment of value for TO21 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO22_Pos _UINT32_(22) /* (CAN_TXBTO) Transmission Occurred 22 Position */ +#define CAN_TXBTO_TO22_Msk (_UINT32_(0x1) << CAN_TXBTO_TO22_Pos) /* (CAN_TXBTO) Transmission Occurred 22 Mask */ +#define CAN_TXBTO_TO22(value) (CAN_TXBTO_TO22_Msk & (_UINT32_(value) << CAN_TXBTO_TO22_Pos)) /* Assigment of value for TO22 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO23_Pos _UINT32_(23) /* (CAN_TXBTO) Transmission Occurred 23 Position */ +#define CAN_TXBTO_TO23_Msk (_UINT32_(0x1) << CAN_TXBTO_TO23_Pos) /* (CAN_TXBTO) Transmission Occurred 23 Mask */ +#define CAN_TXBTO_TO23(value) (CAN_TXBTO_TO23_Msk & (_UINT32_(value) << CAN_TXBTO_TO23_Pos)) /* Assigment of value for TO23 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO24_Pos _UINT32_(24) /* (CAN_TXBTO) Transmission Occurred 24 Position */ +#define CAN_TXBTO_TO24_Msk (_UINT32_(0x1) << CAN_TXBTO_TO24_Pos) /* (CAN_TXBTO) Transmission Occurred 24 Mask */ +#define CAN_TXBTO_TO24(value) (CAN_TXBTO_TO24_Msk & (_UINT32_(value) << CAN_TXBTO_TO24_Pos)) /* Assigment of value for TO24 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO25_Pos _UINT32_(25) /* (CAN_TXBTO) Transmission Occurred 25 Position */ +#define CAN_TXBTO_TO25_Msk (_UINT32_(0x1) << CAN_TXBTO_TO25_Pos) /* (CAN_TXBTO) Transmission Occurred 25 Mask */ +#define CAN_TXBTO_TO25(value) (CAN_TXBTO_TO25_Msk & (_UINT32_(value) << CAN_TXBTO_TO25_Pos)) /* Assigment of value for TO25 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO26_Pos _UINT32_(26) /* (CAN_TXBTO) Transmission Occurred 26 Position */ +#define CAN_TXBTO_TO26_Msk (_UINT32_(0x1) << CAN_TXBTO_TO26_Pos) /* (CAN_TXBTO) Transmission Occurred 26 Mask */ +#define CAN_TXBTO_TO26(value) (CAN_TXBTO_TO26_Msk & (_UINT32_(value) << CAN_TXBTO_TO26_Pos)) /* Assigment of value for TO26 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO27_Pos _UINT32_(27) /* (CAN_TXBTO) Transmission Occurred 27 Position */ +#define CAN_TXBTO_TO27_Msk (_UINT32_(0x1) << CAN_TXBTO_TO27_Pos) /* (CAN_TXBTO) Transmission Occurred 27 Mask */ +#define CAN_TXBTO_TO27(value) (CAN_TXBTO_TO27_Msk & (_UINT32_(value) << CAN_TXBTO_TO27_Pos)) /* Assigment of value for TO27 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO28_Pos _UINT32_(28) /* (CAN_TXBTO) Transmission Occurred 28 Position */ +#define CAN_TXBTO_TO28_Msk (_UINT32_(0x1) << CAN_TXBTO_TO28_Pos) /* (CAN_TXBTO) Transmission Occurred 28 Mask */ +#define CAN_TXBTO_TO28(value) (CAN_TXBTO_TO28_Msk & (_UINT32_(value) << CAN_TXBTO_TO28_Pos)) /* Assigment of value for TO28 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO29_Pos _UINT32_(29) /* (CAN_TXBTO) Transmission Occurred 29 Position */ +#define CAN_TXBTO_TO29_Msk (_UINT32_(0x1) << CAN_TXBTO_TO29_Pos) /* (CAN_TXBTO) Transmission Occurred 29 Mask */ +#define CAN_TXBTO_TO29(value) (CAN_TXBTO_TO29_Msk & (_UINT32_(value) << CAN_TXBTO_TO29_Pos)) /* Assigment of value for TO29 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO30_Pos _UINT32_(30) /* (CAN_TXBTO) Transmission Occurred 30 Position */ +#define CAN_TXBTO_TO30_Msk (_UINT32_(0x1) << CAN_TXBTO_TO30_Pos) /* (CAN_TXBTO) Transmission Occurred 30 Mask */ +#define CAN_TXBTO_TO30(value) (CAN_TXBTO_TO30_Msk & (_UINT32_(value) << CAN_TXBTO_TO30_Pos)) /* Assigment of value for TO30 in the CAN_TXBTO register */ +#define CAN_TXBTO_TO31_Pos _UINT32_(31) /* (CAN_TXBTO) Transmission Occurred 31 Position */ +#define CAN_TXBTO_TO31_Msk (_UINT32_(0x1) << CAN_TXBTO_TO31_Pos) /* (CAN_TXBTO) Transmission Occurred 31 Mask */ +#define CAN_TXBTO_TO31(value) (CAN_TXBTO_TO31_Msk & (_UINT32_(value) << CAN_TXBTO_TO31_Pos)) /* Assigment of value for TO31 in the CAN_TXBTO register */ +#define CAN_TXBTO_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTO) Register Mask */ + +#define CAN_TXBTO_TO_Pos _UINT32_(0) /* (CAN_TXBTO Position) Transmission Occurred 3x */ +#define CAN_TXBTO_TO_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTO_TO_Pos) /* (CAN_TXBTO Mask) TO */ +#define CAN_TXBTO_TO(value) (CAN_TXBTO_TO_Msk & (_UINT32_(value) << CAN_TXBTO_TO_Pos)) + +/* -------- CAN_TXBCF : (CAN Offset: 0xDC) ( R/ 32) Tx Buffer Cancellation Finished -------- */ +#define CAN_TXBCF_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Reset Value */ + +#define CAN_TXBCF_CF0_Pos _UINT32_(0) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Position */ +#define CAN_TXBCF_CF0_Msk (_UINT32_(0x1) << CAN_TXBCF_CF0_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Mask */ +#define CAN_TXBCF_CF0(value) (CAN_TXBCF_CF0_Msk & (_UINT32_(value) << CAN_TXBCF_CF0_Pos)) /* Assigment of value for CF0 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF1_Pos _UINT32_(1) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Position */ +#define CAN_TXBCF_CF1_Msk (_UINT32_(0x1) << CAN_TXBCF_CF1_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Mask */ +#define CAN_TXBCF_CF1(value) (CAN_TXBCF_CF1_Msk & (_UINT32_(value) << CAN_TXBCF_CF1_Pos)) /* Assigment of value for CF1 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF2_Pos _UINT32_(2) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Position */ +#define CAN_TXBCF_CF2_Msk (_UINT32_(0x1) << CAN_TXBCF_CF2_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Mask */ +#define CAN_TXBCF_CF2(value) (CAN_TXBCF_CF2_Msk & (_UINT32_(value) << CAN_TXBCF_CF2_Pos)) /* Assigment of value for CF2 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF3_Pos _UINT32_(3) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Position */ +#define CAN_TXBCF_CF3_Msk (_UINT32_(0x1) << CAN_TXBCF_CF3_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Mask */ +#define CAN_TXBCF_CF3(value) (CAN_TXBCF_CF3_Msk & (_UINT32_(value) << CAN_TXBCF_CF3_Pos)) /* Assigment of value for CF3 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF4_Pos _UINT32_(4) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Position */ +#define CAN_TXBCF_CF4_Msk (_UINT32_(0x1) << CAN_TXBCF_CF4_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Mask */ +#define CAN_TXBCF_CF4(value) (CAN_TXBCF_CF4_Msk & (_UINT32_(value) << CAN_TXBCF_CF4_Pos)) /* Assigment of value for CF4 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF5_Pos _UINT32_(5) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Position */ +#define CAN_TXBCF_CF5_Msk (_UINT32_(0x1) << CAN_TXBCF_CF5_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Mask */ +#define CAN_TXBCF_CF5(value) (CAN_TXBCF_CF5_Msk & (_UINT32_(value) << CAN_TXBCF_CF5_Pos)) /* Assigment of value for CF5 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF6_Pos _UINT32_(6) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Position */ +#define CAN_TXBCF_CF6_Msk (_UINT32_(0x1) << CAN_TXBCF_CF6_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Mask */ +#define CAN_TXBCF_CF6(value) (CAN_TXBCF_CF6_Msk & (_UINT32_(value) << CAN_TXBCF_CF6_Pos)) /* Assigment of value for CF6 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF7_Pos _UINT32_(7) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Position */ +#define CAN_TXBCF_CF7_Msk (_UINT32_(0x1) << CAN_TXBCF_CF7_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Mask */ +#define CAN_TXBCF_CF7(value) (CAN_TXBCF_CF7_Msk & (_UINT32_(value) << CAN_TXBCF_CF7_Pos)) /* Assigment of value for CF7 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF8_Pos _UINT32_(8) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Position */ +#define CAN_TXBCF_CF8_Msk (_UINT32_(0x1) << CAN_TXBCF_CF8_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Mask */ +#define CAN_TXBCF_CF8(value) (CAN_TXBCF_CF8_Msk & (_UINT32_(value) << CAN_TXBCF_CF8_Pos)) /* Assigment of value for CF8 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF9_Pos _UINT32_(9) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Position */ +#define CAN_TXBCF_CF9_Msk (_UINT32_(0x1) << CAN_TXBCF_CF9_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Mask */ +#define CAN_TXBCF_CF9(value) (CAN_TXBCF_CF9_Msk & (_UINT32_(value) << CAN_TXBCF_CF9_Pos)) /* Assigment of value for CF9 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF10_Pos _UINT32_(10) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Position */ +#define CAN_TXBCF_CF10_Msk (_UINT32_(0x1) << CAN_TXBCF_CF10_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Mask */ +#define CAN_TXBCF_CF10(value) (CAN_TXBCF_CF10_Msk & (_UINT32_(value) << CAN_TXBCF_CF10_Pos)) /* Assigment of value for CF10 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF11_Pos _UINT32_(11) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Position */ +#define CAN_TXBCF_CF11_Msk (_UINT32_(0x1) << CAN_TXBCF_CF11_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Mask */ +#define CAN_TXBCF_CF11(value) (CAN_TXBCF_CF11_Msk & (_UINT32_(value) << CAN_TXBCF_CF11_Pos)) /* Assigment of value for CF11 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF12_Pos _UINT32_(12) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Position */ +#define CAN_TXBCF_CF12_Msk (_UINT32_(0x1) << CAN_TXBCF_CF12_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Mask */ +#define CAN_TXBCF_CF12(value) (CAN_TXBCF_CF12_Msk & (_UINT32_(value) << CAN_TXBCF_CF12_Pos)) /* Assigment of value for CF12 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF13_Pos _UINT32_(13) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Position */ +#define CAN_TXBCF_CF13_Msk (_UINT32_(0x1) << CAN_TXBCF_CF13_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Mask */ +#define CAN_TXBCF_CF13(value) (CAN_TXBCF_CF13_Msk & (_UINT32_(value) << CAN_TXBCF_CF13_Pos)) /* Assigment of value for CF13 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF14_Pos _UINT32_(14) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Position */ +#define CAN_TXBCF_CF14_Msk (_UINT32_(0x1) << CAN_TXBCF_CF14_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Mask */ +#define CAN_TXBCF_CF14(value) (CAN_TXBCF_CF14_Msk & (_UINT32_(value) << CAN_TXBCF_CF14_Pos)) /* Assigment of value for CF14 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF15_Pos _UINT32_(15) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Position */ +#define CAN_TXBCF_CF15_Msk (_UINT32_(0x1) << CAN_TXBCF_CF15_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Mask */ +#define CAN_TXBCF_CF15(value) (CAN_TXBCF_CF15_Msk & (_UINT32_(value) << CAN_TXBCF_CF15_Pos)) /* Assigment of value for CF15 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF16_Pos _UINT32_(16) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Position */ +#define CAN_TXBCF_CF16_Msk (_UINT32_(0x1) << CAN_TXBCF_CF16_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Mask */ +#define CAN_TXBCF_CF16(value) (CAN_TXBCF_CF16_Msk & (_UINT32_(value) << CAN_TXBCF_CF16_Pos)) /* Assigment of value for CF16 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF17_Pos _UINT32_(17) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Position */ +#define CAN_TXBCF_CF17_Msk (_UINT32_(0x1) << CAN_TXBCF_CF17_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Mask */ +#define CAN_TXBCF_CF17(value) (CAN_TXBCF_CF17_Msk & (_UINT32_(value) << CAN_TXBCF_CF17_Pos)) /* Assigment of value for CF17 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF18_Pos _UINT32_(18) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Position */ +#define CAN_TXBCF_CF18_Msk (_UINT32_(0x1) << CAN_TXBCF_CF18_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Mask */ +#define CAN_TXBCF_CF18(value) (CAN_TXBCF_CF18_Msk & (_UINT32_(value) << CAN_TXBCF_CF18_Pos)) /* Assigment of value for CF18 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF19_Pos _UINT32_(19) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Position */ +#define CAN_TXBCF_CF19_Msk (_UINT32_(0x1) << CAN_TXBCF_CF19_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Mask */ +#define CAN_TXBCF_CF19(value) (CAN_TXBCF_CF19_Msk & (_UINT32_(value) << CAN_TXBCF_CF19_Pos)) /* Assigment of value for CF19 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF20_Pos _UINT32_(20) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Position */ +#define CAN_TXBCF_CF20_Msk (_UINT32_(0x1) << CAN_TXBCF_CF20_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Mask */ +#define CAN_TXBCF_CF20(value) (CAN_TXBCF_CF20_Msk & (_UINT32_(value) << CAN_TXBCF_CF20_Pos)) /* Assigment of value for CF20 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF21_Pos _UINT32_(21) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Position */ +#define CAN_TXBCF_CF21_Msk (_UINT32_(0x1) << CAN_TXBCF_CF21_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Mask */ +#define CAN_TXBCF_CF21(value) (CAN_TXBCF_CF21_Msk & (_UINT32_(value) << CAN_TXBCF_CF21_Pos)) /* Assigment of value for CF21 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF22_Pos _UINT32_(22) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Position */ +#define CAN_TXBCF_CF22_Msk (_UINT32_(0x1) << CAN_TXBCF_CF22_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Mask */ +#define CAN_TXBCF_CF22(value) (CAN_TXBCF_CF22_Msk & (_UINT32_(value) << CAN_TXBCF_CF22_Pos)) /* Assigment of value for CF22 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF23_Pos _UINT32_(23) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Position */ +#define CAN_TXBCF_CF23_Msk (_UINT32_(0x1) << CAN_TXBCF_CF23_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Mask */ +#define CAN_TXBCF_CF23(value) (CAN_TXBCF_CF23_Msk & (_UINT32_(value) << CAN_TXBCF_CF23_Pos)) /* Assigment of value for CF23 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF24_Pos _UINT32_(24) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Position */ +#define CAN_TXBCF_CF24_Msk (_UINT32_(0x1) << CAN_TXBCF_CF24_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Mask */ +#define CAN_TXBCF_CF24(value) (CAN_TXBCF_CF24_Msk & (_UINT32_(value) << CAN_TXBCF_CF24_Pos)) /* Assigment of value for CF24 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF25_Pos _UINT32_(25) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Position */ +#define CAN_TXBCF_CF25_Msk (_UINT32_(0x1) << CAN_TXBCF_CF25_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Mask */ +#define CAN_TXBCF_CF25(value) (CAN_TXBCF_CF25_Msk & (_UINT32_(value) << CAN_TXBCF_CF25_Pos)) /* Assigment of value for CF25 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF26_Pos _UINT32_(26) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Position */ +#define CAN_TXBCF_CF26_Msk (_UINT32_(0x1) << CAN_TXBCF_CF26_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Mask */ +#define CAN_TXBCF_CF26(value) (CAN_TXBCF_CF26_Msk & (_UINT32_(value) << CAN_TXBCF_CF26_Pos)) /* Assigment of value for CF26 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF27_Pos _UINT32_(27) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Position */ +#define CAN_TXBCF_CF27_Msk (_UINT32_(0x1) << CAN_TXBCF_CF27_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Mask */ +#define CAN_TXBCF_CF27(value) (CAN_TXBCF_CF27_Msk & (_UINT32_(value) << CAN_TXBCF_CF27_Pos)) /* Assigment of value for CF27 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF28_Pos _UINT32_(28) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Position */ +#define CAN_TXBCF_CF28_Msk (_UINT32_(0x1) << CAN_TXBCF_CF28_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Mask */ +#define CAN_TXBCF_CF28(value) (CAN_TXBCF_CF28_Msk & (_UINT32_(value) << CAN_TXBCF_CF28_Pos)) /* Assigment of value for CF28 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF29_Pos _UINT32_(29) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Position */ +#define CAN_TXBCF_CF29_Msk (_UINT32_(0x1) << CAN_TXBCF_CF29_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Mask */ +#define CAN_TXBCF_CF29(value) (CAN_TXBCF_CF29_Msk & (_UINT32_(value) << CAN_TXBCF_CF29_Pos)) /* Assigment of value for CF29 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF30_Pos _UINT32_(30) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Position */ +#define CAN_TXBCF_CF30_Msk (_UINT32_(0x1) << CAN_TXBCF_CF30_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Mask */ +#define CAN_TXBCF_CF30(value) (CAN_TXBCF_CF30_Msk & (_UINT32_(value) << CAN_TXBCF_CF30_Pos)) /* Assigment of value for CF30 in the CAN_TXBCF register */ +#define CAN_TXBCF_CF31_Pos _UINT32_(31) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Position */ +#define CAN_TXBCF_CF31_Msk (_UINT32_(0x1) << CAN_TXBCF_CF31_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Mask */ +#define CAN_TXBCF_CF31(value) (CAN_TXBCF_CF31_Msk & (_UINT32_(value) << CAN_TXBCF_CF31_Pos)) /* Assigment of value for CF31 in the CAN_TXBCF register */ +#define CAN_TXBCF_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCF) Register Mask */ + +#define CAN_TXBCF_CF_Pos _UINT32_(0) /* (CAN_TXBCF Position) Tx Buffer Cancellation Finished 3x */ +#define CAN_TXBCF_CF_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCF_CF_Pos) /* (CAN_TXBCF Mask) CF */ +#define CAN_TXBCF_CF(value) (CAN_TXBCF_CF_Msk & (_UINT32_(value) << CAN_TXBCF_CF_Pos)) + +/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ +#define CAN_TXBTIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Reset Value */ + +#define CAN_TXBTIE_TIE0_Pos _UINT32_(0) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Position */ +#define CAN_TXBTIE_TIE0_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE0_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Mask */ +#define CAN_TXBTIE_TIE0(value) (CAN_TXBTIE_TIE0_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE0_Pos)) /* Assigment of value for TIE0 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE1_Pos _UINT32_(1) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Position */ +#define CAN_TXBTIE_TIE1_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE1_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Mask */ +#define CAN_TXBTIE_TIE1(value) (CAN_TXBTIE_TIE1_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE1_Pos)) /* Assigment of value for TIE1 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE2_Pos _UINT32_(2) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Position */ +#define CAN_TXBTIE_TIE2_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE2_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Mask */ +#define CAN_TXBTIE_TIE2(value) (CAN_TXBTIE_TIE2_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE2_Pos)) /* Assigment of value for TIE2 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE3_Pos _UINT32_(3) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Position */ +#define CAN_TXBTIE_TIE3_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE3_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Mask */ +#define CAN_TXBTIE_TIE3(value) (CAN_TXBTIE_TIE3_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE3_Pos)) /* Assigment of value for TIE3 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE4_Pos _UINT32_(4) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Position */ +#define CAN_TXBTIE_TIE4_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE4_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Mask */ +#define CAN_TXBTIE_TIE4(value) (CAN_TXBTIE_TIE4_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE4_Pos)) /* Assigment of value for TIE4 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE5_Pos _UINT32_(5) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Position */ +#define CAN_TXBTIE_TIE5_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE5_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Mask */ +#define CAN_TXBTIE_TIE5(value) (CAN_TXBTIE_TIE5_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE5_Pos)) /* Assigment of value for TIE5 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE6_Pos _UINT32_(6) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Position */ +#define CAN_TXBTIE_TIE6_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE6_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Mask */ +#define CAN_TXBTIE_TIE6(value) (CAN_TXBTIE_TIE6_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE6_Pos)) /* Assigment of value for TIE6 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE7_Pos _UINT32_(7) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Position */ +#define CAN_TXBTIE_TIE7_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE7_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Mask */ +#define CAN_TXBTIE_TIE7(value) (CAN_TXBTIE_TIE7_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE7_Pos)) /* Assigment of value for TIE7 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE8_Pos _UINT32_(8) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Position */ +#define CAN_TXBTIE_TIE8_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE8_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Mask */ +#define CAN_TXBTIE_TIE8(value) (CAN_TXBTIE_TIE8_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE8_Pos)) /* Assigment of value for TIE8 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE9_Pos _UINT32_(9) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Position */ +#define CAN_TXBTIE_TIE9_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE9_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Mask */ +#define CAN_TXBTIE_TIE9(value) (CAN_TXBTIE_TIE9_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE9_Pos)) /* Assigment of value for TIE9 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE10_Pos _UINT32_(10) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Position */ +#define CAN_TXBTIE_TIE10_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE10_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Mask */ +#define CAN_TXBTIE_TIE10(value) (CAN_TXBTIE_TIE10_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE10_Pos)) /* Assigment of value for TIE10 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE11_Pos _UINT32_(11) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Position */ +#define CAN_TXBTIE_TIE11_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE11_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Mask */ +#define CAN_TXBTIE_TIE11(value) (CAN_TXBTIE_TIE11_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE11_Pos)) /* Assigment of value for TIE11 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE12_Pos _UINT32_(12) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Position */ +#define CAN_TXBTIE_TIE12_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE12_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Mask */ +#define CAN_TXBTIE_TIE12(value) (CAN_TXBTIE_TIE12_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE12_Pos)) /* Assigment of value for TIE12 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE13_Pos _UINT32_(13) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Position */ +#define CAN_TXBTIE_TIE13_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE13_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Mask */ +#define CAN_TXBTIE_TIE13(value) (CAN_TXBTIE_TIE13_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE13_Pos)) /* Assigment of value for TIE13 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE14_Pos _UINT32_(14) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Position */ +#define CAN_TXBTIE_TIE14_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE14_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Mask */ +#define CAN_TXBTIE_TIE14(value) (CAN_TXBTIE_TIE14_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE14_Pos)) /* Assigment of value for TIE14 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE15_Pos _UINT32_(15) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Position */ +#define CAN_TXBTIE_TIE15_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE15_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Mask */ +#define CAN_TXBTIE_TIE15(value) (CAN_TXBTIE_TIE15_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE15_Pos)) /* Assigment of value for TIE15 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE16_Pos _UINT32_(16) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Position */ +#define CAN_TXBTIE_TIE16_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE16_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Mask */ +#define CAN_TXBTIE_TIE16(value) (CAN_TXBTIE_TIE16_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE16_Pos)) /* Assigment of value for TIE16 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE17_Pos _UINT32_(17) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Position */ +#define CAN_TXBTIE_TIE17_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE17_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Mask */ +#define CAN_TXBTIE_TIE17(value) (CAN_TXBTIE_TIE17_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE17_Pos)) /* Assigment of value for TIE17 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE18_Pos _UINT32_(18) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Position */ +#define CAN_TXBTIE_TIE18_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE18_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Mask */ +#define CAN_TXBTIE_TIE18(value) (CAN_TXBTIE_TIE18_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE18_Pos)) /* Assigment of value for TIE18 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE19_Pos _UINT32_(19) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Position */ +#define CAN_TXBTIE_TIE19_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE19_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Mask */ +#define CAN_TXBTIE_TIE19(value) (CAN_TXBTIE_TIE19_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE19_Pos)) /* Assigment of value for TIE19 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE20_Pos _UINT32_(20) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Position */ +#define CAN_TXBTIE_TIE20_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE20_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Mask */ +#define CAN_TXBTIE_TIE20(value) (CAN_TXBTIE_TIE20_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE20_Pos)) /* Assigment of value for TIE20 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE21_Pos _UINT32_(21) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Position */ +#define CAN_TXBTIE_TIE21_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE21_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Mask */ +#define CAN_TXBTIE_TIE21(value) (CAN_TXBTIE_TIE21_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE21_Pos)) /* Assigment of value for TIE21 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE22_Pos _UINT32_(22) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Position */ +#define CAN_TXBTIE_TIE22_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE22_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Mask */ +#define CAN_TXBTIE_TIE22(value) (CAN_TXBTIE_TIE22_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE22_Pos)) /* Assigment of value for TIE22 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE23_Pos _UINT32_(23) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Position */ +#define CAN_TXBTIE_TIE23_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE23_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Mask */ +#define CAN_TXBTIE_TIE23(value) (CAN_TXBTIE_TIE23_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE23_Pos)) /* Assigment of value for TIE23 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE24_Pos _UINT32_(24) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Position */ +#define CAN_TXBTIE_TIE24_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE24_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Mask */ +#define CAN_TXBTIE_TIE24(value) (CAN_TXBTIE_TIE24_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE24_Pos)) /* Assigment of value for TIE24 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE25_Pos _UINT32_(25) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Position */ +#define CAN_TXBTIE_TIE25_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE25_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Mask */ +#define CAN_TXBTIE_TIE25(value) (CAN_TXBTIE_TIE25_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE25_Pos)) /* Assigment of value for TIE25 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE26_Pos _UINT32_(26) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Position */ +#define CAN_TXBTIE_TIE26_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE26_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Mask */ +#define CAN_TXBTIE_TIE26(value) (CAN_TXBTIE_TIE26_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE26_Pos)) /* Assigment of value for TIE26 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE27_Pos _UINT32_(27) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Position */ +#define CAN_TXBTIE_TIE27_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE27_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Mask */ +#define CAN_TXBTIE_TIE27(value) (CAN_TXBTIE_TIE27_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE27_Pos)) /* Assigment of value for TIE27 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE28_Pos _UINT32_(28) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Position */ +#define CAN_TXBTIE_TIE28_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE28_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Mask */ +#define CAN_TXBTIE_TIE28(value) (CAN_TXBTIE_TIE28_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE28_Pos)) /* Assigment of value for TIE28 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE29_Pos _UINT32_(29) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Position */ +#define CAN_TXBTIE_TIE29_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE29_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Mask */ +#define CAN_TXBTIE_TIE29(value) (CAN_TXBTIE_TIE29_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE29_Pos)) /* Assigment of value for TIE29 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE30_Pos _UINT32_(30) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Position */ +#define CAN_TXBTIE_TIE30_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE30_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Mask */ +#define CAN_TXBTIE_TIE30(value) (CAN_TXBTIE_TIE30_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE30_Pos)) /* Assigment of value for TIE30 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_TIE31_Pos _UINT32_(31) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Position */ +#define CAN_TXBTIE_TIE31_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE31_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Mask */ +#define CAN_TXBTIE_TIE31(value) (CAN_TXBTIE_TIE31_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE31_Pos)) /* Assigment of value for TIE31 in the CAN_TXBTIE register */ +#define CAN_TXBTIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTIE) Register Mask */ + +#define CAN_TXBTIE_TIE_Pos _UINT32_(0) /* (CAN_TXBTIE Position) Transmission Interrupt Enable 3x */ +#define CAN_TXBTIE_TIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTIE_TIE_Pos) /* (CAN_TXBTIE Mask) TIE */ +#define CAN_TXBTIE_TIE(value) (CAN_TXBTIE_TIE_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE_Pos)) + +/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ +#define CAN_TXBCIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Reset Value */ + +#define CAN_TXBCIE_CFIE0_Pos _UINT32_(0) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Position */ +#define CAN_TXBCIE_CFIE0_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE0_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Mask */ +#define CAN_TXBCIE_CFIE0(value) (CAN_TXBCIE_CFIE0_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE0_Pos)) /* Assigment of value for CFIE0 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE1_Pos _UINT32_(1) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Position */ +#define CAN_TXBCIE_CFIE1_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE1_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Mask */ +#define CAN_TXBCIE_CFIE1(value) (CAN_TXBCIE_CFIE1_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE1_Pos)) /* Assigment of value for CFIE1 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE2_Pos _UINT32_(2) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Position */ +#define CAN_TXBCIE_CFIE2_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE2_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Mask */ +#define CAN_TXBCIE_CFIE2(value) (CAN_TXBCIE_CFIE2_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE2_Pos)) /* Assigment of value for CFIE2 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE3_Pos _UINT32_(3) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Position */ +#define CAN_TXBCIE_CFIE3_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE3_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Mask */ +#define CAN_TXBCIE_CFIE3(value) (CAN_TXBCIE_CFIE3_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE3_Pos)) /* Assigment of value for CFIE3 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE4_Pos _UINT32_(4) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Position */ +#define CAN_TXBCIE_CFIE4_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE4_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Mask */ +#define CAN_TXBCIE_CFIE4(value) (CAN_TXBCIE_CFIE4_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE4_Pos)) /* Assigment of value for CFIE4 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE5_Pos _UINT32_(5) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Position */ +#define CAN_TXBCIE_CFIE5_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE5_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Mask */ +#define CAN_TXBCIE_CFIE5(value) (CAN_TXBCIE_CFIE5_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE5_Pos)) /* Assigment of value for CFIE5 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE6_Pos _UINT32_(6) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Position */ +#define CAN_TXBCIE_CFIE6_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE6_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Mask */ +#define CAN_TXBCIE_CFIE6(value) (CAN_TXBCIE_CFIE6_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE6_Pos)) /* Assigment of value for CFIE6 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE7_Pos _UINT32_(7) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Position */ +#define CAN_TXBCIE_CFIE7_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE7_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Mask */ +#define CAN_TXBCIE_CFIE7(value) (CAN_TXBCIE_CFIE7_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE7_Pos)) /* Assigment of value for CFIE7 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE8_Pos _UINT32_(8) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Position */ +#define CAN_TXBCIE_CFIE8_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE8_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Mask */ +#define CAN_TXBCIE_CFIE8(value) (CAN_TXBCIE_CFIE8_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE8_Pos)) /* Assigment of value for CFIE8 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE9_Pos _UINT32_(9) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Position */ +#define CAN_TXBCIE_CFIE9_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE9_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Mask */ +#define CAN_TXBCIE_CFIE9(value) (CAN_TXBCIE_CFIE9_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE9_Pos)) /* Assigment of value for CFIE9 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE10_Pos _UINT32_(10) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Position */ +#define CAN_TXBCIE_CFIE10_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE10_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Mask */ +#define CAN_TXBCIE_CFIE10(value) (CAN_TXBCIE_CFIE10_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE10_Pos)) /* Assigment of value for CFIE10 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE11_Pos _UINT32_(11) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Position */ +#define CAN_TXBCIE_CFIE11_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE11_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Mask */ +#define CAN_TXBCIE_CFIE11(value) (CAN_TXBCIE_CFIE11_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE11_Pos)) /* Assigment of value for CFIE11 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE12_Pos _UINT32_(12) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Position */ +#define CAN_TXBCIE_CFIE12_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE12_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Mask */ +#define CAN_TXBCIE_CFIE12(value) (CAN_TXBCIE_CFIE12_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE12_Pos)) /* Assigment of value for CFIE12 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE13_Pos _UINT32_(13) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Position */ +#define CAN_TXBCIE_CFIE13_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE13_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Mask */ +#define CAN_TXBCIE_CFIE13(value) (CAN_TXBCIE_CFIE13_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE13_Pos)) /* Assigment of value for CFIE13 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE14_Pos _UINT32_(14) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Position */ +#define CAN_TXBCIE_CFIE14_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE14_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Mask */ +#define CAN_TXBCIE_CFIE14(value) (CAN_TXBCIE_CFIE14_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE14_Pos)) /* Assigment of value for CFIE14 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE15_Pos _UINT32_(15) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Position */ +#define CAN_TXBCIE_CFIE15_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE15_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Mask */ +#define CAN_TXBCIE_CFIE15(value) (CAN_TXBCIE_CFIE15_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE15_Pos)) /* Assigment of value for CFIE15 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE16_Pos _UINT32_(16) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Position */ +#define CAN_TXBCIE_CFIE16_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE16_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Mask */ +#define CAN_TXBCIE_CFIE16(value) (CAN_TXBCIE_CFIE16_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE16_Pos)) /* Assigment of value for CFIE16 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE17_Pos _UINT32_(17) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Position */ +#define CAN_TXBCIE_CFIE17_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE17_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Mask */ +#define CAN_TXBCIE_CFIE17(value) (CAN_TXBCIE_CFIE17_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE17_Pos)) /* Assigment of value for CFIE17 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE18_Pos _UINT32_(18) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Position */ +#define CAN_TXBCIE_CFIE18_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE18_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Mask */ +#define CAN_TXBCIE_CFIE18(value) (CAN_TXBCIE_CFIE18_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE18_Pos)) /* Assigment of value for CFIE18 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE19_Pos _UINT32_(19) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Position */ +#define CAN_TXBCIE_CFIE19_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE19_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Mask */ +#define CAN_TXBCIE_CFIE19(value) (CAN_TXBCIE_CFIE19_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE19_Pos)) /* Assigment of value for CFIE19 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE20_Pos _UINT32_(20) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Position */ +#define CAN_TXBCIE_CFIE20_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE20_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Mask */ +#define CAN_TXBCIE_CFIE20(value) (CAN_TXBCIE_CFIE20_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE20_Pos)) /* Assigment of value for CFIE20 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE21_Pos _UINT32_(21) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Position */ +#define CAN_TXBCIE_CFIE21_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE21_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Mask */ +#define CAN_TXBCIE_CFIE21(value) (CAN_TXBCIE_CFIE21_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE21_Pos)) /* Assigment of value for CFIE21 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE22_Pos _UINT32_(22) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Position */ +#define CAN_TXBCIE_CFIE22_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE22_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Mask */ +#define CAN_TXBCIE_CFIE22(value) (CAN_TXBCIE_CFIE22_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE22_Pos)) /* Assigment of value for CFIE22 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE23_Pos _UINT32_(23) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Position */ +#define CAN_TXBCIE_CFIE23_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE23_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Mask */ +#define CAN_TXBCIE_CFIE23(value) (CAN_TXBCIE_CFIE23_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE23_Pos)) /* Assigment of value for CFIE23 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE24_Pos _UINT32_(24) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Position */ +#define CAN_TXBCIE_CFIE24_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE24_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Mask */ +#define CAN_TXBCIE_CFIE24(value) (CAN_TXBCIE_CFIE24_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE24_Pos)) /* Assigment of value for CFIE24 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE25_Pos _UINT32_(25) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Position */ +#define CAN_TXBCIE_CFIE25_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE25_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Mask */ +#define CAN_TXBCIE_CFIE25(value) (CAN_TXBCIE_CFIE25_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE25_Pos)) /* Assigment of value for CFIE25 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE26_Pos _UINT32_(26) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Position */ +#define CAN_TXBCIE_CFIE26_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE26_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Mask */ +#define CAN_TXBCIE_CFIE26(value) (CAN_TXBCIE_CFIE26_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE26_Pos)) /* Assigment of value for CFIE26 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE27_Pos _UINT32_(27) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Position */ +#define CAN_TXBCIE_CFIE27_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE27_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Mask */ +#define CAN_TXBCIE_CFIE27(value) (CAN_TXBCIE_CFIE27_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE27_Pos)) /* Assigment of value for CFIE27 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE28_Pos _UINT32_(28) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Position */ +#define CAN_TXBCIE_CFIE28_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE28_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Mask */ +#define CAN_TXBCIE_CFIE28(value) (CAN_TXBCIE_CFIE28_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE28_Pos)) /* Assigment of value for CFIE28 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE29_Pos _UINT32_(29) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Position */ +#define CAN_TXBCIE_CFIE29_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE29_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Mask */ +#define CAN_TXBCIE_CFIE29(value) (CAN_TXBCIE_CFIE29_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE29_Pos)) /* Assigment of value for CFIE29 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE30_Pos _UINT32_(30) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Position */ +#define CAN_TXBCIE_CFIE30_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE30_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Mask */ +#define CAN_TXBCIE_CFIE30(value) (CAN_TXBCIE_CFIE30_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE30_Pos)) /* Assigment of value for CFIE30 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_CFIE31_Pos _UINT32_(31) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Position */ +#define CAN_TXBCIE_CFIE31_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE31_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Mask */ +#define CAN_TXBCIE_CFIE31(value) (CAN_TXBCIE_CFIE31_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE31_Pos)) /* Assigment of value for CFIE31 in the CAN_TXBCIE register */ +#define CAN_TXBCIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCIE) Register Mask */ + +#define CAN_TXBCIE_CFIE_Pos _UINT32_(0) /* (CAN_TXBCIE Position) Cancellation Finished Interrupt Enable 3x */ +#define CAN_TXBCIE_CFIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCIE_CFIE_Pos) /* (CAN_TXBCIE Mask) CFIE */ +#define CAN_TXBCIE_CFIE(value) (CAN_TXBCIE_CFIE_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE_Pos)) + +/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ +#define CAN_TXEFC_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFC) Tx Event FIFO Configuration Reset Value */ + +#define CAN_TXEFC_EFSA_Pos _UINT32_(0) /* (CAN_TXEFC) Event FIFO Start Address Position */ +#define CAN_TXEFC_EFSA_Msk (_UINT32_(0xFFFF) << CAN_TXEFC_EFSA_Pos) /* (CAN_TXEFC) Event FIFO Start Address Mask */ +#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & (_UINT32_(value) << CAN_TXEFC_EFSA_Pos)) /* Assigment of value for EFSA in the CAN_TXEFC register */ +#define CAN_TXEFC_EFS_Pos _UINT32_(16) /* (CAN_TXEFC) Event FIFO Size Position */ +#define CAN_TXEFC_EFS_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFS_Pos) /* (CAN_TXEFC) Event FIFO Size Mask */ +#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & (_UINT32_(value) << CAN_TXEFC_EFS_Pos)) /* Assigment of value for EFS in the CAN_TXEFC register */ +#define CAN_TXEFC_EFWM_Pos _UINT32_(24) /* (CAN_TXEFC) Event FIFO Watermark Position */ +#define CAN_TXEFC_EFWM_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFWM_Pos) /* (CAN_TXEFC) Event FIFO Watermark Mask */ +#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & (_UINT32_(value) << CAN_TXEFC_EFWM_Pos)) /* Assigment of value for EFWM in the CAN_TXEFC register */ +#define CAN_TXEFC_Msk _UINT32_(0x3F3FFFFF) /* (CAN_TXEFC) Register Mask */ + + +/* -------- CAN_TXEFS : (CAN Offset: 0xF4) ( R/ 32) Tx Event FIFO Status -------- */ +#define CAN_TXEFS_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFS) Tx Event FIFO Status Reset Value */ + +#define CAN_TXEFS_EFFL_Pos _UINT32_(0) /* (CAN_TXEFS) Event FIFO Fill Level Position */ +#define CAN_TXEFS_EFFL_Msk (_UINT32_(0x3F) << CAN_TXEFS_EFFL_Pos) /* (CAN_TXEFS) Event FIFO Fill Level Mask */ +#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & (_UINT32_(value) << CAN_TXEFS_EFFL_Pos)) /* Assigment of value for EFFL in the CAN_TXEFS register */ +#define CAN_TXEFS_EFGI_Pos _UINT32_(8) /* (CAN_TXEFS) Event FIFO Get Index Position */ +#define CAN_TXEFS_EFGI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFGI_Pos) /* (CAN_TXEFS) Event FIFO Get Index Mask */ +#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & (_UINT32_(value) << CAN_TXEFS_EFGI_Pos)) /* Assigment of value for EFGI in the CAN_TXEFS register */ +#define CAN_TXEFS_EFPI_Pos _UINT32_(16) /* (CAN_TXEFS) Event FIFO Put Index Position */ +#define CAN_TXEFS_EFPI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFPI_Pos) /* (CAN_TXEFS) Event FIFO Put Index Mask */ +#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & (_UINT32_(value) << CAN_TXEFS_EFPI_Pos)) /* Assigment of value for EFPI in the CAN_TXEFS register */ +#define CAN_TXEFS_EFF_Pos _UINT32_(24) /* (CAN_TXEFS) Event FIFO Full Position */ +#define CAN_TXEFS_EFF_Msk (_UINT32_(0x1) << CAN_TXEFS_EFF_Pos) /* (CAN_TXEFS) Event FIFO Full Mask */ +#define CAN_TXEFS_EFF(value) (CAN_TXEFS_EFF_Msk & (_UINT32_(value) << CAN_TXEFS_EFF_Pos)) /* Assigment of value for EFF in the CAN_TXEFS register */ +#define CAN_TXEFS_TEFL_Pos _UINT32_(25) /* (CAN_TXEFS) Tx Event FIFO Element Lost Position */ +#define CAN_TXEFS_TEFL_Msk (_UINT32_(0x1) << CAN_TXEFS_TEFL_Pos) /* (CAN_TXEFS) Tx Event FIFO Element Lost Mask */ +#define CAN_TXEFS_TEFL(value) (CAN_TXEFS_TEFL_Msk & (_UINT32_(value) << CAN_TXEFS_TEFL_Pos)) /* Assigment of value for TEFL in the CAN_TXEFS register */ +#define CAN_TXEFS_Msk _UINT32_(0x031F1F3F) /* (CAN_TXEFS) Register Mask */ + + +/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ +#define CAN_TXEFA_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Reset Value */ + +#define CAN_TXEFA_EFAI_Pos _UINT32_(0) /* (CAN_TXEFA) Event FIFO Acknowledge Index Position */ +#define CAN_TXEFA_EFAI_Msk (_UINT32_(0x1F) << CAN_TXEFA_EFAI_Pos) /* (CAN_TXEFA) Event FIFO Acknowledge Index Mask */ +#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & (_UINT32_(value) << CAN_TXEFA_EFAI_Pos)) /* Assigment of value for EFAI in the CAN_TXEFA register */ +#define CAN_TXEFA_Msk _UINT32_(0x0000001F) /* (CAN_TXEFA) Register Mask */ + + +/** \brief CAN register offsets definitions */ +#define CAN_RXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_RXBE_0) Rx Buffer Element 0 Offset */ +#define CAN_RXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_RXBE_1) Rx Buffer Element 1 Offset */ +#define CAN_RXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXBE_DATA) Rx Buffer Element Data Offset */ +#define CAN_RXF0E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ +#define CAN_RXF0E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ +#define CAN_RXF0E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ +#define CAN_RXF1E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ +#define CAN_RXF1E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ +#define CAN_RXF1E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ +#define CAN_TXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXBE_0) Tx Buffer Element 0 Offset */ +#define CAN_TXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXBE_1) Tx Buffer Element 1 Offset */ +#define CAN_TXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_TXBE_DATA) Tx Buffer Element Data Offset */ +#define CAN_TXEFE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ +#define CAN_TXEFE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ +#define CAN_SIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ +#define CAN_XIDFE_1_REG_OFST _UINT32_(0x04) /* (CAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ +#define CAN_CREL_REG_OFST _UINT32_(0x00) /* (CAN_CREL) Core Release Offset */ +#define CAN_ENDN_REG_OFST _UINT32_(0x04) /* (CAN_ENDN) Endian Offset */ +#define CAN_MRCFG_REG_OFST _UINT32_(0x08) /* (CAN_MRCFG) Message RAM Configuration Offset */ +#define CAN_DBTP_REG_OFST _UINT32_(0x0C) /* (CAN_DBTP) Fast Bit Timing and Prescaler Offset */ +#define CAN_TEST_REG_OFST _UINT32_(0x10) /* (CAN_TEST) Test Offset */ +#define CAN_RWD_REG_OFST _UINT32_(0x14) /* (CAN_RWD) RAM Watchdog Offset */ +#define CAN_CCCR_REG_OFST _UINT32_(0x18) /* (CAN_CCCR) CC Control Offset */ +#define CAN_NBTP_REG_OFST _UINT32_(0x1C) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Offset */ +#define CAN_TSCC_REG_OFST _UINT32_(0x20) /* (CAN_TSCC) Timestamp Counter Configuration Offset */ +#define CAN_TSCV_REG_OFST _UINT32_(0x24) /* (CAN_TSCV) Timestamp Counter Value Offset */ +#define CAN_TOCC_REG_OFST _UINT32_(0x28) /* (CAN_TOCC) Timeout Counter Configuration Offset */ +#define CAN_TOCV_REG_OFST _UINT32_(0x2C) /* (CAN_TOCV) Timeout Counter Value Offset */ +#define CAN_ECR_REG_OFST _UINT32_(0x40) /* (CAN_ECR) Error Counter Offset */ +#define CAN_PSR_REG_OFST _UINT32_(0x44) /* (CAN_PSR) Protocol Status Offset */ +#define CAN_TDCR_REG_OFST _UINT32_(0x48) /* (CAN_TDCR) Extended ID Filter Configuration Offset */ +#define CAN_IR_REG_OFST _UINT32_(0x50) /* (CAN_IR) Interrupt Offset */ +#define CAN_IE_REG_OFST _UINT32_(0x54) /* (CAN_IE) Interrupt Enable Offset */ +#define CAN_ILS_REG_OFST _UINT32_(0x58) /* (CAN_ILS) Interrupt Line Select Offset */ +#define CAN_ILE_REG_OFST _UINT32_(0x5C) /* (CAN_ILE) Interrupt Line Enable Offset */ +#define CAN_GFC_REG_OFST _UINT32_(0x80) /* (CAN_GFC) Global Filter Configuration Offset */ +#define CAN_SIDFC_REG_OFST _UINT32_(0x84) /* (CAN_SIDFC) Standard ID Filter Configuration Offset */ +#define CAN_XIDFC_REG_OFST _UINT32_(0x88) /* (CAN_XIDFC) Extended ID Filter Configuration Offset */ +#define CAN_XIDAM_REG_OFST _UINT32_(0x90) /* (CAN_XIDAM) Extended ID AND Mask Offset */ +#define CAN_HPMS_REG_OFST _UINT32_(0x94) /* (CAN_HPMS) High Priority Message Status Offset */ +#define CAN_NDAT1_REG_OFST _UINT32_(0x98) /* (CAN_NDAT1) New Data 1 Offset */ +#define CAN_NDAT2_REG_OFST _UINT32_(0x9C) /* (CAN_NDAT2) New Data 2 Offset */ +#define CAN_RXF0C_REG_OFST _UINT32_(0xA0) /* (CAN_RXF0C) Rx FIFO 0 Configuration Offset */ +#define CAN_RXF0S_REG_OFST _UINT32_(0xA4) /* (CAN_RXF0S) Rx FIFO 0 Status Offset */ +#define CAN_RXF0A_REG_OFST _UINT32_(0xA8) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Offset */ +#define CAN_RXBC_REG_OFST _UINT32_(0xAC) /* (CAN_RXBC) Rx Buffer Configuration Offset */ +#define CAN_RXF1C_REG_OFST _UINT32_(0xB0) /* (CAN_RXF1C) Rx FIFO 1 Configuration Offset */ +#define CAN_RXF1S_REG_OFST _UINT32_(0xB4) /* (CAN_RXF1S) Rx FIFO 1 Status Offset */ +#define CAN_RXF1A_REG_OFST _UINT32_(0xB8) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Offset */ +#define CAN_RXESC_REG_OFST _UINT32_(0xBC) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Offset */ +#define CAN_TXBC_REG_OFST _UINT32_(0xC0) /* (CAN_TXBC) Tx Buffer Configuration Offset */ +#define CAN_TXFQS_REG_OFST _UINT32_(0xC4) /* (CAN_TXFQS) Tx FIFO / Queue Status Offset */ +#define CAN_TXESC_REG_OFST _UINT32_(0xC8) /* (CAN_TXESC) Tx Buffer Element Size Configuration Offset */ +#define CAN_TXBRP_REG_OFST _UINT32_(0xCC) /* (CAN_TXBRP) Tx Buffer Request Pending Offset */ +#define CAN_TXBAR_REG_OFST _UINT32_(0xD0) /* (CAN_TXBAR) Tx Buffer Add Request Offset */ +#define CAN_TXBCR_REG_OFST _UINT32_(0xD4) /* (CAN_TXBCR) Tx Buffer Cancellation Request Offset */ +#define CAN_TXBTO_REG_OFST _UINT32_(0xD8) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Offset */ +#define CAN_TXBCF_REG_OFST _UINT32_(0xDC) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Offset */ +#define CAN_TXBTIE_REG_OFST _UINT32_(0xE0) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Offset */ +#define CAN_TXBCIE_REG_OFST _UINT32_(0xE4) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Offset */ +#define CAN_TXEFC_REG_OFST _UINT32_(0xF0) /* (CAN_TXEFC) Tx Event FIFO Configuration Offset */ +#define CAN_TXEFS_REG_OFST _UINT32_(0xF4) /* (CAN_TXEFS) Tx Event FIFO Status Offset */ +#define CAN_TXEFA_REG_OFST _UINT32_(0xF8) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CAN_RXBE register API structure */ +typedef struct +{ /* Rx Buffer Element */ + __IO uint32_t CAN_RXBE_0; /**< Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO uint32_t CAN_RXBE_1; /**< Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO uint32_t CAN_RXBE_DATA; /**< Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} can_rxbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_RXF0E register API structure */ +typedef struct +{ /* Rx FIFO 0 Element */ + __IO uint32_t CAN_RXF0E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO uint32_t CAN_RXF0E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO uint32_t CAN_RXF0E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} can_rxf0e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_RXF1E register API structure */ +typedef struct +{ /* Rx FIFO 1 Element */ + __IO uint32_t CAN_RXF1E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO uint32_t CAN_RXF1E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO uint32_t CAN_RXF1E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} can_rxf1e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_TXBE register API structure */ +typedef struct +{ /* Tx Buffer Element */ + __IO uint32_t CAN_TXBE_0; /**< Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO uint32_t CAN_TXBE_1; /**< Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO uint32_t CAN_TXBE_DATA; /**< Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} can_txbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_TXEFE register API structure */ +typedef struct +{ /* Tx Event FIFO Element */ + __IO uint32_t CAN_TXEFE_0; /**< Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO uint32_t CAN_TXEFE_1; /**< Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} can_txefe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_SIDFE register API structure */ +typedef struct +{ /* Standard Message ID Filter Element */ + __IO uint32_t CAN_SIDFE_0; /**< Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ +} can_sidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN_XIDFE register API structure */ +typedef struct +{ /* Extended Message ID Filter Element */ + __IO uint32_t CAN_XIDFE_0; /**< Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO uint32_t CAN_XIDFE_1; /**< Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} can_xidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief CAN register API structure */ +typedef struct +{ /* Control Area Network */ + __I uint32_t CAN_CREL; /**< Offset: 0x00 (R/ 32) Core Release */ + __I uint32_t CAN_ENDN; /**< Offset: 0x04 (R/ 32) Endian */ + __IO uint32_t CAN_MRCFG; /**< Offset: 0x08 (R/W 32) Message RAM Configuration */ + __IO uint32_t CAN_DBTP; /**< Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ + __IO uint32_t CAN_TEST; /**< Offset: 0x10 (R/W 32) Test */ + __IO uint32_t CAN_RWD; /**< Offset: 0x14 (R/W 32) RAM Watchdog */ + __IO uint32_t CAN_CCCR; /**< Offset: 0x18 (R/W 32) CC Control */ + __IO uint32_t CAN_NBTP; /**< Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ + __IO uint32_t CAN_TSCC; /**< Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ + __I uint32_t CAN_TSCV; /**< Offset: 0x24 (R/ 32) Timestamp Counter Value */ + __IO uint32_t CAN_TOCC; /**< Offset: 0x28 (R/W 32) Timeout Counter Configuration */ + __IO uint32_t CAN_TOCV; /**< Offset: 0x2C (R/W 32) Timeout Counter Value */ + __I uint8_t Reserved1[0x10]; + __I uint32_t CAN_ECR; /**< Offset: 0x40 (R/ 32) Error Counter */ + __I uint32_t CAN_PSR; /**< Offset: 0x44 (R/ 32) Protocol Status */ + __IO uint32_t CAN_TDCR; /**< Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t CAN_IR; /**< Offset: 0x50 (R/W 32) Interrupt */ + __IO uint32_t CAN_IE; /**< Offset: 0x54 (R/W 32) Interrupt Enable */ + __IO uint32_t CAN_ILS; /**< Offset: 0x58 (R/W 32) Interrupt Line Select */ + __IO uint32_t CAN_ILE; /**< Offset: 0x5C (R/W 32) Interrupt Line Enable */ + __I uint8_t Reserved3[0x20]; + __IO uint32_t CAN_GFC; /**< Offset: 0x80 (R/W 32) Global Filter Configuration */ + __IO uint32_t CAN_SIDFC; /**< Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ + __IO uint32_t CAN_XIDFC; /**< Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t CAN_XIDAM; /**< Offset: 0x90 (R/W 32) Extended ID AND Mask */ + __I uint32_t CAN_HPMS; /**< Offset: 0x94 (R/ 32) High Priority Message Status */ + __IO uint32_t CAN_NDAT1; /**< Offset: 0x98 (R/W 32) New Data 1 */ + __IO uint32_t CAN_NDAT2; /**< Offset: 0x9C (R/W 32) New Data 2 */ + __IO uint32_t CAN_RXF0C; /**< Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ + __I uint32_t CAN_RXF0S; /**< Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ + __IO uint32_t CAN_RXF0A; /**< Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ + __IO uint32_t CAN_RXBC; /**< Offset: 0xAC (R/W 32) Rx Buffer Configuration */ + __IO uint32_t CAN_RXF1C; /**< Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ + __I uint32_t CAN_RXF1S; /**< Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ + __IO uint32_t CAN_RXF1A; /**< Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ + __IO uint32_t CAN_RXESC; /**< Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ + __IO uint32_t CAN_TXBC; /**< Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ + __I uint32_t CAN_TXFQS; /**< Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ + __IO uint32_t CAN_TXESC; /**< Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ + __I uint32_t CAN_TXBRP; /**< Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ + __IO uint32_t CAN_TXBAR; /**< Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ + __IO uint32_t CAN_TXBCR; /**< Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ + __I uint32_t CAN_TXBTO; /**< Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ + __I uint32_t CAN_TXBCF; /**< Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ + __IO uint32_t CAN_TXBTIE; /**< Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ + __IO uint32_t CAN_TXBCIE; /**< Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ + __I uint8_t Reserved5[0x08]; + __IO uint32_t CAN_TXEFC; /**< Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ + __I uint32_t CAN_TXEFS; /**< Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ + __IO uint32_t CAN_TXEFA; /**< Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ +} can_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_CAN_COMPONENT_H_ */ diff --git a/os/common/ext/Microchip/SAME54/component/ccl.h b/os/common/ext/Microchip/SAME54/component/ccl.h new file mode 100644 index 0000000000..42db4fe17e --- /dev/null +++ b/os/common/ext/Microchip/SAME54/component/ccl.h @@ -0,0 +1,220 @@ +/* + * Component description for CCL + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:08Z */ +#ifndef _SAME54_CCL_COMPONENT_H_ +#define _SAME54_CCL_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CCL */ +/* ************************************************************************** */ + +/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */ +#define CCL_CTRL_RESETVALUE _UINT8_(0x00) /* (CCL_CTRL) Control Reset Value */ + +#define CCL_CTRL_SWRST_Pos _UINT8_(0) /* (CCL_CTRL) Software Reset Position */ +#define CCL_CTRL_SWRST_Msk (_UINT8_(0x1) << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) Software Reset Mask */ +#define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & (_UINT8_(value) << CCL_CTRL_SWRST_Pos)) /* Assigment of value for SWRST in the CCL_CTRL register */ +#define CCL_CTRL_SWRST_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is not reset */ +#define CCL_CTRL_SWRST_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is reset */ +#define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is not reset Position */ +#define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /* (CCL_CTRL) The peripheral is reset Position */ +#define CCL_CTRL_ENABLE_Pos _UINT8_(1) /* (CCL_CTRL) Enable Position */ +#define CCL_CTRL_ENABLE_Msk (_UINT8_(0x1) << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) Enable Mask */ +#define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & (_UINT8_(value) << CCL_CTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the CCL_CTRL register */ +#define CCL_CTRL_ENABLE_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) The peripheral is disabled */ +#define CCL_CTRL_ENABLE_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) The peripheral is enabled */ +#define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is disabled Position */ +#define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /* (CCL_CTRL) The peripheral is enabled Position */ +#define CCL_CTRL_RUNSTDBY_Pos _UINT8_(6) /* (CCL_CTRL) Run in Standby Position */ +#define CCL_CTRL_RUNSTDBY_Msk (_UINT8_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Run in Standby Mask */ +#define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & (_UINT8_(value) << CCL_CTRL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the CCL_CTRL register */ +#define CCL_CTRL_RUNSTDBY_DISABLE_Val _UINT8_(0x0) /* (CCL_CTRL) Generic clock is not required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_ENABLE_Val _UINT8_(0x1) /* (CCL_CTRL) Generic clock is required in standby sleep mode */ +#define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is not required in standby sleep mode Position */ +#define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /* (CCL_CTRL) Generic clock is required in standby sleep mode Position */ +#define CCL_CTRL_Msk _UINT8_(0x43) /* (CCL_CTRL) Register Mask */ + + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */ +#define CCL_SEQCTRL_RESETVALUE _UINT8_(0x00) /* (CCL_SEQCTRL) SEQ Control x Reset Value */ + +#define CCL_SEQCTRL_SEQSEL_Pos _UINT8_(0) /* (CCL_SEQCTRL) Sequential Selection Position */ +#define CCL_SEQCTRL_SEQSEL_Msk (_UINT8_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential Selection Mask */ +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & (_UINT8_(value) << CCL_SEQCTRL_SEQSEL_Pos)) /* Assigment of value for SEQSEL in the CCL_SEQCTRL register */ +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _UINT8_(0x0) /* (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _UINT8_(0x1) /* (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _UINT8_(0x2) /* (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _UINT8_(0x3) /* (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _UINT8_(0x4) /* (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) Sequential logic is disabled Position */ +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) JK flip flop Position */ +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) D latch Position */ +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /* (CCL_SEQCTRL) RS latch Position */ +#define CCL_SEQCTRL_Msk _UINT8_(0x0F) /* (CCL_SEQCTRL) Register Mask */ + + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */ +#define CCL_LUTCTRL_RESETVALUE _UINT32_(0x00) /* (CCL_LUTCTRL) LUT Control x Reset Value */ + +#define CCL_LUTCTRL_ENABLE_Pos _UINT32_(1) /* (CCL_LUTCTRL) LUT Enable Position */ +#define CCL_LUTCTRL_ENABLE_Msk (_UINT32_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT Enable Mask */ +#define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & (_UINT32_(value) << CCL_LUTCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_ENABLE_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT block is disabled */ +#define CCL_LUTCTRL_ENABLE_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT block is enabled */ +#define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is disabled Position */ +#define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /* (CCL_LUTCTRL) LUT block is enabled Position */ +#define CCL_LUTCTRL_FILTSEL_Pos _UINT32_(4) /* (CCL_LUTCTRL) Filter Selection Position */ +#define CCL_LUTCTRL_FILTSEL_Msk (_UINT32_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter Selection Mask */ +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_FILTSEL_Pos)) /* Assigment of value for FILTSEL in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter disabled Position */ +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Synchronizer enabled Position */ +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /* (CCL_LUTCTRL) Filter enabled Position */ +#define CCL_LUTCTRL_EDGESEL_Pos _UINT32_(7) /* (CCL_LUTCTRL) Edge Selection Position */ +#define CCL_LUTCTRL_EDGESEL_Msk (_UINT32_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge Selection Mask */ +#define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & (_UINT32_(value) << CCL_LUTCTRL_EDGESEL_Pos)) /* Assigment of value for EDGESEL in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_EDGESEL_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Edge detector is disabled */ +#define CCL_LUTCTRL_EDGESEL_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Edge detector is enabled */ +#define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is disabled Position */ +#define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /* (CCL_LUTCTRL) Edge detector is enabled Position */ +#define CCL_LUTCTRL_INSEL0_Pos _UINT32_(8) /* (CCL_LUTCTRL) Input Selection 0 Position */ +#define CCL_LUTCTRL_INSEL0_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Input Selection 0 Mask */ +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL0_Pos)) /* Assigment of value for INSEL0 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL0_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _UINT32_(0x8) /* (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL1_Pos _UINT32_(12) /* (CCL_LUTCTRL) Input Selection 1 Position */ +#define CCL_LUTCTRL_INSEL1_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Input Selection 1 Mask */ +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL1_Pos)) /* Assigment of value for INSEL1 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL1_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_TCC_Val _UINT32_(0x8) /* (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INSEL2_Pos _UINT32_(16) /* (CCL_LUTCTRL) Input Selection 2 Position */ +#define CCL_LUTCTRL_INSEL2_Msk (_UINT32_(0xF) << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Input Selection 2 Mask */ +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & (_UINT32_(value) << CCL_LUTCTRL_INSEL2_Pos)) /* Assigment of value for INSEL2 in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INSEL2_MASK_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _UINT32_(0x2) /* (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _UINT32_(0x3) /* (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _UINT32_(0x4) /* (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _UINT32_(0x5) /* (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _UINT32_(0x6) /* (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _UINT32_(0x7) /* (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_TCC_Val _UINT32_(0x8) /* (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _UINT32_(0x9) /* (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Masked input Position */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Feedback input source Position */ +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Linked LUT input source Position */ +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Event input source Position */ +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) I/O pin input source Position */ +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) AC input source Position */ +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) TC input source Position */ +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) Alternate TC input source Position */ +#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) TCC input source Position */ +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) /* (CCL_LUTCTRL) SERCOM input source Position */ +#define CCL_LUTCTRL_INVEI_Pos _UINT32_(20) /* (CCL_LUTCTRL) Inverted Event Input Enable Position */ +#define CCL_LUTCTRL_INVEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Inverted Event Input Enable Mask */ +#define CCL_LUTCTRL_INVEI(value) (CCL_LUTCTRL_INVEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_INVEI_Pos)) /* Assigment of value for INVEI in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_INVEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) Incoming event is not inverted */ +#define CCL_LUTCTRL_INVEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) Incoming event is inverted */ +#define CCL_LUTCTRL_INVEI_DISABLE (CCL_LUTCTRL_INVEI_DISABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is not inverted Position */ +#define CCL_LUTCTRL_INVEI_ENABLE (CCL_LUTCTRL_INVEI_ENABLE_Val << CCL_LUTCTRL_INVEI_Pos) /* (CCL_LUTCTRL) Incoming event is inverted Position */ +#define CCL_LUTCTRL_LUTEI_Pos _UINT32_(21) /* (CCL_LUTCTRL) LUT Event Input Enable Position */ +#define CCL_LUTCTRL_LUTEI_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT Event Input Enable Mask */ +#define CCL_LUTCTRL_LUTEI(value) (CCL_LUTCTRL_LUTEI_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEI_Pos)) /* Assigment of value for LUTEI in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_LUTEI_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT incoming event is disabled */ +#define CCL_LUTCTRL_LUTEI_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT incoming event is enabled */ +#define CCL_LUTCTRL_LUTEI_DISABLE (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is disabled Position */ +#define CCL_LUTCTRL_LUTEI_ENABLE (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /* (CCL_LUTCTRL) LUT incoming event is enabled Position */ +#define CCL_LUTCTRL_LUTEO_Pos _UINT32_(22) /* (CCL_LUTCTRL) LUT Event Output Enable Position */ +#define CCL_LUTCTRL_LUTEO_Msk (_UINT32_(0x1) << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT Event Output Enable Mask */ +#define CCL_LUTCTRL_LUTEO(value) (CCL_LUTCTRL_LUTEO_Msk & (_UINT32_(value) << CCL_LUTCTRL_LUTEO_Pos)) /* Assigment of value for LUTEO in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_LUTEO_DISABLE_Val _UINT32_(0x0) /* (CCL_LUTCTRL) LUT event output is disabled */ +#define CCL_LUTCTRL_LUTEO_ENABLE_Val _UINT32_(0x1) /* (CCL_LUTCTRL) LUT event output is enabled */ +#define CCL_LUTCTRL_LUTEO_DISABLE (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is disabled Position */ +#define CCL_LUTCTRL_LUTEO_ENABLE (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /* (CCL_LUTCTRL) LUT event output is enabled Position */ +#define CCL_LUTCTRL_TRUTH_Pos _UINT32_(24) /* (CCL_LUTCTRL) Truth Value Position */ +#define CCL_LUTCTRL_TRUTH_Msk (_UINT32_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) /* (CCL_LUTCTRL) Truth Value Mask */ +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & (_UINT32_(value) << CCL_LUTCTRL_TRUTH_Pos)) /* Assigment of value for TRUTH in the CCL_LUTCTRL register */ +#define CCL_LUTCTRL_Msk _UINT32_(0xFF7FFFB2) /* (CCL_LUTCTRL) Register Mask */ + + +/** \brief CCL register offsets definitions */ +#define CCL_CTRL_REG_OFST _UINT32_(0x00) /* (CCL_CTRL) Control Offset */ +#define CCL_SEQCTRL_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL) SEQ Control x Offset */ +#define CCL_SEQCTRL0_REG_OFST _UINT32_(0x04) /* (CCL_SEQCTRL0) SEQ Control x Offset */ +#define CCL_SEQCTRL1_REG_OFST _UINT32_(0x05) /* (CCL_SEQCTRL1) SEQ Control x Offset */ +#define CCL_LUTCTRL_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL) LUT Control x Offset */ +#define CCL_LUTCTRL0_REG_OFST _UINT32_(0x08) /* (CCL_LUTCTRL0) LUT Control x Offset */ +#define CCL_LUTCTRL1_REG_OFST _UINT32_(0x0C) /* (CCL_LUTCTRL1) LUT Control x Offset */ +#define CCL_LUTCTRL2_REG_OFST _UINT32_(0x10) /* (CCL_LUTCTRL2) LUT Control x Offset */ +#define CCL_LUTCTRL3_REG_OFST _UINT32_(0x14) /* (CCL_LUTCTRL3) LUT Control x Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CCL register API structure */ +typedef struct +{ /* Configurable Custom Logic */ + __IO uint8_t CCL_CTRL; /**< Offset: 0x00 (R/W 8) Control */ + __I uint8_t Reserved1[0x03]; + __IO uint8_t CCL_SEQCTRL[2]; /**< Offset: 0x04 (R/W 8) SEQ Control x */ + __I uint8_t Reserved2[0x02]; + __IO uint32_t CCL_LUTCTRL[4]; /**< Offset: 0x08 (R/W 32) LUT Control x */ +} ccl_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_CCL_COMPONENT_H_ */ diff --git a/os/common/ext/Microchip/SAME54/component/cmcc.h b/os/common/ext/Microchip/SAME54/component/cmcc.h new file mode 100644 index 0000000000..89bca27f2d --- /dev/null +++ b/os/common/ext/Microchip/SAME54/component/cmcc.h @@ -0,0 +1,214 @@ +/* + * Component description for CMCC + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:08Z */ +#ifndef _SAME54_CMCC_COMPONENT_H_ +#define _SAME54_CMCC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CMCC */ +/* ************************************************************************** */ + +/* -------- CMCC_TYPE : (CMCC Offset: 0x00) ( R/ 32) Cache Type Register -------- */ +#define CMCC_TYPE_RESETVALUE _UINT32_(0x12D2) /* (CMCC_TYPE) Cache Type Register Reset Value */ + +#define CMCC_TYPE_GCLK_Pos _UINT32_(1) /* (CMCC_TYPE) dynamic Clock Gating supported Position */ +#define CMCC_TYPE_GCLK_Msk (_UINT32_(0x1) << CMCC_TYPE_GCLK_Pos) /* (CMCC_TYPE) dynamic Clock Gating supported Mask */ +#define CMCC_TYPE_GCLK(value) (CMCC_TYPE_GCLK_Msk & (_UINT32_(value) << CMCC_TYPE_GCLK_Pos)) /* Assigment of value for GCLK in the CMCC_TYPE register */ +#define CMCC_TYPE_RRP_Pos _UINT32_(4) /* (CMCC_TYPE) Round Robin Policy supported Position */ +#define CMCC_TYPE_RRP_Msk (_UINT32_(0x1) << CMCC_TYPE_RRP_Pos) /* (CMCC_TYPE) Round Robin Policy supported Mask */ +#define CMCC_TYPE_RRP(value) (CMCC_TYPE_RRP_Msk & (_UINT32_(value) << CMCC_TYPE_RRP_Pos)) /* Assigment of value for RRP in the CMCC_TYPE register */ +#define CMCC_TYPE_WAYNUM_Pos _UINT32_(5) /* (CMCC_TYPE) Number of Way Position */ +#define CMCC_TYPE_WAYNUM_Msk (_UINT32_(0x3) << CMCC_TYPE_WAYNUM_Pos) /* (CMCC_TYPE) Number of Way Mask */ +#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & (_UINT32_(value) << CMCC_TYPE_WAYNUM_Pos)) /* Assigment of value for WAYNUM in the CMCC_TYPE register */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _UINT32_(0x2) /* (CMCC_TYPE) 4-WAY set associative */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) /* (CMCC_TYPE) 4-WAY set associative Position */ +#define CMCC_TYPE_LCKDOWN_Pos _UINT32_(7) /* (CMCC_TYPE) Lock Down supported Position */ +#define CMCC_TYPE_LCKDOWN_Msk (_UINT32_(0x1) << CMCC_TYPE_LCKDOWN_Pos) /* (CMCC_TYPE) Lock Down supported Mask */ +#define CMCC_TYPE_LCKDOWN(value) (CMCC_TYPE_LCKDOWN_Msk & (_UINT32_(value) << CMCC_TYPE_LCKDOWN_Pos)) /* Assigment of value for LCKDOWN in the CMCC_TYPE register */ +#define CMCC_TYPE_CSIZE_Pos _UINT32_(8) /* (CMCC_TYPE) Cache Size Position */ +#define CMCC_TYPE_CSIZE_Msk (_UINT32_(0x7) << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size Mask */ +#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & (_UINT32_(value) << CMCC_TYPE_CSIZE_Pos)) /* Assigment of value for CSIZE in the CMCC_TYPE register */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _UINT32_(0x0) /* (CMCC_TYPE) Cache Size is 1 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _UINT32_(0x1) /* (CMCC_TYPE) Cache Size is 2 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _UINT32_(0x2) /* (CMCC_TYPE) Cache Size is 4 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size is 1 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size is 2 KB Position */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size is 4 KB Position */ +#define CMCC_TYPE_CLSIZE_Pos _UINT32_(11) /* (CMCC_TYPE) Cache Line Size Position */ +#define CMCC_TYPE_CLSIZE_Msk (_UINT32_(0x7) << CMCC_TYPE_CLSIZE_Pos) /* (CMCC_TYPE) Cache Line Size Mask */ +#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & (_UINT32_(value) << CMCC_TYPE_CLSIZE_Pos)) /* Assigment of value for CLSIZE in the CMCC_TYPE register */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _UINT32_(0x2) /* (CMCC_TYPE) Cache Line Size is 16 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) /* (CMCC_TYPE) Cache Line Size is 16 bytes Position */ +#define CMCC_TYPE_Msk _UINT32_(0x00003FF2) /* (CMCC_TYPE) Register Mask */ + + +/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ +#define CMCC_CFG_RESETVALUE _UINT32_(0x20) /* (CMCC_CFG) Cache Configuration Register Reset Value */ + +#define CMCC_CFG_ICDIS_Pos _UINT32_(1) /* (CMCC_CFG) Instruction Cache Disable Position */ +#define CMCC_CFG_ICDIS_Msk (_UINT32_(0x1) << CMCC_CFG_ICDIS_Pos) /* (CMCC_CFG) Instruction Cache Disable Mask */ +#define CMCC_CFG_ICDIS(value) (CMCC_CFG_ICDIS_Msk & (_UINT32_(value) << CMCC_CFG_ICDIS_Pos)) /* Assigment of value for ICDIS in the CMCC_CFG register */ +#define CMCC_CFG_DCDIS_Pos _UINT32_(2) /* (CMCC_CFG) Data Cache Disable Position */ +#define CMCC_CFG_DCDIS_Msk (_UINT32_(0x1) << CMCC_CFG_DCDIS_Pos) /* (CMCC_CFG) Data Cache Disable Mask */ +#define CMCC_CFG_DCDIS(value) (CMCC_CFG_DCDIS_Msk & (_UINT32_(value) << CMCC_CFG_DCDIS_Pos)) /* Assigment of value for DCDIS in the CMCC_CFG register */ +#define CMCC_CFG_CSIZESW_Pos _UINT32_(4) /* (CMCC_CFG) Cache size configured by software Position */ +#define CMCC_CFG_CSIZESW_Msk (_UINT32_(0x7) << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) Cache size configured by software Mask */ +#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & (_UINT32_(value) << CMCC_CFG_CSIZESW_Pos)) /* Assigment of value for CSIZESW in the CMCC_CFG register */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _UINT32_(0x0) /* (CMCC_CFG) The Cache Size is configured to 1KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _UINT32_(0x1) /* (CMCC_CFG) The Cache Size is configured to 2KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _UINT32_(0x2) /* (CMCC_CFG) The Cache Size is configured to 4KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) The Cache Size is configured to 1KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) The Cache Size is configured to 2KB Position */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) The Cache Size is configured to 4KB Position */ +#define CMCC_CFG_Msk _UINT32_(0x00000076) /* (CMCC_CFG) Register Mask */ + + +/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ +#define CMCC_CTRL_RESETVALUE _UINT32_(0x00) /* (CMCC_CTRL) Cache Control Register Reset Value */ + +#define CMCC_CTRL_CEN_Pos _UINT32_(0) /* (CMCC_CTRL) Cache Controller Enable Position */ +#define CMCC_CTRL_CEN_Msk (_UINT32_(0x1) << CMCC_CTRL_CEN_Pos) /* (CMCC_CTRL) Cache Controller Enable Mask */ +#define CMCC_CTRL_CEN(value) (CMCC_CTRL_CEN_Msk & (_UINT32_(value) << CMCC_CTRL_CEN_Pos)) /* Assigment of value for CEN in the CMCC_CTRL register */ +#define CMCC_CTRL_Msk _UINT32_(0x00000001) /* (CMCC_CTRL) Register Mask */ + + +/* -------- CMCC_SR : (CMCC Offset: 0x0C) ( R/ 32) Cache Status Register -------- */ +#define CMCC_SR_RESETVALUE _UINT32_(0x00) /* (CMCC_SR) Cache Status Register Reset Value */ + +#define CMCC_SR_CSTS_Pos _UINT32_(0) /* (CMCC_SR) Cache Controller Status Position */ +#define CMCC_SR_CSTS_Msk (_UINT32_(0x1) << CMCC_SR_CSTS_Pos) /* (CMCC_SR) Cache Controller Status Mask */ +#define CMCC_SR_CSTS(value) (CMCC_SR_CSTS_Msk & (_UINT32_(value) << CMCC_SR_CSTS_Pos)) /* Assigment of value for CSTS in the CMCC_SR register */ +#define CMCC_SR_Msk _UINT32_(0x00000001) /* (CMCC_SR) Register Mask */ + + +/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ +#define CMCC_LCKWAY_RESETVALUE _UINT32_(0x00) /* (CMCC_LCKWAY) Cache Lock per Way Register Reset Value */ + +#define CMCC_LCKWAY_LCKWAY_Pos _UINT32_(0) /* (CMCC_LCKWAY) Lockdown way Register Position */ +#define CMCC_LCKWAY_LCKWAY_Msk (_UINT32_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) /* (CMCC_LCKWAY) Lockdown way Register Mask */ +#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & (_UINT32_(value) << CMCC_LCKWAY_LCKWAY_Pos)) /* Assigment of value for LCKWAY in the CMCC_LCKWAY register */ +#define CMCC_LCKWAY_Msk _UINT32_(0x0000000F) /* (CMCC_LCKWAY) Register Mask */ + + +/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ +#define CMCC_MAINT0_RESETVALUE _UINT32_(0x00) /* (CMCC_MAINT0) Cache Maintenance Register 0 Reset Value */ + +#define CMCC_MAINT0_INVALL_Pos _UINT32_(0) /* (CMCC_MAINT0) Cache Controller invalidate All Position */ +#define CMCC_MAINT0_INVALL_Msk (_UINT32_(0x1) << CMCC_MAINT0_INVALL_Pos) /* (CMCC_MAINT0) Cache Controller invalidate All Mask */ +#define CMCC_MAINT0_INVALL(value) (CMCC_MAINT0_INVALL_Msk & (_UINT32_(value) << CMCC_MAINT0_INVALL_Pos)) /* Assigment of value for INVALL in the CMCC_MAINT0 register */ +#define CMCC_MAINT0_Msk _UINT32_(0x00000001) /* (CMCC_MAINT0) Register Mask */ + + +/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ +#define CMCC_MAINT1_RESETVALUE _UINT32_(0x00) /* (CMCC_MAINT1) Cache Maintenance Register 1 Reset Value */ + +#define CMCC_MAINT1_INDEX_Pos _UINT32_(4) /* (CMCC_MAINT1) Invalidate Index Position */ +#define CMCC_MAINT1_INDEX_Msk (_UINT32_(0xFF) << CMCC_MAINT1_INDEX_Pos) /* (CMCC_MAINT1) Invalidate Index Mask */ +#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & (_UINT32_(value) << CMCC_MAINT1_INDEX_Pos)) /* Assigment of value for INDEX in the CMCC_MAINT1 register */ +#define CMCC_MAINT1_WAY_Pos _UINT32_(28) /* (CMCC_MAINT1) Invalidate Way Position */ +#define CMCC_MAINT1_WAY_Msk (_UINT32_(0xF) << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Invalidate Way Mask */ +#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & (_UINT32_(value) << CMCC_MAINT1_WAY_Pos)) /* Assigment of value for WAY in the CMCC_MAINT1 register */ +#define CMCC_MAINT1_WAY_WAY0_Val _UINT32_(0x0) /* (CMCC_MAINT1) Way 0 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY1_Val _UINT32_(0x1) /* (CMCC_MAINT1) Way 1 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY2_Val _UINT32_(0x2) /* (CMCC_MAINT1) Way 2 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY3_Val _UINT32_(0x3) /* (CMCC_MAINT1) Way 3 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 0 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 1 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 2 is selection for index invalidation Position */ +#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 3 is selection for index invalidation Position */ +#define CMCC_MAINT1_Msk _UINT32_(0xF0000FF0) /* (CMCC_MAINT1) Register Mask */ + + +/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ +#define CMCC_MCFG_RESETVALUE _UINT32_(0x00) /* (CMCC_MCFG) Cache Monitor Configuration Register Reset Value */ + +#define CMCC_MCFG_MODE_Pos _UINT32_(0) /* (CMCC_MCFG) Cache Controller Monitor Counter Mode Position */ +#define CMCC_MCFG_MODE_Msk (_UINT32_(0x3) << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Cache Controller Monitor Counter Mode Mask */ +#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & (_UINT32_(value) << CMCC_MCFG_MODE_Pos)) /* Assigment of value for MODE in the CMCC_MCFG register */ +#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _UINT32_(0x0) /* (CMCC_MCFG) Cycle counter */ +#define CMCC_MCFG_MODE_IHIT_COUNT_Val _UINT32_(0x1) /* (CMCC_MCFG) Instruction hit counter */ +#define CMCC_MCFG_MODE_DHIT_COUNT_Val _UINT32_(0x2) /* (CMCC_MCFG) Data hit counter */ +#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Cycle counter Position */ +#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Instruction hit counter Position */ +#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Data hit counter Position */ +#define CMCC_MCFG_Msk _UINT32_(0x00000003) /* (CMCC_MCFG) Register Mask */ + + +/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ +#define CMCC_MEN_RESETVALUE _UINT32_(0x00) /* (CMCC_MEN) Cache Monitor Enable Register Reset Value */ + +#define CMCC_MEN_MENABLE_Pos _UINT32_(0) /* (CMCC_MEN) Cache Controller Monitor Enable Position */ +#define CMCC_MEN_MENABLE_Msk (_UINT32_(0x1) << CMCC_MEN_MENABLE_Pos) /* (CMCC_MEN) Cache Controller Monitor Enable Mask */ +#define CMCC_MEN_MENABLE(value) (CMCC_MEN_MENABLE_Msk & (_UINT32_(value) << CMCC_MEN_MENABLE_Pos)) /* Assigment of value for MENABLE in the CMCC_MEN register */ +#define CMCC_MEN_Msk _UINT32_(0x00000001) /* (CMCC_MEN) Register Mask */ + + +/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ +#define CMCC_MCTRL_RESETVALUE _UINT32_(0x00) /* (CMCC_MCTRL) Cache Monitor Control Register Reset Value */ + +#define CMCC_MCTRL_SWRST_Pos _UINT32_(0) /* (CMCC_MCTRL) Cache Controller Software Reset Position */ +#define CMCC_MCTRL_SWRST_Msk (_UINT32_(0x1) << CMCC_MCTRL_SWRST_Pos) /* (CMCC_MCTRL) Cache Controller Software Reset Mask */ +#define CMCC_MCTRL_SWRST(value) (CMCC_MCTRL_SWRST_Msk & (_UINT32_(value) << CMCC_MCTRL_SWRST_Pos)) /* Assigment of value for SWRST in the CMCC_MCTRL register */ +#define CMCC_MCTRL_Msk _UINT32_(0x00000001) /* (CMCC_MCTRL) Register Mask */ + + +/* -------- CMCC_MSR : (CMCC Offset: 0x34) ( R/ 32) Cache Monitor Status Register -------- */ +#define CMCC_MSR_RESETVALUE _UINT32_(0x00) /* (CMCC_MSR) Cache Monitor Status Register Reset Value */ + +#define CMCC_MSR_EVENT_CNT_Pos _UINT32_(0) /* (CMCC_MSR) Monitor Event Counter Position */ +#define CMCC_MSR_EVENT_CNT_Msk (_UINT32_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) /* (CMCC_MSR) Monitor Event Counter Mask */ +#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & (_UINT32_(value) << CMCC_MSR_EVENT_CNT_Pos)) /* Assigment of value for EVENT_CNT in the CMCC_MSR register */ +#define CMCC_MSR_Msk _UINT32_(0xFFFFFFFF) /* (CMCC_MSR) Register Mask */ + + +/** \brief CMCC register offsets definitions */ +#define CMCC_TYPE_REG_OFST _UINT32_(0x00) /* (CMCC_TYPE) Cache Type Register Offset */ +#define CMCC_CFG_REG_OFST _UINT32_(0x04) /* (CMCC_CFG) Cache Configuration Register Offset */ +#define CMCC_CTRL_REG_OFST _UINT32_(0x08) /* (CMCC_CTRL) Cache Control Register Offset */ +#define CMCC_SR_REG_OFST _UINT32_(0x0C) /* (CMCC_SR) Cache Status Register Offset */ +#define CMCC_LCKWAY_REG_OFST _UINT32_(0x10) /* (CMCC_LCKWAY) Cache Lock per Way Register Offset */ +#define CMCC_MAINT0_REG_OFST _UINT32_(0x20) /* (CMCC_MAINT0) Cache Maintenance Register 0 Offset */ +#define CMCC_MAINT1_REG_OFST _UINT32_(0x24) /* (CMCC_MAINT1) Cache Maintenance Register 1 Offset */ +#define CMCC_MCFG_REG_OFST _UINT32_(0x28) /* (CMCC_MCFG) Cache Monitor Configuration Register Offset */ +#define CMCC_MEN_REG_OFST _UINT32_(0x2C) /* (CMCC_MEN) Cache Monitor Enable Register Offset */ +#define CMCC_MCTRL_REG_OFST _UINT32_(0x30) /* (CMCC_MCTRL) Cache Monitor Control Register Offset */ +#define CMCC_MSR_REG_OFST _UINT32_(0x34) /* (CMCC_MSR) Cache Monitor Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CMCC register API structure */ +typedef struct +{ /* Cortex M Cache Controller */ + __I uint32_t CMCC_TYPE; /**< Offset: 0x00 (R/ 32) Cache Type Register */ + __IO uint32_t CMCC_CFG; /**< Offset: 0x04 (R/W 32) Cache Configuration Register */ + __O uint32_t CMCC_CTRL; /**< Offset: 0x08 ( /W 32) Cache Control Register */ + __I uint32_t CMCC_SR; /**< Offset: 0x0C (R/ 32) Cache Status Register */ + __IO uint32_t CMCC_LCKWAY; /**< Offset: 0x10 (R/W 32) Cache Lock per Way Register */ + __I uint8_t Reserved1[0x0C]; + __O uint32_t CMCC_MAINT0; /**< Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ + __O uint32_t CMCC_MAINT1; /**< Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ + __IO uint32_t CMCC_MCFG; /**< Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ + __IO uint32_t CMCC_MEN; /**< Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ + __O uint32_t CMCC_MCTRL; /**< Offset: 0x30 ( /W 32) Cache Monitor Control Register */ + __I uint32_t CMCC_MSR; /**< Offset: 0x34 (R/ 32) Cache Monitor Status Register */ +} cmcc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_CMCC_COMPONENT_H_ */ diff --git a/os/common/ext/Microchip/SAME54/component/dac.h b/os/common/ext/Microchip/SAME54/component/dac.h new file mode 100644 index 0000000000..e37e64df10 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/component/dac.h @@ -0,0 +1,444 @@ +/* + * Component description for DAC + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:08Z */ +#ifndef _SAME54_DAC_COMPONENT_H_ +#define _SAME54_DAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DAC */ +/* ************************************************************************** */ + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#define DAC_CTRLA_RESETVALUE _UINT8_(0x00) /* (DAC_CTRLA) Control A Reset Value */ + +#define DAC_CTRLA_SWRST_Pos _UINT8_(0) /* (DAC_CTRLA) Software Reset Position */ +#define DAC_CTRLA_SWRST_Msk (_UINT8_(0x1) << DAC_CTRLA_SWRST_Pos) /* (DAC_CTRLA) Software Reset Mask */ +#define DAC_CTRLA_SWRST(value) (DAC_CTRLA_SWRST_Msk & (_UINT8_(value) << DAC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the DAC_CTRLA register */ +#define DAC_CTRLA_ENABLE_Pos _UINT8_(1) /* (DAC_CTRLA) Enable DAC Controller Position */ +#define DAC_CTRLA_ENABLE_Msk (_UINT8_(0x1) << DAC_CTRLA_ENABLE_Pos) /* (DAC_CTRLA) Enable DAC Controller Mask */ +#define DAC_CTRLA_ENABLE(value) (DAC_CTRLA_ENABLE_Msk & (_UINT8_(value) << DAC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the DAC_CTRLA register */ +#define DAC_CTRLA_Msk _UINT8_(0x03) /* (DAC_CTRLA) Register Mask */ + + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#define DAC_CTRLB_RESETVALUE _UINT8_(0x02) /* (DAC_CTRLB) Control B Reset Value */ + +#define DAC_CTRLB_DIFF_Pos _UINT8_(0) /* (DAC_CTRLB) Differential mode enable Position */ +#define DAC_CTRLB_DIFF_Msk (_UINT8_(0x1) << DAC_CTRLB_DIFF_Pos) /* (DAC_CTRLB) Differential mode enable Mask */ +#define DAC_CTRLB_DIFF(value) (DAC_CTRLB_DIFF_Msk & (_UINT8_(value) << DAC_CTRLB_DIFF_Pos)) /* Assigment of value for DIFF in the DAC_CTRLB register */ +#define DAC_CTRLB_REFSEL_Pos _UINT8_(1) /* (DAC_CTRLB) Reference Selection for DAC0/1 Position */ +#define DAC_CTRLB_REFSEL_Msk (_UINT8_(0x3) << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Reference Selection for DAC0/1 Mask */ +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & (_UINT8_(value) << DAC_CTRLB_REFSEL_Pos)) /* Assigment of value for REFSEL in the DAC_CTRLB register */ +#define DAC_CTRLB_REFSEL_VREFPU_Val _UINT8_(0x0) /* (DAC_CTRLB) External reference unbuffered */ +#define DAC_CTRLB_REFSEL_VDDANA_Val _UINT8_(0x1) /* (DAC_CTRLB) Analog supply */ +#define DAC_CTRLB_REFSEL_VREFPB_Val _UINT8_(0x2) /* (DAC_CTRLB) External reference buffered */ +#define DAC_CTRLB_REFSEL_INTREF_Val _UINT8_(0x3) /* (DAC_CTRLB) Internal bandgap reference */ +#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) External reference unbuffered Position */ +#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Analog supply Position */ +#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) External reference buffered Position */ +#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) /* (DAC_CTRLB) Internal bandgap reference Position */ +#define DAC_CTRLB_Msk _UINT8_(0x07) /* (DAC_CTRLB) Register Mask */ + + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#define DAC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_EVCTRL) Event Control Reset Value */ + +#define DAC_EVCTRL_STARTEI0_Pos _UINT8_(0) /* (DAC_EVCTRL) Start Conversion Event Input DAC 0 Position */ +#define DAC_EVCTRL_STARTEI0_Msk (_UINT8_(0x1) << DAC_EVCTRL_STARTEI0_Pos) /* (DAC_EVCTRL) Start Conversion Event Input DAC 0 Mask */ +#define DAC_EVCTRL_STARTEI0(value) (DAC_EVCTRL_STARTEI0_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI0_Pos)) /* Assigment of value for STARTEI0 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_STARTEI1_Pos _UINT8_(1) /* (DAC_EVCTRL) Start Conversion Event Input DAC 1 Position */ +#define DAC_EVCTRL_STARTEI1_Msk (_UINT8_(0x1) << DAC_EVCTRL_STARTEI1_Pos) /* (DAC_EVCTRL) Start Conversion Event Input DAC 1 Mask */ +#define DAC_EVCTRL_STARTEI1(value) (DAC_EVCTRL_STARTEI1_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI1_Pos)) /* Assigment of value for STARTEI1 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_EMPTYEO0_Pos _UINT8_(2) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Position */ +#define DAC_EVCTRL_EMPTYEO0_Msk (_UINT8_(0x1) << DAC_EVCTRL_EMPTYEO0_Pos) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Mask */ +#define DAC_EVCTRL_EMPTYEO0(value) (DAC_EVCTRL_EMPTYEO0_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO0_Pos)) /* Assigment of value for EMPTYEO0 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_EMPTYEO1_Pos _UINT8_(3) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Position */ +#define DAC_EVCTRL_EMPTYEO1_Msk (_UINT8_(0x1) << DAC_EVCTRL_EMPTYEO1_Pos) /* (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Mask */ +#define DAC_EVCTRL_EMPTYEO1(value) (DAC_EVCTRL_EMPTYEO1_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO1_Pos)) /* Assigment of value for EMPTYEO1 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_INVEI0_Pos _UINT8_(4) /* (DAC_EVCTRL) Enable Invertion of DAC 0 input event Position */ +#define DAC_EVCTRL_INVEI0_Msk (_UINT8_(0x1) << DAC_EVCTRL_INVEI0_Pos) /* (DAC_EVCTRL) Enable Invertion of DAC 0 input event Mask */ +#define DAC_EVCTRL_INVEI0(value) (DAC_EVCTRL_INVEI0_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI0_Pos)) /* Assigment of value for INVEI0 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_INVEI1_Pos _UINT8_(5) /* (DAC_EVCTRL) Enable Invertion of DAC 1 input event Position */ +#define DAC_EVCTRL_INVEI1_Msk (_UINT8_(0x1) << DAC_EVCTRL_INVEI1_Pos) /* (DAC_EVCTRL) Enable Invertion of DAC 1 input event Mask */ +#define DAC_EVCTRL_INVEI1(value) (DAC_EVCTRL_INVEI1_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI1_Pos)) /* Assigment of value for INVEI1 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_RESRDYEO0_Pos _UINT8_(6) /* (DAC_EVCTRL) Result Ready Event Output 0 Position */ +#define DAC_EVCTRL_RESRDYEO0_Msk (_UINT8_(0x1) << DAC_EVCTRL_RESRDYEO0_Pos) /* (DAC_EVCTRL) Result Ready Event Output 0 Mask */ +#define DAC_EVCTRL_RESRDYEO0(value) (DAC_EVCTRL_RESRDYEO0_Msk & (_UINT8_(value) << DAC_EVCTRL_RESRDYEO0_Pos)) /* Assigment of value for RESRDYEO0 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_RESRDYEO1_Pos _UINT8_(7) /* (DAC_EVCTRL) Result Ready Event Output 1 Position */ +#define DAC_EVCTRL_RESRDYEO1_Msk (_UINT8_(0x1) << DAC_EVCTRL_RESRDYEO1_Pos) /* (DAC_EVCTRL) Result Ready Event Output 1 Mask */ +#define DAC_EVCTRL_RESRDYEO1(value) (DAC_EVCTRL_RESRDYEO1_Msk & (_UINT8_(value) << DAC_EVCTRL_RESRDYEO1_Pos)) /* Assigment of value for RESRDYEO1 in the DAC_EVCTRL register */ +#define DAC_EVCTRL_Msk _UINT8_(0xFF) /* (DAC_EVCTRL) Register Mask */ + +#define DAC_EVCTRL_STARTEI_Pos _UINT8_(0) /* (DAC_EVCTRL Position) Start Conversion Event Input DAC x */ +#define DAC_EVCTRL_STARTEI_Msk (_UINT8_(0x3) << DAC_EVCTRL_STARTEI_Pos) /* (DAC_EVCTRL Mask) STARTEI */ +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & (_UINT8_(value) << DAC_EVCTRL_STARTEI_Pos)) +#define DAC_EVCTRL_EMPTYEO_Pos _UINT8_(2) /* (DAC_EVCTRL Position) Data Buffer Empty Event Output DAC x */ +#define DAC_EVCTRL_EMPTYEO_Msk (_UINT8_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) /* (DAC_EVCTRL Mask) EMPTYEO */ +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & (_UINT8_(value) << DAC_EVCTRL_EMPTYEO_Pos)) +#define DAC_EVCTRL_INVEI_Pos _UINT8_(4) /* (DAC_EVCTRL Position) Enable Invertion of DAC x input event */ +#define DAC_EVCTRL_INVEI_Msk (_UINT8_(0x3) << DAC_EVCTRL_INVEI_Pos) /* (DAC_EVCTRL Mask) INVEI */ +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & (_UINT8_(value) << DAC_EVCTRL_INVEI_Pos)) +#define DAC_EVCTRL_RESRDYEO_Pos _UINT8_(6) /* (DAC_EVCTRL Position) Result Ready Event Output x */ +#define DAC_EVCTRL_RESRDYEO_Msk (_UINT8_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) /* (DAC_EVCTRL Mask) RESRDYEO */ +#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & (_UINT8_(value) << DAC_EVCTRL_RESRDYEO_Pos)) + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#define DAC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (DAC_INTENCLR) Interrupt Enable Clear Reset Value */ + +#define DAC_INTENCLR_UNDERRUN0_Pos _UINT8_(0) /* (DAC_INTENCLR) Underrun 0 Interrupt Enable Position */ +#define DAC_INTENCLR_UNDERRUN0_Msk (_UINT8_(0x1) << DAC_INTENCLR_UNDERRUN0_Pos) /* (DAC_INTENCLR) Underrun 0 Interrupt Enable Mask */ +#define DAC_INTENCLR_UNDERRUN0(value) (DAC_INTENCLR_UNDERRUN0_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN0_Pos)) /* Assigment of value for UNDERRUN0 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_UNDERRUN1_Pos _UINT8_(1) /* (DAC_INTENCLR) Underrun 1 Interrupt Enable Position */ +#define DAC_INTENCLR_UNDERRUN1_Msk (_UINT8_(0x1) << DAC_INTENCLR_UNDERRUN1_Pos) /* (DAC_INTENCLR) Underrun 1 Interrupt Enable Mask */ +#define DAC_INTENCLR_UNDERRUN1(value) (DAC_INTENCLR_UNDERRUN1_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN1_Pos)) /* Assigment of value for UNDERRUN1 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_EMPTY0_Pos _UINT8_(2) /* (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Position */ +#define DAC_INTENCLR_EMPTY0_Msk (_UINT8_(0x1) << DAC_INTENCLR_EMPTY0_Pos) /* (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Mask */ +#define DAC_INTENCLR_EMPTY0(value) (DAC_INTENCLR_EMPTY0_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY0_Pos)) /* Assigment of value for EMPTY0 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_EMPTY1_Pos _UINT8_(3) /* (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Position */ +#define DAC_INTENCLR_EMPTY1_Msk (_UINT8_(0x1) << DAC_INTENCLR_EMPTY1_Pos) /* (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Mask */ +#define DAC_INTENCLR_EMPTY1(value) (DAC_INTENCLR_EMPTY1_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY1_Pos)) /* Assigment of value for EMPTY1 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_RESRDY0_Pos _UINT8_(4) /* (DAC_INTENCLR) Result 0 Ready Interrupt Enable Position */ +#define DAC_INTENCLR_RESRDY0_Msk (_UINT8_(0x1) << DAC_INTENCLR_RESRDY0_Pos) /* (DAC_INTENCLR) Result 0 Ready Interrupt Enable Mask */ +#define DAC_INTENCLR_RESRDY0(value) (DAC_INTENCLR_RESRDY0_Msk & (_UINT8_(value) << DAC_INTENCLR_RESRDY0_Pos)) /* Assigment of value for RESRDY0 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_RESRDY1_Pos _UINT8_(5) /* (DAC_INTENCLR) Result 1 Ready Interrupt Enable Position */ +#define DAC_INTENCLR_RESRDY1_Msk (_UINT8_(0x1) << DAC_INTENCLR_RESRDY1_Pos) /* (DAC_INTENCLR) Result 1 Ready Interrupt Enable Mask */ +#define DAC_INTENCLR_RESRDY1(value) (DAC_INTENCLR_RESRDY1_Msk & (_UINT8_(value) << DAC_INTENCLR_RESRDY1_Pos)) /* Assigment of value for RESRDY1 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_OVERRUN0_Pos _UINT8_(6) /* (DAC_INTENCLR) Overrun 0 Interrupt Enable Position */ +#define DAC_INTENCLR_OVERRUN0_Msk (_UINT8_(0x1) << DAC_INTENCLR_OVERRUN0_Pos) /* (DAC_INTENCLR) Overrun 0 Interrupt Enable Mask */ +#define DAC_INTENCLR_OVERRUN0(value) (DAC_INTENCLR_OVERRUN0_Msk & (_UINT8_(value) << DAC_INTENCLR_OVERRUN0_Pos)) /* Assigment of value for OVERRUN0 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_OVERRUN1_Pos _UINT8_(7) /* (DAC_INTENCLR) Overrun 1 Interrupt Enable Position */ +#define DAC_INTENCLR_OVERRUN1_Msk (_UINT8_(0x1) << DAC_INTENCLR_OVERRUN1_Pos) /* (DAC_INTENCLR) Overrun 1 Interrupt Enable Mask */ +#define DAC_INTENCLR_OVERRUN1(value) (DAC_INTENCLR_OVERRUN1_Msk & (_UINT8_(value) << DAC_INTENCLR_OVERRUN1_Pos)) /* Assigment of value for OVERRUN1 in the DAC_INTENCLR register */ +#define DAC_INTENCLR_Msk _UINT8_(0xFF) /* (DAC_INTENCLR) Register Mask */ + +#define DAC_INTENCLR_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENCLR Position) Underrun x Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN_Msk (_UINT8_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) /* (DAC_INTENCLR Mask) UNDERRUN */ +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENCLR_UNDERRUN_Pos)) +#define DAC_INTENCLR_EMPTY_Pos _UINT8_(2) /* (DAC_INTENCLR Position) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY_Msk (_UINT8_(0x3) << DAC_INTENCLR_EMPTY_Pos) /* (DAC_INTENCLR Mask) EMPTY */ +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & (_UINT8_(value) << DAC_INTENCLR_EMPTY_Pos)) +#define DAC_INTENCLR_RESRDY_Pos _UINT8_(4) /* (DAC_INTENCLR Position) Result x Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY_Msk (_UINT8_(0x3) << DAC_INTENCLR_RESRDY_Pos) /* (DAC_INTENCLR Mask) RESRDY */ +#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & (_UINT8_(value) << DAC_INTENCLR_RESRDY_Pos)) +#define DAC_INTENCLR_OVERRUN_Pos _UINT8_(6) /* (DAC_INTENCLR Position) Overrun x Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN_Msk (_UINT8_(0x3) << DAC_INTENCLR_OVERRUN_Pos) /* (DAC_INTENCLR Mask) OVERRUN */ +#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & (_UINT8_(value) << DAC_INTENCLR_OVERRUN_Pos)) + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#define DAC_INTENSET_RESETVALUE _UINT8_(0x00) /* (DAC_INTENSET) Interrupt Enable Set Reset Value */ + +#define DAC_INTENSET_UNDERRUN0_Pos _UINT8_(0) /* (DAC_INTENSET) Underrun 0 Interrupt Enable Position */ +#define DAC_INTENSET_UNDERRUN0_Msk (_UINT8_(0x1) << DAC_INTENSET_UNDERRUN0_Pos) /* (DAC_INTENSET) Underrun 0 Interrupt Enable Mask */ +#define DAC_INTENSET_UNDERRUN0(value) (DAC_INTENSET_UNDERRUN0_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN0_Pos)) /* Assigment of value for UNDERRUN0 in the DAC_INTENSET register */ +#define DAC_INTENSET_UNDERRUN1_Pos _UINT8_(1) /* (DAC_INTENSET) Underrun 1 Interrupt Enable Position */ +#define DAC_INTENSET_UNDERRUN1_Msk (_UINT8_(0x1) << DAC_INTENSET_UNDERRUN1_Pos) /* (DAC_INTENSET) Underrun 1 Interrupt Enable Mask */ +#define DAC_INTENSET_UNDERRUN1(value) (DAC_INTENSET_UNDERRUN1_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN1_Pos)) /* Assigment of value for UNDERRUN1 in the DAC_INTENSET register */ +#define DAC_INTENSET_EMPTY0_Pos _UINT8_(2) /* (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Position */ +#define DAC_INTENSET_EMPTY0_Msk (_UINT8_(0x1) << DAC_INTENSET_EMPTY0_Pos) /* (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Mask */ +#define DAC_INTENSET_EMPTY0(value) (DAC_INTENSET_EMPTY0_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY0_Pos)) /* Assigment of value for EMPTY0 in the DAC_INTENSET register */ +#define DAC_INTENSET_EMPTY1_Pos _UINT8_(3) /* (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Position */ +#define DAC_INTENSET_EMPTY1_Msk (_UINT8_(0x1) << DAC_INTENSET_EMPTY1_Pos) /* (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Mask */ +#define DAC_INTENSET_EMPTY1(value) (DAC_INTENSET_EMPTY1_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY1_Pos)) /* Assigment of value for EMPTY1 in the DAC_INTENSET register */ +#define DAC_INTENSET_RESRDY0_Pos _UINT8_(4) /* (DAC_INTENSET) Result 0 Ready Interrupt Enable Position */ +#define DAC_INTENSET_RESRDY0_Msk (_UINT8_(0x1) << DAC_INTENSET_RESRDY0_Pos) /* (DAC_INTENSET) Result 0 Ready Interrupt Enable Mask */ +#define DAC_INTENSET_RESRDY0(value) (DAC_INTENSET_RESRDY0_Msk & (_UINT8_(value) << DAC_INTENSET_RESRDY0_Pos)) /* Assigment of value for RESRDY0 in the DAC_INTENSET register */ +#define DAC_INTENSET_RESRDY1_Pos _UINT8_(5) /* (DAC_INTENSET) Result 1 Ready Interrupt Enable Position */ +#define DAC_INTENSET_RESRDY1_Msk (_UINT8_(0x1) << DAC_INTENSET_RESRDY1_Pos) /* (DAC_INTENSET) Result 1 Ready Interrupt Enable Mask */ +#define DAC_INTENSET_RESRDY1(value) (DAC_INTENSET_RESRDY1_Msk & (_UINT8_(value) << DAC_INTENSET_RESRDY1_Pos)) /* Assigment of value for RESRDY1 in the DAC_INTENSET register */ +#define DAC_INTENSET_OVERRUN0_Pos _UINT8_(6) /* (DAC_INTENSET) Overrun 0 Interrupt Enable Position */ +#define DAC_INTENSET_OVERRUN0_Msk (_UINT8_(0x1) << DAC_INTENSET_OVERRUN0_Pos) /* (DAC_INTENSET) Overrun 0 Interrupt Enable Mask */ +#define DAC_INTENSET_OVERRUN0(value) (DAC_INTENSET_OVERRUN0_Msk & (_UINT8_(value) << DAC_INTENSET_OVERRUN0_Pos)) /* Assigment of value for OVERRUN0 in the DAC_INTENSET register */ +#define DAC_INTENSET_OVERRUN1_Pos _UINT8_(7) /* (DAC_INTENSET) Overrun 1 Interrupt Enable Position */ +#define DAC_INTENSET_OVERRUN1_Msk (_UINT8_(0x1) << DAC_INTENSET_OVERRUN1_Pos) /* (DAC_INTENSET) Overrun 1 Interrupt Enable Mask */ +#define DAC_INTENSET_OVERRUN1(value) (DAC_INTENSET_OVERRUN1_Msk & (_UINT8_(value) << DAC_INTENSET_OVERRUN1_Pos)) /* Assigment of value for OVERRUN1 in the DAC_INTENSET register */ +#define DAC_INTENSET_Msk _UINT8_(0xFF) /* (DAC_INTENSET) Register Mask */ + +#define DAC_INTENSET_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTENSET Position) Underrun x Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN_Msk (_UINT8_(0x3) << DAC_INTENSET_UNDERRUN_Pos) /* (DAC_INTENSET Mask) UNDERRUN */ +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTENSET_UNDERRUN_Pos)) +#define DAC_INTENSET_EMPTY_Pos _UINT8_(2) /* (DAC_INTENSET Position) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY_Msk (_UINT8_(0x3) << DAC_INTENSET_EMPTY_Pos) /* (DAC_INTENSET Mask) EMPTY */ +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & (_UINT8_(value) << DAC_INTENSET_EMPTY_Pos)) +#define DAC_INTENSET_RESRDY_Pos _UINT8_(4) /* (DAC_INTENSET Position) Result x Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY_Msk (_UINT8_(0x3) << DAC_INTENSET_RESRDY_Pos) /* (DAC_INTENSET Mask) RESRDY */ +#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & (_UINT8_(value) << DAC_INTENSET_RESRDY_Pos)) +#define DAC_INTENSET_OVERRUN_Pos _UINT8_(6) /* (DAC_INTENSET Position) Overrun x Interrupt Enable */ +#define DAC_INTENSET_OVERRUN_Msk (_UINT8_(0x3) << DAC_INTENSET_OVERRUN_Pos) /* (DAC_INTENSET Mask) OVERRUN */ +#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & (_UINT8_(value) << DAC_INTENSET_OVERRUN_Pos)) + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#define DAC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ + +#define DAC_INTFLAG_UNDERRUN0_Pos _UINT8_(0) /* (DAC_INTFLAG) Result 0 Underrun Position */ +#define DAC_INTFLAG_UNDERRUN0_Msk (_UINT8_(0x1) << DAC_INTFLAG_UNDERRUN0_Pos) /* (DAC_INTFLAG) Result 0 Underrun Mask */ +#define DAC_INTFLAG_UNDERRUN0(value) (DAC_INTFLAG_UNDERRUN0_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN0_Pos)) /* Assigment of value for UNDERRUN0 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_UNDERRUN1_Pos _UINT8_(1) /* (DAC_INTFLAG) Result 1 Underrun Position */ +#define DAC_INTFLAG_UNDERRUN1_Msk (_UINT8_(0x1) << DAC_INTFLAG_UNDERRUN1_Pos) /* (DAC_INTFLAG) Result 1 Underrun Mask */ +#define DAC_INTFLAG_UNDERRUN1(value) (DAC_INTFLAG_UNDERRUN1_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN1_Pos)) /* Assigment of value for UNDERRUN1 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_EMPTY0_Pos _UINT8_(2) /* (DAC_INTFLAG) Data Buffer 0 Empty Position */ +#define DAC_INTFLAG_EMPTY0_Msk (_UINT8_(0x1) << DAC_INTFLAG_EMPTY0_Pos) /* (DAC_INTFLAG) Data Buffer 0 Empty Mask */ +#define DAC_INTFLAG_EMPTY0(value) (DAC_INTFLAG_EMPTY0_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY0_Pos)) /* Assigment of value for EMPTY0 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_EMPTY1_Pos _UINT8_(3) /* (DAC_INTFLAG) Data Buffer 1 Empty Position */ +#define DAC_INTFLAG_EMPTY1_Msk (_UINT8_(0x1) << DAC_INTFLAG_EMPTY1_Pos) /* (DAC_INTFLAG) Data Buffer 1 Empty Mask */ +#define DAC_INTFLAG_EMPTY1(value) (DAC_INTFLAG_EMPTY1_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY1_Pos)) /* Assigment of value for EMPTY1 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_RESRDY0_Pos _UINT8_(4) /* (DAC_INTFLAG) Result 0 Ready Position */ +#define DAC_INTFLAG_RESRDY0_Msk (_UINT8_(0x1) << DAC_INTFLAG_RESRDY0_Pos) /* (DAC_INTFLAG) Result 0 Ready Mask */ +#define DAC_INTFLAG_RESRDY0(value) (DAC_INTFLAG_RESRDY0_Msk & (_UINT8_(value) << DAC_INTFLAG_RESRDY0_Pos)) /* Assigment of value for RESRDY0 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_RESRDY1_Pos _UINT8_(5) /* (DAC_INTFLAG) Result 1 Ready Position */ +#define DAC_INTFLAG_RESRDY1_Msk (_UINT8_(0x1) << DAC_INTFLAG_RESRDY1_Pos) /* (DAC_INTFLAG) Result 1 Ready Mask */ +#define DAC_INTFLAG_RESRDY1(value) (DAC_INTFLAG_RESRDY1_Msk & (_UINT8_(value) << DAC_INTFLAG_RESRDY1_Pos)) /* Assigment of value for RESRDY1 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_OVERRUN0_Pos _UINT8_(6) /* (DAC_INTFLAG) Result 0 Overrun Position */ +#define DAC_INTFLAG_OVERRUN0_Msk (_UINT8_(0x1) << DAC_INTFLAG_OVERRUN0_Pos) /* (DAC_INTFLAG) Result 0 Overrun Mask */ +#define DAC_INTFLAG_OVERRUN0(value) (DAC_INTFLAG_OVERRUN0_Msk & (_UINT8_(value) << DAC_INTFLAG_OVERRUN0_Pos)) /* Assigment of value for OVERRUN0 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_OVERRUN1_Pos _UINT8_(7) /* (DAC_INTFLAG) Result 1 Overrun Position */ +#define DAC_INTFLAG_OVERRUN1_Msk (_UINT8_(0x1) << DAC_INTFLAG_OVERRUN1_Pos) /* (DAC_INTFLAG) Result 1 Overrun Mask */ +#define DAC_INTFLAG_OVERRUN1(value) (DAC_INTFLAG_OVERRUN1_Msk & (_UINT8_(value) << DAC_INTFLAG_OVERRUN1_Pos)) /* Assigment of value for OVERRUN1 in the DAC_INTFLAG register */ +#define DAC_INTFLAG_Msk _UINT8_(0xFF) /* (DAC_INTFLAG) Register Mask */ + +#define DAC_INTFLAG_UNDERRUN_Pos _UINT8_(0) /* (DAC_INTFLAG Position) Result x Underrun */ +#define DAC_INTFLAG_UNDERRUN_Msk (_UINT8_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) /* (DAC_INTFLAG Mask) UNDERRUN */ +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & (_UINT8_(value) << DAC_INTFLAG_UNDERRUN_Pos)) +#define DAC_INTFLAG_EMPTY_Pos _UINT8_(2) /* (DAC_INTFLAG Position) Data Buffer x Empty */ +#define DAC_INTFLAG_EMPTY_Msk (_UINT8_(0x3) << DAC_INTFLAG_EMPTY_Pos) /* (DAC_INTFLAG Mask) EMPTY */ +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & (_UINT8_(value) << DAC_INTFLAG_EMPTY_Pos)) +#define DAC_INTFLAG_RESRDY_Pos _UINT8_(4) /* (DAC_INTFLAG Position) Result x Ready */ +#define DAC_INTFLAG_RESRDY_Msk (_UINT8_(0x3) << DAC_INTFLAG_RESRDY_Pos) /* (DAC_INTFLAG Mask) RESRDY */ +#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & (_UINT8_(value) << DAC_INTFLAG_RESRDY_Pos)) +#define DAC_INTFLAG_OVERRUN_Pos _UINT8_(6) /* (DAC_INTFLAG Position) Result x Overrun */ +#define DAC_INTFLAG_OVERRUN_Msk (_UINT8_(0x3) << DAC_INTFLAG_OVERRUN_Pos) /* (DAC_INTFLAG Mask) OVERRUN */ +#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & (_UINT8_(value) << DAC_INTFLAG_OVERRUN_Pos)) + +/* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */ +#define DAC_STATUS_RESETVALUE _UINT8_(0x00) /* (DAC_STATUS) Status Reset Value */ + +#define DAC_STATUS_READY0_Pos _UINT8_(0) /* (DAC_STATUS) DAC 0 Startup Ready Position */ +#define DAC_STATUS_READY0_Msk (_UINT8_(0x1) << DAC_STATUS_READY0_Pos) /* (DAC_STATUS) DAC 0 Startup Ready Mask */ +#define DAC_STATUS_READY0(value) (DAC_STATUS_READY0_Msk & (_UINT8_(value) << DAC_STATUS_READY0_Pos)) /* Assigment of value for READY0 in the DAC_STATUS register */ +#define DAC_STATUS_READY1_Pos _UINT8_(1) /* (DAC_STATUS) DAC 1 Startup Ready Position */ +#define DAC_STATUS_READY1_Msk (_UINT8_(0x1) << DAC_STATUS_READY1_Pos) /* (DAC_STATUS) DAC 1 Startup Ready Mask */ +#define DAC_STATUS_READY1(value) (DAC_STATUS_READY1_Msk & (_UINT8_(value) << DAC_STATUS_READY1_Pos)) /* Assigment of value for READY1 in the DAC_STATUS register */ +#define DAC_STATUS_EOC0_Pos _UINT8_(2) /* (DAC_STATUS) DAC 0 End of Conversion Position */ +#define DAC_STATUS_EOC0_Msk (_UINT8_(0x1) << DAC_STATUS_EOC0_Pos) /* (DAC_STATUS) DAC 0 End of Conversion Mask */ +#define DAC_STATUS_EOC0(value) (DAC_STATUS_EOC0_Msk & (_UINT8_(value) << DAC_STATUS_EOC0_Pos)) /* Assigment of value for EOC0 in the DAC_STATUS register */ +#define DAC_STATUS_EOC1_Pos _UINT8_(3) /* (DAC_STATUS) DAC 1 End of Conversion Position */ +#define DAC_STATUS_EOC1_Msk (_UINT8_(0x1) << DAC_STATUS_EOC1_Pos) /* (DAC_STATUS) DAC 1 End of Conversion Mask */ +#define DAC_STATUS_EOC1(value) (DAC_STATUS_EOC1_Msk & (_UINT8_(value) << DAC_STATUS_EOC1_Pos)) /* Assigment of value for EOC1 in the DAC_STATUS register */ +#define DAC_STATUS_Msk _UINT8_(0x0F) /* (DAC_STATUS) Register Mask */ + +#define DAC_STATUS_READY_Pos _UINT8_(0) /* (DAC_STATUS Position) DAC x Startup Ready */ +#define DAC_STATUS_READY_Msk (_UINT8_(0x3) << DAC_STATUS_READY_Pos) /* (DAC_STATUS Mask) READY */ +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & (_UINT8_(value) << DAC_STATUS_READY_Pos)) +#define DAC_STATUS_EOC_Pos _UINT8_(2) /* (DAC_STATUS Position) DAC x End of Conversion */ +#define DAC_STATUS_EOC_Msk (_UINT8_(0x3) << DAC_STATUS_EOC_Pos) /* (DAC_STATUS Mask) EOC */ +#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & (_UINT8_(value) << DAC_STATUS_EOC_Pos)) + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) ( R/ 32) Synchronization Busy -------- */ +#define DAC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (DAC_SYNCBUSY) Synchronization Busy Reset Value */ + +#define DAC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (DAC_SYNCBUSY) Software Reset Position */ +#define DAC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_SWRST_Pos) /* (DAC_SYNCBUSY) Software Reset Mask */ +#define DAC_SYNCBUSY_SWRST(value) (DAC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << DAC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (DAC_SYNCBUSY) DAC Enable Status Position */ +#define DAC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) /* (DAC_SYNCBUSY) DAC Enable Status Mask */ +#define DAC_SYNCBUSY_ENABLE(value) (DAC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << DAC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATA0_Pos _UINT32_(2) /* (DAC_SYNCBUSY) Data DAC 0 Position */ +#define DAC_SYNCBUSY_DATA0_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATA0_Pos) /* (DAC_SYNCBUSY) Data DAC 0 Mask */ +#define DAC_SYNCBUSY_DATA0(value) (DAC_SYNCBUSY_DATA0_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA0_Pos)) /* Assigment of value for DATA0 in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATA1_Pos _UINT32_(3) /* (DAC_SYNCBUSY) Data DAC 1 Position */ +#define DAC_SYNCBUSY_DATA1_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATA1_Pos) /* (DAC_SYNCBUSY) Data DAC 1 Mask */ +#define DAC_SYNCBUSY_DATA1(value) (DAC_SYNCBUSY_DATA1_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA1_Pos)) /* Assigment of value for DATA1 in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATABUF0_Pos _UINT32_(4) /* (DAC_SYNCBUSY) Data Buffer DAC 0 Position */ +#define DAC_SYNCBUSY_DATABUF0_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATABUF0_Pos) /* (DAC_SYNCBUSY) Data Buffer DAC 0 Mask */ +#define DAC_SYNCBUSY_DATABUF0(value) (DAC_SYNCBUSY_DATABUF0_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF0_Pos)) /* Assigment of value for DATABUF0 in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_DATABUF1_Pos _UINT32_(5) /* (DAC_SYNCBUSY) Data Buffer DAC 1 Position */ +#define DAC_SYNCBUSY_DATABUF1_Msk (_UINT32_(0x1) << DAC_SYNCBUSY_DATABUF1_Pos) /* (DAC_SYNCBUSY) Data Buffer DAC 1 Mask */ +#define DAC_SYNCBUSY_DATABUF1(value) (DAC_SYNCBUSY_DATABUF1_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF1_Pos)) /* Assigment of value for DATABUF1 in the DAC_SYNCBUSY register */ +#define DAC_SYNCBUSY_Msk _UINT32_(0x0000003F) /* (DAC_SYNCBUSY) Register Mask */ + +#define DAC_SYNCBUSY_DATA_Pos _UINT32_(2) /* (DAC_SYNCBUSY Position) Data DAC x */ +#define DAC_SYNCBUSY_DATA_Msk (_UINT32_(0x3) << DAC_SYNCBUSY_DATA_Pos) /* (DAC_SYNCBUSY Mask) DATA */ +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATA_Pos)) +#define DAC_SYNCBUSY_DATABUF_Pos _UINT32_(4) /* (DAC_SYNCBUSY Position) Data Buffer DAC x */ +#define DAC_SYNCBUSY_DATABUF_Msk (_UINT32_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) /* (DAC_SYNCBUSY Mask) DATABUF */ +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & (_UINT32_(value) << DAC_SYNCBUSY_DATABUF_Pos)) + +/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ +#define DAC_DACCTRL_RESETVALUE _UINT16_(0x00) /* (DAC_DACCTRL) DAC n Control Reset Value */ + +#define DAC_DACCTRL_LEFTADJ_Pos _UINT16_(0) /* (DAC_DACCTRL) Left Adjusted Data Position */ +#define DAC_DACCTRL_LEFTADJ_Msk (_UINT16_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) /* (DAC_DACCTRL) Left Adjusted Data Mask */ +#define DAC_DACCTRL_LEFTADJ(value) (DAC_DACCTRL_LEFTADJ_Msk & (_UINT16_(value) << DAC_DACCTRL_LEFTADJ_Pos)) /* Assigment of value for LEFTADJ in the DAC_DACCTRL register */ +#define DAC_DACCTRL_ENABLE_Pos _UINT16_(1) /* (DAC_DACCTRL) Enable DAC0 Position */ +#define DAC_DACCTRL_ENABLE_Msk (_UINT16_(0x1) << DAC_DACCTRL_ENABLE_Pos) /* (DAC_DACCTRL) Enable DAC0 Mask */ +#define DAC_DACCTRL_ENABLE(value) (DAC_DACCTRL_ENABLE_Msk & (_UINT16_(value) << DAC_DACCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the DAC_DACCTRL register */ +#define DAC_DACCTRL_CCTRL_Pos _UINT16_(2) /* (DAC_DACCTRL) Current Control Position */ +#define DAC_DACCTRL_CCTRL_Msk (_UINT16_(0x3) << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) Current Control Mask */ +#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & (_UINT16_(value) << DAC_DACCTRL_CCTRL_Pos)) /* Assigment of value for CCTRL in the DAC_DACCTRL register */ +#define DAC_DACCTRL_CCTRL_CC100K_Val _UINT16_(0x0) /* (DAC_DACCTRL) 100kSPS */ +#define DAC_DACCTRL_CCTRL_CC1M_Val _UINT16_(0x1) /* (DAC_DACCTRL) 500kSPS */ +#define DAC_DACCTRL_CCTRL_CC12M_Val _UINT16_(0x2) /* (DAC_DACCTRL) 1MSPS */ +#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) 100kSPS Position */ +#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) 500kSPS Position */ +#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) /* (DAC_DACCTRL) 1MSPS Position */ +#define DAC_DACCTRL_FEXT_Pos _UINT16_(5) /* (DAC_DACCTRL) Standalone Filter Position */ +#define DAC_DACCTRL_FEXT_Msk (_UINT16_(0x1) << DAC_DACCTRL_FEXT_Pos) /* (DAC_DACCTRL) Standalone Filter Mask */ +#define DAC_DACCTRL_FEXT(value) (DAC_DACCTRL_FEXT_Msk & (_UINT16_(value) << DAC_DACCTRL_FEXT_Pos)) /* Assigment of value for FEXT in the DAC_DACCTRL register */ +#define DAC_DACCTRL_RUNSTDBY_Pos _UINT16_(6) /* (DAC_DACCTRL) Run in Standby Position */ +#define DAC_DACCTRL_RUNSTDBY_Msk (_UINT16_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) /* (DAC_DACCTRL) Run in Standby Mask */ +#define DAC_DACCTRL_RUNSTDBY(value) (DAC_DACCTRL_RUNSTDBY_Msk & (_UINT16_(value) << DAC_DACCTRL_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the DAC_DACCTRL register */ +#define DAC_DACCTRL_DITHER_Pos _UINT16_(7) /* (DAC_DACCTRL) Dithering Mode Position */ +#define DAC_DACCTRL_DITHER_Msk (_UINT16_(0x1) << DAC_DACCTRL_DITHER_Pos) /* (DAC_DACCTRL) Dithering Mode Mask */ +#define DAC_DACCTRL_DITHER(value) (DAC_DACCTRL_DITHER_Msk & (_UINT16_(value) << DAC_DACCTRL_DITHER_Pos)) /* Assigment of value for DITHER in the DAC_DACCTRL register */ +#define DAC_DACCTRL_REFRESH_Pos _UINT16_(8) /* (DAC_DACCTRL) Refresh period Position */ +#define DAC_DACCTRL_REFRESH_Msk (_UINT16_(0xF) << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh period Mask */ +#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & (_UINT16_(value) << DAC_DACCTRL_REFRESH_Pos)) /* Assigment of value for REFRESH in the DAC_DACCTRL register */ +#define DAC_DACCTRL_REFRESH_REFRESH_0_Val _UINT16_(0x0) /* (DAC_DACCTRL) Do not Refresh */ +#define DAC_DACCTRL_REFRESH_REFRESH_1_Val _UINT16_(0x1) /* (DAC_DACCTRL) Refresh every 30 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_2_Val _UINT16_(0x2) /* (DAC_DACCTRL) Refresh every 60 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_3_Val _UINT16_(0x3) /* (DAC_DACCTRL) Refresh every 90 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_4_Val _UINT16_(0x4) /* (DAC_DACCTRL) Refresh every 120 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_5_Val _UINT16_(0x5) /* (DAC_DACCTRL) Refresh every 150 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_6_Val _UINT16_(0x6) /* (DAC_DACCTRL) Refresh every 180 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_7_Val _UINT16_(0x7) /* (DAC_DACCTRL) Refresh every 210 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_8_Val _UINT16_(0x8) /* (DAC_DACCTRL) Refresh every 240 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_9_Val _UINT16_(0x9) /* (DAC_DACCTRL) Refresh every 270 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_10_Val _UINT16_(0xA) /* (DAC_DACCTRL) Refresh every 300 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_11_Val _UINT16_(0xB) /* (DAC_DACCTRL) Refresh every 330 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_12_Val _UINT16_(0xC) /* (DAC_DACCTRL) Refresh every 360 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_13_Val _UINT16_(0xD) /* (DAC_DACCTRL) Refresh every 390 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_14_Val _UINT16_(0xE) /* (DAC_DACCTRL) Refresh every 420 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_15_Val _UINT16_(0xF) /* (DAC_DACCTRL) Refresh every 450 us */ +#define DAC_DACCTRL_REFRESH_REFRESH_0 (DAC_DACCTRL_REFRESH_REFRESH_0_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Do not Refresh Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_1 (DAC_DACCTRL_REFRESH_REFRESH_1_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 30 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_2 (DAC_DACCTRL_REFRESH_REFRESH_2_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 60 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_3 (DAC_DACCTRL_REFRESH_REFRESH_3_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 90 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_4 (DAC_DACCTRL_REFRESH_REFRESH_4_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 120 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_5 (DAC_DACCTRL_REFRESH_REFRESH_5_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 150 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_6 (DAC_DACCTRL_REFRESH_REFRESH_6_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 180 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_7 (DAC_DACCTRL_REFRESH_REFRESH_7_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 210 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_8 (DAC_DACCTRL_REFRESH_REFRESH_8_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 240 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_9 (DAC_DACCTRL_REFRESH_REFRESH_9_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 270 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_10 (DAC_DACCTRL_REFRESH_REFRESH_10_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 300 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_11 (DAC_DACCTRL_REFRESH_REFRESH_11_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 330 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_12 (DAC_DACCTRL_REFRESH_REFRESH_12_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 360 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_13 (DAC_DACCTRL_REFRESH_REFRESH_13_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 390 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_14 (DAC_DACCTRL_REFRESH_REFRESH_14_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 420 us Position */ +#define DAC_DACCTRL_REFRESH_REFRESH_15 (DAC_DACCTRL_REFRESH_REFRESH_15_Val << DAC_DACCTRL_REFRESH_Pos) /* (DAC_DACCTRL) Refresh every 450 us Position */ +#define DAC_DACCTRL_OSR_Pos _UINT16_(13) /* (DAC_DACCTRL) Sampling Rate Position */ +#define DAC_DACCTRL_OSR_Msk (_UINT16_(0x7) << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) Sampling Rate Mask */ +#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & (_UINT16_(value) << DAC_DACCTRL_OSR_Pos)) /* Assigment of value for OSR in the DAC_DACCTRL register */ +#define DAC_DACCTRL_OSR_OSR_1_Val _UINT16_(0x0) /* (DAC_DACCTRL) No Over Sampling */ +#define DAC_DACCTRL_OSR_OSR_2_Val _UINT16_(0x1) /* (DAC_DACCTRL) 2x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_4_Val _UINT16_(0x2) /* (DAC_DACCTRL) 4x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_8_Val _UINT16_(0x3) /* (DAC_DACCTRL) 8x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_16_Val _UINT16_(0x4) /* (DAC_DACCTRL) 16x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_32_Val _UINT16_(0x5) /* (DAC_DACCTRL) 32x Over Sampling Ratio */ +#define DAC_DACCTRL_OSR_OSR_1 (DAC_DACCTRL_OSR_OSR_1_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) No Over Sampling Position */ +#define DAC_DACCTRL_OSR_OSR_2 (DAC_DACCTRL_OSR_OSR_2_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) 2x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_4 (DAC_DACCTRL_OSR_OSR_4_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) 4x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_8 (DAC_DACCTRL_OSR_OSR_8_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) 8x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_16 (DAC_DACCTRL_OSR_OSR_16_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) 16x Over Sampling Ratio Position */ +#define DAC_DACCTRL_OSR_OSR_32 (DAC_DACCTRL_OSR_OSR_32_Val << DAC_DACCTRL_OSR_Pos) /* (DAC_DACCTRL) 32x Over Sampling Ratio Position */ +#define DAC_DACCTRL_Msk _UINT16_(0xEFEF) /* (DAC_DACCTRL) Register Mask */ + + +/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ +#define DAC_DATA_RESETVALUE _UINT16_(0x00) /* (DAC_DATA) DAC n Data Reset Value */ + +#define DAC_DATA_DATA_Pos _UINT16_(0) /* (DAC_DATA) DAC0 Data Position */ +#define DAC_DATA_DATA_Msk (_UINT16_(0xFFFF) << DAC_DATA_DATA_Pos) /* (DAC_DATA) DAC0 Data Mask */ +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & (_UINT16_(value) << DAC_DATA_DATA_Pos)) /* Assigment of value for DATA in the DAC_DATA register */ +#define DAC_DATA_Msk _UINT16_(0xFFFF) /* (DAC_DATA) Register Mask */ + + +/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ +#define DAC_DATABUF_RESETVALUE _UINT16_(0x00) /* (DAC_DATABUF) DAC n Data Buffer Reset Value */ + +#define DAC_DATABUF_DATABUF_Pos _UINT16_(0) /* (DAC_DATABUF) DAC0 Data Buffer Position */ +#define DAC_DATABUF_DATABUF_Msk (_UINT16_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) /* (DAC_DATABUF) DAC0 Data Buffer Mask */ +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & (_UINT16_(value) << DAC_DATABUF_DATABUF_Pos)) /* Assigment of value for DATABUF in the DAC_DATABUF register */ +#define DAC_DATABUF_Msk _UINT16_(0xFFFF) /* (DAC_DATABUF) Register Mask */ + + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ +#define DAC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (DAC_DBGCTRL) Debug Control Reset Value */ + +#define DAC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (DAC_DBGCTRL) Debug Run Position */ +#define DAC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) /* (DAC_DBGCTRL) Debug Run Mask */ +#define DAC_DBGCTRL_DBGRUN(value) (DAC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << DAC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the DAC_DBGCTRL register */ +#define DAC_DBGCTRL_Msk _UINT8_(0x01) /* (DAC_DBGCTRL) Register Mask */ + + +/* -------- DAC_RESULT : (DAC Offset: 0x1C) ( R/ 16) Filter Result -------- */ +#define DAC_RESULT_RESETVALUE _UINT16_(0x00) /* (DAC_RESULT) Filter Result Reset Value */ + +#define DAC_RESULT_RESULT_Pos _UINT16_(0) /* (DAC_RESULT) Filter Result Position */ +#define DAC_RESULT_RESULT_Msk (_UINT16_(0xFFFF) << DAC_RESULT_RESULT_Pos) /* (DAC_RESULT) Filter Result Mask */ +#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & (_UINT16_(value) << DAC_RESULT_RESULT_Pos)) /* Assigment of value for RESULT in the DAC_RESULT register */ +#define DAC_RESULT_Msk _UINT16_(0xFFFF) /* (DAC_RESULT) Register Mask */ + + +/** \brief DAC register offsets definitions */ +#define DAC_CTRLA_REG_OFST _UINT32_(0x00) /* (DAC_CTRLA) Control A Offset */ +#define DAC_CTRLB_REG_OFST _UINT32_(0x01) /* (DAC_CTRLB) Control B Offset */ +#define DAC_EVCTRL_REG_OFST _UINT32_(0x02) /* (DAC_EVCTRL) Event Control Offset */ +#define DAC_INTENCLR_REG_OFST _UINT32_(0x04) /* (DAC_INTENCLR) Interrupt Enable Clear Offset */ +#define DAC_INTENSET_REG_OFST _UINT32_(0x05) /* (DAC_INTENSET) Interrupt Enable Set Offset */ +#define DAC_INTFLAG_REG_OFST _UINT32_(0x06) /* (DAC_INTFLAG) Interrupt Flag Status and Clear Offset */ +#define DAC_STATUS_REG_OFST _UINT32_(0x07) /* (DAC_STATUS) Status Offset */ +#define DAC_SYNCBUSY_REG_OFST _UINT32_(0x08) /* (DAC_SYNCBUSY) Synchronization Busy Offset */ +#define DAC_DACCTRL_REG_OFST _UINT32_(0x0C) /* (DAC_DACCTRL) DAC n Control Offset */ +#define DAC_DACCTRL0_REG_OFST _UINT32_(0x0C) /* (DAC_DACCTRL0) DAC n Control Offset */ +#define DAC_DACCTRL1_REG_OFST _UINT32_(0x0E) /* (DAC_DACCTRL1) DAC n Control Offset */ +#define DAC_DATA_REG_OFST _UINT32_(0x10) /* (DAC_DATA) DAC n Data Offset */ +#define DAC_DATA0_REG_OFST _UINT32_(0x10) /* (DAC_DATA0) DAC n Data Offset */ +#define DAC_DATA1_REG_OFST _UINT32_(0x12) /* (DAC_DATA1) DAC n Data Offset */ +#define DAC_DATABUF_REG_OFST _UINT32_(0x14) /* (DAC_DATABUF) DAC n Data Buffer Offset */ +#define DAC_DATABUF0_REG_OFST _UINT32_(0x14) /* (DAC_DATABUF0) DAC n Data Buffer Offset */ +#define DAC_DATABUF1_REG_OFST _UINT32_(0x16) /* (DAC_DATABUF1) DAC n Data Buffer Offset */ +#define DAC_DBGCTRL_REG_OFST _UINT32_(0x18) /* (DAC_DBGCTRL) Debug Control Offset */ +#define DAC_RESULT_REG_OFST _UINT32_(0x1C) /* (DAC_RESULT) Filter Result Offset */ +#define DAC_RESULT0_REG_OFST _UINT32_(0x1C) /* (DAC_RESULT0) Filter Result Offset */ +#define DAC_RESULT1_REG_OFST _UINT32_(0x1E) /* (DAC_RESULT1) Filter Result Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DAC register API structure */ +typedef struct +{ /* Digital-to-Analog Converter */ + __IO uint8_t DAC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ + __IO uint8_t DAC_CTRLB; /**< Offset: 0x01 (R/W 8) Control B */ + __IO uint8_t DAC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ + __I uint8_t Reserved1[0x01]; + __IO uint8_t DAC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO uint8_t DAC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO uint8_t DAC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I uint8_t DAC_STATUS; /**< Offset: 0x07 (R/ 8) Status */ + __I uint32_t DAC_SYNCBUSY; /**< Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO uint16_t DAC_DACCTRL[2]; /**< Offset: 0x0C (R/W 16) DAC n Control */ + __O uint16_t DAC_DATA[2]; /**< Offset: 0x10 ( /W 16) DAC n Data */ + __O uint16_t DAC_DATABUF[2]; /**< Offset: 0x14 ( /W 16) DAC n Data Buffer */ + __IO uint8_t DAC_DBGCTRL; /**< Offset: 0x18 (R/W 8) Debug Control */ + __I uint8_t Reserved2[0x03]; + __I uint16_t DAC_RESULT[2]; /**< Offset: 0x1C (R/ 16) Filter Result */ +} dac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME54_DAC_COMPONENT_H_ */ diff --git a/os/common/ext/Microchip/SAME54/component/dmac.h b/os/common/ext/Microchip/SAME54/component/dmac.h new file mode 100644 index 0000000000..d045444412 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/component/dmac.h @@ -0,0 +1,1186 @@ +/* + * Component description for DMAC + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:08Z */ +#ifndef _SAME54_DMAC_COMPONENT_H_ +#define _SAME54_DMAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DMAC */ +/* ************************************************************************** */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#define DMAC_BTCTRL_RESETVALUE _UINT16_(0x00) /* (DMAC_BTCTRL) Block Transfer Control Reset Value */ + +#define DMAC_BTCTRL_VALID_Pos _UINT16_(0) /* (DMAC_BTCTRL) Descriptor Valid Position */ +#define DMAC_BTCTRL_VALID_Msk (_UINT16_(0x1) << DMAC_BTCTRL_VALID_Pos) /* (DMAC_BTCTRL) Descriptor Valid Mask */ +#define DMAC_BTCTRL_VALID(value) (DMAC_BTCTRL_VALID_Msk & (_UINT16_(value) << DMAC_BTCTRL_VALID_Pos)) /* Assigment of value for VALID in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_EVOSEL_Pos _UINT16_(1) /* (DMAC_BTCTRL) Block Event Output Selection Position */ +#define DMAC_BTCTRL_EVOSEL_Msk (_UINT16_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Block Event Output Selection Mask */ +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_EVOSEL_Pos)) /* Assigment of value for EVOSEL in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Block event strobe */ +#define DMAC_BTCTRL_EVOSEL_BURST_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Burst event strobe */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Event generation disabled Position */ +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Block event strobe Position */ +#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) /* (DMAC_BTCTRL) Burst event strobe Position */ +#define DMAC_BTCTRL_BLOCKACT_Pos _UINT16_(3) /* (DMAC_BTCTRL) Block Action Position */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Block Action Mask */ +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & (_UINT16_(value) << DMAC_BTCTRL_BLOCKACT_Pos)) /* Assigment of value for BLOCKACT in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _UINT16_(0x2) /* (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _UINT16_(0x3) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction Position */ +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt Position */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Channel suspend operation is completed Position */ +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) /* (DMAC_BTCTRL) Both channel suspend operation and block interrupt Position */ +#define DMAC_BTCTRL_BEATSIZE_Pos _UINT16_(8) /* (DMAC_BTCTRL) Beat Size Position */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_UINT16_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) Beat Size Mask */ +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_BEATSIZE_Pos)) /* Assigment of value for BEATSIZE in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _UINT16_(0x0) /* (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _UINT16_(0x1) /* (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _UINT16_(0x2) /* (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 8-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 16-bit bus transfer Position */ +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /* (DMAC_BTCTRL) 32-bit bus transfer Position */ +#define DMAC_BTCTRL_SRCINC_Pos _UINT16_(10) /* (DMAC_BTCTRL) Source Address Increment Enable Position */ +#define DMAC_BTCTRL_SRCINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_SRCINC_Pos) /* (DMAC_BTCTRL) Source Address Increment Enable Mask */ +#define DMAC_BTCTRL_SRCINC(value) (DMAC_BTCTRL_SRCINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_SRCINC_Pos)) /* Assigment of value for SRCINC in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_DSTINC_Pos _UINT16_(11) /* (DMAC_BTCTRL) Destination Address Increment Enable Position */ +#define DMAC_BTCTRL_DSTINC_Msk (_UINT16_(0x1) << DMAC_BTCTRL_DSTINC_Pos) /* (DMAC_BTCTRL) Destination Address Increment Enable Mask */ +#define DMAC_BTCTRL_DSTINC(value) (DMAC_BTCTRL_DSTINC_Msk & (_UINT16_(value) << DMAC_BTCTRL_DSTINC_Pos)) /* Assigment of value for DSTINC in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSEL_Pos _UINT16_(12) /* (DMAC_BTCTRL) Step Selection Position */ +#define DMAC_BTCTRL_STEPSEL_Msk (_UINT16_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step Selection Mask */ +#define DMAC_BTCTRL_STEPSEL(value) (DMAC_BTCTRL_STEPSEL_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSEL_Pos)) /* Assigment of value for STEPSEL in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSEL_DST_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _UINT16_(0x1) /* (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the destination address Position */ +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) /* (DMAC_BTCTRL) Step size settings apply to the source address Position */ +#define DMAC_BTCTRL_STEPSIZE_Pos _UINT16_(13) /* (DMAC_BTCTRL) Address Increment Step Size Position */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_UINT16_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) /* (DMAC_BTCTRL) Address Increment Step Size Mask */ +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & (_UINT16_(value) << DMAC_BTCTRL_STEPSIZE_Pos)) /* Assigment of value for STEPSIZE in the DMAC_BTCTRL register */ +#define DMAC_BTCTRL_STEPSIZE_X1_Val _UINT16_(0x0) /* (DMAC_BTCTRL) Next ADDR = ADDR + (1< 8 bits, 1 -> 16 bits */ +#define USB_EPNUM (8) /* parameter for rtl : max of ENDPOINT and PIPE NUM */ +#define USB_EPT_NUM (8) /* Number of USB end points */ +#define USB_GCLK_ID (10) /* Index of Generic Clock */ +#define USB_INITIAL_CONTROL_QOS (3) /* CONTROL QOS RESET value */ +#define USB_INITIAL_DATA_QOS (3) /* DATA QOS RESET value */ +#define USB_INSTANCE_ID (32) /* Instance index for USB */ +#define USB_MISSING_SOF_DET_IMPLEMENTED (1) /* 48 mHz xPLL feature implemented */ +#define USB_PIPE_NUM (8) /* Number of USB pipes */ +#define USB_SYSTEM_CLOCK_IS_CKUSB (0) /* Dual (1'b0) or Single (1'b1) clock system */ +#define USB_2_AHB_FIFO_DEPTH (4) /* bytes number, should be at least 2, and 2^n (4,8,16 ...) */ +#define USB_2_AHB_RD_DATA_BITS (16) /* 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode */ +#define USB_2_AHB_RD_THRESHOLD (2) /* as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested */ +#define USB_2_AHB_WR_DATA_BITS (8) /* 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode */ + +#endif /* _SAME54_USB_INSTANCE_ */ diff --git a/os/common/ext/Microchip/SAME54/instance/wdt.h b/os/common/ext/Microchip/SAME54/instance/wdt.h new file mode 100644 index 0000000000..a9fdd5bfca --- /dev/null +++ b/os/common/ext/Microchip/SAME54/instance/wdt.h @@ -0,0 +1,28 @@ +/* + * Instance header file for ATSAME54P20A + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:08Z */ +#ifndef _SAME54_WDT_INSTANCE_ +#define _SAME54_WDT_INSTANCE_ + + +/* ========== Instance Parameter definitions for WDT peripheral ========== */ +#define WDT_INSTANCE_ID (8) /* Instance index for WDT */ + +#endif /* _SAME54_WDT_INSTANCE_ */ diff --git a/os/common/ext/Microchip/SAME54/pio/same54n19a.h b/os/common/ext/Microchip/SAME54/pio/same54n19a.h new file mode 100644 index 0000000000..5fd448555f --- /dev/null +++ b/os/common/ext/Microchip/SAME54/pio/same54n19a.h @@ -0,0 +1,3262 @@ +/* + * Peripheral I/O description for SAME54N19A + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:05Z */ +#ifndef _SAME54N19A_GPIO_H_ +#define _SAME54N19A_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA00 ( 0) /**< Pin Number for PA00 */ +#define PIN_PA01 ( 1) /**< Pin Number for PA01 */ +#define PIN_PA02 ( 2) /**< Pin Number for PA02 */ +#define PIN_PA03 ( 3) /**< Pin Number for PA03 */ +#define PIN_PA04 ( 4) /**< Pin Number for PA04 */ +#define PIN_PA05 ( 5) /**< Pin Number for PA05 */ +#define PIN_PA06 ( 6) /**< Pin Number for PA06 */ +#define PIN_PA07 ( 7) /**< Pin Number for PA07 */ +#define PIN_PA08 ( 8) /**< Pin Number for PA08 */ +#define PIN_PA09 ( 9) /**< Pin Number for PA09 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB00 ( 32) /**< Pin Number for PB00 */ +#define PIN_PB01 ( 33) /**< Pin Number for PB01 */ +#define PIN_PB02 ( 34) /**< Pin Number for PB02 */ +#define PIN_PB03 ( 35) /**< Pin Number for PB03 */ +#define PIN_PB04 ( 36) /**< Pin Number for PB04 */ +#define PIN_PB05 ( 37) /**< Pin Number for PB05 */ +#define PIN_PB06 ( 38) /**< Pin Number for PB06 */ +#define PIN_PB07 ( 39) /**< Pin Number for PB07 */ +#define PIN_PB08 ( 40) /**< Pin Number for PB08 */ +#define PIN_PB09 ( 41) /**< Pin Number for PB09 */ +#define PIN_PB10 ( 42) /**< Pin Number for PB10 */ +#define PIN_PB11 ( 43) /**< Pin Number for PB11 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PB14 ( 46) /**< Pin Number for PB14 */ +#define PIN_PB15 ( 47) /**< Pin Number for PB15 */ +#define PIN_PB16 ( 48) /**< Pin Number for PB16 */ +#define PIN_PB17 ( 49) /**< Pin Number for PB17 */ +#define PIN_PB18 ( 50) /**< Pin Number for PB18 */ +#define PIN_PB19 ( 51) /**< Pin Number for PB19 */ +#define PIN_PB20 ( 52) /**< Pin Number for PB20 */ +#define PIN_PB21 ( 53) /**< Pin Number for PB21 */ +#define PIN_PB22 ( 54) /**< Pin Number for PB22 */ +#define PIN_PB23 ( 55) /**< Pin Number for PB23 */ +#define PIN_PB24 ( 56) /**< Pin Number for PB24 */ +#define PIN_PB25 ( 57) /**< Pin Number for PB25 */ +#define PIN_PB30 ( 62) /**< Pin Number for PB30 */ +#define PIN_PB31 ( 63) /**< Pin Number for PB31 */ +#define PIN_PC00 ( 64) /**< Pin Number for PC00 */ +#define PIN_PC01 ( 65) /**< Pin Number for PC01 */ +#define PIN_PC02 ( 66) /**< Pin Number for PC02 */ +#define PIN_PC03 ( 67) /**< Pin Number for PC03 */ +#define PIN_PC05 ( 69) /**< Pin Number for PC05 */ +#define PIN_PC06 ( 70) /**< Pin Number for PC06 */ +#define PIN_PC07 ( 71) /**< Pin Number for PC07 */ +#define PIN_PC10 ( 74) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85) /**< Pin Number for PC21 */ +#define PIN_PC24 ( 88) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92) /**< Pin Number for PC28 */ + +/* ========== Peripheral I/O masks ========== */ +#define PORT_PA00 (_UINT32_(1) << 0) /**< PORT mask for PA00 */ +#define PORT_PA01 (_UINT32_(1) << 1) /**< PORT mask for PA01 */ +#define PORT_PA02 (_UINT32_(1) << 2) /**< PORT mask for PA02 */ +#define PORT_PA03 (_UINT32_(1) << 3) /**< PORT mask for PA03 */ +#define PORT_PA04 (_UINT32_(1) << 4) /**< PORT mask for PA04 */ +#define PORT_PA05 (_UINT32_(1) << 5) /**< PORT mask for PA05 */ +#define PORT_PA06 (_UINT32_(1) << 6) /**< PORT mask for PA06 */ +#define PORT_PA07 (_UINT32_(1) << 7) /**< PORT mask for PA07 */ +#define PORT_PA08 (_UINT32_(1) << 8) /**< PORT mask for PA08 */ +#define PORT_PA09 (_UINT32_(1) << 9) /**< PORT mask for PA09 */ +#define PORT_PA10 (_UINT32_(1) << 10) /**< PORT mask for PA10 */ +#define PORT_PA11 (_UINT32_(1) << 11) /**< PORT mask for PA11 */ +#define PORT_PA12 (_UINT32_(1) << 12) /**< PORT mask for PA12 */ +#define PORT_PA13 (_UINT32_(1) << 13) /**< PORT mask for PA13 */ +#define PORT_PA14 (_UINT32_(1) << 14) /**< PORT mask for PA14 */ +#define PORT_PA15 (_UINT32_(1) << 15) /**< PORT mask for PA15 */ +#define PORT_PA16 (_UINT32_(1) << 16) /**< PORT mask for PA16 */ +#define PORT_PA17 (_UINT32_(1) << 17) /**< PORT mask for PA17 */ +#define PORT_PA18 (_UINT32_(1) << 18) /**< PORT mask for PA18 */ +#define PORT_PA19 (_UINT32_(1) << 19) /**< PORT mask for PA19 */ +#define PORT_PA20 (_UINT32_(1) << 20) /**< PORT mask for PA20 */ +#define PORT_PA21 (_UINT32_(1) << 21) /**< PORT mask for PA21 */ +#define PORT_PA22 (_UINT32_(1) << 22) /**< PORT mask for PA22 */ +#define PORT_PA23 (_UINT32_(1) << 23) /**< PORT mask for PA23 */ +#define PORT_PA24 (_UINT32_(1) << 24) /**< PORT mask for PA24 */ +#define PORT_PA25 (_UINT32_(1) << 25) /**< PORT mask for PA25 */ +#define PORT_PA27 (_UINT32_(1) << 27) /**< PORT mask for PA27 */ +#define PORT_PA30 (_UINT32_(1) << 30) /**< PORT mask for PA30 */ +#define PORT_PA31 (_UINT32_(1) << 31) /**< PORT mask for PA31 */ +#define PORT_PB00 (_UINT32_(1) << 0) /**< PORT mask for PB00 */ +#define PORT_PB01 (_UINT32_(1) << 1) /**< PORT mask for PB01 */ +#define PORT_PB02 (_UINT32_(1) << 2) /**< PORT mask for PB02 */ +#define PORT_PB03 (_UINT32_(1) << 3) /**< PORT mask for PB03 */ +#define PORT_PB04 (_UINT32_(1) << 4) /**< PORT mask for PB04 */ +#define PORT_PB05 (_UINT32_(1) << 5) /**< PORT mask for PB05 */ +#define PORT_PB06 (_UINT32_(1) << 6) /**< PORT mask for PB06 */ +#define PORT_PB07 (_UINT32_(1) << 7) /**< PORT mask for PB07 */ +#define PORT_PB08 (_UINT32_(1) << 8) /**< PORT mask for PB08 */ +#define PORT_PB09 (_UINT32_(1) << 9) /**< PORT mask for PB09 */ +#define PORT_PB10 (_UINT32_(1) << 10) /**< PORT mask for PB10 */ +#define PORT_PB11 (_UINT32_(1) << 11) /**< PORT mask for PB11 */ +#define PORT_PB12 (_UINT32_(1) << 12) /**< PORT mask for PB12 */ +#define PORT_PB13 (_UINT32_(1) << 13) /**< PORT mask for PB13 */ +#define PORT_PB14 (_UINT32_(1) << 14) /**< PORT mask for PB14 */ +#define PORT_PB15 (_UINT32_(1) << 15) /**< PORT mask for PB15 */ +#define PORT_PB16 (_UINT32_(1) << 16) /**< PORT mask for PB16 */ +#define PORT_PB17 (_UINT32_(1) << 17) /**< PORT mask for PB17 */ +#define PORT_PB18 (_UINT32_(1) << 18) /**< PORT mask for PB18 */ +#define PORT_PB19 (_UINT32_(1) << 19) /**< PORT mask for PB19 */ +#define PORT_PB20 (_UINT32_(1) << 20) /**< PORT mask for PB20 */ +#define PORT_PB21 (_UINT32_(1) << 21) /**< PORT mask for PB21 */ +#define PORT_PB22 (_UINT32_(1) << 22) /**< PORT mask for PB22 */ +#define PORT_PB23 (_UINT32_(1) << 23) /**< PORT mask for PB23 */ +#define PORT_PB24 (_UINT32_(1) << 24) /**< PORT mask for PB24 */ +#define PORT_PB25 (_UINT32_(1) << 25) /**< PORT mask for PB25 */ +#define PORT_PB30 (_UINT32_(1) << 30) /**< PORT mask for PB30 */ +#define PORT_PB31 (_UINT32_(1) << 31) /**< PORT mask for PB31 */ +#define PORT_PC00 (_UINT32_(1) << 0) /**< PORT mask for PC00 */ +#define PORT_PC01 (_UINT32_(1) << 1) /**< PORT mask for PC01 */ +#define PORT_PC02 (_UINT32_(1) << 2) /**< PORT mask for PC02 */ +#define PORT_PC03 (_UINT32_(1) << 3) /**< PORT mask for PC03 */ +#define PORT_PC05 (_UINT32_(1) << 5) /**< PORT mask for PC05 */ +#define PORT_PC06 (_UINT32_(1) << 6) /**< PORT mask for PC06 */ +#define PORT_PC07 (_UINT32_(1) << 7) /**< PORT mask for PC07 */ +#define PORT_PC10 (_UINT32_(1) << 10) /**< PORT mask for PC10 */ +#define PORT_PC11 (_UINT32_(1) << 11) /**< PORT mask for PC11 */ +#define PORT_PC12 (_UINT32_(1) << 12) /**< PORT mask for PC12 */ +#define PORT_PC13 (_UINT32_(1) << 13) /**< PORT mask for PC13 */ +#define PORT_PC14 (_UINT32_(1) << 14) /**< PORT mask for PC14 */ +#define PORT_PC15 (_UINT32_(1) << 15) /**< PORT mask for PC15 */ +#define PORT_PC16 (_UINT32_(1) << 16) /**< PORT mask for PC16 */ +#define PORT_PC17 (_UINT32_(1) << 17) /**< PORT mask for PC17 */ +#define PORT_PC18 (_UINT32_(1) << 18) /**< PORT mask for PC18 */ +#define PORT_PC19 (_UINT32_(1) << 19) /**< PORT mask for PC19 */ +#define PORT_PC20 (_UINT32_(1) << 20) /**< PORT mask for PC20 */ +#define PORT_PC21 (_UINT32_(1) << 21) /**< PORT mask for PC21 */ +#define PORT_PC24 (_UINT32_(1) << 24) /**< PORT mask for PC24 */ +#define PORT_PC25 (_UINT32_(1) << 25) /**< PORT mask for PC25 */ +#define PORT_PC26 (_UINT32_(1) << 26) /**< PORT mask for PC26 */ +#define PORT_PC27 (_UINT32_(1) << 27) /**< PORT mask for PC27 */ +#define PORT_PC28 (_UINT32_(1) << 28) /**< PORT mask for PC28 */ + +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _UINT32_(4) +#define MUX_PA04B_AC_AIN0 _UINT32_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UINT32_(1) << 4) + +#define PIN_PA05B_AC_AIN1 _UINT32_(5) +#define MUX_PA05B_AC_AIN1 _UINT32_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UINT32_(1) << 5) + +#define PIN_PA06B_AC_AIN2 _UINT32_(6) +#define MUX_PA06B_AC_AIN2 _UINT32_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UINT32_(1) << 6) + +#define PIN_PA07B_AC_AIN3 _UINT32_(7) +#define MUX_PA07B_AC_AIN3 _UINT32_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UINT32_(1) << 7) + +#define PIN_PA12M_AC_CMP0 _UINT32_(12) +#define MUX_PA12M_AC_CMP0 _UINT32_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UINT32_(1) << 12) + +#define PIN_PA18M_AC_CMP0 _UINT32_(18) +#define MUX_PA18M_AC_CMP0 _UINT32_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UINT32_(1) << 18) + +#define PIN_PB24M_AC_CMP0 _UINT32_(56) +#define MUX_PB24M_AC_CMP0 _UINT32_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UINT32_(1) << 24) + +#define PIN_PA13M_AC_CMP1 _UINT32_(13) +#define MUX_PA13M_AC_CMP1 _UINT32_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UINT32_(1) << 13) + +#define PIN_PA19M_AC_CMP1 _UINT32_(19) +#define MUX_PA19M_AC_CMP1 _UINT32_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UINT32_(1) << 19) + +#define PIN_PB25M_AC_CMP1 _UINT32_(57) +#define MUX_PB25M_AC_CMP1 _UINT32_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UINT32_(1) << 25) + +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _UINT32_(2) +#define MUX_PA02B_ADC0_AIN0 _UINT32_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UINT32_(1) << 2) + +#define PIN_PA03B_ADC0_AIN1 _UINT32_(3) +#define MUX_PA03B_ADC0_AIN1 _UINT32_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_AIN2 _UINT32_(40) +#define MUX_PB08B_ADC0_AIN2 _UINT32_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_AIN3 _UINT32_(41) +#define MUX_PB09B_ADC0_AIN3 _UINT32_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_AIN4 _UINT32_(4) +#define MUX_PA04B_ADC0_AIN4 _UINT32_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UINT32_(1) << 4) + +#define PIN_PA05B_ADC0_AIN5 _UINT32_(5) +#define MUX_PA05B_ADC0_AIN5 _UINT32_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UINT32_(1) << 5) + +#define PIN_PA06B_ADC0_AIN6 _UINT32_(6) +#define MUX_PA06B_ADC0_AIN6 _UINT32_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_AIN7 _UINT32_(7) +#define MUX_PA07B_ADC0_AIN7 _UINT32_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_AIN8 _UINT32_(8) +#define MUX_PA08B_ADC0_AIN8 _UINT32_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_AIN9 _UINT32_(9) +#define MUX_PA09B_ADC0_AIN9 _UINT32_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_AIN10 _UINT32_(10) +#define MUX_PA10B_ADC0_AIN10 _UINT32_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_AIN11 _UINT32_(11) +#define MUX_PA11B_ADC0_AIN11 _UINT32_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UINT32_(1) << 11) + +#define PIN_PB00B_ADC0_AIN12 _UINT32_(32) +#define MUX_PB00B_ADC0_AIN12 _UINT32_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_AIN13 _UINT32_(33) +#define MUX_PB01B_ADC0_AIN13 _UINT32_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UINT32_(1) << 1) + +#define PIN_PB02B_ADC0_AIN14 _UINT32_(34) +#define MUX_PB02B_ADC0_AIN14 _UINT32_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_AIN15 _UINT32_(35) +#define MUX_PB03B_ADC0_AIN15 _UINT32_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UINT32_(1) << 3) + +#define PIN_PA03B_ADC0_VREFA _UINT32_(3) +#define MUX_PA03B_ADC0_VREFA _UINT32_(1) +#define PINMUX_PA03B_ADC0_VREFA ((PIN_PA03B_ADC0_VREFA << 16) | MUX_PA03B_ADC0_VREFA) +#define PORT_PA03B_ADC0_VREFA (_UINT32_(1) << 3) + +#define PIN_PA04B_ADC0_VREFB _UINT32_(4) +#define MUX_PA04B_ADC0_VREFB _UINT32_(1) +#define PINMUX_PA04B_ADC0_VREFB ((PIN_PA04B_ADC0_VREFB << 16) | MUX_PA04B_ADC0_VREFB) +#define PORT_PA04B_ADC0_VREFB (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_VREFC _UINT32_(6) +#define MUX_PA06B_ADC0_VREFC _UINT32_(1) +#define PINMUX_PA06B_ADC0_VREFC ((PIN_PA06B_ADC0_VREFC << 16) | MUX_PA06B_ADC0_VREFC) +#define PORT_PA06B_ADC0_VREFC (_UINT32_(1) << 6) + +#define PIN_PA03B_ADC0_X0 _UINT32_(3) +#define MUX_PA03B_ADC0_X0 _UINT32_(1) +#define PINMUX_PA03B_ADC0_X0 ((PIN_PA03B_ADC0_X0 << 16) | MUX_PA03B_ADC0_X0) +#define PORT_PA03B_ADC0_X0 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_X1 _UINT32_(40) +#define MUX_PB08B_ADC0_X1 _UINT32_(1) +#define PINMUX_PB08B_ADC0_X1 ((PIN_PB08B_ADC0_X1 << 16) | MUX_PB08B_ADC0_X1) +#define PORT_PB08B_ADC0_X1 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_X2 _UINT32_(41) +#define MUX_PB09B_ADC0_X2 _UINT32_(1) +#define PINMUX_PB09B_ADC0_X2 ((PIN_PB09B_ADC0_X2 << 16) | MUX_PB09B_ADC0_X2) +#define PORT_PB09B_ADC0_X2 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_X3 _UINT32_(4) +#define MUX_PA04B_ADC0_X3 _UINT32_(1) +#define PINMUX_PA04B_ADC0_X3 ((PIN_PA04B_ADC0_X3 << 16) | MUX_PA04B_ADC0_X3) +#define PORT_PA04B_ADC0_X3 (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_X4 _UINT32_(6) +#define MUX_PA06B_ADC0_X4 _UINT32_(1) +#define PINMUX_PA06B_ADC0_X4 ((PIN_PA06B_ADC0_X4 << 16) | MUX_PA06B_ADC0_X4) +#define PORT_PA06B_ADC0_X4 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_X5 _UINT32_(7) +#define MUX_PA07B_ADC0_X5 _UINT32_(1) +#define PINMUX_PA07B_ADC0_X5 ((PIN_PA07B_ADC0_X5 << 16) | MUX_PA07B_ADC0_X5) +#define PORT_PA07B_ADC0_X5 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_X6 _UINT32_(8) +#define MUX_PA08B_ADC0_X6 _UINT32_(1) +#define PINMUX_PA08B_ADC0_X6 ((PIN_PA08B_ADC0_X6 << 16) | MUX_PA08B_ADC0_X6) +#define PORT_PA08B_ADC0_X6 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_X7 _UINT32_(9) +#define MUX_PA09B_ADC0_X7 _UINT32_(1) +#define PINMUX_PA09B_ADC0_X7 ((PIN_PA09B_ADC0_X7 << 16) | MUX_PA09B_ADC0_X7) +#define PORT_PA09B_ADC0_X7 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_X8 _UINT32_(10) +#define MUX_PA10B_ADC0_X8 _UINT32_(1) +#define PINMUX_PA10B_ADC0_X8 ((PIN_PA10B_ADC0_X8 << 16) | MUX_PA10B_ADC0_X8) +#define PORT_PA10B_ADC0_X8 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_X9 _UINT32_(11) +#define MUX_PA11B_ADC0_X9 _UINT32_(1) +#define PINMUX_PA11B_ADC0_X9 ((PIN_PA11B_ADC0_X9 << 16) | MUX_PA11B_ADC0_X9) +#define PORT_PA11B_ADC0_X9 (_UINT32_(1) << 11) + +#define PIN_PA16B_ADC0_X10 _UINT32_(16) +#define MUX_PA16B_ADC0_X10 _UINT32_(1) +#define PINMUX_PA16B_ADC0_X10 ((PIN_PA16B_ADC0_X10 << 16) | MUX_PA16B_ADC0_X10) +#define PORT_PA16B_ADC0_X10 (_UINT32_(1) << 16) + +#define PIN_PA17B_ADC0_X11 _UINT32_(17) +#define MUX_PA17B_ADC0_X11 _UINT32_(1) +#define PINMUX_PA17B_ADC0_X11 ((PIN_PA17B_ADC0_X11 << 16) | MUX_PA17B_ADC0_X11) +#define PORT_PA17B_ADC0_X11 (_UINT32_(1) << 17) + +#define PIN_PA18B_ADC0_X12 _UINT32_(18) +#define MUX_PA18B_ADC0_X12 _UINT32_(1) +#define PINMUX_PA18B_ADC0_X12 ((PIN_PA18B_ADC0_X12 << 16) | MUX_PA18B_ADC0_X12) +#define PORT_PA18B_ADC0_X12 (_UINT32_(1) << 18) + +#define PIN_PA19B_ADC0_X13 _UINT32_(19) +#define MUX_PA19B_ADC0_X13 _UINT32_(1) +#define PINMUX_PA19B_ADC0_X13 ((PIN_PA19B_ADC0_X13 << 16) | MUX_PA19B_ADC0_X13) +#define PORT_PA19B_ADC0_X13 (_UINT32_(1) << 19) + +#define PIN_PA20B_ADC0_X14 _UINT32_(20) +#define MUX_PA20B_ADC0_X14 _UINT32_(1) +#define PINMUX_PA20B_ADC0_X14 ((PIN_PA20B_ADC0_X14 << 16) | MUX_PA20B_ADC0_X14) +#define PORT_PA20B_ADC0_X14 (_UINT32_(1) << 20) + +#define PIN_PA21B_ADC0_X15 _UINT32_(21) +#define MUX_PA21B_ADC0_X15 _UINT32_(1) +#define PINMUX_PA21B_ADC0_X15 ((PIN_PA21B_ADC0_X15 << 16) | MUX_PA21B_ADC0_X15) +#define PORT_PA21B_ADC0_X15 (_UINT32_(1) << 21) + +#define PIN_PA22B_ADC0_X16 _UINT32_(22) +#define MUX_PA22B_ADC0_X16 _UINT32_(1) +#define PINMUX_PA22B_ADC0_X16 ((PIN_PA22B_ADC0_X16 << 16) | MUX_PA22B_ADC0_X16) +#define PORT_PA22B_ADC0_X16 (_UINT32_(1) << 22) + +#define PIN_PA23B_ADC0_X17 _UINT32_(23) +#define MUX_PA23B_ADC0_X17 _UINT32_(1) +#define PINMUX_PA23B_ADC0_X17 ((PIN_PA23B_ADC0_X17 << 16) | MUX_PA23B_ADC0_X17) +#define PORT_PA23B_ADC0_X17 (_UINT32_(1) << 23) + +#define PIN_PA27B_ADC0_X18 _UINT32_(27) +#define MUX_PA27B_ADC0_X18 _UINT32_(1) +#define PINMUX_PA27B_ADC0_X18 ((PIN_PA27B_ADC0_X18 << 16) | MUX_PA27B_ADC0_X18) +#define PORT_PA27B_ADC0_X18 (_UINT32_(1) << 27) + +#define PIN_PA30B_ADC0_X19 _UINT32_(30) +#define MUX_PA30B_ADC0_X19 _UINT32_(1) +#define PINMUX_PA30B_ADC0_X19 ((PIN_PA30B_ADC0_X19 << 16) | MUX_PA30B_ADC0_X19) +#define PORT_PA30B_ADC0_X19 (_UINT32_(1) << 30) + +#define PIN_PB02B_ADC0_X20 _UINT32_(34) +#define MUX_PB02B_ADC0_X20 _UINT32_(1) +#define PINMUX_PB02B_ADC0_X20 ((PIN_PB02B_ADC0_X20 << 16) | MUX_PB02B_ADC0_X20) +#define PORT_PB02B_ADC0_X20 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_X21 _UINT32_(35) +#define MUX_PB03B_ADC0_X21 _UINT32_(1) +#define PINMUX_PB03B_ADC0_X21 ((PIN_PB03B_ADC0_X21 << 16) | MUX_PB03B_ADC0_X21) +#define PORT_PB03B_ADC0_X21 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC0_X22 _UINT32_(36) +#define MUX_PB04B_ADC0_X22 _UINT32_(1) +#define PINMUX_PB04B_ADC0_X22 ((PIN_PB04B_ADC0_X22 << 16) | MUX_PB04B_ADC0_X22) +#define PORT_PB04B_ADC0_X22 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC0_X23 _UINT32_(37) +#define MUX_PB05B_ADC0_X23 _UINT32_(1) +#define PINMUX_PB05B_ADC0_X23 ((PIN_PB05B_ADC0_X23 << 16) | MUX_PB05B_ADC0_X23) +#define PORT_PB05B_ADC0_X23 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC0_X24 _UINT32_(38) +#define MUX_PB06B_ADC0_X24 _UINT32_(1) +#define PINMUX_PB06B_ADC0_X24 ((PIN_PB06B_ADC0_X24 << 16) | MUX_PB06B_ADC0_X24) +#define PORT_PB06B_ADC0_X24 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC0_X25 _UINT32_(39) +#define MUX_PB07B_ADC0_X25 _UINT32_(1) +#define PINMUX_PB07B_ADC0_X25 ((PIN_PB07B_ADC0_X25 << 16) | MUX_PB07B_ADC0_X25) +#define PORT_PB07B_ADC0_X25 (_UINT32_(1) << 7) + +#define PIN_PB12B_ADC0_X26 _UINT32_(44) +#define MUX_PB12B_ADC0_X26 _UINT32_(1) +#define PINMUX_PB12B_ADC0_X26 ((PIN_PB12B_ADC0_X26 << 16) | MUX_PB12B_ADC0_X26) +#define PORT_PB12B_ADC0_X26 (_UINT32_(1) << 12) + +#define PIN_PB13B_ADC0_X27 _UINT32_(45) +#define MUX_PB13B_ADC0_X27 _UINT32_(1) +#define PINMUX_PB13B_ADC0_X27 ((PIN_PB13B_ADC0_X27 << 16) | MUX_PB13B_ADC0_X27) +#define PORT_PB13B_ADC0_X27 (_UINT32_(1) << 13) + +#define PIN_PB14B_ADC0_X28 _UINT32_(46) +#define MUX_PB14B_ADC0_X28 _UINT32_(1) +#define PINMUX_PB14B_ADC0_X28 ((PIN_PB14B_ADC0_X28 << 16) | MUX_PB14B_ADC0_X28) +#define PORT_PB14B_ADC0_X28 (_UINT32_(1) << 14) + +#define PIN_PB15B_ADC0_X29 _UINT32_(47) +#define MUX_PB15B_ADC0_X29 _UINT32_(1) +#define PINMUX_PB15B_ADC0_X29 ((PIN_PB15B_ADC0_X29 << 16) | MUX_PB15B_ADC0_X29) +#define PORT_PB15B_ADC0_X29 (_UINT32_(1) << 15) + +#define PIN_PB00B_ADC0_X30 _UINT32_(32) +#define MUX_PB00B_ADC0_X30 _UINT32_(1) +#define PINMUX_PB00B_ADC0_X30 ((PIN_PB00B_ADC0_X30 << 16) | MUX_PB00B_ADC0_X30) +#define PORT_PB00B_ADC0_X30 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_X31 _UINT32_(33) +#define MUX_PB01B_ADC0_X31 _UINT32_(1) +#define PINMUX_PB01B_ADC0_X31 ((PIN_PB01B_ADC0_X31 << 16) | MUX_PB01B_ADC0_X31) +#define PORT_PB01B_ADC0_X31 (_UINT32_(1) << 1) + +#define PIN_PA03B_ADC0_Y0 _UINT32_(3) +#define MUX_PA03B_ADC0_Y0 _UINT32_(1) +#define PINMUX_PA03B_ADC0_Y0 ((PIN_PA03B_ADC0_Y0 << 16) | MUX_PA03B_ADC0_Y0) +#define PORT_PA03B_ADC0_Y0 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_Y1 _UINT32_(40) +#define MUX_PB08B_ADC0_Y1 _UINT32_(1) +#define PINMUX_PB08B_ADC0_Y1 ((PIN_PB08B_ADC0_Y1 << 16) | MUX_PB08B_ADC0_Y1) +#define PORT_PB08B_ADC0_Y1 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_Y2 _UINT32_(41) +#define MUX_PB09B_ADC0_Y2 _UINT32_(1) +#define PINMUX_PB09B_ADC0_Y2 ((PIN_PB09B_ADC0_Y2 << 16) | MUX_PB09B_ADC0_Y2) +#define PORT_PB09B_ADC0_Y2 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_Y3 _UINT32_(4) +#define MUX_PA04B_ADC0_Y3 _UINT32_(1) +#define PINMUX_PA04B_ADC0_Y3 ((PIN_PA04B_ADC0_Y3 << 16) | MUX_PA04B_ADC0_Y3) +#define PORT_PA04B_ADC0_Y3 (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_Y4 _UINT32_(6) +#define MUX_PA06B_ADC0_Y4 _UINT32_(1) +#define PINMUX_PA06B_ADC0_Y4 ((PIN_PA06B_ADC0_Y4 << 16) | MUX_PA06B_ADC0_Y4) +#define PORT_PA06B_ADC0_Y4 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_Y5 _UINT32_(7) +#define MUX_PA07B_ADC0_Y5 _UINT32_(1) +#define PINMUX_PA07B_ADC0_Y5 ((PIN_PA07B_ADC0_Y5 << 16) | MUX_PA07B_ADC0_Y5) +#define PORT_PA07B_ADC0_Y5 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_Y6 _UINT32_(8) +#define MUX_PA08B_ADC0_Y6 _UINT32_(1) +#define PINMUX_PA08B_ADC0_Y6 ((PIN_PA08B_ADC0_Y6 << 16) | MUX_PA08B_ADC0_Y6) +#define PORT_PA08B_ADC0_Y6 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_Y7 _UINT32_(9) +#define MUX_PA09B_ADC0_Y7 _UINT32_(1) +#define PINMUX_PA09B_ADC0_Y7 ((PIN_PA09B_ADC0_Y7 << 16) | MUX_PA09B_ADC0_Y7) +#define PORT_PA09B_ADC0_Y7 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_Y8 _UINT32_(10) +#define MUX_PA10B_ADC0_Y8 _UINT32_(1) +#define PINMUX_PA10B_ADC0_Y8 ((PIN_PA10B_ADC0_Y8 << 16) | MUX_PA10B_ADC0_Y8) +#define PORT_PA10B_ADC0_Y8 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_Y9 _UINT32_(11) +#define MUX_PA11B_ADC0_Y9 _UINT32_(1) +#define PINMUX_PA11B_ADC0_Y9 ((PIN_PA11B_ADC0_Y9 << 16) | MUX_PA11B_ADC0_Y9) +#define PORT_PA11B_ADC0_Y9 (_UINT32_(1) << 11) + +#define PIN_PA16B_ADC0_Y10 _UINT32_(16) +#define MUX_PA16B_ADC0_Y10 _UINT32_(1) +#define PINMUX_PA16B_ADC0_Y10 ((PIN_PA16B_ADC0_Y10 << 16) | MUX_PA16B_ADC0_Y10) +#define PORT_PA16B_ADC0_Y10 (_UINT32_(1) << 16) + +#define PIN_PA17B_ADC0_Y11 _UINT32_(17) +#define MUX_PA17B_ADC0_Y11 _UINT32_(1) +#define PINMUX_PA17B_ADC0_Y11 ((PIN_PA17B_ADC0_Y11 << 16) | MUX_PA17B_ADC0_Y11) +#define PORT_PA17B_ADC0_Y11 (_UINT32_(1) << 17) + +#define PIN_PA18B_ADC0_Y12 _UINT32_(18) +#define MUX_PA18B_ADC0_Y12 _UINT32_(1) +#define PINMUX_PA18B_ADC0_Y12 ((PIN_PA18B_ADC0_Y12 << 16) | MUX_PA18B_ADC0_Y12) +#define PORT_PA18B_ADC0_Y12 (_UINT32_(1) << 18) + +#define PIN_PA19B_ADC0_Y13 _UINT32_(19) +#define MUX_PA19B_ADC0_Y13 _UINT32_(1) +#define PINMUX_PA19B_ADC0_Y13 ((PIN_PA19B_ADC0_Y13 << 16) | MUX_PA19B_ADC0_Y13) +#define PORT_PA19B_ADC0_Y13 (_UINT32_(1) << 19) + +#define PIN_PA20B_ADC0_Y14 _UINT32_(20) +#define MUX_PA20B_ADC0_Y14 _UINT32_(1) +#define PINMUX_PA20B_ADC0_Y14 ((PIN_PA20B_ADC0_Y14 << 16) | MUX_PA20B_ADC0_Y14) +#define PORT_PA20B_ADC0_Y14 (_UINT32_(1) << 20) + +#define PIN_PA21B_ADC0_Y15 _UINT32_(21) +#define MUX_PA21B_ADC0_Y15 _UINT32_(1) +#define PINMUX_PA21B_ADC0_Y15 ((PIN_PA21B_ADC0_Y15 << 16) | MUX_PA21B_ADC0_Y15) +#define PORT_PA21B_ADC0_Y15 (_UINT32_(1) << 21) + +#define PIN_PA22B_ADC0_Y16 _UINT32_(22) +#define MUX_PA22B_ADC0_Y16 _UINT32_(1) +#define PINMUX_PA22B_ADC0_Y16 ((PIN_PA22B_ADC0_Y16 << 16) | MUX_PA22B_ADC0_Y16) +#define PORT_PA22B_ADC0_Y16 (_UINT32_(1) << 22) + +#define PIN_PA23B_ADC0_Y17 _UINT32_(23) +#define MUX_PA23B_ADC0_Y17 _UINT32_(1) +#define PINMUX_PA23B_ADC0_Y17 ((PIN_PA23B_ADC0_Y17 << 16) | MUX_PA23B_ADC0_Y17) +#define PORT_PA23B_ADC0_Y17 (_UINT32_(1) << 23) + +#define PIN_PA27B_ADC0_Y18 _UINT32_(27) +#define MUX_PA27B_ADC0_Y18 _UINT32_(1) +#define PINMUX_PA27B_ADC0_Y18 ((PIN_PA27B_ADC0_Y18 << 16) | MUX_PA27B_ADC0_Y18) +#define PORT_PA27B_ADC0_Y18 (_UINT32_(1) << 27) + +#define PIN_PA30B_ADC0_Y19 _UINT32_(30) +#define MUX_PA30B_ADC0_Y19 _UINT32_(1) +#define PINMUX_PA30B_ADC0_Y19 ((PIN_PA30B_ADC0_Y19 << 16) | MUX_PA30B_ADC0_Y19) +#define PORT_PA30B_ADC0_Y19 (_UINT32_(1) << 30) + +#define PIN_PB02B_ADC0_Y20 _UINT32_(34) +#define MUX_PB02B_ADC0_Y20 _UINT32_(1) +#define PINMUX_PB02B_ADC0_Y20 ((PIN_PB02B_ADC0_Y20 << 16) | MUX_PB02B_ADC0_Y20) +#define PORT_PB02B_ADC0_Y20 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_Y21 _UINT32_(35) +#define MUX_PB03B_ADC0_Y21 _UINT32_(1) +#define PINMUX_PB03B_ADC0_Y21 ((PIN_PB03B_ADC0_Y21 << 16) | MUX_PB03B_ADC0_Y21) +#define PORT_PB03B_ADC0_Y21 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC0_Y22 _UINT32_(36) +#define MUX_PB04B_ADC0_Y22 _UINT32_(1) +#define PINMUX_PB04B_ADC0_Y22 ((PIN_PB04B_ADC0_Y22 << 16) | MUX_PB04B_ADC0_Y22) +#define PORT_PB04B_ADC0_Y22 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC0_Y23 _UINT32_(37) +#define MUX_PB05B_ADC0_Y23 _UINT32_(1) +#define PINMUX_PB05B_ADC0_Y23 ((PIN_PB05B_ADC0_Y23 << 16) | MUX_PB05B_ADC0_Y23) +#define PORT_PB05B_ADC0_Y23 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC0_Y24 _UINT32_(38) +#define MUX_PB06B_ADC0_Y24 _UINT32_(1) +#define PINMUX_PB06B_ADC0_Y24 ((PIN_PB06B_ADC0_Y24 << 16) | MUX_PB06B_ADC0_Y24) +#define PORT_PB06B_ADC0_Y24 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC0_Y25 _UINT32_(39) +#define MUX_PB07B_ADC0_Y25 _UINT32_(1) +#define PINMUX_PB07B_ADC0_Y25 ((PIN_PB07B_ADC0_Y25 << 16) | MUX_PB07B_ADC0_Y25) +#define PORT_PB07B_ADC0_Y25 (_UINT32_(1) << 7) + +#define PIN_PB12B_ADC0_Y26 _UINT32_(44) +#define MUX_PB12B_ADC0_Y26 _UINT32_(1) +#define PINMUX_PB12B_ADC0_Y26 ((PIN_PB12B_ADC0_Y26 << 16) | MUX_PB12B_ADC0_Y26) +#define PORT_PB12B_ADC0_Y26 (_UINT32_(1) << 12) + +#define PIN_PB13B_ADC0_Y27 _UINT32_(45) +#define MUX_PB13B_ADC0_Y27 _UINT32_(1) +#define PINMUX_PB13B_ADC0_Y27 ((PIN_PB13B_ADC0_Y27 << 16) | MUX_PB13B_ADC0_Y27) +#define PORT_PB13B_ADC0_Y27 (_UINT32_(1) << 13) + +#define PIN_PB14B_ADC0_Y28 _UINT32_(46) +#define MUX_PB14B_ADC0_Y28 _UINT32_(1) +#define PINMUX_PB14B_ADC0_Y28 ((PIN_PB14B_ADC0_Y28 << 16) | MUX_PB14B_ADC0_Y28) +#define PORT_PB14B_ADC0_Y28 (_UINT32_(1) << 14) + +#define PIN_PB15B_ADC0_Y29 _UINT32_(47) +#define MUX_PB15B_ADC0_Y29 _UINT32_(1) +#define PINMUX_PB15B_ADC0_Y29 ((PIN_PB15B_ADC0_Y29 << 16) | MUX_PB15B_ADC0_Y29) +#define PORT_PB15B_ADC0_Y29 (_UINT32_(1) << 15) + +#define PIN_PB00B_ADC0_Y30 _UINT32_(32) +#define MUX_PB00B_ADC0_Y30 _UINT32_(1) +#define PINMUX_PB00B_ADC0_Y30 ((PIN_PB00B_ADC0_Y30 << 16) | MUX_PB00B_ADC0_Y30) +#define PORT_PB00B_ADC0_Y30 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_Y31 _UINT32_(33) +#define MUX_PB01B_ADC0_Y31 _UINT32_(1) +#define PINMUX_PB01B_ADC0_Y31 ((PIN_PB01B_ADC0_Y31 << 16) | MUX_PB01B_ADC0_Y31) +#define PORT_PB01B_ADC0_Y31 (_UINT32_(1) << 1) + +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _UINT32_(40) +#define MUX_PB08B_ADC1_AIN0 _UINT32_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC1_AIN1 _UINT32_(41) +#define MUX_PB09B_ADC1_AIN1 _UINT32_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UINT32_(1) << 9) + +#define PIN_PA08B_ADC1_AIN2 _UINT32_(8) +#define MUX_PA08B_ADC1_AIN2 _UINT32_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC1_AIN3 _UINT32_(9) +#define MUX_PA09B_ADC1_AIN3 _UINT32_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UINT32_(1) << 9) + +#define PIN_PC02B_ADC1_AIN4 _UINT32_(66) +#define MUX_PC02B_ADC1_AIN4 _UINT32_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UINT32_(1) << 2) + +#define PIN_PC03B_ADC1_AIN5 _UINT32_(67) +#define MUX_PC03B_ADC1_AIN5 _UINT32_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC1_AIN6 _UINT32_(36) +#define MUX_PB04B_ADC1_AIN6 _UINT32_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC1_AIN7 _UINT32_(37) +#define MUX_PB05B_ADC1_AIN7 _UINT32_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC1_AIN8 _UINT32_(38) +#define MUX_PB06B_ADC1_AIN8 _UINT32_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC1_AIN9 _UINT32_(39) +#define MUX_PB07B_ADC1_AIN9 _UINT32_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UINT32_(1) << 7) + +#define PIN_PC00B_ADC1_AIN10 _UINT32_(64) +#define MUX_PC00B_ADC1_AIN10 _UINT32_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UINT32_(1) << 0) + +#define PIN_PC01B_ADC1_AIN11 _UINT32_(65) +#define MUX_PC01B_ADC1_AIN11 _UINT32_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UINT32_(1) << 1) + +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _UINT32_(23) +#define MUX_PA23I_CAN0_RX _UINT32_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UINT32_(1) << 23) + +#define PIN_PA25I_CAN0_RX _UINT32_(25) +#define MUX_PA25I_CAN0_RX _UINT32_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UINT32_(1) << 25) + +#define PIN_PA22I_CAN0_TX _UINT32_(22) +#define MUX_PA22I_CAN0_TX _UINT32_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UINT32_(1) << 22) + +#define PIN_PA24I_CAN0_TX _UINT32_(24) +#define MUX_PA24I_CAN0_TX _UINT32_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UINT32_(1) << 24) + +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _UINT32_(45) +#define MUX_PB13H_CAN1_RX _UINT32_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UINT32_(1) << 13) + +#define PIN_PB15H_CAN1_RX _UINT32_(47) +#define MUX_PB15H_CAN1_RX _UINT32_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UINT32_(1) << 15) + +#define PIN_PB12H_CAN1_TX _UINT32_(44) +#define MUX_PB12H_CAN1_TX _UINT32_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UINT32_(1) << 12) + +#define PIN_PB14H_CAN1_TX _UINT32_(46) +#define MUX_PB14H_CAN1_TX _UINT32_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UINT32_(1) << 14) + +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _UINT32_(4) +#define MUX_PA04N_CCL_IN0 _UINT32_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UINT32_(1) << 4) + +#define PIN_PA16N_CCL_IN0 _UINT32_(16) +#define MUX_PA16N_CCL_IN0 _UINT32_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UINT32_(1) << 16) + +#define PIN_PB22N_CCL_IN0 _UINT32_(54) +#define MUX_PB22N_CCL_IN0 _UINT32_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UINT32_(1) << 22) + +#define PIN_PA05N_CCL_IN1 _UINT32_(5) +#define MUX_PA05N_CCL_IN1 _UINT32_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UINT32_(1) << 5) + +#define PIN_PA17N_CCL_IN1 _UINT32_(17) +#define MUX_PA17N_CCL_IN1 _UINT32_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UINT32_(1) << 17) + +#define PIN_PB00N_CCL_IN1 _UINT32_(32) +#define MUX_PB00N_CCL_IN1 _UINT32_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UINT32_(1) << 0) + +#define PIN_PA06N_CCL_IN2 _UINT32_(6) +#define MUX_PA06N_CCL_IN2 _UINT32_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UINT32_(1) << 6) + +#define PIN_PA18N_CCL_IN2 _UINT32_(18) +#define MUX_PA18N_CCL_IN2 _UINT32_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UINT32_(1) << 18) + +#define PIN_PB01N_CCL_IN2 _UINT32_(33) +#define MUX_PB01N_CCL_IN2 _UINT32_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UINT32_(1) << 1) + +#define PIN_PA08N_CCL_IN3 _UINT32_(8) +#define MUX_PA08N_CCL_IN3 _UINT32_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UINT32_(1) << 8) + +#define PIN_PA30N_CCL_IN3 _UINT32_(30) +#define MUX_PA30N_CCL_IN3 _UINT32_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UINT32_(1) << 30) + +#define PIN_PA09N_CCL_IN4 _UINT32_(9) +#define MUX_PA09N_CCL_IN4 _UINT32_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UINT32_(1) << 9) + +#define PIN_PC27N_CCL_IN4 _UINT32_(91) +#define MUX_PC27N_CCL_IN4 _UINT32_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UINT32_(1) << 27) + +#define PIN_PA10N_CCL_IN5 _UINT32_(10) +#define MUX_PA10N_CCL_IN5 _UINT32_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UINT32_(1) << 10) + +#define PIN_PC28N_CCL_IN5 _UINT32_(92) +#define MUX_PC28N_CCL_IN5 _UINT32_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UINT32_(1) << 28) + +#define PIN_PA22N_CCL_IN6 _UINT32_(22) +#define MUX_PA22N_CCL_IN6 _UINT32_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UINT32_(1) << 22) + +#define PIN_PB06N_CCL_IN6 _UINT32_(38) +#define MUX_PB06N_CCL_IN6 _UINT32_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UINT32_(1) << 6) + +#define PIN_PA23N_CCL_IN7 _UINT32_(23) +#define MUX_PA23N_CCL_IN7 _UINT32_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UINT32_(1) << 23) + +#define PIN_PB07N_CCL_IN7 _UINT32_(39) +#define MUX_PB07N_CCL_IN7 _UINT32_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UINT32_(1) << 7) + +#define PIN_PA24N_CCL_IN8 _UINT32_(24) +#define MUX_PA24N_CCL_IN8 _UINT32_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UINT32_(1) << 24) + +#define PIN_PB08N_CCL_IN8 _UINT32_(40) +#define MUX_PB08N_CCL_IN8 _UINT32_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UINT32_(1) << 8) + +#define PIN_PB14N_CCL_IN9 _UINT32_(46) +#define MUX_PB14N_CCL_IN9 _UINT32_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UINT32_(1) << 14) + +#define PIN_PC20N_CCL_IN9 _UINT32_(84) +#define MUX_PC20N_CCL_IN9 _UINT32_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UINT32_(1) << 20) + +#define PIN_PB15N_CCL_IN10 _UINT32_(47) +#define MUX_PB15N_CCL_IN10 _UINT32_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UINT32_(1) << 15) + +#define PIN_PC21N_CCL_IN10 _UINT32_(85) +#define MUX_PC21N_CCL_IN10 _UINT32_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UINT32_(1) << 21) + +#define PIN_PB10N_CCL_IN11 _UINT32_(42) +#define MUX_PB10N_CCL_IN11 _UINT32_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UINT32_(1) << 10) + +#define PIN_PB16N_CCL_IN11 _UINT32_(48) +#define MUX_PB16N_CCL_IN11 _UINT32_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UINT32_(1) << 16) + +#define PIN_PA07N_CCL_OUT0 _UINT32_(7) +#define MUX_PA07N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UINT32_(1) << 7) + +#define PIN_PA19N_CCL_OUT0 _UINT32_(19) +#define MUX_PA19N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UINT32_(1) << 19) + +#define PIN_PB02N_CCL_OUT0 _UINT32_(34) +#define MUX_PB02N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UINT32_(1) << 2) + +#define PIN_PB23N_CCL_OUT0 _UINT32_(55) +#define MUX_PB23N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UINT32_(1) << 23) + +#define PIN_PA11N_CCL_OUT1 _UINT32_(11) +#define MUX_PA11N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UINT32_(1) << 11) + +#define PIN_PA31N_CCL_OUT1 _UINT32_(31) +#define MUX_PA31N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UINT32_(1) << 31) + +#define PIN_PB11N_CCL_OUT1 _UINT32_(43) +#define MUX_PB11N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UINT32_(1) << 11) + +#define PIN_PA25N_CCL_OUT2 _UINT32_(25) +#define MUX_PA25N_CCL_OUT2 _UINT32_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UINT32_(1) << 25) + +#define PIN_PB09N_CCL_OUT2 _UINT32_(41) +#define MUX_PB09N_CCL_OUT2 _UINT32_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UINT32_(1) << 9) + +#define PIN_PB17N_CCL_OUT3 _UINT32_(49) +#define MUX_PB17N_CCL_OUT3 _UINT32_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UINT32_(1) << 17) + +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _UINT32_(2) +#define MUX_PA02B_DAC_VOUT0 _UINT32_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UINT32_(1) << 2) + +#define PIN_PA05B_DAC_VOUT1 _UINT32_(5) +#define MUX_PA05B_DAC_VOUT1 _UINT32_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UINT32_(1) << 5) + +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _UINT32_(0) +#define MUX_PA00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA00 External Interrupt Line */ + +#define PIN_PA16A_EIC_EXTINT0 _UINT32_(16) +#define MUX_PA16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA16 External Interrupt Line */ + +#define PIN_PB00A_EIC_EXTINT0 _UINT32_(32) +#define MUX_PB00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB00 External Interrupt Line */ + +#define PIN_PB16A_EIC_EXTINT0 _UINT32_(48) +#define MUX_PB16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB16 External Interrupt Line */ + +#define PIN_PC00A_EIC_EXTINT0 _UINT32_(64) +#define MUX_PC00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PC00 External Interrupt Line */ + +#define PIN_PC16A_EIC_EXTINT0 _UINT32_(80) +#define MUX_PC16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PC16 External Interrupt Line */ + +#define PIN_PA01A_EIC_EXTINT1 _UINT32_(1) +#define MUX_PA01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA01 External Interrupt Line */ + +#define PIN_PA17A_EIC_EXTINT1 _UINT32_(17) +#define MUX_PA17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA17 External Interrupt Line */ + +#define PIN_PB01A_EIC_EXTINT1 _UINT32_(33) +#define MUX_PB01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB01 External Interrupt Line */ + +#define PIN_PB17A_EIC_EXTINT1 _UINT32_(49) +#define MUX_PB17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB17 External Interrupt Line */ + +#define PIN_PC01A_EIC_EXTINT1 _UINT32_(65) +#define MUX_PC01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PC01 External Interrupt Line */ + +#define PIN_PC17A_EIC_EXTINT1 _UINT32_(81) +#define MUX_PC17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PC17 External Interrupt Line */ + +#define PIN_PA02A_EIC_EXTINT2 _UINT32_(2) +#define MUX_PA02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA02 External Interrupt Line */ + +#define PIN_PA18A_EIC_EXTINT2 _UINT32_(18) +#define MUX_PA18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA18 External Interrupt Line */ + +#define PIN_PB02A_EIC_EXTINT2 _UINT32_(34) +#define MUX_PB02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB02 External Interrupt Line */ + +#define PIN_PB18A_EIC_EXTINT2 _UINT32_(50) +#define MUX_PB18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB18 External Interrupt Line */ + +#define PIN_PC02A_EIC_EXTINT2 _UINT32_(66) +#define MUX_PC02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PC02 External Interrupt Line */ + +#define PIN_PC18A_EIC_EXTINT2 _UINT32_(82) +#define MUX_PC18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PC18 External Interrupt Line */ + +#define PIN_PA03A_EIC_EXTINT3 _UINT32_(3) +#define MUX_PA03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA03 External Interrupt Line */ + +#define PIN_PA19A_EIC_EXTINT3 _UINT32_(19) +#define MUX_PA19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA19 External Interrupt Line */ + +#define PIN_PB03A_EIC_EXTINT3 _UINT32_(35) +#define MUX_PB03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB03 External Interrupt Line */ + +#define PIN_PB19A_EIC_EXTINT3 _UINT32_(51) +#define MUX_PB19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB19 External Interrupt Line */ + +#define PIN_PC03A_EIC_EXTINT3 _UINT32_(67) +#define MUX_PC03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PC03 External Interrupt Line */ + +#define PIN_PC19A_EIC_EXTINT3 _UINT32_(83) +#define MUX_PC19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PC19 External Interrupt Line */ + +#define PIN_PA04A_EIC_EXTINT4 _UINT32_(4) +#define MUX_PA04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA04 External Interrupt Line */ + +#define PIN_PA20A_EIC_EXTINT4 _UINT32_(20) +#define MUX_PA20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA20 External Interrupt Line */ + +#define PIN_PB04A_EIC_EXTINT4 _UINT32_(36) +#define MUX_PB04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB04 External Interrupt Line */ + +#define PIN_PB20A_EIC_EXTINT4 _UINT32_(52) +#define MUX_PB20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB20 External Interrupt Line */ + +#define PIN_PC20A_EIC_EXTINT4 _UINT32_(84) +#define MUX_PC20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PC20 External Interrupt Line */ + +#define PIN_PA05A_EIC_EXTINT5 _UINT32_(5) +#define MUX_PA05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA05 External Interrupt Line */ + +#define PIN_PA21A_EIC_EXTINT5 _UINT32_(21) +#define MUX_PA21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA21 External Interrupt Line */ + +#define PIN_PB05A_EIC_EXTINT5 _UINT32_(37) +#define MUX_PB05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB05 External Interrupt Line */ + +#define PIN_PB21A_EIC_EXTINT5 _UINT32_(53) +#define MUX_PB21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB21 External Interrupt Line */ + +#define PIN_PC05A_EIC_EXTINT5 _UINT32_(69) +#define MUX_PC05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PC05 External Interrupt Line */ + +#define PIN_PC21A_EIC_EXTINT5 _UINT32_(85) +#define MUX_PC21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PC21 External Interrupt Line */ + +#define PIN_PA06A_EIC_EXTINT6 _UINT32_(6) +#define MUX_PA06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA06 External Interrupt Line */ + +#define PIN_PA22A_EIC_EXTINT6 _UINT32_(22) +#define MUX_PA22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA22 External Interrupt Line */ + +#define PIN_PB06A_EIC_EXTINT6 _UINT32_(38) +#define MUX_PB06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB06 External Interrupt Line */ + +#define PIN_PB22A_EIC_EXTINT6 _UINT32_(54) +#define MUX_PB22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB22 External Interrupt Line */ + +#define PIN_PC06A_EIC_EXTINT6 _UINT32_(70) +#define MUX_PC06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PC06 External Interrupt Line */ + +#define PIN_PA07A_EIC_EXTINT7 _UINT32_(7) +#define MUX_PA07A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UINT32_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA07 External Interrupt Line */ + +#define PIN_PA23A_EIC_EXTINT7 _UINT32_(23) +#define MUX_PA23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA23 External Interrupt Line */ + +#define PIN_PB07A_EIC_EXTINT7 _UINT32_(39) +#define MUX_PB07A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UINT32_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB07 External Interrupt Line */ + +#define PIN_PB23A_EIC_EXTINT7 _UINT32_(55) +#define MUX_PB23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB23 External Interrupt Line */ + +#define PIN_PA24A_EIC_EXTINT8 _UINT32_(24) +#define MUX_PA24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PA24 External Interrupt Line */ + +#define PIN_PB08A_EIC_EXTINT8 _UINT32_(40) +#define MUX_PB08A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UINT32_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PB08 External Interrupt Line */ + +#define PIN_PB24A_EIC_EXTINT8 _UINT32_(56) +#define MUX_PB24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PB24 External Interrupt Line */ + +#define PIN_PC24A_EIC_EXTINT8 _UINT32_(88) +#define MUX_PC24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PC24 External Interrupt Line */ + +#define PIN_PA09A_EIC_EXTINT9 _UINT32_(9) +#define MUX_PA09A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UINT32_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA09 External Interrupt Line */ + +#define PIN_PA25A_EIC_EXTINT9 _UINT32_(25) +#define MUX_PA25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA25 External Interrupt Line */ + +#define PIN_PB09A_EIC_EXTINT9 _UINT32_(41) +#define MUX_PB09A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UINT32_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PB09 External Interrupt Line */ + +#define PIN_PB25A_EIC_EXTINT9 _UINT32_(57) +#define MUX_PB25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PB25 External Interrupt Line */ + +#define PIN_PC07A_EIC_EXTINT9 _UINT32_(71) +#define MUX_PC07A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UINT32_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PC07 External Interrupt Line */ + +#define PIN_PC25A_EIC_EXTINT9 _UINT32_(89) +#define MUX_PC25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PC25 External Interrupt Line */ + +#define PIN_PA10A_EIC_EXTINT10 _UINT32_(10) +#define MUX_PA10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PA10 External Interrupt Line */ + +#define PIN_PB10A_EIC_EXTINT10 _UINT32_(42) +#define MUX_PB10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PB10 External Interrupt Line */ + +#define PIN_PC10A_EIC_EXTINT10 _UINT32_(74) +#define MUX_PC10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PC10 External Interrupt Line */ + +#define PIN_PC26A_EIC_EXTINT10 _UINT32_(90) +#define MUX_PC26A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UINT32_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PC26 External Interrupt Line */ + +#define PIN_PA11A_EIC_EXTINT11 _UINT32_(11) +#define MUX_PA11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA11 External Interrupt Line */ + +#define PIN_PA27A_EIC_EXTINT11 _UINT32_(27) +#define MUX_PA27A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UINT32_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA27 External Interrupt Line */ + +#define PIN_PB11A_EIC_EXTINT11 _UINT32_(43) +#define MUX_PB11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PB11 External Interrupt Line */ + +#define PIN_PC11A_EIC_EXTINT11 _UINT32_(75) +#define MUX_PC11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PC11 External Interrupt Line */ + +#define PIN_PC27A_EIC_EXTINT11 _UINT32_(91) +#define MUX_PC27A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UINT32_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PC27 External Interrupt Line */ + +#define PIN_PA12A_EIC_EXTINT12 _UINT32_(12) +#define MUX_PA12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PA12 External Interrupt Line */ + +#define PIN_PB12A_EIC_EXTINT12 _UINT32_(44) +#define MUX_PB12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PB12 External Interrupt Line */ + +#define PIN_PC12A_EIC_EXTINT12 _UINT32_(76) +#define MUX_PC12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PC12 External Interrupt Line */ + +#define PIN_PC28A_EIC_EXTINT12 _UINT32_(92) +#define MUX_PC28A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UINT32_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PC28 External Interrupt Line */ + +#define PIN_PA13A_EIC_EXTINT13 _UINT32_(13) +#define MUX_PA13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PA13 External Interrupt Line */ + +#define PIN_PB13A_EIC_EXTINT13 _UINT32_(45) +#define MUX_PB13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PB13 External Interrupt Line */ + +#define PIN_PC13A_EIC_EXTINT13 _UINT32_(77) +#define MUX_PC13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PC13 External Interrupt Line */ + +#define PIN_PA30A_EIC_EXTINT14 _UINT32_(30) +#define MUX_PA30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA30 External Interrupt Line */ + +#define PIN_PB14A_EIC_EXTINT14 _UINT32_(46) +#define MUX_PB14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB14 External Interrupt Line */ + +#define PIN_PB30A_EIC_EXTINT14 _UINT32_(62) +#define MUX_PB30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB30 External Interrupt Line */ + +#define PIN_PC14A_EIC_EXTINT14 _UINT32_(78) +#define MUX_PC14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PC14 External Interrupt Line */ + +#define PIN_PA14A_EIC_EXTINT14 _UINT32_(14) +#define MUX_PA14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA14 External Interrupt Line */ + +#define PIN_PA15A_EIC_EXTINT15 _UINT32_(15) +#define MUX_PA15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA15 External Interrupt Line */ + +#define PIN_PA31A_EIC_EXTINT15 _UINT32_(31) +#define MUX_PA31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA31 External Interrupt Line */ + +#define PIN_PB15A_EIC_EXTINT15 _UINT32_(47) +#define MUX_PB15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB15 External Interrupt Line */ + +#define PIN_PB31A_EIC_EXTINT15 _UINT32_(63) +#define MUX_PB31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB31 External Interrupt Line */ + +#define PIN_PC15A_EIC_EXTINT15 _UINT32_(79) +#define MUX_PC15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PC15 External Interrupt Line */ + +#define PIN_PA08A_EIC_NMI _UINT32_(8) +#define MUX_PA08A_EIC_NMI _UINT32_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UINT32_(1) << 8) + +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _UINT32_(30) +#define MUX_PA30M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UINT32_(1) << 30) + +#define PIN_PB14M_GCLK_IO0 _UINT32_(46) +#define MUX_PB14M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UINT32_(1) << 14) + +#define PIN_PA14M_GCLK_IO0 _UINT32_(14) +#define MUX_PA14M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UINT32_(1) << 14) + +#define PIN_PB22M_GCLK_IO0 _UINT32_(54) +#define MUX_PB22M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UINT32_(1) << 22) + +#define PIN_PB15M_GCLK_IO1 _UINT32_(47) +#define MUX_PB15M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UINT32_(1) << 15) + +#define PIN_PA15M_GCLK_IO1 _UINT32_(15) +#define MUX_PA15M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UINT32_(1) << 15) + +#define PIN_PB23M_GCLK_IO1 _UINT32_(55) +#define MUX_PB23M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UINT32_(1) << 23) + +#define PIN_PA27M_GCLK_IO1 _UINT32_(27) +#define MUX_PA27M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UINT32_(1) << 27) + +#define PIN_PA16M_GCLK_IO2 _UINT32_(16) +#define MUX_PA16M_GCLK_IO2 _UINT32_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UINT32_(1) << 16) + +#define PIN_PB16M_GCLK_IO2 _UINT32_(48) +#define MUX_PB16M_GCLK_IO2 _UINT32_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UINT32_(1) << 16) + +#define PIN_PA17M_GCLK_IO3 _UINT32_(17) +#define MUX_PA17M_GCLK_IO3 _UINT32_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UINT32_(1) << 17) + +#define PIN_PB17M_GCLK_IO3 _UINT32_(49) +#define MUX_PB17M_GCLK_IO3 _UINT32_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UINT32_(1) << 17) + +#define PIN_PA10M_GCLK_IO4 _UINT32_(10) +#define MUX_PA10M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UINT32_(1) << 10) + +#define PIN_PB10M_GCLK_IO4 _UINT32_(42) +#define MUX_PB10M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UINT32_(1) << 10) + +#define PIN_PB18M_GCLK_IO4 _UINT32_(50) +#define MUX_PB18M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UINT32_(1) << 18) + +#define PIN_PA11M_GCLK_IO5 _UINT32_(11) +#define MUX_PA11M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UINT32_(1) << 11) + +#define PIN_PB11M_GCLK_IO5 _UINT32_(43) +#define MUX_PB11M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UINT32_(1) << 11) + +#define PIN_PB19M_GCLK_IO5 _UINT32_(51) +#define MUX_PB19M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UINT32_(1) << 19) + +#define PIN_PB12M_GCLK_IO6 _UINT32_(44) +#define MUX_PB12M_GCLK_IO6 _UINT32_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UINT32_(1) << 12) + +#define PIN_PB20M_GCLK_IO6 _UINT32_(52) +#define MUX_PB20M_GCLK_IO6 _UINT32_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UINT32_(1) << 20) + +#define PIN_PB13M_GCLK_IO7 _UINT32_(45) +#define MUX_PB13M_GCLK_IO7 _UINT32_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UINT32_(1) << 13) + +#define PIN_PB21M_GCLK_IO7 _UINT32_(53) +#define MUX_PB21M_GCLK_IO7 _UINT32_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UINT32_(1) << 21) + +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _UINT32_(85) +#define MUX_PC21L_GMAC_GCOL _UINT32_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UINT32_(1) << 21) + +#define PIN_PA16L_GMAC_GCRS _UINT32_(16) +#define MUX_PA16L_GMAC_GCRS _UINT32_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UINT32_(1) << 16) + +#define PIN_PA20L_GMAC_GMDC _UINT32_(20) +#define MUX_PA20L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UINT32_(1) << 20) + +#define PIN_PB14L_GMAC_GMDC _UINT32_(46) +#define MUX_PB14L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UINT32_(1) << 14) + +#define PIN_PC11L_GMAC_GMDC _UINT32_(75) +#define MUX_PC11L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UINT32_(1) << 11) + +#define PIN_PA21L_GMAC_GMDIO _UINT32_(21) +#define MUX_PA21L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UINT32_(1) << 21) + +#define PIN_PB15L_GMAC_GMDIO _UINT32_(47) +#define MUX_PB15L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UINT32_(1) << 15) + +#define PIN_PC12L_GMAC_GMDIO _UINT32_(76) +#define MUX_PC12L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UINT32_(1) << 12) + +#define PIN_PA13L_GMAC_GRX0 _UINT32_(13) +#define MUX_PA13L_GMAC_GRX0 _UINT32_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UINT32_(1) << 13) + +#define PIN_PA12L_GMAC_GRX1 _UINT32_(12) +#define MUX_PA12L_GMAC_GRX1 _UINT32_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UINT32_(1) << 12) + +#define PIN_PC15L_GMAC_GRX2 _UINT32_(79) +#define MUX_PC15L_GMAC_GRX2 _UINT32_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UINT32_(1) << 15) + +#define PIN_PC14L_GMAC_GRX3 _UINT32_(78) +#define MUX_PC14L_GMAC_GRX3 _UINT32_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UINT32_(1) << 14) + +#define PIN_PC18L_GMAC_GRXCK _UINT32_(82) +#define MUX_PC18L_GMAC_GRXCK _UINT32_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UINT32_(1) << 18) + +#define PIN_PC20L_GMAC_GRXDV _UINT32_(84) +#define MUX_PC20L_GMAC_GRXDV _UINT32_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UINT32_(1) << 20) + +#define PIN_PA15L_GMAC_GRXER _UINT32_(15) +#define MUX_PA15L_GMAC_GRXER _UINT32_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UINT32_(1) << 15) + +#define PIN_PA18L_GMAC_GTX0 _UINT32_(18) +#define MUX_PA18L_GMAC_GTX0 _UINT32_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UINT32_(1) << 18) + +#define PIN_PA19L_GMAC_GTX1 _UINT32_(19) +#define MUX_PA19L_GMAC_GTX1 _UINT32_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UINT32_(1) << 19) + +#define PIN_PC16L_GMAC_GTX2 _UINT32_(80) +#define MUX_PC16L_GMAC_GTX2 _UINT32_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UINT32_(1) << 16) + +#define PIN_PC17L_GMAC_GTX3 _UINT32_(81) +#define MUX_PC17L_GMAC_GTX3 _UINT32_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UINT32_(1) << 17) + +#define PIN_PA14L_GMAC_GTXCK _UINT32_(14) +#define MUX_PA14L_GMAC_GTXCK _UINT32_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UINT32_(1) << 14) + +#define PIN_PA17L_GMAC_GTXEN _UINT32_(17) +#define MUX_PA17L_GMAC_GTXEN _UINT32_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UINT32_(1) << 17) + +#define PIN_PC19L_GMAC_GTXER _UINT32_(83) +#define MUX_PC19L_GMAC_GTXER _UINT32_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UINT32_(1) << 19) + +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _UINT32_(9) +#define MUX_PA09J_I2S_FS0 _UINT32_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UINT32_(1) << 9) + +#define PIN_PA20J_I2S_FS0 _UINT32_(20) +#define MUX_PA20J_I2S_FS0 _UINT32_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UINT32_(1) << 20) + +#define PIN_PA23J_I2S_FS1 _UINT32_(23) +#define MUX_PA23J_I2S_FS1 _UINT32_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UINT32_(1) << 23) + +#define PIN_PB11J_I2S_FS1 _UINT32_(43) +#define MUX_PB11J_I2S_FS1 _UINT32_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UINT32_(1) << 11) + +#define PIN_PA08J_I2S_MCK0 _UINT32_(8) +#define MUX_PA08J_I2S_MCK0 _UINT32_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UINT32_(1) << 8) + +#define PIN_PB17J_I2S_MCK0 _UINT32_(49) +#define MUX_PB17J_I2S_MCK0 _UINT32_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UINT32_(1) << 17) + +#define PIN_PB13J_I2S_MCK1 _UINT32_(45) +#define MUX_PB13J_I2S_MCK1 _UINT32_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UINT32_(1) << 13) + +#define PIN_PA10J_I2S_SCK0 _UINT32_(10) +#define MUX_PA10J_I2S_SCK0 _UINT32_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UINT32_(1) << 10) + +#define PIN_PB16J_I2S_SCK0 _UINT32_(48) +#define MUX_PB16J_I2S_SCK0 _UINT32_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UINT32_(1) << 16) + +#define PIN_PB12J_I2S_SCK1 _UINT32_(44) +#define MUX_PB12J_I2S_SCK1 _UINT32_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UINT32_(1) << 12) + +#define PIN_PA22J_I2S_SDI _UINT32_(22) +#define MUX_PA22J_I2S_SDI _UINT32_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UINT32_(1) << 22) + +#define PIN_PB10J_I2S_SDI _UINT32_(42) +#define MUX_PB10J_I2S_SDI _UINT32_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UINT32_(1) << 10) + +#define PIN_PA11J_I2S_SDO _UINT32_(11) +#define MUX_PA11J_I2S_SDO _UINT32_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UINT32_(1) << 11) + +#define PIN_PA21J_I2S_SDO _UINT32_(21) +#define MUX_PA21J_I2S_SDO _UINT32_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UINT32_(1) << 21) + +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _UINT32_(14) +#define MUX_PA14K_PCC_CLK _UINT32_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UINT32_(1) << 14) + +#define PIN_PA16K_PCC_DATA0 _UINT32_(16) +#define MUX_PA16K_PCC_DATA0 _UINT32_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UINT32_(1) << 16) + +#define PIN_PA17K_PCC_DATA1 _UINT32_(17) +#define MUX_PA17K_PCC_DATA1 _UINT32_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UINT32_(1) << 17) + +#define PIN_PA18K_PCC_DATA2 _UINT32_(18) +#define MUX_PA18K_PCC_DATA2 _UINT32_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UINT32_(1) << 18) + +#define PIN_PA19K_PCC_DATA3 _UINT32_(19) +#define MUX_PA19K_PCC_DATA3 _UINT32_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UINT32_(1) << 19) + +#define PIN_PA20K_PCC_DATA4 _UINT32_(20) +#define MUX_PA20K_PCC_DATA4 _UINT32_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UINT32_(1) << 20) + +#define PIN_PA21K_PCC_DATA5 _UINT32_(21) +#define MUX_PA21K_PCC_DATA5 _UINT32_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UINT32_(1) << 21) + +#define PIN_PA22K_PCC_DATA6 _UINT32_(22) +#define MUX_PA22K_PCC_DATA6 _UINT32_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UINT32_(1) << 22) + +#define PIN_PA23K_PCC_DATA7 _UINT32_(23) +#define MUX_PA23K_PCC_DATA7 _UINT32_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UINT32_(1) << 23) + +#define PIN_PB14K_PCC_DATA8 _UINT32_(46) +#define MUX_PB14K_PCC_DATA8 _UINT32_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UINT32_(1) << 14) + +#define PIN_PB15K_PCC_DATA9 _UINT32_(47) +#define MUX_PB15K_PCC_DATA9 _UINT32_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UINT32_(1) << 15) + +#define PIN_PC12K_PCC_DATA10 _UINT32_(76) +#define MUX_PC12K_PCC_DATA10 _UINT32_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UINT32_(1) << 12) + +#define PIN_PC13K_PCC_DATA11 _UINT32_(77) +#define MUX_PC13K_PCC_DATA11 _UINT32_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UINT32_(1) << 13) + +#define PIN_PC14K_PCC_DATA12 _UINT32_(78) +#define MUX_PC14K_PCC_DATA12 _UINT32_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UINT32_(1) << 14) + +#define PIN_PC15K_PCC_DATA13 _UINT32_(79) +#define MUX_PC15K_PCC_DATA13 _UINT32_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UINT32_(1) << 15) + +#define PIN_PA12K_PCC_DEN1 _UINT32_(12) +#define MUX_PA12K_PCC_DEN1 _UINT32_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UINT32_(1) << 12) + +#define PIN_PA13K_PCC_DEN2 _UINT32_(13) +#define MUX_PA13K_PCC_DEN2 _UINT32_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UINT32_(1) << 13) + +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _UINT32_(50) +#define MUX_PB18G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UINT32_(1) << 18) + +#define PIN_PB23G_PDEC_QDI0 _UINT32_(55) +#define MUX_PB23G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UINT32_(1) << 23) + +#define PIN_PC16G_PDEC_QDI0 _UINT32_(80) +#define MUX_PC16G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UINT32_(1) << 16) + +#define PIN_PA24G_PDEC_QDI0 _UINT32_(24) +#define MUX_PA24G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UINT32_(1) << 24) + +#define PIN_PB19G_PDEC_QDI1 _UINT32_(51) +#define MUX_PB19G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UINT32_(1) << 19) + +#define PIN_PB24G_PDEC_QDI1 _UINT32_(56) +#define MUX_PB24G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UINT32_(1) << 24) + +#define PIN_PC17G_PDEC_QDI1 _UINT32_(81) +#define MUX_PC17G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UINT32_(1) << 17) + +#define PIN_PA25G_PDEC_QDI1 _UINT32_(25) +#define MUX_PA25G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UINT32_(1) << 25) + +#define PIN_PB20G_PDEC_QDI2 _UINT32_(52) +#define MUX_PB20G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UINT32_(1) << 20) + +#define PIN_PB25G_PDEC_QDI2 _UINT32_(57) +#define MUX_PB25G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UINT32_(1) << 25) + +#define PIN_PC18G_PDEC_QDI2 _UINT32_(82) +#define MUX_PC18G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UINT32_(1) << 18) + +#define PIN_PB22G_PDEC_QDI2 _UINT32_(54) +#define MUX_PB22G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UINT32_(1) << 22) + +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _UINT32_(43) +#define MUX_PB11H_QSPI_CS _UINT32_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UINT32_(1) << 11) + +#define PIN_PA08H_QSPI_DATA0 _UINT32_(8) +#define MUX_PA08H_QSPI_DATA0 _UINT32_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UINT32_(1) << 8) + +#define PIN_PA09H_QSPI_DATA1 _UINT32_(9) +#define MUX_PA09H_QSPI_DATA1 _UINT32_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UINT32_(1) << 9) + +#define PIN_PA10H_QSPI_DATA2 _UINT32_(10) +#define MUX_PA10H_QSPI_DATA2 _UINT32_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UINT32_(1) << 10) + +#define PIN_PA11H_QSPI_DATA3 _UINT32_(11) +#define MUX_PA11H_QSPI_DATA3 _UINT32_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UINT32_(1) << 11) + +#define PIN_PB10H_QSPI_SCK _UINT32_(42) +#define MUX_PB10H_QSPI_SCK _UINT32_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UINT32_(1) << 10) + +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _UINT32_(6) +#define MUX_PA06I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UINT32_(1) << 6) + +#define PIN_PA12I_SDHC0_SDCD _UINT32_(12) +#define MUX_PA12I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UINT32_(1) << 12) + +#define PIN_PB12I_SDHC0_SDCD _UINT32_(44) +#define MUX_PB12I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UINT32_(1) << 12) + +#define PIN_PC06I_SDHC0_SDCD _UINT32_(70) +#define MUX_PC06I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UINT32_(1) << 6) + +#define PIN_PB11I_SDHC0_SDCK _UINT32_(43) +#define MUX_PB11I_SDHC0_SDCK _UINT32_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UINT32_(1) << 11) + +#define PIN_PA08I_SDHC0_SDCMD _UINT32_(8) +#define MUX_PA08I_SDHC0_SDCMD _UINT32_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UINT32_(1) << 8) + +#define PIN_PA09I_SDHC0_SDDAT0 _UINT32_(9) +#define MUX_PA09I_SDHC0_SDDAT0 _UINT32_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UINT32_(1) << 9) + +#define PIN_PA10I_SDHC0_SDDAT1 _UINT32_(10) +#define MUX_PA10I_SDHC0_SDDAT1 _UINT32_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UINT32_(1) << 10) + +#define PIN_PA11I_SDHC0_SDDAT2 _UINT32_(11) +#define MUX_PA11I_SDHC0_SDDAT2 _UINT32_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UINT32_(1) << 11) + +#define PIN_PB10I_SDHC0_SDDAT3 _UINT32_(42) +#define MUX_PB10I_SDHC0_SDDAT3 _UINT32_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UINT32_(1) << 10) + +#define PIN_PA07I_SDHC0_SDWP _UINT32_(7) +#define MUX_PA07I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UINT32_(1) << 7) + +#define PIN_PA13I_SDHC0_SDWP _UINT32_(13) +#define MUX_PA13I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UINT32_(1) << 13) + +#define PIN_PB13I_SDHC0_SDWP _UINT32_(45) +#define MUX_PB13I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UINT32_(1) << 13) + +#define PIN_PC07I_SDHC0_SDWP _UINT32_(71) +#define MUX_PC07I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UINT32_(1) << 7) + +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _UINT32_(48) +#define MUX_PB16I_SDHC1_SDCD _UINT32_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UINT32_(1) << 16) + +#define PIN_PC20I_SDHC1_SDCD _UINT32_(84) +#define MUX_PC20I_SDHC1_SDCD _UINT32_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UINT32_(1) << 20) + +#define PIN_PA21I_SDHC1_SDCK _UINT32_(21) +#define MUX_PA21I_SDHC1_SDCK _UINT32_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UINT32_(1) << 21) + +#define PIN_PA20I_SDHC1_SDCMD _UINT32_(20) +#define MUX_PA20I_SDHC1_SDCMD _UINT32_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UINT32_(1) << 20) + +#define PIN_PB18I_SDHC1_SDDAT0 _UINT32_(50) +#define MUX_PB18I_SDHC1_SDDAT0 _UINT32_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UINT32_(1) << 18) + +#define PIN_PB19I_SDHC1_SDDAT1 _UINT32_(51) +#define MUX_PB19I_SDHC1_SDDAT1 _UINT32_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UINT32_(1) << 19) + +#define PIN_PB20I_SDHC1_SDDAT2 _UINT32_(52) +#define MUX_PB20I_SDHC1_SDDAT2 _UINT32_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UINT32_(1) << 20) + +#define PIN_PB21I_SDHC1_SDDAT3 _UINT32_(53) +#define MUX_PB21I_SDHC1_SDDAT3 _UINT32_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UINT32_(1) << 21) + +#define PIN_PB17I_SDHC1_SDWP _UINT32_(49) +#define MUX_PB17I_SDHC1_SDWP _UINT32_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UINT32_(1) << 17) + +#define PIN_PC21I_SDHC1_SDWP _UINT32_(85) +#define MUX_PC21I_SDHC1_SDWP _UINT32_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UINT32_(1) << 21) + +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _UINT32_(4) +#define MUX_PA04D_SERCOM0_PAD0 _UINT32_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UINT32_(1) << 4) + +#define PIN_PC17D_SERCOM0_PAD0 _UINT32_(81) +#define MUX_PC17D_SERCOM0_PAD0 _UINT32_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UINT32_(1) << 17) + +#define PIN_PA08C_SERCOM0_PAD0 _UINT32_(8) +#define MUX_PA08C_SERCOM0_PAD0 _UINT32_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UINT32_(1) << 8) + +#define PIN_PB24C_SERCOM0_PAD0 _UINT32_(56) +#define MUX_PB24C_SERCOM0_PAD0 _UINT32_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UINT32_(1) << 24) + +#define PIN_PA05D_SERCOM0_PAD1 _UINT32_(5) +#define MUX_PA05D_SERCOM0_PAD1 _UINT32_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UINT32_(1) << 5) + +#define PIN_PC16D_SERCOM0_PAD1 _UINT32_(80) +#define MUX_PC16D_SERCOM0_PAD1 _UINT32_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UINT32_(1) << 16) + +#define PIN_PA09C_SERCOM0_PAD1 _UINT32_(9) +#define MUX_PA09C_SERCOM0_PAD1 _UINT32_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UINT32_(1) << 9) + +#define PIN_PB25C_SERCOM0_PAD1 _UINT32_(57) +#define MUX_PB25C_SERCOM0_PAD1 _UINT32_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UINT32_(1) << 25) + +#define PIN_PA06D_SERCOM0_PAD2 _UINT32_(6) +#define MUX_PA06D_SERCOM0_PAD2 _UINT32_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UINT32_(1) << 6) + +#define PIN_PC18D_SERCOM0_PAD2 _UINT32_(82) +#define MUX_PC18D_SERCOM0_PAD2 _UINT32_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA10C_SERCOM0_PAD2 _UINT32_(10) +#define MUX_PA10C_SERCOM0_PAD2 _UINT32_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC24C_SERCOM0_PAD2 _UINT32_(88) +#define MUX_PC24C_SERCOM0_PAD2 _UINT32_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UINT32_(1) << 24) + +#define PIN_PA07D_SERCOM0_PAD3 _UINT32_(7) +#define MUX_PA07D_SERCOM0_PAD3 _UINT32_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UINT32_(1) << 7) + +#define PIN_PC19D_SERCOM0_PAD3 _UINT32_(83) +#define MUX_PC19D_SERCOM0_PAD3 _UINT32_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UINT32_(1) << 19) + +#define PIN_PA11C_SERCOM0_PAD3 _UINT32_(11) +#define MUX_PA11C_SERCOM0_PAD3 _UINT32_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC25C_SERCOM0_PAD3 _UINT32_(89) +#define MUX_PC25C_SERCOM0_PAD3 _UINT32_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UINT32_(1) << 25) + +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _UINT32_(0) +#define MUX_PA00D_SERCOM1_PAD0 _UINT32_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UINT32_(1) << 0) + +#define PIN_PA16C_SERCOM1_PAD0 _UINT32_(16) +#define MUX_PA16C_SERCOM1_PAD0 _UINT32_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UINT32_(1) << 16) + +#define PIN_PC27C_SERCOM1_PAD0 _UINT32_(91) +#define MUX_PC27C_SERCOM1_PAD0 _UINT32_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UINT32_(1) << 27) + +#define PIN_PA01D_SERCOM1_PAD1 _UINT32_(1) +#define MUX_PA01D_SERCOM1_PAD1 _UINT32_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UINT32_(1) << 1) + +#define PIN_PA17C_SERCOM1_PAD1 _UINT32_(17) +#define MUX_PA17C_SERCOM1_PAD1 _UINT32_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UINT32_(1) << 17) + +#define PIN_PC28C_SERCOM1_PAD1 _UINT32_(92) +#define MUX_PC28C_SERCOM1_PAD1 _UINT32_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UINT32_(1) << 28) + +#define PIN_PA30D_SERCOM1_PAD2 _UINT32_(30) +#define MUX_PA30D_SERCOM1_PAD2 _UINT32_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UINT32_(1) << 30) + +#define PIN_PA18C_SERCOM1_PAD2 _UINT32_(18) +#define MUX_PA18C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UINT32_(1) << 18) + +#define PIN_PB22C_SERCOM1_PAD2 _UINT32_(54) +#define MUX_PB22C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UINT32_(1) << 22) + +#define PIN_PA31D_SERCOM1_PAD3 _UINT32_(31) +#define MUX_PA31D_SERCOM1_PAD3 _UINT32_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UINT32_(1) << 31) + +#define PIN_PA19C_SERCOM1_PAD3 _UINT32_(19) +#define MUX_PA19C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UINT32_(1) << 19) + +#define PIN_PB23C_SERCOM1_PAD3 _UINT32_(55) +#define MUX_PB23C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UINT32_(1) << 23) + +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _UINT32_(9) +#define MUX_PA09D_SERCOM2_PAD0 _UINT32_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UINT32_(1) << 9) + +#define PIN_PB25D_SERCOM2_PAD0 _UINT32_(57) +#define MUX_PB25D_SERCOM2_PAD0 _UINT32_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UINT32_(1) << 25) + +#define PIN_PA12C_SERCOM2_PAD0 _UINT32_(12) +#define MUX_PA12C_SERCOM2_PAD0 _UINT32_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UINT32_(1) << 12) + +#define PIN_PA08D_SERCOM2_PAD1 _UINT32_(8) +#define MUX_PA08D_SERCOM2_PAD1 _UINT32_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UINT32_(1) << 8) + +#define PIN_PB24D_SERCOM2_PAD1 _UINT32_(56) +#define MUX_PB24D_SERCOM2_PAD1 _UINT32_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UINT32_(1) << 24) + +#define PIN_PA13C_SERCOM2_PAD1 _UINT32_(13) +#define MUX_PA13C_SERCOM2_PAD1 _UINT32_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UINT32_(1) << 13) + +#define PIN_PA10D_SERCOM2_PAD2 _UINT32_(10) +#define MUX_PA10D_SERCOM2_PAD2 _UINT32_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC24D_SERCOM2_PAD2 _UINT32_(88) +#define MUX_PC24D_SERCOM2_PAD2 _UINT32_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UINT32_(1) << 24) + +#define PIN_PA14C_SERCOM2_PAD2 _UINT32_(14) +#define MUX_PA14C_SERCOM2_PAD2 _UINT32_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UINT32_(1) << 14) + +#define PIN_PA11D_SERCOM2_PAD3 _UINT32_(11) +#define MUX_PA11D_SERCOM2_PAD3 _UINT32_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC25D_SERCOM2_PAD3 _UINT32_(89) +#define MUX_PC25D_SERCOM2_PAD3 _UINT32_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UINT32_(1) << 25) + +#define PIN_PA15C_SERCOM2_PAD3 _UINT32_(15) +#define MUX_PA15C_SERCOM2_PAD3 _UINT32_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UINT32_(1) << 15) + +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _UINT32_(17) +#define MUX_PA17D_SERCOM3_PAD0 _UINT32_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UINT32_(1) << 17) + +#define PIN_PA22C_SERCOM3_PAD0 _UINT32_(22) +#define MUX_PA22C_SERCOM3_PAD0 _UINT32_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UINT32_(1) << 22) + +#define PIN_PB20C_SERCOM3_PAD0 _UINT32_(52) +#define MUX_PB20C_SERCOM3_PAD0 _UINT32_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UINT32_(1) << 20) + +#define PIN_PA16D_SERCOM3_PAD1 _UINT32_(16) +#define MUX_PA16D_SERCOM3_PAD1 _UINT32_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UINT32_(1) << 16) + +#define PIN_PA23C_SERCOM3_PAD1 _UINT32_(23) +#define MUX_PA23C_SERCOM3_PAD1 _UINT32_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UINT32_(1) << 23) + +#define PIN_PB21C_SERCOM3_PAD1 _UINT32_(53) +#define MUX_PB21C_SERCOM3_PAD1 _UINT32_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UINT32_(1) << 21) + +#define PIN_PA18D_SERCOM3_PAD2 _UINT32_(18) +#define MUX_PA18D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA20D_SERCOM3_PAD2 _UINT32_(20) +#define MUX_PA20D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UINT32_(1) << 20) + +#define PIN_PA24C_SERCOM3_PAD2 _UINT32_(24) +#define MUX_PA24C_SERCOM3_PAD2 _UINT32_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UINT32_(1) << 24) + +#define PIN_PA19D_SERCOM3_PAD3 _UINT32_(19) +#define MUX_PA19D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UINT32_(1) << 19) + +#define PIN_PA21D_SERCOM3_PAD3 _UINT32_(21) +#define MUX_PA21D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UINT32_(1) << 21) + +#define PIN_PA25C_SERCOM3_PAD3 _UINT32_(25) +#define MUX_PA25C_SERCOM3_PAD3 _UINT32_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UINT32_(1) << 25) + +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _UINT32_(13) +#define MUX_PA13D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UINT32_(1) << 13) + +#define PIN_PB08D_SERCOM4_PAD0 _UINT32_(40) +#define MUX_PB08D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UINT32_(1) << 8) + +#define PIN_PB12C_SERCOM4_PAD0 _UINT32_(44) +#define MUX_PB12C_SERCOM4_PAD0 _UINT32_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UINT32_(1) << 12) + +#define PIN_PA12D_SERCOM4_PAD1 _UINT32_(12) +#define MUX_PA12D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UINT32_(1) << 12) + +#define PIN_PB09D_SERCOM4_PAD1 _UINT32_(41) +#define MUX_PB09D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UINT32_(1) << 9) + +#define PIN_PB13C_SERCOM4_PAD1 _UINT32_(45) +#define MUX_PB13C_SERCOM4_PAD1 _UINT32_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UINT32_(1) << 13) + +#define PIN_PA14D_SERCOM4_PAD2 _UINT32_(14) +#define MUX_PA14D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UINT32_(1) << 14) + +#define PIN_PB10D_SERCOM4_PAD2 _UINT32_(42) +#define MUX_PB10D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UINT32_(1) << 10) + +#define PIN_PB14C_SERCOM4_PAD2 _UINT32_(46) +#define MUX_PB14C_SERCOM4_PAD2 _UINT32_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UINT32_(1) << 14) + +#define PIN_PB11D_SERCOM4_PAD3 _UINT32_(43) +#define MUX_PB11D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UINT32_(1) << 11) + +#define PIN_PA15D_SERCOM4_PAD3 _UINT32_(15) +#define MUX_PA15D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UINT32_(1) << 15) + +#define PIN_PB15C_SERCOM4_PAD3 _UINT32_(47) +#define MUX_PB15C_SERCOM4_PAD3 _UINT32_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UINT32_(1) << 15) + +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _UINT32_(23) +#define MUX_PA23D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UINT32_(1) << 23) + +#define PIN_PB02D_SERCOM5_PAD0 _UINT32_(34) +#define MUX_PB02D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UINT32_(1) << 2) + +#define PIN_PB31D_SERCOM5_PAD0 _UINT32_(63) +#define MUX_PB31D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UINT32_(1) << 31) + +#define PIN_PB16C_SERCOM5_PAD0 _UINT32_(48) +#define MUX_PB16C_SERCOM5_PAD0 _UINT32_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UINT32_(1) << 16) + +#define PIN_PA22D_SERCOM5_PAD1 _UINT32_(22) +#define MUX_PA22D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UINT32_(1) << 22) + +#define PIN_PB03D_SERCOM5_PAD1 _UINT32_(35) +#define MUX_PB03D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UINT32_(1) << 3) + +#define PIN_PB30D_SERCOM5_PAD1 _UINT32_(62) +#define MUX_PB30D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UINT32_(1) << 30) + +#define PIN_PB17C_SERCOM5_PAD1 _UINT32_(49) +#define MUX_PB17C_SERCOM5_PAD1 _UINT32_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UINT32_(1) << 17) + +#define PIN_PA24D_SERCOM5_PAD2 _UINT32_(24) +#define MUX_PA24D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UINT32_(1) << 24) + +#define PIN_PB00D_SERCOM5_PAD2 _UINT32_(32) +#define MUX_PB00D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UINT32_(1) << 0) + +#define PIN_PB22D_SERCOM5_PAD2 _UINT32_(54) +#define MUX_PB22D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UINT32_(1) << 22) + +#define PIN_PA20C_SERCOM5_PAD2 _UINT32_(20) +#define MUX_PA20C_SERCOM5_PAD2 _UINT32_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UINT32_(1) << 20) + +#define PIN_PB18C_SERCOM5_PAD2 _UINT32_(50) +#define MUX_PB18C_SERCOM5_PAD2 _UINT32_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA25D_SERCOM5_PAD3 _UINT32_(25) +#define MUX_PA25D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UINT32_(1) << 25) + +#define PIN_PB01D_SERCOM5_PAD3 _UINT32_(33) +#define MUX_PB01D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UINT32_(1) << 1) + +#define PIN_PB23D_SERCOM5_PAD3 _UINT32_(55) +#define MUX_PB23D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UINT32_(1) << 23) + +#define PIN_PA21C_SERCOM5_PAD3 _UINT32_(21) +#define MUX_PA21C_SERCOM5_PAD3 _UINT32_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UINT32_(1) << 21) + +#define PIN_PB19C_SERCOM5_PAD3 _UINT32_(51) +#define MUX_PB19C_SERCOM5_PAD3 _UINT32_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UINT32_(1) << 19) + +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _UINT32_(77) +#define MUX_PC13D_SERCOM6_PAD0 _UINT32_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UINT32_(1) << 13) + +#define PIN_PC16C_SERCOM6_PAD0 _UINT32_(80) +#define MUX_PC16C_SERCOM6_PAD0 _UINT32_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UINT32_(1) << 16) + +#define PIN_PC12D_SERCOM6_PAD1 _UINT32_(76) +#define MUX_PC12D_SERCOM6_PAD1 _UINT32_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UINT32_(1) << 12) + +#define PIN_PC05C_SERCOM6_PAD1 _UINT32_(69) +#define MUX_PC05C_SERCOM6_PAD1 _UINT32_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UINT32_(1) << 5) + +#define PIN_PC17C_SERCOM6_PAD1 _UINT32_(81) +#define MUX_PC17C_SERCOM6_PAD1 _UINT32_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UINT32_(1) << 17) + +#define PIN_PC14D_SERCOM6_PAD2 _UINT32_(78) +#define MUX_PC14D_SERCOM6_PAD2 _UINT32_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UINT32_(1) << 14) + +#define PIN_PC06C_SERCOM6_PAD2 _UINT32_(70) +#define MUX_PC06C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UINT32_(1) << 6) + +#define PIN_PC10C_SERCOM6_PAD2 _UINT32_(74) +#define MUX_PC10C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC18C_SERCOM6_PAD2 _UINT32_(82) +#define MUX_PC18C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UINT32_(1) << 18) + +#define PIN_PC15D_SERCOM6_PAD3 _UINT32_(79) +#define MUX_PC15D_SERCOM6_PAD3 _UINT32_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UINT32_(1) << 15) + +#define PIN_PC07C_SERCOM6_PAD3 _UINT32_(71) +#define MUX_PC07C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UINT32_(1) << 7) + +#define PIN_PC11C_SERCOM6_PAD3 _UINT32_(75) +#define MUX_PC11C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC19C_SERCOM6_PAD3 _UINT32_(83) +#define MUX_PC19C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UINT32_(1) << 19) + +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _UINT32_(53) +#define MUX_PB21D_SERCOM7_PAD0 _UINT32_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UINT32_(1) << 21) + +#define PIN_PB30C_SERCOM7_PAD0 _UINT32_(62) +#define MUX_PB30C_SERCOM7_PAD0 _UINT32_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UINT32_(1) << 30) + +#define PIN_PC12C_SERCOM7_PAD0 _UINT32_(76) +#define MUX_PC12C_SERCOM7_PAD0 _UINT32_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UINT32_(1) << 12) + +#define PIN_PB20D_SERCOM7_PAD1 _UINT32_(52) +#define MUX_PB20D_SERCOM7_PAD1 _UINT32_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UINT32_(1) << 20) + +#define PIN_PB31C_SERCOM7_PAD1 _UINT32_(63) +#define MUX_PB31C_SERCOM7_PAD1 _UINT32_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UINT32_(1) << 31) + +#define PIN_PC13C_SERCOM7_PAD1 _UINT32_(77) +#define MUX_PC13C_SERCOM7_PAD1 _UINT32_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UINT32_(1) << 13) + +#define PIN_PB18D_SERCOM7_PAD2 _UINT32_(50) +#define MUX_PB18D_SERCOM7_PAD2 _UINT32_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UINT32_(1) << 18) + +#define PIN_PC10D_SERCOM7_PAD2 _UINT32_(74) +#define MUX_PC10D_SERCOM7_PAD2 _UINT32_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC14C_SERCOM7_PAD2 _UINT32_(78) +#define MUX_PC14C_SERCOM7_PAD2 _UINT32_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UINT32_(1) << 14) + +#define PIN_PA30C_SERCOM7_PAD2 _UINT32_(30) +#define MUX_PA30C_SERCOM7_PAD2 _UINT32_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UINT32_(1) << 30) + +#define PIN_PB19D_SERCOM7_PAD3 _UINT32_(51) +#define MUX_PB19D_SERCOM7_PAD3 _UINT32_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UINT32_(1) << 19) + +#define PIN_PC11D_SERCOM7_PAD3 _UINT32_(75) +#define MUX_PC11D_SERCOM7_PAD3 _UINT32_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC15C_SERCOM7_PAD3 _UINT32_(79) +#define MUX_PC15C_SERCOM7_PAD3 _UINT32_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UINT32_(1) << 15) + +#define PIN_PA31C_SERCOM7_PAD3 _UINT32_(31) +#define MUX_PA31C_SERCOM7_PAD3 _UINT32_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UINT32_(1) << 31) + +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _UINT32_(4) +#define MUX_PA04E_TC0_WO0 _UINT32_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UINT32_(1) << 4) + +#define PIN_PA08E_TC0_WO0 _UINT32_(8) +#define MUX_PA08E_TC0_WO0 _UINT32_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UINT32_(1) << 8) + +#define PIN_PB30E_TC0_WO0 _UINT32_(62) +#define MUX_PB30E_TC0_WO0 _UINT32_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UINT32_(1) << 30) + +#define PIN_PA05E_TC0_WO1 _UINT32_(5) +#define MUX_PA05E_TC0_WO1 _UINT32_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UINT32_(1) << 5) + +#define PIN_PA09E_TC0_WO1 _UINT32_(9) +#define MUX_PA09E_TC0_WO1 _UINT32_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UINT32_(1) << 9) + +#define PIN_PB31E_TC0_WO1 _UINT32_(63) +#define MUX_PB31E_TC0_WO1 _UINT32_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UINT32_(1) << 31) + +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _UINT32_(6) +#define MUX_PA06E_TC1_WO0 _UINT32_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UINT32_(1) << 6) + +#define PIN_PA10E_TC1_WO0 _UINT32_(10) +#define MUX_PA10E_TC1_WO0 _UINT32_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UINT32_(1) << 10) + +#define PIN_PA07E_TC1_WO1 _UINT32_(7) +#define MUX_PA07E_TC1_WO1 _UINT32_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UINT32_(1) << 7) + +#define PIN_PA11E_TC1_WO1 _UINT32_(11) +#define MUX_PA11E_TC1_WO1 _UINT32_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UINT32_(1) << 11) + +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _UINT32_(12) +#define MUX_PA12E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UINT32_(1) << 12) + +#define PIN_PA16E_TC2_WO0 _UINT32_(16) +#define MUX_PA16E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UINT32_(1) << 16) + +#define PIN_PA00E_TC2_WO0 _UINT32_(0) +#define MUX_PA00E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UINT32_(1) << 0) + +#define PIN_PA01E_TC2_WO1 _UINT32_(1) +#define MUX_PA01E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UINT32_(1) << 1) + +#define PIN_PA13E_TC2_WO1 _UINT32_(13) +#define MUX_PA13E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UINT32_(1) << 13) + +#define PIN_PA17E_TC2_WO1 _UINT32_(17) +#define MUX_PA17E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _UINT32_(18) +#define MUX_PA18E_TC3_WO0 _UINT32_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UINT32_(1) << 18) + +#define PIN_PA14E_TC3_WO0 _UINT32_(14) +#define MUX_PA14E_TC3_WO0 _UINT32_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UINT32_(1) << 14) + +#define PIN_PA15E_TC3_WO1 _UINT32_(15) +#define MUX_PA15E_TC3_WO1 _UINT32_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UINT32_(1) << 15) + +#define PIN_PA19E_TC3_WO1 _UINT32_(19) +#define MUX_PA19E_TC3_WO1 _UINT32_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UINT32_(1) << 19) + +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _UINT32_(22) +#define MUX_PA22E_TC4_WO0 _UINT32_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UINT32_(1) << 22) + +#define PIN_PB08E_TC4_WO0 _UINT32_(40) +#define MUX_PB08E_TC4_WO0 _UINT32_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UINT32_(1) << 8) + +#define PIN_PB12E_TC4_WO0 _UINT32_(44) +#define MUX_PB12E_TC4_WO0 _UINT32_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UINT32_(1) << 12) + +#define PIN_PA23E_TC4_WO1 _UINT32_(23) +#define MUX_PA23E_TC4_WO1 _UINT32_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UINT32_(1) << 23) + +#define PIN_PB09E_TC4_WO1 _UINT32_(41) +#define MUX_PB09E_TC4_WO1 _UINT32_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UINT32_(1) << 9) + +#define PIN_PB13E_TC4_WO1 _UINT32_(45) +#define MUX_PB13E_TC4_WO1 _UINT32_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UINT32_(1) << 13) + +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _UINT32_(24) +#define MUX_PA24E_TC5_WO0 _UINT32_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UINT32_(1) << 24) + +#define PIN_PB10E_TC5_WO0 _UINT32_(42) +#define MUX_PB10E_TC5_WO0 _UINT32_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UINT32_(1) << 10) + +#define PIN_PB14E_TC5_WO0 _UINT32_(46) +#define MUX_PB14E_TC5_WO0 _UINT32_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UINT32_(1) << 14) + +#define PIN_PA25E_TC5_WO1 _UINT32_(25) +#define MUX_PA25E_TC5_WO1 _UINT32_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UINT32_(1) << 25) + +#define PIN_PB11E_TC5_WO1 _UINT32_(43) +#define MUX_PB11E_TC5_WO1 _UINT32_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UINT32_(1) << 11) + +#define PIN_PB15E_TC5_WO1 _UINT32_(47) +#define MUX_PB15E_TC5_WO1 _UINT32_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UINT32_(1) << 15) + +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _UINT32_(30) +#define MUX_PA30E_TC6_WO0 _UINT32_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UINT32_(1) << 30) + +#define PIN_PB02E_TC6_WO0 _UINT32_(34) +#define MUX_PB02E_TC6_WO0 _UINT32_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UINT32_(1) << 2) + +#define PIN_PB16E_TC6_WO0 _UINT32_(48) +#define MUX_PB16E_TC6_WO0 _UINT32_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UINT32_(1) << 16) + +#define PIN_PA31E_TC6_WO1 _UINT32_(31) +#define MUX_PA31E_TC6_WO1 _UINT32_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UINT32_(1) << 31) + +#define PIN_PB03E_TC6_WO1 _UINT32_(35) +#define MUX_PB03E_TC6_WO1 _UINT32_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UINT32_(1) << 3) + +#define PIN_PB17E_TC6_WO1 _UINT32_(49) +#define MUX_PB17E_TC6_WO1 _UINT32_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _UINT32_(20) +#define MUX_PA20E_TC7_WO0 _UINT32_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UINT32_(1) << 20) + +#define PIN_PB00E_TC7_WO0 _UINT32_(32) +#define MUX_PB00E_TC7_WO0 _UINT32_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UINT32_(1) << 0) + +#define PIN_PB22E_TC7_WO0 _UINT32_(54) +#define MUX_PB22E_TC7_WO0 _UINT32_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UINT32_(1) << 22) + +#define PIN_PA21E_TC7_WO1 _UINT32_(21) +#define MUX_PA21E_TC7_WO1 _UINT32_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UINT32_(1) << 21) + +#define PIN_PB01E_TC7_WO1 _UINT32_(33) +#define MUX_PB01E_TC7_WO1 _UINT32_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UINT32_(1) << 1) + +#define PIN_PB23E_TC7_WO1 _UINT32_(55) +#define MUX_PB23E_TC7_WO1 _UINT32_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UINT32_(1) << 23) + +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _UINT32_(20) +#define MUX_PA20G_TCC0_WO0 _UINT32_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UINT32_(1) << 20) + +#define PIN_PB12G_TCC0_WO0 _UINT32_(44) +#define MUX_PB12G_TCC0_WO0 _UINT32_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UINT32_(1) << 12) + +#define PIN_PA08F_TCC0_WO0 _UINT32_(8) +#define MUX_PA08F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UINT32_(1) << 8) + +#define PIN_PC10F_TCC0_WO0 _UINT32_(74) +#define MUX_PC10F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UINT32_(1) << 10) + +#define PIN_PC16F_TCC0_WO0 _UINT32_(80) +#define MUX_PC16F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UINT32_(1) << 16) + +#define PIN_PA21G_TCC0_WO1 _UINT32_(21) +#define MUX_PA21G_TCC0_WO1 _UINT32_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UINT32_(1) << 21) + +#define PIN_PB13G_TCC0_WO1 _UINT32_(45) +#define MUX_PB13G_TCC0_WO1 _UINT32_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UINT32_(1) << 13) + +#define PIN_PA09F_TCC0_WO1 _UINT32_(9) +#define MUX_PA09F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UINT32_(1) << 9) + +#define PIN_PC11F_TCC0_WO1 _UINT32_(75) +#define MUX_PC11F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UINT32_(1) << 11) + +#define PIN_PC17F_TCC0_WO1 _UINT32_(81) +#define MUX_PC17F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UINT32_(1) << 17) + +#define PIN_PA22G_TCC0_WO2 _UINT32_(22) +#define MUX_PA22G_TCC0_WO2 _UINT32_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UINT32_(1) << 22) + +#define PIN_PB14G_TCC0_WO2 _UINT32_(46) +#define MUX_PB14G_TCC0_WO2 _UINT32_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UINT32_(1) << 14) + +#define PIN_PA10F_TCC0_WO2 _UINT32_(10) +#define MUX_PA10F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UINT32_(1) << 10) + +#define PIN_PC12F_TCC0_WO2 _UINT32_(76) +#define MUX_PC12F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UINT32_(1) << 12) + +#define PIN_PC18F_TCC0_WO2 _UINT32_(82) +#define MUX_PC18F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UINT32_(1) << 18) + +#define PIN_PA23G_TCC0_WO3 _UINT32_(23) +#define MUX_PA23G_TCC0_WO3 _UINT32_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UINT32_(1) << 23) + +#define PIN_PB15G_TCC0_WO3 _UINT32_(47) +#define MUX_PB15G_TCC0_WO3 _UINT32_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UINT32_(1) << 15) + +#define PIN_PA11F_TCC0_WO3 _UINT32_(11) +#define MUX_PA11F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UINT32_(1) << 11) + +#define PIN_PC13F_TCC0_WO3 _UINT32_(77) +#define MUX_PC13F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UINT32_(1) << 13) + +#define PIN_PC19F_TCC0_WO3 _UINT32_(83) +#define MUX_PC19F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UINT32_(1) << 19) + +#define PIN_PA16G_TCC0_WO4 _UINT32_(16) +#define MUX_PA16G_TCC0_WO4 _UINT32_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UINT32_(1) << 16) + +#define PIN_PB16G_TCC0_WO4 _UINT32_(48) +#define MUX_PB16G_TCC0_WO4 _UINT32_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UINT32_(1) << 16) + +#define PIN_PB10F_TCC0_WO4 _UINT32_(42) +#define MUX_PB10F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UINT32_(1) << 10) + +#define PIN_PC14F_TCC0_WO4 _UINT32_(78) +#define MUX_PC14F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UINT32_(1) << 14) + +#define PIN_PC20F_TCC0_WO4 _UINT32_(84) +#define MUX_PC20F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UINT32_(1) << 20) + +#define PIN_PA17G_TCC0_WO5 _UINT32_(17) +#define MUX_PA17G_TCC0_WO5 _UINT32_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UINT32_(1) << 17) + +#define PIN_PB17G_TCC0_WO5 _UINT32_(49) +#define MUX_PB17G_TCC0_WO5 _UINT32_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UINT32_(1) << 17) + +#define PIN_PB11F_TCC0_WO5 _UINT32_(43) +#define MUX_PB11F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UINT32_(1) << 11) + +#define PIN_PC15F_TCC0_WO5 _UINT32_(79) +#define MUX_PC15F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UINT32_(1) << 15) + +#define PIN_PC21F_TCC0_WO5 _UINT32_(85) +#define MUX_PC21F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UINT32_(1) << 21) + +#define PIN_PA18G_TCC0_WO6 _UINT32_(18) +#define MUX_PA18G_TCC0_WO6 _UINT32_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UINT32_(1) << 18) + +#define PIN_PB30G_TCC0_WO6 _UINT32_(62) +#define MUX_PB30G_TCC0_WO6 _UINT32_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UINT32_(1) << 30) + +#define PIN_PA12F_TCC0_WO6 _UINT32_(12) +#define MUX_PA12F_TCC0_WO6 _UINT32_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UINT32_(1) << 12) + +#define PIN_PA19G_TCC0_WO7 _UINT32_(19) +#define MUX_PA19G_TCC0_WO7 _UINT32_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UINT32_(1) << 19) + +#define PIN_PB31G_TCC0_WO7 _UINT32_(63) +#define MUX_PB31G_TCC0_WO7 _UINT32_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UINT32_(1) << 31) + +#define PIN_PA13F_TCC0_WO7 _UINT32_(13) +#define MUX_PA13F_TCC0_WO7 _UINT32_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UINT32_(1) << 13) + +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _UINT32_(42) +#define MUX_PB10G_TCC1_WO0 _UINT32_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UINT32_(1) << 10) + +#define PIN_PC14G_TCC1_WO0 _UINT32_(78) +#define MUX_PC14G_TCC1_WO0 _UINT32_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UINT32_(1) << 14) + +#define PIN_PA16F_TCC1_WO0 _UINT32_(16) +#define MUX_PA16F_TCC1_WO0 _UINT32_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UINT32_(1) << 16) + +#define PIN_PB18F_TCC1_WO0 _UINT32_(50) +#define MUX_PB18F_TCC1_WO0 _UINT32_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UINT32_(1) << 18) + +#define PIN_PB11G_TCC1_WO1 _UINT32_(43) +#define MUX_PB11G_TCC1_WO1 _UINT32_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UINT32_(1) << 11) + +#define PIN_PC15G_TCC1_WO1 _UINT32_(79) +#define MUX_PC15G_TCC1_WO1 _UINT32_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UINT32_(1) << 15) + +#define PIN_PA17F_TCC1_WO1 _UINT32_(17) +#define MUX_PA17F_TCC1_WO1 _UINT32_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UINT32_(1) << 17) + +#define PIN_PB19F_TCC1_WO1 _UINT32_(51) +#define MUX_PB19F_TCC1_WO1 _UINT32_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UINT32_(1) << 19) + +#define PIN_PA12G_TCC1_WO2 _UINT32_(12) +#define MUX_PA12G_TCC1_WO2 _UINT32_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UINT32_(1) << 12) + +#define PIN_PA14G_TCC1_WO2 _UINT32_(14) +#define MUX_PA14G_TCC1_WO2 _UINT32_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UINT32_(1) << 14) + +#define PIN_PA18F_TCC1_WO2 _UINT32_(18) +#define MUX_PA18F_TCC1_WO2 _UINT32_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UINT32_(1) << 18) + +#define PIN_PB20F_TCC1_WO2 _UINT32_(52) +#define MUX_PB20F_TCC1_WO2 _UINT32_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UINT32_(1) << 20) + +#define PIN_PA13G_TCC1_WO3 _UINT32_(13) +#define MUX_PA13G_TCC1_WO3 _UINT32_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UINT32_(1) << 13) + +#define PIN_PA15G_TCC1_WO3 _UINT32_(15) +#define MUX_PA15G_TCC1_WO3 _UINT32_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UINT32_(1) << 15) + +#define PIN_PA19F_TCC1_WO3 _UINT32_(19) +#define MUX_PA19F_TCC1_WO3 _UINT32_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UINT32_(1) << 19) + +#define PIN_PB21F_TCC1_WO3 _UINT32_(53) +#define MUX_PB21F_TCC1_WO3 _UINT32_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UINT32_(1) << 21) + +#define PIN_PA08G_TCC1_WO4 _UINT32_(8) +#define MUX_PA08G_TCC1_WO4 _UINT32_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UINT32_(1) << 8) + +#define PIN_PC10G_TCC1_WO4 _UINT32_(74) +#define MUX_PC10G_TCC1_WO4 _UINT32_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UINT32_(1) << 10) + +#define PIN_PA20F_TCC1_WO4 _UINT32_(20) +#define MUX_PA20F_TCC1_WO4 _UINT32_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UINT32_(1) << 20) + +#define PIN_PA09G_TCC1_WO5 _UINT32_(9) +#define MUX_PA09G_TCC1_WO5 _UINT32_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UINT32_(1) << 9) + +#define PIN_PC11G_TCC1_WO5 _UINT32_(75) +#define MUX_PC11G_TCC1_WO5 _UINT32_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UINT32_(1) << 11) + +#define PIN_PA21F_TCC1_WO5 _UINT32_(21) +#define MUX_PA21F_TCC1_WO5 _UINT32_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UINT32_(1) << 21) + +#define PIN_PA10G_TCC1_WO6 _UINT32_(10) +#define MUX_PA10G_TCC1_WO6 _UINT32_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UINT32_(1) << 10) + +#define PIN_PC12G_TCC1_WO6 _UINT32_(76) +#define MUX_PC12G_TCC1_WO6 _UINT32_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UINT32_(1) << 12) + +#define PIN_PA22F_TCC1_WO6 _UINT32_(22) +#define MUX_PA22F_TCC1_WO6 _UINT32_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UINT32_(1) << 22) + +#define PIN_PA11G_TCC1_WO7 _UINT32_(11) +#define MUX_PA11G_TCC1_WO7 _UINT32_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UINT32_(1) << 11) + +#define PIN_PC13G_TCC1_WO7 _UINT32_(77) +#define MUX_PC13G_TCC1_WO7 _UINT32_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UINT32_(1) << 13) + +#define PIN_PA23F_TCC1_WO7 _UINT32_(23) +#define MUX_PA23F_TCC1_WO7 _UINT32_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UINT32_(1) << 23) + +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _UINT32_(14) +#define MUX_PA14F_TCC2_WO0 _UINT32_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UINT32_(1) << 14) + +#define PIN_PA30F_TCC2_WO0 _UINT32_(30) +#define MUX_PA30F_TCC2_WO0 _UINT32_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UINT32_(1) << 30) + +#define PIN_PA15F_TCC2_WO1 _UINT32_(15) +#define MUX_PA15F_TCC2_WO1 _UINT32_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UINT32_(1) << 15) + +#define PIN_PA31F_TCC2_WO1 _UINT32_(31) +#define MUX_PA31F_TCC2_WO1 _UINT32_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UINT32_(1) << 31) + +#define PIN_PA24F_TCC2_WO2 _UINT32_(24) +#define MUX_PA24F_TCC2_WO2 _UINT32_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UINT32_(1) << 24) + +#define PIN_PB02F_TCC2_WO2 _UINT32_(34) +#define MUX_PB02F_TCC2_WO2 _UINT32_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UINT32_(1) << 2) + +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _UINT32_(44) +#define MUX_PB12F_TCC3_WO0 _UINT32_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UINT32_(1) << 12) + +#define PIN_PB16F_TCC3_WO0 _UINT32_(48) +#define MUX_PB16F_TCC3_WO0 _UINT32_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UINT32_(1) << 16) + +#define PIN_PB13F_TCC3_WO1 _UINT32_(45) +#define MUX_PB13F_TCC3_WO1 _UINT32_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UINT32_(1) << 13) + +#define PIN_PB17F_TCC3_WO1 _UINT32_(49) +#define MUX_PB17F_TCC3_WO1 _UINT32_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _UINT32_(46) +#define MUX_PB14F_TCC4_WO0 _UINT32_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UINT32_(1) << 14) + +#define PIN_PB30F_TCC4_WO0 _UINT32_(62) +#define MUX_PB30F_TCC4_WO0 _UINT32_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UINT32_(1) << 30) + +#define PIN_PB15F_TCC4_WO1 _UINT32_(47) +#define MUX_PB15F_TCC4_WO1 _UINT32_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UINT32_(1) << 15) + +#define PIN_PB31F_TCC4_WO1 _UINT32_(63) +#define MUX_PB31F_TCC4_WO1 _UINT32_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UINT32_(1) << 31) + +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _UINT32_(24) +#define MUX_PA24H_USB_DM _UINT32_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UINT32_(1) << 24) + +#define PIN_PA25H_USB_DP _UINT32_(25) +#define MUX_PA25H_USB_DP _UINT32_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UINT32_(1) << 25) + +#define PIN_PA23H_USB_SOF_1KHZ _UINT32_(23) +#define MUX_PA23H_USB_SOF_1KHZ _UINT32_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UINT32_(1) << 23) + +#define PIN_PB22H_USB_SOF_1KHZ _UINT32_(54) +#define MUX_PB22H_USB_SOF_1KHZ _UINT32_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UINT32_(1) << 22) + +/* ========== PORT definition for TPIU peripheral ========== */ +#define PIN_PC27H_TPIU_TRACECLK _UINT32_(91) +#define MUX_PC27H_TPIU_TRACECLK _UINT32_(7) +#define PINMUX_PC27H_TPIU_TRACECLK ((PIN_PC27H_TPIU_TRACECLK << 16) | MUX_PC27H_TPIU_TRACECLK) +#define PORT_PC27H_TPIU_TRACECLK (_UINT32_(1) << 27) + +#define PIN_PC28H_TPIU_TRACED0 _UINT32_(92) +#define MUX_PC28H_TPIU_TRACED0 _UINT32_(7) +#define PINMUX_PC28H_TPIU_TRACED0 ((PIN_PC28H_TPIU_TRACED0 << 16) | MUX_PC28H_TPIU_TRACED0) +#define PORT_PC28H_TPIU_TRACED0 (_UINT32_(1) << 28) + +#define PIN_PC26H_TPIU_TRACED1 _UINT32_(90) +#define MUX_PC26H_TPIU_TRACED1 _UINT32_(7) +#define PINMUX_PC26H_TPIU_TRACED1 ((PIN_PC26H_TPIU_TRACED1 << 16) | MUX_PC26H_TPIU_TRACED1) +#define PORT_PC26H_TPIU_TRACED1 (_UINT32_(1) << 26) + +#define PIN_PC25H_TPIU_TRACED2 _UINT32_(89) +#define MUX_PC25H_TPIU_TRACED2 _UINT32_(7) +#define PINMUX_PC25H_TPIU_TRACED2 ((PIN_PC25H_TPIU_TRACED2 << 16) | MUX_PC25H_TPIU_TRACED2) +#define PORT_PC25H_TPIU_TRACED2 (_UINT32_(1) << 25) + +#define PIN_PC24H_TPIU_TRACED3 _UINT32_(88) +#define MUX_PC24H_TPIU_TRACED3 _UINT32_(7) +#define PINMUX_PC24H_TPIU_TRACED3 ((PIN_PC24H_TPIU_TRACED3 << 16) | MUX_PC24H_TPIU_TRACED3) +#define PORT_PC24H_TPIU_TRACED3 (_UINT32_(1) << 24) + + + +#endif /* _SAME54N19A_GPIO_H_ */ + diff --git a/os/common/ext/Microchip/SAME54/pio/same54n20a.h b/os/common/ext/Microchip/SAME54/pio/same54n20a.h new file mode 100644 index 0000000000..0a51db6e10 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/pio/same54n20a.h @@ -0,0 +1,3262 @@ +/* + * Peripheral I/O description for SAME54N20A + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:06Z */ +#ifndef _SAME54N20A_GPIO_H_ +#define _SAME54N20A_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA00 ( 0) /**< Pin Number for PA00 */ +#define PIN_PA01 ( 1) /**< Pin Number for PA01 */ +#define PIN_PA02 ( 2) /**< Pin Number for PA02 */ +#define PIN_PA03 ( 3) /**< Pin Number for PA03 */ +#define PIN_PA04 ( 4) /**< Pin Number for PA04 */ +#define PIN_PA05 ( 5) /**< Pin Number for PA05 */ +#define PIN_PA06 ( 6) /**< Pin Number for PA06 */ +#define PIN_PA07 ( 7) /**< Pin Number for PA07 */ +#define PIN_PA08 ( 8) /**< Pin Number for PA08 */ +#define PIN_PA09 ( 9) /**< Pin Number for PA09 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB00 ( 32) /**< Pin Number for PB00 */ +#define PIN_PB01 ( 33) /**< Pin Number for PB01 */ +#define PIN_PB02 ( 34) /**< Pin Number for PB02 */ +#define PIN_PB03 ( 35) /**< Pin Number for PB03 */ +#define PIN_PB04 ( 36) /**< Pin Number for PB04 */ +#define PIN_PB05 ( 37) /**< Pin Number for PB05 */ +#define PIN_PB06 ( 38) /**< Pin Number for PB06 */ +#define PIN_PB07 ( 39) /**< Pin Number for PB07 */ +#define PIN_PB08 ( 40) /**< Pin Number for PB08 */ +#define PIN_PB09 ( 41) /**< Pin Number for PB09 */ +#define PIN_PB10 ( 42) /**< Pin Number for PB10 */ +#define PIN_PB11 ( 43) /**< Pin Number for PB11 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PB14 ( 46) /**< Pin Number for PB14 */ +#define PIN_PB15 ( 47) /**< Pin Number for PB15 */ +#define PIN_PB16 ( 48) /**< Pin Number for PB16 */ +#define PIN_PB17 ( 49) /**< Pin Number for PB17 */ +#define PIN_PB18 ( 50) /**< Pin Number for PB18 */ +#define PIN_PB19 ( 51) /**< Pin Number for PB19 */ +#define PIN_PB20 ( 52) /**< Pin Number for PB20 */ +#define PIN_PB21 ( 53) /**< Pin Number for PB21 */ +#define PIN_PB22 ( 54) /**< Pin Number for PB22 */ +#define PIN_PB23 ( 55) /**< Pin Number for PB23 */ +#define PIN_PB24 ( 56) /**< Pin Number for PB24 */ +#define PIN_PB25 ( 57) /**< Pin Number for PB25 */ +#define PIN_PB30 ( 62) /**< Pin Number for PB30 */ +#define PIN_PB31 ( 63) /**< Pin Number for PB31 */ +#define PIN_PC00 ( 64) /**< Pin Number for PC00 */ +#define PIN_PC01 ( 65) /**< Pin Number for PC01 */ +#define PIN_PC02 ( 66) /**< Pin Number for PC02 */ +#define PIN_PC03 ( 67) /**< Pin Number for PC03 */ +#define PIN_PC05 ( 69) /**< Pin Number for PC05 */ +#define PIN_PC06 ( 70) /**< Pin Number for PC06 */ +#define PIN_PC07 ( 71) /**< Pin Number for PC07 */ +#define PIN_PC10 ( 74) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85) /**< Pin Number for PC21 */ +#define PIN_PC24 ( 88) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92) /**< Pin Number for PC28 */ + +/* ========== Peripheral I/O masks ========== */ +#define PORT_PA00 (_UINT32_(1) << 0) /**< PORT mask for PA00 */ +#define PORT_PA01 (_UINT32_(1) << 1) /**< PORT mask for PA01 */ +#define PORT_PA02 (_UINT32_(1) << 2) /**< PORT mask for PA02 */ +#define PORT_PA03 (_UINT32_(1) << 3) /**< PORT mask for PA03 */ +#define PORT_PA04 (_UINT32_(1) << 4) /**< PORT mask for PA04 */ +#define PORT_PA05 (_UINT32_(1) << 5) /**< PORT mask for PA05 */ +#define PORT_PA06 (_UINT32_(1) << 6) /**< PORT mask for PA06 */ +#define PORT_PA07 (_UINT32_(1) << 7) /**< PORT mask for PA07 */ +#define PORT_PA08 (_UINT32_(1) << 8) /**< PORT mask for PA08 */ +#define PORT_PA09 (_UINT32_(1) << 9) /**< PORT mask for PA09 */ +#define PORT_PA10 (_UINT32_(1) << 10) /**< PORT mask for PA10 */ +#define PORT_PA11 (_UINT32_(1) << 11) /**< PORT mask for PA11 */ +#define PORT_PA12 (_UINT32_(1) << 12) /**< PORT mask for PA12 */ +#define PORT_PA13 (_UINT32_(1) << 13) /**< PORT mask for PA13 */ +#define PORT_PA14 (_UINT32_(1) << 14) /**< PORT mask for PA14 */ +#define PORT_PA15 (_UINT32_(1) << 15) /**< PORT mask for PA15 */ +#define PORT_PA16 (_UINT32_(1) << 16) /**< PORT mask for PA16 */ +#define PORT_PA17 (_UINT32_(1) << 17) /**< PORT mask for PA17 */ +#define PORT_PA18 (_UINT32_(1) << 18) /**< PORT mask for PA18 */ +#define PORT_PA19 (_UINT32_(1) << 19) /**< PORT mask for PA19 */ +#define PORT_PA20 (_UINT32_(1) << 20) /**< PORT mask for PA20 */ +#define PORT_PA21 (_UINT32_(1) << 21) /**< PORT mask for PA21 */ +#define PORT_PA22 (_UINT32_(1) << 22) /**< PORT mask for PA22 */ +#define PORT_PA23 (_UINT32_(1) << 23) /**< PORT mask for PA23 */ +#define PORT_PA24 (_UINT32_(1) << 24) /**< PORT mask for PA24 */ +#define PORT_PA25 (_UINT32_(1) << 25) /**< PORT mask for PA25 */ +#define PORT_PA27 (_UINT32_(1) << 27) /**< PORT mask for PA27 */ +#define PORT_PA30 (_UINT32_(1) << 30) /**< PORT mask for PA30 */ +#define PORT_PA31 (_UINT32_(1) << 31) /**< PORT mask for PA31 */ +#define PORT_PB00 (_UINT32_(1) << 0) /**< PORT mask for PB00 */ +#define PORT_PB01 (_UINT32_(1) << 1) /**< PORT mask for PB01 */ +#define PORT_PB02 (_UINT32_(1) << 2) /**< PORT mask for PB02 */ +#define PORT_PB03 (_UINT32_(1) << 3) /**< PORT mask for PB03 */ +#define PORT_PB04 (_UINT32_(1) << 4) /**< PORT mask for PB04 */ +#define PORT_PB05 (_UINT32_(1) << 5) /**< PORT mask for PB05 */ +#define PORT_PB06 (_UINT32_(1) << 6) /**< PORT mask for PB06 */ +#define PORT_PB07 (_UINT32_(1) << 7) /**< PORT mask for PB07 */ +#define PORT_PB08 (_UINT32_(1) << 8) /**< PORT mask for PB08 */ +#define PORT_PB09 (_UINT32_(1) << 9) /**< PORT mask for PB09 */ +#define PORT_PB10 (_UINT32_(1) << 10) /**< PORT mask for PB10 */ +#define PORT_PB11 (_UINT32_(1) << 11) /**< PORT mask for PB11 */ +#define PORT_PB12 (_UINT32_(1) << 12) /**< PORT mask for PB12 */ +#define PORT_PB13 (_UINT32_(1) << 13) /**< PORT mask for PB13 */ +#define PORT_PB14 (_UINT32_(1) << 14) /**< PORT mask for PB14 */ +#define PORT_PB15 (_UINT32_(1) << 15) /**< PORT mask for PB15 */ +#define PORT_PB16 (_UINT32_(1) << 16) /**< PORT mask for PB16 */ +#define PORT_PB17 (_UINT32_(1) << 17) /**< PORT mask for PB17 */ +#define PORT_PB18 (_UINT32_(1) << 18) /**< PORT mask for PB18 */ +#define PORT_PB19 (_UINT32_(1) << 19) /**< PORT mask for PB19 */ +#define PORT_PB20 (_UINT32_(1) << 20) /**< PORT mask for PB20 */ +#define PORT_PB21 (_UINT32_(1) << 21) /**< PORT mask for PB21 */ +#define PORT_PB22 (_UINT32_(1) << 22) /**< PORT mask for PB22 */ +#define PORT_PB23 (_UINT32_(1) << 23) /**< PORT mask for PB23 */ +#define PORT_PB24 (_UINT32_(1) << 24) /**< PORT mask for PB24 */ +#define PORT_PB25 (_UINT32_(1) << 25) /**< PORT mask for PB25 */ +#define PORT_PB30 (_UINT32_(1) << 30) /**< PORT mask for PB30 */ +#define PORT_PB31 (_UINT32_(1) << 31) /**< PORT mask for PB31 */ +#define PORT_PC00 (_UINT32_(1) << 0) /**< PORT mask for PC00 */ +#define PORT_PC01 (_UINT32_(1) << 1) /**< PORT mask for PC01 */ +#define PORT_PC02 (_UINT32_(1) << 2) /**< PORT mask for PC02 */ +#define PORT_PC03 (_UINT32_(1) << 3) /**< PORT mask for PC03 */ +#define PORT_PC05 (_UINT32_(1) << 5) /**< PORT mask for PC05 */ +#define PORT_PC06 (_UINT32_(1) << 6) /**< PORT mask for PC06 */ +#define PORT_PC07 (_UINT32_(1) << 7) /**< PORT mask for PC07 */ +#define PORT_PC10 (_UINT32_(1) << 10) /**< PORT mask for PC10 */ +#define PORT_PC11 (_UINT32_(1) << 11) /**< PORT mask for PC11 */ +#define PORT_PC12 (_UINT32_(1) << 12) /**< PORT mask for PC12 */ +#define PORT_PC13 (_UINT32_(1) << 13) /**< PORT mask for PC13 */ +#define PORT_PC14 (_UINT32_(1) << 14) /**< PORT mask for PC14 */ +#define PORT_PC15 (_UINT32_(1) << 15) /**< PORT mask for PC15 */ +#define PORT_PC16 (_UINT32_(1) << 16) /**< PORT mask for PC16 */ +#define PORT_PC17 (_UINT32_(1) << 17) /**< PORT mask for PC17 */ +#define PORT_PC18 (_UINT32_(1) << 18) /**< PORT mask for PC18 */ +#define PORT_PC19 (_UINT32_(1) << 19) /**< PORT mask for PC19 */ +#define PORT_PC20 (_UINT32_(1) << 20) /**< PORT mask for PC20 */ +#define PORT_PC21 (_UINT32_(1) << 21) /**< PORT mask for PC21 */ +#define PORT_PC24 (_UINT32_(1) << 24) /**< PORT mask for PC24 */ +#define PORT_PC25 (_UINT32_(1) << 25) /**< PORT mask for PC25 */ +#define PORT_PC26 (_UINT32_(1) << 26) /**< PORT mask for PC26 */ +#define PORT_PC27 (_UINT32_(1) << 27) /**< PORT mask for PC27 */ +#define PORT_PC28 (_UINT32_(1) << 28) /**< PORT mask for PC28 */ + +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _UINT32_(4) +#define MUX_PA04B_AC_AIN0 _UINT32_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UINT32_(1) << 4) + +#define PIN_PA05B_AC_AIN1 _UINT32_(5) +#define MUX_PA05B_AC_AIN1 _UINT32_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UINT32_(1) << 5) + +#define PIN_PA06B_AC_AIN2 _UINT32_(6) +#define MUX_PA06B_AC_AIN2 _UINT32_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UINT32_(1) << 6) + +#define PIN_PA07B_AC_AIN3 _UINT32_(7) +#define MUX_PA07B_AC_AIN3 _UINT32_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UINT32_(1) << 7) + +#define PIN_PA12M_AC_CMP0 _UINT32_(12) +#define MUX_PA12M_AC_CMP0 _UINT32_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UINT32_(1) << 12) + +#define PIN_PA18M_AC_CMP0 _UINT32_(18) +#define MUX_PA18M_AC_CMP0 _UINT32_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UINT32_(1) << 18) + +#define PIN_PB24M_AC_CMP0 _UINT32_(56) +#define MUX_PB24M_AC_CMP0 _UINT32_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UINT32_(1) << 24) + +#define PIN_PA13M_AC_CMP1 _UINT32_(13) +#define MUX_PA13M_AC_CMP1 _UINT32_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UINT32_(1) << 13) + +#define PIN_PA19M_AC_CMP1 _UINT32_(19) +#define MUX_PA19M_AC_CMP1 _UINT32_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UINT32_(1) << 19) + +#define PIN_PB25M_AC_CMP1 _UINT32_(57) +#define MUX_PB25M_AC_CMP1 _UINT32_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UINT32_(1) << 25) + +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _UINT32_(2) +#define MUX_PA02B_ADC0_AIN0 _UINT32_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UINT32_(1) << 2) + +#define PIN_PA03B_ADC0_AIN1 _UINT32_(3) +#define MUX_PA03B_ADC0_AIN1 _UINT32_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_AIN2 _UINT32_(40) +#define MUX_PB08B_ADC0_AIN2 _UINT32_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_AIN3 _UINT32_(41) +#define MUX_PB09B_ADC0_AIN3 _UINT32_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_AIN4 _UINT32_(4) +#define MUX_PA04B_ADC0_AIN4 _UINT32_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UINT32_(1) << 4) + +#define PIN_PA05B_ADC0_AIN5 _UINT32_(5) +#define MUX_PA05B_ADC0_AIN5 _UINT32_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UINT32_(1) << 5) + +#define PIN_PA06B_ADC0_AIN6 _UINT32_(6) +#define MUX_PA06B_ADC0_AIN6 _UINT32_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_AIN7 _UINT32_(7) +#define MUX_PA07B_ADC0_AIN7 _UINT32_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_AIN8 _UINT32_(8) +#define MUX_PA08B_ADC0_AIN8 _UINT32_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_AIN9 _UINT32_(9) +#define MUX_PA09B_ADC0_AIN9 _UINT32_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_AIN10 _UINT32_(10) +#define MUX_PA10B_ADC0_AIN10 _UINT32_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_AIN11 _UINT32_(11) +#define MUX_PA11B_ADC0_AIN11 _UINT32_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UINT32_(1) << 11) + +#define PIN_PB00B_ADC0_AIN12 _UINT32_(32) +#define MUX_PB00B_ADC0_AIN12 _UINT32_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_AIN13 _UINT32_(33) +#define MUX_PB01B_ADC0_AIN13 _UINT32_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UINT32_(1) << 1) + +#define PIN_PB02B_ADC0_AIN14 _UINT32_(34) +#define MUX_PB02B_ADC0_AIN14 _UINT32_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_AIN15 _UINT32_(35) +#define MUX_PB03B_ADC0_AIN15 _UINT32_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UINT32_(1) << 3) + +#define PIN_PA03B_ADC0_VREFA _UINT32_(3) +#define MUX_PA03B_ADC0_VREFA _UINT32_(1) +#define PINMUX_PA03B_ADC0_VREFA ((PIN_PA03B_ADC0_VREFA << 16) | MUX_PA03B_ADC0_VREFA) +#define PORT_PA03B_ADC0_VREFA (_UINT32_(1) << 3) + +#define PIN_PA04B_ADC0_VREFB _UINT32_(4) +#define MUX_PA04B_ADC0_VREFB _UINT32_(1) +#define PINMUX_PA04B_ADC0_VREFB ((PIN_PA04B_ADC0_VREFB << 16) | MUX_PA04B_ADC0_VREFB) +#define PORT_PA04B_ADC0_VREFB (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_VREFC _UINT32_(6) +#define MUX_PA06B_ADC0_VREFC _UINT32_(1) +#define PINMUX_PA06B_ADC0_VREFC ((PIN_PA06B_ADC0_VREFC << 16) | MUX_PA06B_ADC0_VREFC) +#define PORT_PA06B_ADC0_VREFC (_UINT32_(1) << 6) + +#define PIN_PA03B_ADC0_X0 _UINT32_(3) +#define MUX_PA03B_ADC0_X0 _UINT32_(1) +#define PINMUX_PA03B_ADC0_X0 ((PIN_PA03B_ADC0_X0 << 16) | MUX_PA03B_ADC0_X0) +#define PORT_PA03B_ADC0_X0 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_X1 _UINT32_(40) +#define MUX_PB08B_ADC0_X1 _UINT32_(1) +#define PINMUX_PB08B_ADC0_X1 ((PIN_PB08B_ADC0_X1 << 16) | MUX_PB08B_ADC0_X1) +#define PORT_PB08B_ADC0_X1 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_X2 _UINT32_(41) +#define MUX_PB09B_ADC0_X2 _UINT32_(1) +#define PINMUX_PB09B_ADC0_X2 ((PIN_PB09B_ADC0_X2 << 16) | MUX_PB09B_ADC0_X2) +#define PORT_PB09B_ADC0_X2 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_X3 _UINT32_(4) +#define MUX_PA04B_ADC0_X3 _UINT32_(1) +#define PINMUX_PA04B_ADC0_X3 ((PIN_PA04B_ADC0_X3 << 16) | MUX_PA04B_ADC0_X3) +#define PORT_PA04B_ADC0_X3 (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_X4 _UINT32_(6) +#define MUX_PA06B_ADC0_X4 _UINT32_(1) +#define PINMUX_PA06B_ADC0_X4 ((PIN_PA06B_ADC0_X4 << 16) | MUX_PA06B_ADC0_X4) +#define PORT_PA06B_ADC0_X4 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_X5 _UINT32_(7) +#define MUX_PA07B_ADC0_X5 _UINT32_(1) +#define PINMUX_PA07B_ADC0_X5 ((PIN_PA07B_ADC0_X5 << 16) | MUX_PA07B_ADC0_X5) +#define PORT_PA07B_ADC0_X5 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_X6 _UINT32_(8) +#define MUX_PA08B_ADC0_X6 _UINT32_(1) +#define PINMUX_PA08B_ADC0_X6 ((PIN_PA08B_ADC0_X6 << 16) | MUX_PA08B_ADC0_X6) +#define PORT_PA08B_ADC0_X6 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_X7 _UINT32_(9) +#define MUX_PA09B_ADC0_X7 _UINT32_(1) +#define PINMUX_PA09B_ADC0_X7 ((PIN_PA09B_ADC0_X7 << 16) | MUX_PA09B_ADC0_X7) +#define PORT_PA09B_ADC0_X7 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_X8 _UINT32_(10) +#define MUX_PA10B_ADC0_X8 _UINT32_(1) +#define PINMUX_PA10B_ADC0_X8 ((PIN_PA10B_ADC0_X8 << 16) | MUX_PA10B_ADC0_X8) +#define PORT_PA10B_ADC0_X8 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_X9 _UINT32_(11) +#define MUX_PA11B_ADC0_X9 _UINT32_(1) +#define PINMUX_PA11B_ADC0_X9 ((PIN_PA11B_ADC0_X9 << 16) | MUX_PA11B_ADC0_X9) +#define PORT_PA11B_ADC0_X9 (_UINT32_(1) << 11) + +#define PIN_PA16B_ADC0_X10 _UINT32_(16) +#define MUX_PA16B_ADC0_X10 _UINT32_(1) +#define PINMUX_PA16B_ADC0_X10 ((PIN_PA16B_ADC0_X10 << 16) | MUX_PA16B_ADC0_X10) +#define PORT_PA16B_ADC0_X10 (_UINT32_(1) << 16) + +#define PIN_PA17B_ADC0_X11 _UINT32_(17) +#define MUX_PA17B_ADC0_X11 _UINT32_(1) +#define PINMUX_PA17B_ADC0_X11 ((PIN_PA17B_ADC0_X11 << 16) | MUX_PA17B_ADC0_X11) +#define PORT_PA17B_ADC0_X11 (_UINT32_(1) << 17) + +#define PIN_PA18B_ADC0_X12 _UINT32_(18) +#define MUX_PA18B_ADC0_X12 _UINT32_(1) +#define PINMUX_PA18B_ADC0_X12 ((PIN_PA18B_ADC0_X12 << 16) | MUX_PA18B_ADC0_X12) +#define PORT_PA18B_ADC0_X12 (_UINT32_(1) << 18) + +#define PIN_PA19B_ADC0_X13 _UINT32_(19) +#define MUX_PA19B_ADC0_X13 _UINT32_(1) +#define PINMUX_PA19B_ADC0_X13 ((PIN_PA19B_ADC0_X13 << 16) | MUX_PA19B_ADC0_X13) +#define PORT_PA19B_ADC0_X13 (_UINT32_(1) << 19) + +#define PIN_PA20B_ADC0_X14 _UINT32_(20) +#define MUX_PA20B_ADC0_X14 _UINT32_(1) +#define PINMUX_PA20B_ADC0_X14 ((PIN_PA20B_ADC0_X14 << 16) | MUX_PA20B_ADC0_X14) +#define PORT_PA20B_ADC0_X14 (_UINT32_(1) << 20) + +#define PIN_PA21B_ADC0_X15 _UINT32_(21) +#define MUX_PA21B_ADC0_X15 _UINT32_(1) +#define PINMUX_PA21B_ADC0_X15 ((PIN_PA21B_ADC0_X15 << 16) | MUX_PA21B_ADC0_X15) +#define PORT_PA21B_ADC0_X15 (_UINT32_(1) << 21) + +#define PIN_PA22B_ADC0_X16 _UINT32_(22) +#define MUX_PA22B_ADC0_X16 _UINT32_(1) +#define PINMUX_PA22B_ADC0_X16 ((PIN_PA22B_ADC0_X16 << 16) | MUX_PA22B_ADC0_X16) +#define PORT_PA22B_ADC0_X16 (_UINT32_(1) << 22) + +#define PIN_PA23B_ADC0_X17 _UINT32_(23) +#define MUX_PA23B_ADC0_X17 _UINT32_(1) +#define PINMUX_PA23B_ADC0_X17 ((PIN_PA23B_ADC0_X17 << 16) | MUX_PA23B_ADC0_X17) +#define PORT_PA23B_ADC0_X17 (_UINT32_(1) << 23) + +#define PIN_PA27B_ADC0_X18 _UINT32_(27) +#define MUX_PA27B_ADC0_X18 _UINT32_(1) +#define PINMUX_PA27B_ADC0_X18 ((PIN_PA27B_ADC0_X18 << 16) | MUX_PA27B_ADC0_X18) +#define PORT_PA27B_ADC0_X18 (_UINT32_(1) << 27) + +#define PIN_PA30B_ADC0_X19 _UINT32_(30) +#define MUX_PA30B_ADC0_X19 _UINT32_(1) +#define PINMUX_PA30B_ADC0_X19 ((PIN_PA30B_ADC0_X19 << 16) | MUX_PA30B_ADC0_X19) +#define PORT_PA30B_ADC0_X19 (_UINT32_(1) << 30) + +#define PIN_PB02B_ADC0_X20 _UINT32_(34) +#define MUX_PB02B_ADC0_X20 _UINT32_(1) +#define PINMUX_PB02B_ADC0_X20 ((PIN_PB02B_ADC0_X20 << 16) | MUX_PB02B_ADC0_X20) +#define PORT_PB02B_ADC0_X20 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_X21 _UINT32_(35) +#define MUX_PB03B_ADC0_X21 _UINT32_(1) +#define PINMUX_PB03B_ADC0_X21 ((PIN_PB03B_ADC0_X21 << 16) | MUX_PB03B_ADC0_X21) +#define PORT_PB03B_ADC0_X21 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC0_X22 _UINT32_(36) +#define MUX_PB04B_ADC0_X22 _UINT32_(1) +#define PINMUX_PB04B_ADC0_X22 ((PIN_PB04B_ADC0_X22 << 16) | MUX_PB04B_ADC0_X22) +#define PORT_PB04B_ADC0_X22 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC0_X23 _UINT32_(37) +#define MUX_PB05B_ADC0_X23 _UINT32_(1) +#define PINMUX_PB05B_ADC0_X23 ((PIN_PB05B_ADC0_X23 << 16) | MUX_PB05B_ADC0_X23) +#define PORT_PB05B_ADC0_X23 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC0_X24 _UINT32_(38) +#define MUX_PB06B_ADC0_X24 _UINT32_(1) +#define PINMUX_PB06B_ADC0_X24 ((PIN_PB06B_ADC0_X24 << 16) | MUX_PB06B_ADC0_X24) +#define PORT_PB06B_ADC0_X24 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC0_X25 _UINT32_(39) +#define MUX_PB07B_ADC0_X25 _UINT32_(1) +#define PINMUX_PB07B_ADC0_X25 ((PIN_PB07B_ADC0_X25 << 16) | MUX_PB07B_ADC0_X25) +#define PORT_PB07B_ADC0_X25 (_UINT32_(1) << 7) + +#define PIN_PB12B_ADC0_X26 _UINT32_(44) +#define MUX_PB12B_ADC0_X26 _UINT32_(1) +#define PINMUX_PB12B_ADC0_X26 ((PIN_PB12B_ADC0_X26 << 16) | MUX_PB12B_ADC0_X26) +#define PORT_PB12B_ADC0_X26 (_UINT32_(1) << 12) + +#define PIN_PB13B_ADC0_X27 _UINT32_(45) +#define MUX_PB13B_ADC0_X27 _UINT32_(1) +#define PINMUX_PB13B_ADC0_X27 ((PIN_PB13B_ADC0_X27 << 16) | MUX_PB13B_ADC0_X27) +#define PORT_PB13B_ADC0_X27 (_UINT32_(1) << 13) + +#define PIN_PB14B_ADC0_X28 _UINT32_(46) +#define MUX_PB14B_ADC0_X28 _UINT32_(1) +#define PINMUX_PB14B_ADC0_X28 ((PIN_PB14B_ADC0_X28 << 16) | MUX_PB14B_ADC0_X28) +#define PORT_PB14B_ADC0_X28 (_UINT32_(1) << 14) + +#define PIN_PB15B_ADC0_X29 _UINT32_(47) +#define MUX_PB15B_ADC0_X29 _UINT32_(1) +#define PINMUX_PB15B_ADC0_X29 ((PIN_PB15B_ADC0_X29 << 16) | MUX_PB15B_ADC0_X29) +#define PORT_PB15B_ADC0_X29 (_UINT32_(1) << 15) + +#define PIN_PB00B_ADC0_X30 _UINT32_(32) +#define MUX_PB00B_ADC0_X30 _UINT32_(1) +#define PINMUX_PB00B_ADC0_X30 ((PIN_PB00B_ADC0_X30 << 16) | MUX_PB00B_ADC0_X30) +#define PORT_PB00B_ADC0_X30 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_X31 _UINT32_(33) +#define MUX_PB01B_ADC0_X31 _UINT32_(1) +#define PINMUX_PB01B_ADC0_X31 ((PIN_PB01B_ADC0_X31 << 16) | MUX_PB01B_ADC0_X31) +#define PORT_PB01B_ADC0_X31 (_UINT32_(1) << 1) + +#define PIN_PA03B_ADC0_Y0 _UINT32_(3) +#define MUX_PA03B_ADC0_Y0 _UINT32_(1) +#define PINMUX_PA03B_ADC0_Y0 ((PIN_PA03B_ADC0_Y0 << 16) | MUX_PA03B_ADC0_Y0) +#define PORT_PA03B_ADC0_Y0 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_Y1 _UINT32_(40) +#define MUX_PB08B_ADC0_Y1 _UINT32_(1) +#define PINMUX_PB08B_ADC0_Y1 ((PIN_PB08B_ADC0_Y1 << 16) | MUX_PB08B_ADC0_Y1) +#define PORT_PB08B_ADC0_Y1 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_Y2 _UINT32_(41) +#define MUX_PB09B_ADC0_Y2 _UINT32_(1) +#define PINMUX_PB09B_ADC0_Y2 ((PIN_PB09B_ADC0_Y2 << 16) | MUX_PB09B_ADC0_Y2) +#define PORT_PB09B_ADC0_Y2 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_Y3 _UINT32_(4) +#define MUX_PA04B_ADC0_Y3 _UINT32_(1) +#define PINMUX_PA04B_ADC0_Y3 ((PIN_PA04B_ADC0_Y3 << 16) | MUX_PA04B_ADC0_Y3) +#define PORT_PA04B_ADC0_Y3 (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_Y4 _UINT32_(6) +#define MUX_PA06B_ADC0_Y4 _UINT32_(1) +#define PINMUX_PA06B_ADC0_Y4 ((PIN_PA06B_ADC0_Y4 << 16) | MUX_PA06B_ADC0_Y4) +#define PORT_PA06B_ADC0_Y4 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_Y5 _UINT32_(7) +#define MUX_PA07B_ADC0_Y5 _UINT32_(1) +#define PINMUX_PA07B_ADC0_Y5 ((PIN_PA07B_ADC0_Y5 << 16) | MUX_PA07B_ADC0_Y5) +#define PORT_PA07B_ADC0_Y5 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_Y6 _UINT32_(8) +#define MUX_PA08B_ADC0_Y6 _UINT32_(1) +#define PINMUX_PA08B_ADC0_Y6 ((PIN_PA08B_ADC0_Y6 << 16) | MUX_PA08B_ADC0_Y6) +#define PORT_PA08B_ADC0_Y6 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_Y7 _UINT32_(9) +#define MUX_PA09B_ADC0_Y7 _UINT32_(1) +#define PINMUX_PA09B_ADC0_Y7 ((PIN_PA09B_ADC0_Y7 << 16) | MUX_PA09B_ADC0_Y7) +#define PORT_PA09B_ADC0_Y7 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_Y8 _UINT32_(10) +#define MUX_PA10B_ADC0_Y8 _UINT32_(1) +#define PINMUX_PA10B_ADC0_Y8 ((PIN_PA10B_ADC0_Y8 << 16) | MUX_PA10B_ADC0_Y8) +#define PORT_PA10B_ADC0_Y8 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_Y9 _UINT32_(11) +#define MUX_PA11B_ADC0_Y9 _UINT32_(1) +#define PINMUX_PA11B_ADC0_Y9 ((PIN_PA11B_ADC0_Y9 << 16) | MUX_PA11B_ADC0_Y9) +#define PORT_PA11B_ADC0_Y9 (_UINT32_(1) << 11) + +#define PIN_PA16B_ADC0_Y10 _UINT32_(16) +#define MUX_PA16B_ADC0_Y10 _UINT32_(1) +#define PINMUX_PA16B_ADC0_Y10 ((PIN_PA16B_ADC0_Y10 << 16) | MUX_PA16B_ADC0_Y10) +#define PORT_PA16B_ADC0_Y10 (_UINT32_(1) << 16) + +#define PIN_PA17B_ADC0_Y11 _UINT32_(17) +#define MUX_PA17B_ADC0_Y11 _UINT32_(1) +#define PINMUX_PA17B_ADC0_Y11 ((PIN_PA17B_ADC0_Y11 << 16) | MUX_PA17B_ADC0_Y11) +#define PORT_PA17B_ADC0_Y11 (_UINT32_(1) << 17) + +#define PIN_PA18B_ADC0_Y12 _UINT32_(18) +#define MUX_PA18B_ADC0_Y12 _UINT32_(1) +#define PINMUX_PA18B_ADC0_Y12 ((PIN_PA18B_ADC0_Y12 << 16) | MUX_PA18B_ADC0_Y12) +#define PORT_PA18B_ADC0_Y12 (_UINT32_(1) << 18) + +#define PIN_PA19B_ADC0_Y13 _UINT32_(19) +#define MUX_PA19B_ADC0_Y13 _UINT32_(1) +#define PINMUX_PA19B_ADC0_Y13 ((PIN_PA19B_ADC0_Y13 << 16) | MUX_PA19B_ADC0_Y13) +#define PORT_PA19B_ADC0_Y13 (_UINT32_(1) << 19) + +#define PIN_PA20B_ADC0_Y14 _UINT32_(20) +#define MUX_PA20B_ADC0_Y14 _UINT32_(1) +#define PINMUX_PA20B_ADC0_Y14 ((PIN_PA20B_ADC0_Y14 << 16) | MUX_PA20B_ADC0_Y14) +#define PORT_PA20B_ADC0_Y14 (_UINT32_(1) << 20) + +#define PIN_PA21B_ADC0_Y15 _UINT32_(21) +#define MUX_PA21B_ADC0_Y15 _UINT32_(1) +#define PINMUX_PA21B_ADC0_Y15 ((PIN_PA21B_ADC0_Y15 << 16) | MUX_PA21B_ADC0_Y15) +#define PORT_PA21B_ADC0_Y15 (_UINT32_(1) << 21) + +#define PIN_PA22B_ADC0_Y16 _UINT32_(22) +#define MUX_PA22B_ADC0_Y16 _UINT32_(1) +#define PINMUX_PA22B_ADC0_Y16 ((PIN_PA22B_ADC0_Y16 << 16) | MUX_PA22B_ADC0_Y16) +#define PORT_PA22B_ADC0_Y16 (_UINT32_(1) << 22) + +#define PIN_PA23B_ADC0_Y17 _UINT32_(23) +#define MUX_PA23B_ADC0_Y17 _UINT32_(1) +#define PINMUX_PA23B_ADC0_Y17 ((PIN_PA23B_ADC0_Y17 << 16) | MUX_PA23B_ADC0_Y17) +#define PORT_PA23B_ADC0_Y17 (_UINT32_(1) << 23) + +#define PIN_PA27B_ADC0_Y18 _UINT32_(27) +#define MUX_PA27B_ADC0_Y18 _UINT32_(1) +#define PINMUX_PA27B_ADC0_Y18 ((PIN_PA27B_ADC0_Y18 << 16) | MUX_PA27B_ADC0_Y18) +#define PORT_PA27B_ADC0_Y18 (_UINT32_(1) << 27) + +#define PIN_PA30B_ADC0_Y19 _UINT32_(30) +#define MUX_PA30B_ADC0_Y19 _UINT32_(1) +#define PINMUX_PA30B_ADC0_Y19 ((PIN_PA30B_ADC0_Y19 << 16) | MUX_PA30B_ADC0_Y19) +#define PORT_PA30B_ADC0_Y19 (_UINT32_(1) << 30) + +#define PIN_PB02B_ADC0_Y20 _UINT32_(34) +#define MUX_PB02B_ADC0_Y20 _UINT32_(1) +#define PINMUX_PB02B_ADC0_Y20 ((PIN_PB02B_ADC0_Y20 << 16) | MUX_PB02B_ADC0_Y20) +#define PORT_PB02B_ADC0_Y20 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_Y21 _UINT32_(35) +#define MUX_PB03B_ADC0_Y21 _UINT32_(1) +#define PINMUX_PB03B_ADC0_Y21 ((PIN_PB03B_ADC0_Y21 << 16) | MUX_PB03B_ADC0_Y21) +#define PORT_PB03B_ADC0_Y21 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC0_Y22 _UINT32_(36) +#define MUX_PB04B_ADC0_Y22 _UINT32_(1) +#define PINMUX_PB04B_ADC0_Y22 ((PIN_PB04B_ADC0_Y22 << 16) | MUX_PB04B_ADC0_Y22) +#define PORT_PB04B_ADC0_Y22 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC0_Y23 _UINT32_(37) +#define MUX_PB05B_ADC0_Y23 _UINT32_(1) +#define PINMUX_PB05B_ADC0_Y23 ((PIN_PB05B_ADC0_Y23 << 16) | MUX_PB05B_ADC0_Y23) +#define PORT_PB05B_ADC0_Y23 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC0_Y24 _UINT32_(38) +#define MUX_PB06B_ADC0_Y24 _UINT32_(1) +#define PINMUX_PB06B_ADC0_Y24 ((PIN_PB06B_ADC0_Y24 << 16) | MUX_PB06B_ADC0_Y24) +#define PORT_PB06B_ADC0_Y24 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC0_Y25 _UINT32_(39) +#define MUX_PB07B_ADC0_Y25 _UINT32_(1) +#define PINMUX_PB07B_ADC0_Y25 ((PIN_PB07B_ADC0_Y25 << 16) | MUX_PB07B_ADC0_Y25) +#define PORT_PB07B_ADC0_Y25 (_UINT32_(1) << 7) + +#define PIN_PB12B_ADC0_Y26 _UINT32_(44) +#define MUX_PB12B_ADC0_Y26 _UINT32_(1) +#define PINMUX_PB12B_ADC0_Y26 ((PIN_PB12B_ADC0_Y26 << 16) | MUX_PB12B_ADC0_Y26) +#define PORT_PB12B_ADC0_Y26 (_UINT32_(1) << 12) + +#define PIN_PB13B_ADC0_Y27 _UINT32_(45) +#define MUX_PB13B_ADC0_Y27 _UINT32_(1) +#define PINMUX_PB13B_ADC0_Y27 ((PIN_PB13B_ADC0_Y27 << 16) | MUX_PB13B_ADC0_Y27) +#define PORT_PB13B_ADC0_Y27 (_UINT32_(1) << 13) + +#define PIN_PB14B_ADC0_Y28 _UINT32_(46) +#define MUX_PB14B_ADC0_Y28 _UINT32_(1) +#define PINMUX_PB14B_ADC0_Y28 ((PIN_PB14B_ADC0_Y28 << 16) | MUX_PB14B_ADC0_Y28) +#define PORT_PB14B_ADC0_Y28 (_UINT32_(1) << 14) + +#define PIN_PB15B_ADC0_Y29 _UINT32_(47) +#define MUX_PB15B_ADC0_Y29 _UINT32_(1) +#define PINMUX_PB15B_ADC0_Y29 ((PIN_PB15B_ADC0_Y29 << 16) | MUX_PB15B_ADC0_Y29) +#define PORT_PB15B_ADC0_Y29 (_UINT32_(1) << 15) + +#define PIN_PB00B_ADC0_Y30 _UINT32_(32) +#define MUX_PB00B_ADC0_Y30 _UINT32_(1) +#define PINMUX_PB00B_ADC0_Y30 ((PIN_PB00B_ADC0_Y30 << 16) | MUX_PB00B_ADC0_Y30) +#define PORT_PB00B_ADC0_Y30 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_Y31 _UINT32_(33) +#define MUX_PB01B_ADC0_Y31 _UINT32_(1) +#define PINMUX_PB01B_ADC0_Y31 ((PIN_PB01B_ADC0_Y31 << 16) | MUX_PB01B_ADC0_Y31) +#define PORT_PB01B_ADC0_Y31 (_UINT32_(1) << 1) + +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _UINT32_(40) +#define MUX_PB08B_ADC1_AIN0 _UINT32_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC1_AIN1 _UINT32_(41) +#define MUX_PB09B_ADC1_AIN1 _UINT32_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UINT32_(1) << 9) + +#define PIN_PA08B_ADC1_AIN2 _UINT32_(8) +#define MUX_PA08B_ADC1_AIN2 _UINT32_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC1_AIN3 _UINT32_(9) +#define MUX_PA09B_ADC1_AIN3 _UINT32_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UINT32_(1) << 9) + +#define PIN_PC02B_ADC1_AIN4 _UINT32_(66) +#define MUX_PC02B_ADC1_AIN4 _UINT32_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UINT32_(1) << 2) + +#define PIN_PC03B_ADC1_AIN5 _UINT32_(67) +#define MUX_PC03B_ADC1_AIN5 _UINT32_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC1_AIN6 _UINT32_(36) +#define MUX_PB04B_ADC1_AIN6 _UINT32_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC1_AIN7 _UINT32_(37) +#define MUX_PB05B_ADC1_AIN7 _UINT32_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC1_AIN8 _UINT32_(38) +#define MUX_PB06B_ADC1_AIN8 _UINT32_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC1_AIN9 _UINT32_(39) +#define MUX_PB07B_ADC1_AIN9 _UINT32_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UINT32_(1) << 7) + +#define PIN_PC00B_ADC1_AIN10 _UINT32_(64) +#define MUX_PC00B_ADC1_AIN10 _UINT32_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UINT32_(1) << 0) + +#define PIN_PC01B_ADC1_AIN11 _UINT32_(65) +#define MUX_PC01B_ADC1_AIN11 _UINT32_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UINT32_(1) << 1) + +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _UINT32_(23) +#define MUX_PA23I_CAN0_RX _UINT32_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UINT32_(1) << 23) + +#define PIN_PA25I_CAN0_RX _UINT32_(25) +#define MUX_PA25I_CAN0_RX _UINT32_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UINT32_(1) << 25) + +#define PIN_PA22I_CAN0_TX _UINT32_(22) +#define MUX_PA22I_CAN0_TX _UINT32_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UINT32_(1) << 22) + +#define PIN_PA24I_CAN0_TX _UINT32_(24) +#define MUX_PA24I_CAN0_TX _UINT32_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UINT32_(1) << 24) + +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _UINT32_(45) +#define MUX_PB13H_CAN1_RX _UINT32_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UINT32_(1) << 13) + +#define PIN_PB15H_CAN1_RX _UINT32_(47) +#define MUX_PB15H_CAN1_RX _UINT32_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UINT32_(1) << 15) + +#define PIN_PB12H_CAN1_TX _UINT32_(44) +#define MUX_PB12H_CAN1_TX _UINT32_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UINT32_(1) << 12) + +#define PIN_PB14H_CAN1_TX _UINT32_(46) +#define MUX_PB14H_CAN1_TX _UINT32_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UINT32_(1) << 14) + +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _UINT32_(4) +#define MUX_PA04N_CCL_IN0 _UINT32_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UINT32_(1) << 4) + +#define PIN_PA16N_CCL_IN0 _UINT32_(16) +#define MUX_PA16N_CCL_IN0 _UINT32_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UINT32_(1) << 16) + +#define PIN_PB22N_CCL_IN0 _UINT32_(54) +#define MUX_PB22N_CCL_IN0 _UINT32_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UINT32_(1) << 22) + +#define PIN_PA05N_CCL_IN1 _UINT32_(5) +#define MUX_PA05N_CCL_IN1 _UINT32_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UINT32_(1) << 5) + +#define PIN_PA17N_CCL_IN1 _UINT32_(17) +#define MUX_PA17N_CCL_IN1 _UINT32_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UINT32_(1) << 17) + +#define PIN_PB00N_CCL_IN1 _UINT32_(32) +#define MUX_PB00N_CCL_IN1 _UINT32_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UINT32_(1) << 0) + +#define PIN_PA06N_CCL_IN2 _UINT32_(6) +#define MUX_PA06N_CCL_IN2 _UINT32_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UINT32_(1) << 6) + +#define PIN_PA18N_CCL_IN2 _UINT32_(18) +#define MUX_PA18N_CCL_IN2 _UINT32_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UINT32_(1) << 18) + +#define PIN_PB01N_CCL_IN2 _UINT32_(33) +#define MUX_PB01N_CCL_IN2 _UINT32_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UINT32_(1) << 1) + +#define PIN_PA08N_CCL_IN3 _UINT32_(8) +#define MUX_PA08N_CCL_IN3 _UINT32_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UINT32_(1) << 8) + +#define PIN_PA30N_CCL_IN3 _UINT32_(30) +#define MUX_PA30N_CCL_IN3 _UINT32_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UINT32_(1) << 30) + +#define PIN_PA09N_CCL_IN4 _UINT32_(9) +#define MUX_PA09N_CCL_IN4 _UINT32_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UINT32_(1) << 9) + +#define PIN_PC27N_CCL_IN4 _UINT32_(91) +#define MUX_PC27N_CCL_IN4 _UINT32_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UINT32_(1) << 27) + +#define PIN_PA10N_CCL_IN5 _UINT32_(10) +#define MUX_PA10N_CCL_IN5 _UINT32_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UINT32_(1) << 10) + +#define PIN_PC28N_CCL_IN5 _UINT32_(92) +#define MUX_PC28N_CCL_IN5 _UINT32_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UINT32_(1) << 28) + +#define PIN_PA22N_CCL_IN6 _UINT32_(22) +#define MUX_PA22N_CCL_IN6 _UINT32_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UINT32_(1) << 22) + +#define PIN_PB06N_CCL_IN6 _UINT32_(38) +#define MUX_PB06N_CCL_IN6 _UINT32_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UINT32_(1) << 6) + +#define PIN_PA23N_CCL_IN7 _UINT32_(23) +#define MUX_PA23N_CCL_IN7 _UINT32_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UINT32_(1) << 23) + +#define PIN_PB07N_CCL_IN7 _UINT32_(39) +#define MUX_PB07N_CCL_IN7 _UINT32_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UINT32_(1) << 7) + +#define PIN_PA24N_CCL_IN8 _UINT32_(24) +#define MUX_PA24N_CCL_IN8 _UINT32_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UINT32_(1) << 24) + +#define PIN_PB08N_CCL_IN8 _UINT32_(40) +#define MUX_PB08N_CCL_IN8 _UINT32_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UINT32_(1) << 8) + +#define PIN_PB14N_CCL_IN9 _UINT32_(46) +#define MUX_PB14N_CCL_IN9 _UINT32_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UINT32_(1) << 14) + +#define PIN_PC20N_CCL_IN9 _UINT32_(84) +#define MUX_PC20N_CCL_IN9 _UINT32_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UINT32_(1) << 20) + +#define PIN_PB15N_CCL_IN10 _UINT32_(47) +#define MUX_PB15N_CCL_IN10 _UINT32_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UINT32_(1) << 15) + +#define PIN_PC21N_CCL_IN10 _UINT32_(85) +#define MUX_PC21N_CCL_IN10 _UINT32_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UINT32_(1) << 21) + +#define PIN_PB10N_CCL_IN11 _UINT32_(42) +#define MUX_PB10N_CCL_IN11 _UINT32_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UINT32_(1) << 10) + +#define PIN_PB16N_CCL_IN11 _UINT32_(48) +#define MUX_PB16N_CCL_IN11 _UINT32_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UINT32_(1) << 16) + +#define PIN_PA07N_CCL_OUT0 _UINT32_(7) +#define MUX_PA07N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UINT32_(1) << 7) + +#define PIN_PA19N_CCL_OUT0 _UINT32_(19) +#define MUX_PA19N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UINT32_(1) << 19) + +#define PIN_PB02N_CCL_OUT0 _UINT32_(34) +#define MUX_PB02N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UINT32_(1) << 2) + +#define PIN_PB23N_CCL_OUT0 _UINT32_(55) +#define MUX_PB23N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UINT32_(1) << 23) + +#define PIN_PA11N_CCL_OUT1 _UINT32_(11) +#define MUX_PA11N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UINT32_(1) << 11) + +#define PIN_PA31N_CCL_OUT1 _UINT32_(31) +#define MUX_PA31N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UINT32_(1) << 31) + +#define PIN_PB11N_CCL_OUT1 _UINT32_(43) +#define MUX_PB11N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UINT32_(1) << 11) + +#define PIN_PA25N_CCL_OUT2 _UINT32_(25) +#define MUX_PA25N_CCL_OUT2 _UINT32_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UINT32_(1) << 25) + +#define PIN_PB09N_CCL_OUT2 _UINT32_(41) +#define MUX_PB09N_CCL_OUT2 _UINT32_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UINT32_(1) << 9) + +#define PIN_PB17N_CCL_OUT3 _UINT32_(49) +#define MUX_PB17N_CCL_OUT3 _UINT32_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UINT32_(1) << 17) + +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _UINT32_(2) +#define MUX_PA02B_DAC_VOUT0 _UINT32_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UINT32_(1) << 2) + +#define PIN_PA05B_DAC_VOUT1 _UINT32_(5) +#define MUX_PA05B_DAC_VOUT1 _UINT32_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UINT32_(1) << 5) + +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _UINT32_(0) +#define MUX_PA00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA00 External Interrupt Line */ + +#define PIN_PA16A_EIC_EXTINT0 _UINT32_(16) +#define MUX_PA16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA16 External Interrupt Line */ + +#define PIN_PB00A_EIC_EXTINT0 _UINT32_(32) +#define MUX_PB00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB00 External Interrupt Line */ + +#define PIN_PB16A_EIC_EXTINT0 _UINT32_(48) +#define MUX_PB16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB16 External Interrupt Line */ + +#define PIN_PC00A_EIC_EXTINT0 _UINT32_(64) +#define MUX_PC00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PC00 External Interrupt Line */ + +#define PIN_PC16A_EIC_EXTINT0 _UINT32_(80) +#define MUX_PC16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PC16 External Interrupt Line */ + +#define PIN_PA01A_EIC_EXTINT1 _UINT32_(1) +#define MUX_PA01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA01 External Interrupt Line */ + +#define PIN_PA17A_EIC_EXTINT1 _UINT32_(17) +#define MUX_PA17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA17 External Interrupt Line */ + +#define PIN_PB01A_EIC_EXTINT1 _UINT32_(33) +#define MUX_PB01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB01 External Interrupt Line */ + +#define PIN_PB17A_EIC_EXTINT1 _UINT32_(49) +#define MUX_PB17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB17 External Interrupt Line */ + +#define PIN_PC01A_EIC_EXTINT1 _UINT32_(65) +#define MUX_PC01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PC01 External Interrupt Line */ + +#define PIN_PC17A_EIC_EXTINT1 _UINT32_(81) +#define MUX_PC17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PC17 External Interrupt Line */ + +#define PIN_PA02A_EIC_EXTINT2 _UINT32_(2) +#define MUX_PA02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA02 External Interrupt Line */ + +#define PIN_PA18A_EIC_EXTINT2 _UINT32_(18) +#define MUX_PA18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA18 External Interrupt Line */ + +#define PIN_PB02A_EIC_EXTINT2 _UINT32_(34) +#define MUX_PB02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB02 External Interrupt Line */ + +#define PIN_PB18A_EIC_EXTINT2 _UINT32_(50) +#define MUX_PB18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB18 External Interrupt Line */ + +#define PIN_PC02A_EIC_EXTINT2 _UINT32_(66) +#define MUX_PC02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PC02 External Interrupt Line */ + +#define PIN_PC18A_EIC_EXTINT2 _UINT32_(82) +#define MUX_PC18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PC18 External Interrupt Line */ + +#define PIN_PA03A_EIC_EXTINT3 _UINT32_(3) +#define MUX_PA03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA03 External Interrupt Line */ + +#define PIN_PA19A_EIC_EXTINT3 _UINT32_(19) +#define MUX_PA19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA19 External Interrupt Line */ + +#define PIN_PB03A_EIC_EXTINT3 _UINT32_(35) +#define MUX_PB03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB03 External Interrupt Line */ + +#define PIN_PB19A_EIC_EXTINT3 _UINT32_(51) +#define MUX_PB19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB19 External Interrupt Line */ + +#define PIN_PC03A_EIC_EXTINT3 _UINT32_(67) +#define MUX_PC03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PC03 External Interrupt Line */ + +#define PIN_PC19A_EIC_EXTINT3 _UINT32_(83) +#define MUX_PC19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PC19 External Interrupt Line */ + +#define PIN_PA04A_EIC_EXTINT4 _UINT32_(4) +#define MUX_PA04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA04 External Interrupt Line */ + +#define PIN_PA20A_EIC_EXTINT4 _UINT32_(20) +#define MUX_PA20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA20 External Interrupt Line */ + +#define PIN_PB04A_EIC_EXTINT4 _UINT32_(36) +#define MUX_PB04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB04 External Interrupt Line */ + +#define PIN_PB20A_EIC_EXTINT4 _UINT32_(52) +#define MUX_PB20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB20 External Interrupt Line */ + +#define PIN_PC20A_EIC_EXTINT4 _UINT32_(84) +#define MUX_PC20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PC20 External Interrupt Line */ + +#define PIN_PA05A_EIC_EXTINT5 _UINT32_(5) +#define MUX_PA05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA05 External Interrupt Line */ + +#define PIN_PA21A_EIC_EXTINT5 _UINT32_(21) +#define MUX_PA21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA21 External Interrupt Line */ + +#define PIN_PB05A_EIC_EXTINT5 _UINT32_(37) +#define MUX_PB05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB05 External Interrupt Line */ + +#define PIN_PB21A_EIC_EXTINT5 _UINT32_(53) +#define MUX_PB21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB21 External Interrupt Line */ + +#define PIN_PC05A_EIC_EXTINT5 _UINT32_(69) +#define MUX_PC05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PC05 External Interrupt Line */ + +#define PIN_PC21A_EIC_EXTINT5 _UINT32_(85) +#define MUX_PC21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PC21 External Interrupt Line */ + +#define PIN_PA06A_EIC_EXTINT6 _UINT32_(6) +#define MUX_PA06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA06 External Interrupt Line */ + +#define PIN_PA22A_EIC_EXTINT6 _UINT32_(22) +#define MUX_PA22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA22 External Interrupt Line */ + +#define PIN_PB06A_EIC_EXTINT6 _UINT32_(38) +#define MUX_PB06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB06 External Interrupt Line */ + +#define PIN_PB22A_EIC_EXTINT6 _UINT32_(54) +#define MUX_PB22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB22 External Interrupt Line */ + +#define PIN_PC06A_EIC_EXTINT6 _UINT32_(70) +#define MUX_PC06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PC06 External Interrupt Line */ + +#define PIN_PA07A_EIC_EXTINT7 _UINT32_(7) +#define MUX_PA07A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UINT32_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA07 External Interrupt Line */ + +#define PIN_PA23A_EIC_EXTINT7 _UINT32_(23) +#define MUX_PA23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA23 External Interrupt Line */ + +#define PIN_PB07A_EIC_EXTINT7 _UINT32_(39) +#define MUX_PB07A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UINT32_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB07 External Interrupt Line */ + +#define PIN_PB23A_EIC_EXTINT7 _UINT32_(55) +#define MUX_PB23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB23 External Interrupt Line */ + +#define PIN_PA24A_EIC_EXTINT8 _UINT32_(24) +#define MUX_PA24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PA24 External Interrupt Line */ + +#define PIN_PB08A_EIC_EXTINT8 _UINT32_(40) +#define MUX_PB08A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UINT32_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PB08 External Interrupt Line */ + +#define PIN_PB24A_EIC_EXTINT8 _UINT32_(56) +#define MUX_PB24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PB24 External Interrupt Line */ + +#define PIN_PC24A_EIC_EXTINT8 _UINT32_(88) +#define MUX_PC24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PC24 External Interrupt Line */ + +#define PIN_PA09A_EIC_EXTINT9 _UINT32_(9) +#define MUX_PA09A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UINT32_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA09 External Interrupt Line */ + +#define PIN_PA25A_EIC_EXTINT9 _UINT32_(25) +#define MUX_PA25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA25 External Interrupt Line */ + +#define PIN_PB09A_EIC_EXTINT9 _UINT32_(41) +#define MUX_PB09A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UINT32_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PB09 External Interrupt Line */ + +#define PIN_PB25A_EIC_EXTINT9 _UINT32_(57) +#define MUX_PB25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PB25 External Interrupt Line */ + +#define PIN_PC07A_EIC_EXTINT9 _UINT32_(71) +#define MUX_PC07A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UINT32_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PC07 External Interrupt Line */ + +#define PIN_PC25A_EIC_EXTINT9 _UINT32_(89) +#define MUX_PC25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PC25 External Interrupt Line */ + +#define PIN_PA10A_EIC_EXTINT10 _UINT32_(10) +#define MUX_PA10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PA10 External Interrupt Line */ + +#define PIN_PB10A_EIC_EXTINT10 _UINT32_(42) +#define MUX_PB10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PB10 External Interrupt Line */ + +#define PIN_PC10A_EIC_EXTINT10 _UINT32_(74) +#define MUX_PC10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PC10 External Interrupt Line */ + +#define PIN_PC26A_EIC_EXTINT10 _UINT32_(90) +#define MUX_PC26A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UINT32_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PC26 External Interrupt Line */ + +#define PIN_PA11A_EIC_EXTINT11 _UINT32_(11) +#define MUX_PA11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA11 External Interrupt Line */ + +#define PIN_PA27A_EIC_EXTINT11 _UINT32_(27) +#define MUX_PA27A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UINT32_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA27 External Interrupt Line */ + +#define PIN_PB11A_EIC_EXTINT11 _UINT32_(43) +#define MUX_PB11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PB11 External Interrupt Line */ + +#define PIN_PC11A_EIC_EXTINT11 _UINT32_(75) +#define MUX_PC11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PC11 External Interrupt Line */ + +#define PIN_PC27A_EIC_EXTINT11 _UINT32_(91) +#define MUX_PC27A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UINT32_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PC27 External Interrupt Line */ + +#define PIN_PA12A_EIC_EXTINT12 _UINT32_(12) +#define MUX_PA12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PA12 External Interrupt Line */ + +#define PIN_PB12A_EIC_EXTINT12 _UINT32_(44) +#define MUX_PB12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PB12 External Interrupt Line */ + +#define PIN_PC12A_EIC_EXTINT12 _UINT32_(76) +#define MUX_PC12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PC12 External Interrupt Line */ + +#define PIN_PC28A_EIC_EXTINT12 _UINT32_(92) +#define MUX_PC28A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UINT32_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PC28 External Interrupt Line */ + +#define PIN_PA13A_EIC_EXTINT13 _UINT32_(13) +#define MUX_PA13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PA13 External Interrupt Line */ + +#define PIN_PB13A_EIC_EXTINT13 _UINT32_(45) +#define MUX_PB13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PB13 External Interrupt Line */ + +#define PIN_PC13A_EIC_EXTINT13 _UINT32_(77) +#define MUX_PC13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PC13 External Interrupt Line */ + +#define PIN_PA30A_EIC_EXTINT14 _UINT32_(30) +#define MUX_PA30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA30 External Interrupt Line */ + +#define PIN_PB14A_EIC_EXTINT14 _UINT32_(46) +#define MUX_PB14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB14 External Interrupt Line */ + +#define PIN_PB30A_EIC_EXTINT14 _UINT32_(62) +#define MUX_PB30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB30 External Interrupt Line */ + +#define PIN_PC14A_EIC_EXTINT14 _UINT32_(78) +#define MUX_PC14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PC14 External Interrupt Line */ + +#define PIN_PA14A_EIC_EXTINT14 _UINT32_(14) +#define MUX_PA14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA14 External Interrupt Line */ + +#define PIN_PA15A_EIC_EXTINT15 _UINT32_(15) +#define MUX_PA15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA15 External Interrupt Line */ + +#define PIN_PA31A_EIC_EXTINT15 _UINT32_(31) +#define MUX_PA31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA31 External Interrupt Line */ + +#define PIN_PB15A_EIC_EXTINT15 _UINT32_(47) +#define MUX_PB15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB15 External Interrupt Line */ + +#define PIN_PB31A_EIC_EXTINT15 _UINT32_(63) +#define MUX_PB31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB31 External Interrupt Line */ + +#define PIN_PC15A_EIC_EXTINT15 _UINT32_(79) +#define MUX_PC15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PC15 External Interrupt Line */ + +#define PIN_PA08A_EIC_NMI _UINT32_(8) +#define MUX_PA08A_EIC_NMI _UINT32_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UINT32_(1) << 8) + +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _UINT32_(30) +#define MUX_PA30M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UINT32_(1) << 30) + +#define PIN_PB14M_GCLK_IO0 _UINT32_(46) +#define MUX_PB14M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UINT32_(1) << 14) + +#define PIN_PA14M_GCLK_IO0 _UINT32_(14) +#define MUX_PA14M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UINT32_(1) << 14) + +#define PIN_PB22M_GCLK_IO0 _UINT32_(54) +#define MUX_PB22M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UINT32_(1) << 22) + +#define PIN_PB15M_GCLK_IO1 _UINT32_(47) +#define MUX_PB15M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UINT32_(1) << 15) + +#define PIN_PA15M_GCLK_IO1 _UINT32_(15) +#define MUX_PA15M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UINT32_(1) << 15) + +#define PIN_PB23M_GCLK_IO1 _UINT32_(55) +#define MUX_PB23M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UINT32_(1) << 23) + +#define PIN_PA27M_GCLK_IO1 _UINT32_(27) +#define MUX_PA27M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UINT32_(1) << 27) + +#define PIN_PA16M_GCLK_IO2 _UINT32_(16) +#define MUX_PA16M_GCLK_IO2 _UINT32_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UINT32_(1) << 16) + +#define PIN_PB16M_GCLK_IO2 _UINT32_(48) +#define MUX_PB16M_GCLK_IO2 _UINT32_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UINT32_(1) << 16) + +#define PIN_PA17M_GCLK_IO3 _UINT32_(17) +#define MUX_PA17M_GCLK_IO3 _UINT32_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UINT32_(1) << 17) + +#define PIN_PB17M_GCLK_IO3 _UINT32_(49) +#define MUX_PB17M_GCLK_IO3 _UINT32_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UINT32_(1) << 17) + +#define PIN_PA10M_GCLK_IO4 _UINT32_(10) +#define MUX_PA10M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UINT32_(1) << 10) + +#define PIN_PB10M_GCLK_IO4 _UINT32_(42) +#define MUX_PB10M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UINT32_(1) << 10) + +#define PIN_PB18M_GCLK_IO4 _UINT32_(50) +#define MUX_PB18M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UINT32_(1) << 18) + +#define PIN_PA11M_GCLK_IO5 _UINT32_(11) +#define MUX_PA11M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UINT32_(1) << 11) + +#define PIN_PB11M_GCLK_IO5 _UINT32_(43) +#define MUX_PB11M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UINT32_(1) << 11) + +#define PIN_PB19M_GCLK_IO5 _UINT32_(51) +#define MUX_PB19M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UINT32_(1) << 19) + +#define PIN_PB12M_GCLK_IO6 _UINT32_(44) +#define MUX_PB12M_GCLK_IO6 _UINT32_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UINT32_(1) << 12) + +#define PIN_PB20M_GCLK_IO6 _UINT32_(52) +#define MUX_PB20M_GCLK_IO6 _UINT32_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UINT32_(1) << 20) + +#define PIN_PB13M_GCLK_IO7 _UINT32_(45) +#define MUX_PB13M_GCLK_IO7 _UINT32_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UINT32_(1) << 13) + +#define PIN_PB21M_GCLK_IO7 _UINT32_(53) +#define MUX_PB21M_GCLK_IO7 _UINT32_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UINT32_(1) << 21) + +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _UINT32_(85) +#define MUX_PC21L_GMAC_GCOL _UINT32_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UINT32_(1) << 21) + +#define PIN_PA16L_GMAC_GCRS _UINT32_(16) +#define MUX_PA16L_GMAC_GCRS _UINT32_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UINT32_(1) << 16) + +#define PIN_PA20L_GMAC_GMDC _UINT32_(20) +#define MUX_PA20L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UINT32_(1) << 20) + +#define PIN_PB14L_GMAC_GMDC _UINT32_(46) +#define MUX_PB14L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UINT32_(1) << 14) + +#define PIN_PC11L_GMAC_GMDC _UINT32_(75) +#define MUX_PC11L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UINT32_(1) << 11) + +#define PIN_PA21L_GMAC_GMDIO _UINT32_(21) +#define MUX_PA21L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UINT32_(1) << 21) + +#define PIN_PB15L_GMAC_GMDIO _UINT32_(47) +#define MUX_PB15L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UINT32_(1) << 15) + +#define PIN_PC12L_GMAC_GMDIO _UINT32_(76) +#define MUX_PC12L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UINT32_(1) << 12) + +#define PIN_PA13L_GMAC_GRX0 _UINT32_(13) +#define MUX_PA13L_GMAC_GRX0 _UINT32_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UINT32_(1) << 13) + +#define PIN_PA12L_GMAC_GRX1 _UINT32_(12) +#define MUX_PA12L_GMAC_GRX1 _UINT32_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UINT32_(1) << 12) + +#define PIN_PC15L_GMAC_GRX2 _UINT32_(79) +#define MUX_PC15L_GMAC_GRX2 _UINT32_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UINT32_(1) << 15) + +#define PIN_PC14L_GMAC_GRX3 _UINT32_(78) +#define MUX_PC14L_GMAC_GRX3 _UINT32_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UINT32_(1) << 14) + +#define PIN_PC18L_GMAC_GRXCK _UINT32_(82) +#define MUX_PC18L_GMAC_GRXCK _UINT32_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UINT32_(1) << 18) + +#define PIN_PC20L_GMAC_GRXDV _UINT32_(84) +#define MUX_PC20L_GMAC_GRXDV _UINT32_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UINT32_(1) << 20) + +#define PIN_PA15L_GMAC_GRXER _UINT32_(15) +#define MUX_PA15L_GMAC_GRXER _UINT32_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UINT32_(1) << 15) + +#define PIN_PA18L_GMAC_GTX0 _UINT32_(18) +#define MUX_PA18L_GMAC_GTX0 _UINT32_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UINT32_(1) << 18) + +#define PIN_PA19L_GMAC_GTX1 _UINT32_(19) +#define MUX_PA19L_GMAC_GTX1 _UINT32_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UINT32_(1) << 19) + +#define PIN_PC16L_GMAC_GTX2 _UINT32_(80) +#define MUX_PC16L_GMAC_GTX2 _UINT32_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UINT32_(1) << 16) + +#define PIN_PC17L_GMAC_GTX3 _UINT32_(81) +#define MUX_PC17L_GMAC_GTX3 _UINT32_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UINT32_(1) << 17) + +#define PIN_PA14L_GMAC_GTXCK _UINT32_(14) +#define MUX_PA14L_GMAC_GTXCK _UINT32_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UINT32_(1) << 14) + +#define PIN_PA17L_GMAC_GTXEN _UINT32_(17) +#define MUX_PA17L_GMAC_GTXEN _UINT32_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UINT32_(1) << 17) + +#define PIN_PC19L_GMAC_GTXER _UINT32_(83) +#define MUX_PC19L_GMAC_GTXER _UINT32_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UINT32_(1) << 19) + +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _UINT32_(9) +#define MUX_PA09J_I2S_FS0 _UINT32_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UINT32_(1) << 9) + +#define PIN_PA20J_I2S_FS0 _UINT32_(20) +#define MUX_PA20J_I2S_FS0 _UINT32_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UINT32_(1) << 20) + +#define PIN_PA23J_I2S_FS1 _UINT32_(23) +#define MUX_PA23J_I2S_FS1 _UINT32_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UINT32_(1) << 23) + +#define PIN_PB11J_I2S_FS1 _UINT32_(43) +#define MUX_PB11J_I2S_FS1 _UINT32_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UINT32_(1) << 11) + +#define PIN_PA08J_I2S_MCK0 _UINT32_(8) +#define MUX_PA08J_I2S_MCK0 _UINT32_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UINT32_(1) << 8) + +#define PIN_PB17J_I2S_MCK0 _UINT32_(49) +#define MUX_PB17J_I2S_MCK0 _UINT32_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UINT32_(1) << 17) + +#define PIN_PB13J_I2S_MCK1 _UINT32_(45) +#define MUX_PB13J_I2S_MCK1 _UINT32_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UINT32_(1) << 13) + +#define PIN_PA10J_I2S_SCK0 _UINT32_(10) +#define MUX_PA10J_I2S_SCK0 _UINT32_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UINT32_(1) << 10) + +#define PIN_PB16J_I2S_SCK0 _UINT32_(48) +#define MUX_PB16J_I2S_SCK0 _UINT32_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UINT32_(1) << 16) + +#define PIN_PB12J_I2S_SCK1 _UINT32_(44) +#define MUX_PB12J_I2S_SCK1 _UINT32_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UINT32_(1) << 12) + +#define PIN_PA22J_I2S_SDI _UINT32_(22) +#define MUX_PA22J_I2S_SDI _UINT32_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UINT32_(1) << 22) + +#define PIN_PB10J_I2S_SDI _UINT32_(42) +#define MUX_PB10J_I2S_SDI _UINT32_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UINT32_(1) << 10) + +#define PIN_PA11J_I2S_SDO _UINT32_(11) +#define MUX_PA11J_I2S_SDO _UINT32_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UINT32_(1) << 11) + +#define PIN_PA21J_I2S_SDO _UINT32_(21) +#define MUX_PA21J_I2S_SDO _UINT32_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UINT32_(1) << 21) + +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _UINT32_(14) +#define MUX_PA14K_PCC_CLK _UINT32_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UINT32_(1) << 14) + +#define PIN_PA16K_PCC_DATA0 _UINT32_(16) +#define MUX_PA16K_PCC_DATA0 _UINT32_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UINT32_(1) << 16) + +#define PIN_PA17K_PCC_DATA1 _UINT32_(17) +#define MUX_PA17K_PCC_DATA1 _UINT32_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UINT32_(1) << 17) + +#define PIN_PA18K_PCC_DATA2 _UINT32_(18) +#define MUX_PA18K_PCC_DATA2 _UINT32_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UINT32_(1) << 18) + +#define PIN_PA19K_PCC_DATA3 _UINT32_(19) +#define MUX_PA19K_PCC_DATA3 _UINT32_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UINT32_(1) << 19) + +#define PIN_PA20K_PCC_DATA4 _UINT32_(20) +#define MUX_PA20K_PCC_DATA4 _UINT32_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UINT32_(1) << 20) + +#define PIN_PA21K_PCC_DATA5 _UINT32_(21) +#define MUX_PA21K_PCC_DATA5 _UINT32_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UINT32_(1) << 21) + +#define PIN_PA22K_PCC_DATA6 _UINT32_(22) +#define MUX_PA22K_PCC_DATA6 _UINT32_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UINT32_(1) << 22) + +#define PIN_PA23K_PCC_DATA7 _UINT32_(23) +#define MUX_PA23K_PCC_DATA7 _UINT32_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UINT32_(1) << 23) + +#define PIN_PB14K_PCC_DATA8 _UINT32_(46) +#define MUX_PB14K_PCC_DATA8 _UINT32_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UINT32_(1) << 14) + +#define PIN_PB15K_PCC_DATA9 _UINT32_(47) +#define MUX_PB15K_PCC_DATA9 _UINT32_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UINT32_(1) << 15) + +#define PIN_PC12K_PCC_DATA10 _UINT32_(76) +#define MUX_PC12K_PCC_DATA10 _UINT32_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UINT32_(1) << 12) + +#define PIN_PC13K_PCC_DATA11 _UINT32_(77) +#define MUX_PC13K_PCC_DATA11 _UINT32_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UINT32_(1) << 13) + +#define PIN_PC14K_PCC_DATA12 _UINT32_(78) +#define MUX_PC14K_PCC_DATA12 _UINT32_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UINT32_(1) << 14) + +#define PIN_PC15K_PCC_DATA13 _UINT32_(79) +#define MUX_PC15K_PCC_DATA13 _UINT32_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UINT32_(1) << 15) + +#define PIN_PA12K_PCC_DEN1 _UINT32_(12) +#define MUX_PA12K_PCC_DEN1 _UINT32_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UINT32_(1) << 12) + +#define PIN_PA13K_PCC_DEN2 _UINT32_(13) +#define MUX_PA13K_PCC_DEN2 _UINT32_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UINT32_(1) << 13) + +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _UINT32_(50) +#define MUX_PB18G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UINT32_(1) << 18) + +#define PIN_PB23G_PDEC_QDI0 _UINT32_(55) +#define MUX_PB23G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UINT32_(1) << 23) + +#define PIN_PC16G_PDEC_QDI0 _UINT32_(80) +#define MUX_PC16G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UINT32_(1) << 16) + +#define PIN_PA24G_PDEC_QDI0 _UINT32_(24) +#define MUX_PA24G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UINT32_(1) << 24) + +#define PIN_PB19G_PDEC_QDI1 _UINT32_(51) +#define MUX_PB19G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UINT32_(1) << 19) + +#define PIN_PB24G_PDEC_QDI1 _UINT32_(56) +#define MUX_PB24G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UINT32_(1) << 24) + +#define PIN_PC17G_PDEC_QDI1 _UINT32_(81) +#define MUX_PC17G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UINT32_(1) << 17) + +#define PIN_PA25G_PDEC_QDI1 _UINT32_(25) +#define MUX_PA25G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UINT32_(1) << 25) + +#define PIN_PB20G_PDEC_QDI2 _UINT32_(52) +#define MUX_PB20G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UINT32_(1) << 20) + +#define PIN_PB25G_PDEC_QDI2 _UINT32_(57) +#define MUX_PB25G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UINT32_(1) << 25) + +#define PIN_PC18G_PDEC_QDI2 _UINT32_(82) +#define MUX_PC18G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UINT32_(1) << 18) + +#define PIN_PB22G_PDEC_QDI2 _UINT32_(54) +#define MUX_PB22G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UINT32_(1) << 22) + +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _UINT32_(43) +#define MUX_PB11H_QSPI_CS _UINT32_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UINT32_(1) << 11) + +#define PIN_PA08H_QSPI_DATA0 _UINT32_(8) +#define MUX_PA08H_QSPI_DATA0 _UINT32_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UINT32_(1) << 8) + +#define PIN_PA09H_QSPI_DATA1 _UINT32_(9) +#define MUX_PA09H_QSPI_DATA1 _UINT32_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UINT32_(1) << 9) + +#define PIN_PA10H_QSPI_DATA2 _UINT32_(10) +#define MUX_PA10H_QSPI_DATA2 _UINT32_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UINT32_(1) << 10) + +#define PIN_PA11H_QSPI_DATA3 _UINT32_(11) +#define MUX_PA11H_QSPI_DATA3 _UINT32_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UINT32_(1) << 11) + +#define PIN_PB10H_QSPI_SCK _UINT32_(42) +#define MUX_PB10H_QSPI_SCK _UINT32_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UINT32_(1) << 10) + +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _UINT32_(6) +#define MUX_PA06I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UINT32_(1) << 6) + +#define PIN_PA12I_SDHC0_SDCD _UINT32_(12) +#define MUX_PA12I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UINT32_(1) << 12) + +#define PIN_PB12I_SDHC0_SDCD _UINT32_(44) +#define MUX_PB12I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UINT32_(1) << 12) + +#define PIN_PC06I_SDHC0_SDCD _UINT32_(70) +#define MUX_PC06I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UINT32_(1) << 6) + +#define PIN_PB11I_SDHC0_SDCK _UINT32_(43) +#define MUX_PB11I_SDHC0_SDCK _UINT32_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UINT32_(1) << 11) + +#define PIN_PA08I_SDHC0_SDCMD _UINT32_(8) +#define MUX_PA08I_SDHC0_SDCMD _UINT32_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UINT32_(1) << 8) + +#define PIN_PA09I_SDHC0_SDDAT0 _UINT32_(9) +#define MUX_PA09I_SDHC0_SDDAT0 _UINT32_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UINT32_(1) << 9) + +#define PIN_PA10I_SDHC0_SDDAT1 _UINT32_(10) +#define MUX_PA10I_SDHC0_SDDAT1 _UINT32_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UINT32_(1) << 10) + +#define PIN_PA11I_SDHC0_SDDAT2 _UINT32_(11) +#define MUX_PA11I_SDHC0_SDDAT2 _UINT32_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UINT32_(1) << 11) + +#define PIN_PB10I_SDHC0_SDDAT3 _UINT32_(42) +#define MUX_PB10I_SDHC0_SDDAT3 _UINT32_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UINT32_(1) << 10) + +#define PIN_PA07I_SDHC0_SDWP _UINT32_(7) +#define MUX_PA07I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UINT32_(1) << 7) + +#define PIN_PA13I_SDHC0_SDWP _UINT32_(13) +#define MUX_PA13I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UINT32_(1) << 13) + +#define PIN_PB13I_SDHC0_SDWP _UINT32_(45) +#define MUX_PB13I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UINT32_(1) << 13) + +#define PIN_PC07I_SDHC0_SDWP _UINT32_(71) +#define MUX_PC07I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UINT32_(1) << 7) + +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _UINT32_(48) +#define MUX_PB16I_SDHC1_SDCD _UINT32_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UINT32_(1) << 16) + +#define PIN_PC20I_SDHC1_SDCD _UINT32_(84) +#define MUX_PC20I_SDHC1_SDCD _UINT32_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UINT32_(1) << 20) + +#define PIN_PA21I_SDHC1_SDCK _UINT32_(21) +#define MUX_PA21I_SDHC1_SDCK _UINT32_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UINT32_(1) << 21) + +#define PIN_PA20I_SDHC1_SDCMD _UINT32_(20) +#define MUX_PA20I_SDHC1_SDCMD _UINT32_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UINT32_(1) << 20) + +#define PIN_PB18I_SDHC1_SDDAT0 _UINT32_(50) +#define MUX_PB18I_SDHC1_SDDAT0 _UINT32_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UINT32_(1) << 18) + +#define PIN_PB19I_SDHC1_SDDAT1 _UINT32_(51) +#define MUX_PB19I_SDHC1_SDDAT1 _UINT32_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UINT32_(1) << 19) + +#define PIN_PB20I_SDHC1_SDDAT2 _UINT32_(52) +#define MUX_PB20I_SDHC1_SDDAT2 _UINT32_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UINT32_(1) << 20) + +#define PIN_PB21I_SDHC1_SDDAT3 _UINT32_(53) +#define MUX_PB21I_SDHC1_SDDAT3 _UINT32_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UINT32_(1) << 21) + +#define PIN_PB17I_SDHC1_SDWP _UINT32_(49) +#define MUX_PB17I_SDHC1_SDWP _UINT32_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UINT32_(1) << 17) + +#define PIN_PC21I_SDHC1_SDWP _UINT32_(85) +#define MUX_PC21I_SDHC1_SDWP _UINT32_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UINT32_(1) << 21) + +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _UINT32_(4) +#define MUX_PA04D_SERCOM0_PAD0 _UINT32_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UINT32_(1) << 4) + +#define PIN_PC17D_SERCOM0_PAD0 _UINT32_(81) +#define MUX_PC17D_SERCOM0_PAD0 _UINT32_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UINT32_(1) << 17) + +#define PIN_PA08C_SERCOM0_PAD0 _UINT32_(8) +#define MUX_PA08C_SERCOM0_PAD0 _UINT32_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UINT32_(1) << 8) + +#define PIN_PB24C_SERCOM0_PAD0 _UINT32_(56) +#define MUX_PB24C_SERCOM0_PAD0 _UINT32_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UINT32_(1) << 24) + +#define PIN_PA05D_SERCOM0_PAD1 _UINT32_(5) +#define MUX_PA05D_SERCOM0_PAD1 _UINT32_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UINT32_(1) << 5) + +#define PIN_PC16D_SERCOM0_PAD1 _UINT32_(80) +#define MUX_PC16D_SERCOM0_PAD1 _UINT32_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UINT32_(1) << 16) + +#define PIN_PA09C_SERCOM0_PAD1 _UINT32_(9) +#define MUX_PA09C_SERCOM0_PAD1 _UINT32_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UINT32_(1) << 9) + +#define PIN_PB25C_SERCOM0_PAD1 _UINT32_(57) +#define MUX_PB25C_SERCOM0_PAD1 _UINT32_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UINT32_(1) << 25) + +#define PIN_PA06D_SERCOM0_PAD2 _UINT32_(6) +#define MUX_PA06D_SERCOM0_PAD2 _UINT32_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UINT32_(1) << 6) + +#define PIN_PC18D_SERCOM0_PAD2 _UINT32_(82) +#define MUX_PC18D_SERCOM0_PAD2 _UINT32_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA10C_SERCOM0_PAD2 _UINT32_(10) +#define MUX_PA10C_SERCOM0_PAD2 _UINT32_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC24C_SERCOM0_PAD2 _UINT32_(88) +#define MUX_PC24C_SERCOM0_PAD2 _UINT32_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UINT32_(1) << 24) + +#define PIN_PA07D_SERCOM0_PAD3 _UINT32_(7) +#define MUX_PA07D_SERCOM0_PAD3 _UINT32_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UINT32_(1) << 7) + +#define PIN_PC19D_SERCOM0_PAD3 _UINT32_(83) +#define MUX_PC19D_SERCOM0_PAD3 _UINT32_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UINT32_(1) << 19) + +#define PIN_PA11C_SERCOM0_PAD3 _UINT32_(11) +#define MUX_PA11C_SERCOM0_PAD3 _UINT32_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC25C_SERCOM0_PAD3 _UINT32_(89) +#define MUX_PC25C_SERCOM0_PAD3 _UINT32_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UINT32_(1) << 25) + +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _UINT32_(0) +#define MUX_PA00D_SERCOM1_PAD0 _UINT32_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UINT32_(1) << 0) + +#define PIN_PA16C_SERCOM1_PAD0 _UINT32_(16) +#define MUX_PA16C_SERCOM1_PAD0 _UINT32_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UINT32_(1) << 16) + +#define PIN_PC27C_SERCOM1_PAD0 _UINT32_(91) +#define MUX_PC27C_SERCOM1_PAD0 _UINT32_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UINT32_(1) << 27) + +#define PIN_PA01D_SERCOM1_PAD1 _UINT32_(1) +#define MUX_PA01D_SERCOM1_PAD1 _UINT32_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UINT32_(1) << 1) + +#define PIN_PA17C_SERCOM1_PAD1 _UINT32_(17) +#define MUX_PA17C_SERCOM1_PAD1 _UINT32_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UINT32_(1) << 17) + +#define PIN_PC28C_SERCOM1_PAD1 _UINT32_(92) +#define MUX_PC28C_SERCOM1_PAD1 _UINT32_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UINT32_(1) << 28) + +#define PIN_PA30D_SERCOM1_PAD2 _UINT32_(30) +#define MUX_PA30D_SERCOM1_PAD2 _UINT32_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UINT32_(1) << 30) + +#define PIN_PA18C_SERCOM1_PAD2 _UINT32_(18) +#define MUX_PA18C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UINT32_(1) << 18) + +#define PIN_PB22C_SERCOM1_PAD2 _UINT32_(54) +#define MUX_PB22C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UINT32_(1) << 22) + +#define PIN_PA31D_SERCOM1_PAD3 _UINT32_(31) +#define MUX_PA31D_SERCOM1_PAD3 _UINT32_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UINT32_(1) << 31) + +#define PIN_PA19C_SERCOM1_PAD3 _UINT32_(19) +#define MUX_PA19C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UINT32_(1) << 19) + +#define PIN_PB23C_SERCOM1_PAD3 _UINT32_(55) +#define MUX_PB23C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UINT32_(1) << 23) + +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _UINT32_(9) +#define MUX_PA09D_SERCOM2_PAD0 _UINT32_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UINT32_(1) << 9) + +#define PIN_PB25D_SERCOM2_PAD0 _UINT32_(57) +#define MUX_PB25D_SERCOM2_PAD0 _UINT32_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UINT32_(1) << 25) + +#define PIN_PA12C_SERCOM2_PAD0 _UINT32_(12) +#define MUX_PA12C_SERCOM2_PAD0 _UINT32_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UINT32_(1) << 12) + +#define PIN_PA08D_SERCOM2_PAD1 _UINT32_(8) +#define MUX_PA08D_SERCOM2_PAD1 _UINT32_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UINT32_(1) << 8) + +#define PIN_PB24D_SERCOM2_PAD1 _UINT32_(56) +#define MUX_PB24D_SERCOM2_PAD1 _UINT32_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UINT32_(1) << 24) + +#define PIN_PA13C_SERCOM2_PAD1 _UINT32_(13) +#define MUX_PA13C_SERCOM2_PAD1 _UINT32_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UINT32_(1) << 13) + +#define PIN_PA10D_SERCOM2_PAD2 _UINT32_(10) +#define MUX_PA10D_SERCOM2_PAD2 _UINT32_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC24D_SERCOM2_PAD2 _UINT32_(88) +#define MUX_PC24D_SERCOM2_PAD2 _UINT32_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UINT32_(1) << 24) + +#define PIN_PA14C_SERCOM2_PAD2 _UINT32_(14) +#define MUX_PA14C_SERCOM2_PAD2 _UINT32_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UINT32_(1) << 14) + +#define PIN_PA11D_SERCOM2_PAD3 _UINT32_(11) +#define MUX_PA11D_SERCOM2_PAD3 _UINT32_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC25D_SERCOM2_PAD3 _UINT32_(89) +#define MUX_PC25D_SERCOM2_PAD3 _UINT32_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UINT32_(1) << 25) + +#define PIN_PA15C_SERCOM2_PAD3 _UINT32_(15) +#define MUX_PA15C_SERCOM2_PAD3 _UINT32_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UINT32_(1) << 15) + +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _UINT32_(17) +#define MUX_PA17D_SERCOM3_PAD0 _UINT32_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UINT32_(1) << 17) + +#define PIN_PA22C_SERCOM3_PAD0 _UINT32_(22) +#define MUX_PA22C_SERCOM3_PAD0 _UINT32_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UINT32_(1) << 22) + +#define PIN_PB20C_SERCOM3_PAD0 _UINT32_(52) +#define MUX_PB20C_SERCOM3_PAD0 _UINT32_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UINT32_(1) << 20) + +#define PIN_PA16D_SERCOM3_PAD1 _UINT32_(16) +#define MUX_PA16D_SERCOM3_PAD1 _UINT32_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UINT32_(1) << 16) + +#define PIN_PA23C_SERCOM3_PAD1 _UINT32_(23) +#define MUX_PA23C_SERCOM3_PAD1 _UINT32_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UINT32_(1) << 23) + +#define PIN_PB21C_SERCOM3_PAD1 _UINT32_(53) +#define MUX_PB21C_SERCOM3_PAD1 _UINT32_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UINT32_(1) << 21) + +#define PIN_PA18D_SERCOM3_PAD2 _UINT32_(18) +#define MUX_PA18D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA20D_SERCOM3_PAD2 _UINT32_(20) +#define MUX_PA20D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UINT32_(1) << 20) + +#define PIN_PA24C_SERCOM3_PAD2 _UINT32_(24) +#define MUX_PA24C_SERCOM3_PAD2 _UINT32_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UINT32_(1) << 24) + +#define PIN_PA19D_SERCOM3_PAD3 _UINT32_(19) +#define MUX_PA19D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UINT32_(1) << 19) + +#define PIN_PA21D_SERCOM3_PAD3 _UINT32_(21) +#define MUX_PA21D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UINT32_(1) << 21) + +#define PIN_PA25C_SERCOM3_PAD3 _UINT32_(25) +#define MUX_PA25C_SERCOM3_PAD3 _UINT32_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UINT32_(1) << 25) + +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _UINT32_(13) +#define MUX_PA13D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UINT32_(1) << 13) + +#define PIN_PB08D_SERCOM4_PAD0 _UINT32_(40) +#define MUX_PB08D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UINT32_(1) << 8) + +#define PIN_PB12C_SERCOM4_PAD0 _UINT32_(44) +#define MUX_PB12C_SERCOM4_PAD0 _UINT32_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UINT32_(1) << 12) + +#define PIN_PA12D_SERCOM4_PAD1 _UINT32_(12) +#define MUX_PA12D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UINT32_(1) << 12) + +#define PIN_PB09D_SERCOM4_PAD1 _UINT32_(41) +#define MUX_PB09D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UINT32_(1) << 9) + +#define PIN_PB13C_SERCOM4_PAD1 _UINT32_(45) +#define MUX_PB13C_SERCOM4_PAD1 _UINT32_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UINT32_(1) << 13) + +#define PIN_PA14D_SERCOM4_PAD2 _UINT32_(14) +#define MUX_PA14D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UINT32_(1) << 14) + +#define PIN_PB10D_SERCOM4_PAD2 _UINT32_(42) +#define MUX_PB10D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UINT32_(1) << 10) + +#define PIN_PB14C_SERCOM4_PAD2 _UINT32_(46) +#define MUX_PB14C_SERCOM4_PAD2 _UINT32_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UINT32_(1) << 14) + +#define PIN_PB11D_SERCOM4_PAD3 _UINT32_(43) +#define MUX_PB11D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UINT32_(1) << 11) + +#define PIN_PA15D_SERCOM4_PAD3 _UINT32_(15) +#define MUX_PA15D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UINT32_(1) << 15) + +#define PIN_PB15C_SERCOM4_PAD3 _UINT32_(47) +#define MUX_PB15C_SERCOM4_PAD3 _UINT32_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UINT32_(1) << 15) + +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _UINT32_(23) +#define MUX_PA23D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UINT32_(1) << 23) + +#define PIN_PB02D_SERCOM5_PAD0 _UINT32_(34) +#define MUX_PB02D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UINT32_(1) << 2) + +#define PIN_PB31D_SERCOM5_PAD0 _UINT32_(63) +#define MUX_PB31D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UINT32_(1) << 31) + +#define PIN_PB16C_SERCOM5_PAD0 _UINT32_(48) +#define MUX_PB16C_SERCOM5_PAD0 _UINT32_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UINT32_(1) << 16) + +#define PIN_PA22D_SERCOM5_PAD1 _UINT32_(22) +#define MUX_PA22D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UINT32_(1) << 22) + +#define PIN_PB03D_SERCOM5_PAD1 _UINT32_(35) +#define MUX_PB03D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UINT32_(1) << 3) + +#define PIN_PB30D_SERCOM5_PAD1 _UINT32_(62) +#define MUX_PB30D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UINT32_(1) << 30) + +#define PIN_PB17C_SERCOM5_PAD1 _UINT32_(49) +#define MUX_PB17C_SERCOM5_PAD1 _UINT32_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UINT32_(1) << 17) + +#define PIN_PA24D_SERCOM5_PAD2 _UINT32_(24) +#define MUX_PA24D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UINT32_(1) << 24) + +#define PIN_PB00D_SERCOM5_PAD2 _UINT32_(32) +#define MUX_PB00D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UINT32_(1) << 0) + +#define PIN_PB22D_SERCOM5_PAD2 _UINT32_(54) +#define MUX_PB22D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UINT32_(1) << 22) + +#define PIN_PA20C_SERCOM5_PAD2 _UINT32_(20) +#define MUX_PA20C_SERCOM5_PAD2 _UINT32_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UINT32_(1) << 20) + +#define PIN_PB18C_SERCOM5_PAD2 _UINT32_(50) +#define MUX_PB18C_SERCOM5_PAD2 _UINT32_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA25D_SERCOM5_PAD3 _UINT32_(25) +#define MUX_PA25D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UINT32_(1) << 25) + +#define PIN_PB01D_SERCOM5_PAD3 _UINT32_(33) +#define MUX_PB01D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UINT32_(1) << 1) + +#define PIN_PB23D_SERCOM5_PAD3 _UINT32_(55) +#define MUX_PB23D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UINT32_(1) << 23) + +#define PIN_PA21C_SERCOM5_PAD3 _UINT32_(21) +#define MUX_PA21C_SERCOM5_PAD3 _UINT32_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UINT32_(1) << 21) + +#define PIN_PB19C_SERCOM5_PAD3 _UINT32_(51) +#define MUX_PB19C_SERCOM5_PAD3 _UINT32_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UINT32_(1) << 19) + +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _UINT32_(77) +#define MUX_PC13D_SERCOM6_PAD0 _UINT32_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UINT32_(1) << 13) + +#define PIN_PC16C_SERCOM6_PAD0 _UINT32_(80) +#define MUX_PC16C_SERCOM6_PAD0 _UINT32_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UINT32_(1) << 16) + +#define PIN_PC12D_SERCOM6_PAD1 _UINT32_(76) +#define MUX_PC12D_SERCOM6_PAD1 _UINT32_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UINT32_(1) << 12) + +#define PIN_PC05C_SERCOM6_PAD1 _UINT32_(69) +#define MUX_PC05C_SERCOM6_PAD1 _UINT32_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UINT32_(1) << 5) + +#define PIN_PC17C_SERCOM6_PAD1 _UINT32_(81) +#define MUX_PC17C_SERCOM6_PAD1 _UINT32_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UINT32_(1) << 17) + +#define PIN_PC14D_SERCOM6_PAD2 _UINT32_(78) +#define MUX_PC14D_SERCOM6_PAD2 _UINT32_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UINT32_(1) << 14) + +#define PIN_PC06C_SERCOM6_PAD2 _UINT32_(70) +#define MUX_PC06C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UINT32_(1) << 6) + +#define PIN_PC10C_SERCOM6_PAD2 _UINT32_(74) +#define MUX_PC10C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC18C_SERCOM6_PAD2 _UINT32_(82) +#define MUX_PC18C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UINT32_(1) << 18) + +#define PIN_PC15D_SERCOM6_PAD3 _UINT32_(79) +#define MUX_PC15D_SERCOM6_PAD3 _UINT32_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UINT32_(1) << 15) + +#define PIN_PC07C_SERCOM6_PAD3 _UINT32_(71) +#define MUX_PC07C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UINT32_(1) << 7) + +#define PIN_PC11C_SERCOM6_PAD3 _UINT32_(75) +#define MUX_PC11C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC19C_SERCOM6_PAD3 _UINT32_(83) +#define MUX_PC19C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UINT32_(1) << 19) + +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _UINT32_(53) +#define MUX_PB21D_SERCOM7_PAD0 _UINT32_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UINT32_(1) << 21) + +#define PIN_PB30C_SERCOM7_PAD0 _UINT32_(62) +#define MUX_PB30C_SERCOM7_PAD0 _UINT32_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UINT32_(1) << 30) + +#define PIN_PC12C_SERCOM7_PAD0 _UINT32_(76) +#define MUX_PC12C_SERCOM7_PAD0 _UINT32_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UINT32_(1) << 12) + +#define PIN_PB20D_SERCOM7_PAD1 _UINT32_(52) +#define MUX_PB20D_SERCOM7_PAD1 _UINT32_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UINT32_(1) << 20) + +#define PIN_PB31C_SERCOM7_PAD1 _UINT32_(63) +#define MUX_PB31C_SERCOM7_PAD1 _UINT32_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UINT32_(1) << 31) + +#define PIN_PC13C_SERCOM7_PAD1 _UINT32_(77) +#define MUX_PC13C_SERCOM7_PAD1 _UINT32_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UINT32_(1) << 13) + +#define PIN_PB18D_SERCOM7_PAD2 _UINT32_(50) +#define MUX_PB18D_SERCOM7_PAD2 _UINT32_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UINT32_(1) << 18) + +#define PIN_PC10D_SERCOM7_PAD2 _UINT32_(74) +#define MUX_PC10D_SERCOM7_PAD2 _UINT32_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC14C_SERCOM7_PAD2 _UINT32_(78) +#define MUX_PC14C_SERCOM7_PAD2 _UINT32_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UINT32_(1) << 14) + +#define PIN_PA30C_SERCOM7_PAD2 _UINT32_(30) +#define MUX_PA30C_SERCOM7_PAD2 _UINT32_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UINT32_(1) << 30) + +#define PIN_PB19D_SERCOM7_PAD3 _UINT32_(51) +#define MUX_PB19D_SERCOM7_PAD3 _UINT32_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UINT32_(1) << 19) + +#define PIN_PC11D_SERCOM7_PAD3 _UINT32_(75) +#define MUX_PC11D_SERCOM7_PAD3 _UINT32_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC15C_SERCOM7_PAD3 _UINT32_(79) +#define MUX_PC15C_SERCOM7_PAD3 _UINT32_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UINT32_(1) << 15) + +#define PIN_PA31C_SERCOM7_PAD3 _UINT32_(31) +#define MUX_PA31C_SERCOM7_PAD3 _UINT32_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UINT32_(1) << 31) + +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _UINT32_(4) +#define MUX_PA04E_TC0_WO0 _UINT32_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UINT32_(1) << 4) + +#define PIN_PA08E_TC0_WO0 _UINT32_(8) +#define MUX_PA08E_TC0_WO0 _UINT32_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UINT32_(1) << 8) + +#define PIN_PB30E_TC0_WO0 _UINT32_(62) +#define MUX_PB30E_TC0_WO0 _UINT32_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UINT32_(1) << 30) + +#define PIN_PA05E_TC0_WO1 _UINT32_(5) +#define MUX_PA05E_TC0_WO1 _UINT32_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UINT32_(1) << 5) + +#define PIN_PA09E_TC0_WO1 _UINT32_(9) +#define MUX_PA09E_TC0_WO1 _UINT32_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UINT32_(1) << 9) + +#define PIN_PB31E_TC0_WO1 _UINT32_(63) +#define MUX_PB31E_TC0_WO1 _UINT32_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UINT32_(1) << 31) + +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _UINT32_(6) +#define MUX_PA06E_TC1_WO0 _UINT32_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UINT32_(1) << 6) + +#define PIN_PA10E_TC1_WO0 _UINT32_(10) +#define MUX_PA10E_TC1_WO0 _UINT32_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UINT32_(1) << 10) + +#define PIN_PA07E_TC1_WO1 _UINT32_(7) +#define MUX_PA07E_TC1_WO1 _UINT32_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UINT32_(1) << 7) + +#define PIN_PA11E_TC1_WO1 _UINT32_(11) +#define MUX_PA11E_TC1_WO1 _UINT32_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UINT32_(1) << 11) + +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _UINT32_(12) +#define MUX_PA12E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UINT32_(1) << 12) + +#define PIN_PA16E_TC2_WO0 _UINT32_(16) +#define MUX_PA16E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UINT32_(1) << 16) + +#define PIN_PA00E_TC2_WO0 _UINT32_(0) +#define MUX_PA00E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UINT32_(1) << 0) + +#define PIN_PA01E_TC2_WO1 _UINT32_(1) +#define MUX_PA01E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UINT32_(1) << 1) + +#define PIN_PA13E_TC2_WO1 _UINT32_(13) +#define MUX_PA13E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UINT32_(1) << 13) + +#define PIN_PA17E_TC2_WO1 _UINT32_(17) +#define MUX_PA17E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _UINT32_(18) +#define MUX_PA18E_TC3_WO0 _UINT32_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UINT32_(1) << 18) + +#define PIN_PA14E_TC3_WO0 _UINT32_(14) +#define MUX_PA14E_TC3_WO0 _UINT32_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UINT32_(1) << 14) + +#define PIN_PA15E_TC3_WO1 _UINT32_(15) +#define MUX_PA15E_TC3_WO1 _UINT32_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UINT32_(1) << 15) + +#define PIN_PA19E_TC3_WO1 _UINT32_(19) +#define MUX_PA19E_TC3_WO1 _UINT32_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UINT32_(1) << 19) + +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _UINT32_(22) +#define MUX_PA22E_TC4_WO0 _UINT32_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UINT32_(1) << 22) + +#define PIN_PB08E_TC4_WO0 _UINT32_(40) +#define MUX_PB08E_TC4_WO0 _UINT32_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UINT32_(1) << 8) + +#define PIN_PB12E_TC4_WO0 _UINT32_(44) +#define MUX_PB12E_TC4_WO0 _UINT32_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UINT32_(1) << 12) + +#define PIN_PA23E_TC4_WO1 _UINT32_(23) +#define MUX_PA23E_TC4_WO1 _UINT32_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UINT32_(1) << 23) + +#define PIN_PB09E_TC4_WO1 _UINT32_(41) +#define MUX_PB09E_TC4_WO1 _UINT32_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UINT32_(1) << 9) + +#define PIN_PB13E_TC4_WO1 _UINT32_(45) +#define MUX_PB13E_TC4_WO1 _UINT32_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UINT32_(1) << 13) + +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _UINT32_(24) +#define MUX_PA24E_TC5_WO0 _UINT32_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UINT32_(1) << 24) + +#define PIN_PB10E_TC5_WO0 _UINT32_(42) +#define MUX_PB10E_TC5_WO0 _UINT32_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UINT32_(1) << 10) + +#define PIN_PB14E_TC5_WO0 _UINT32_(46) +#define MUX_PB14E_TC5_WO0 _UINT32_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UINT32_(1) << 14) + +#define PIN_PA25E_TC5_WO1 _UINT32_(25) +#define MUX_PA25E_TC5_WO1 _UINT32_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UINT32_(1) << 25) + +#define PIN_PB11E_TC5_WO1 _UINT32_(43) +#define MUX_PB11E_TC5_WO1 _UINT32_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UINT32_(1) << 11) + +#define PIN_PB15E_TC5_WO1 _UINT32_(47) +#define MUX_PB15E_TC5_WO1 _UINT32_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UINT32_(1) << 15) + +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _UINT32_(30) +#define MUX_PA30E_TC6_WO0 _UINT32_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UINT32_(1) << 30) + +#define PIN_PB02E_TC6_WO0 _UINT32_(34) +#define MUX_PB02E_TC6_WO0 _UINT32_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UINT32_(1) << 2) + +#define PIN_PB16E_TC6_WO0 _UINT32_(48) +#define MUX_PB16E_TC6_WO0 _UINT32_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UINT32_(1) << 16) + +#define PIN_PA31E_TC6_WO1 _UINT32_(31) +#define MUX_PA31E_TC6_WO1 _UINT32_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UINT32_(1) << 31) + +#define PIN_PB03E_TC6_WO1 _UINT32_(35) +#define MUX_PB03E_TC6_WO1 _UINT32_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UINT32_(1) << 3) + +#define PIN_PB17E_TC6_WO1 _UINT32_(49) +#define MUX_PB17E_TC6_WO1 _UINT32_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _UINT32_(20) +#define MUX_PA20E_TC7_WO0 _UINT32_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UINT32_(1) << 20) + +#define PIN_PB00E_TC7_WO0 _UINT32_(32) +#define MUX_PB00E_TC7_WO0 _UINT32_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UINT32_(1) << 0) + +#define PIN_PB22E_TC7_WO0 _UINT32_(54) +#define MUX_PB22E_TC7_WO0 _UINT32_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UINT32_(1) << 22) + +#define PIN_PA21E_TC7_WO1 _UINT32_(21) +#define MUX_PA21E_TC7_WO1 _UINT32_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UINT32_(1) << 21) + +#define PIN_PB01E_TC7_WO1 _UINT32_(33) +#define MUX_PB01E_TC7_WO1 _UINT32_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UINT32_(1) << 1) + +#define PIN_PB23E_TC7_WO1 _UINT32_(55) +#define MUX_PB23E_TC7_WO1 _UINT32_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UINT32_(1) << 23) + +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _UINT32_(20) +#define MUX_PA20G_TCC0_WO0 _UINT32_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UINT32_(1) << 20) + +#define PIN_PB12G_TCC0_WO0 _UINT32_(44) +#define MUX_PB12G_TCC0_WO0 _UINT32_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UINT32_(1) << 12) + +#define PIN_PA08F_TCC0_WO0 _UINT32_(8) +#define MUX_PA08F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UINT32_(1) << 8) + +#define PIN_PC10F_TCC0_WO0 _UINT32_(74) +#define MUX_PC10F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UINT32_(1) << 10) + +#define PIN_PC16F_TCC0_WO0 _UINT32_(80) +#define MUX_PC16F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UINT32_(1) << 16) + +#define PIN_PA21G_TCC0_WO1 _UINT32_(21) +#define MUX_PA21G_TCC0_WO1 _UINT32_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UINT32_(1) << 21) + +#define PIN_PB13G_TCC0_WO1 _UINT32_(45) +#define MUX_PB13G_TCC0_WO1 _UINT32_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UINT32_(1) << 13) + +#define PIN_PA09F_TCC0_WO1 _UINT32_(9) +#define MUX_PA09F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UINT32_(1) << 9) + +#define PIN_PC11F_TCC0_WO1 _UINT32_(75) +#define MUX_PC11F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UINT32_(1) << 11) + +#define PIN_PC17F_TCC0_WO1 _UINT32_(81) +#define MUX_PC17F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UINT32_(1) << 17) + +#define PIN_PA22G_TCC0_WO2 _UINT32_(22) +#define MUX_PA22G_TCC0_WO2 _UINT32_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UINT32_(1) << 22) + +#define PIN_PB14G_TCC0_WO2 _UINT32_(46) +#define MUX_PB14G_TCC0_WO2 _UINT32_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UINT32_(1) << 14) + +#define PIN_PA10F_TCC0_WO2 _UINT32_(10) +#define MUX_PA10F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UINT32_(1) << 10) + +#define PIN_PC12F_TCC0_WO2 _UINT32_(76) +#define MUX_PC12F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UINT32_(1) << 12) + +#define PIN_PC18F_TCC0_WO2 _UINT32_(82) +#define MUX_PC18F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UINT32_(1) << 18) + +#define PIN_PA23G_TCC0_WO3 _UINT32_(23) +#define MUX_PA23G_TCC0_WO3 _UINT32_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UINT32_(1) << 23) + +#define PIN_PB15G_TCC0_WO3 _UINT32_(47) +#define MUX_PB15G_TCC0_WO3 _UINT32_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UINT32_(1) << 15) + +#define PIN_PA11F_TCC0_WO3 _UINT32_(11) +#define MUX_PA11F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UINT32_(1) << 11) + +#define PIN_PC13F_TCC0_WO3 _UINT32_(77) +#define MUX_PC13F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UINT32_(1) << 13) + +#define PIN_PC19F_TCC0_WO3 _UINT32_(83) +#define MUX_PC19F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UINT32_(1) << 19) + +#define PIN_PA16G_TCC0_WO4 _UINT32_(16) +#define MUX_PA16G_TCC0_WO4 _UINT32_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UINT32_(1) << 16) + +#define PIN_PB16G_TCC0_WO4 _UINT32_(48) +#define MUX_PB16G_TCC0_WO4 _UINT32_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UINT32_(1) << 16) + +#define PIN_PB10F_TCC0_WO4 _UINT32_(42) +#define MUX_PB10F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UINT32_(1) << 10) + +#define PIN_PC14F_TCC0_WO4 _UINT32_(78) +#define MUX_PC14F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UINT32_(1) << 14) + +#define PIN_PC20F_TCC0_WO4 _UINT32_(84) +#define MUX_PC20F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UINT32_(1) << 20) + +#define PIN_PA17G_TCC0_WO5 _UINT32_(17) +#define MUX_PA17G_TCC0_WO5 _UINT32_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UINT32_(1) << 17) + +#define PIN_PB17G_TCC0_WO5 _UINT32_(49) +#define MUX_PB17G_TCC0_WO5 _UINT32_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UINT32_(1) << 17) + +#define PIN_PB11F_TCC0_WO5 _UINT32_(43) +#define MUX_PB11F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UINT32_(1) << 11) + +#define PIN_PC15F_TCC0_WO5 _UINT32_(79) +#define MUX_PC15F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UINT32_(1) << 15) + +#define PIN_PC21F_TCC0_WO5 _UINT32_(85) +#define MUX_PC21F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UINT32_(1) << 21) + +#define PIN_PA18G_TCC0_WO6 _UINT32_(18) +#define MUX_PA18G_TCC0_WO6 _UINT32_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UINT32_(1) << 18) + +#define PIN_PB30G_TCC0_WO6 _UINT32_(62) +#define MUX_PB30G_TCC0_WO6 _UINT32_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UINT32_(1) << 30) + +#define PIN_PA12F_TCC0_WO6 _UINT32_(12) +#define MUX_PA12F_TCC0_WO6 _UINT32_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UINT32_(1) << 12) + +#define PIN_PA19G_TCC0_WO7 _UINT32_(19) +#define MUX_PA19G_TCC0_WO7 _UINT32_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UINT32_(1) << 19) + +#define PIN_PB31G_TCC0_WO7 _UINT32_(63) +#define MUX_PB31G_TCC0_WO7 _UINT32_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UINT32_(1) << 31) + +#define PIN_PA13F_TCC0_WO7 _UINT32_(13) +#define MUX_PA13F_TCC0_WO7 _UINT32_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UINT32_(1) << 13) + +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _UINT32_(42) +#define MUX_PB10G_TCC1_WO0 _UINT32_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UINT32_(1) << 10) + +#define PIN_PC14G_TCC1_WO0 _UINT32_(78) +#define MUX_PC14G_TCC1_WO0 _UINT32_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UINT32_(1) << 14) + +#define PIN_PA16F_TCC1_WO0 _UINT32_(16) +#define MUX_PA16F_TCC1_WO0 _UINT32_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UINT32_(1) << 16) + +#define PIN_PB18F_TCC1_WO0 _UINT32_(50) +#define MUX_PB18F_TCC1_WO0 _UINT32_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UINT32_(1) << 18) + +#define PIN_PB11G_TCC1_WO1 _UINT32_(43) +#define MUX_PB11G_TCC1_WO1 _UINT32_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UINT32_(1) << 11) + +#define PIN_PC15G_TCC1_WO1 _UINT32_(79) +#define MUX_PC15G_TCC1_WO1 _UINT32_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UINT32_(1) << 15) + +#define PIN_PA17F_TCC1_WO1 _UINT32_(17) +#define MUX_PA17F_TCC1_WO1 _UINT32_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UINT32_(1) << 17) + +#define PIN_PB19F_TCC1_WO1 _UINT32_(51) +#define MUX_PB19F_TCC1_WO1 _UINT32_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UINT32_(1) << 19) + +#define PIN_PA12G_TCC1_WO2 _UINT32_(12) +#define MUX_PA12G_TCC1_WO2 _UINT32_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UINT32_(1) << 12) + +#define PIN_PA14G_TCC1_WO2 _UINT32_(14) +#define MUX_PA14G_TCC1_WO2 _UINT32_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UINT32_(1) << 14) + +#define PIN_PA18F_TCC1_WO2 _UINT32_(18) +#define MUX_PA18F_TCC1_WO2 _UINT32_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UINT32_(1) << 18) + +#define PIN_PB20F_TCC1_WO2 _UINT32_(52) +#define MUX_PB20F_TCC1_WO2 _UINT32_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UINT32_(1) << 20) + +#define PIN_PA13G_TCC1_WO3 _UINT32_(13) +#define MUX_PA13G_TCC1_WO3 _UINT32_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UINT32_(1) << 13) + +#define PIN_PA15G_TCC1_WO3 _UINT32_(15) +#define MUX_PA15G_TCC1_WO3 _UINT32_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UINT32_(1) << 15) + +#define PIN_PA19F_TCC1_WO3 _UINT32_(19) +#define MUX_PA19F_TCC1_WO3 _UINT32_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UINT32_(1) << 19) + +#define PIN_PB21F_TCC1_WO3 _UINT32_(53) +#define MUX_PB21F_TCC1_WO3 _UINT32_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UINT32_(1) << 21) + +#define PIN_PA08G_TCC1_WO4 _UINT32_(8) +#define MUX_PA08G_TCC1_WO4 _UINT32_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UINT32_(1) << 8) + +#define PIN_PC10G_TCC1_WO4 _UINT32_(74) +#define MUX_PC10G_TCC1_WO4 _UINT32_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UINT32_(1) << 10) + +#define PIN_PA20F_TCC1_WO4 _UINT32_(20) +#define MUX_PA20F_TCC1_WO4 _UINT32_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UINT32_(1) << 20) + +#define PIN_PA09G_TCC1_WO5 _UINT32_(9) +#define MUX_PA09G_TCC1_WO5 _UINT32_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UINT32_(1) << 9) + +#define PIN_PC11G_TCC1_WO5 _UINT32_(75) +#define MUX_PC11G_TCC1_WO5 _UINT32_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UINT32_(1) << 11) + +#define PIN_PA21F_TCC1_WO5 _UINT32_(21) +#define MUX_PA21F_TCC1_WO5 _UINT32_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UINT32_(1) << 21) + +#define PIN_PA10G_TCC1_WO6 _UINT32_(10) +#define MUX_PA10G_TCC1_WO6 _UINT32_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UINT32_(1) << 10) + +#define PIN_PC12G_TCC1_WO6 _UINT32_(76) +#define MUX_PC12G_TCC1_WO6 _UINT32_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UINT32_(1) << 12) + +#define PIN_PA22F_TCC1_WO6 _UINT32_(22) +#define MUX_PA22F_TCC1_WO6 _UINT32_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UINT32_(1) << 22) + +#define PIN_PA11G_TCC1_WO7 _UINT32_(11) +#define MUX_PA11G_TCC1_WO7 _UINT32_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UINT32_(1) << 11) + +#define PIN_PC13G_TCC1_WO7 _UINT32_(77) +#define MUX_PC13G_TCC1_WO7 _UINT32_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UINT32_(1) << 13) + +#define PIN_PA23F_TCC1_WO7 _UINT32_(23) +#define MUX_PA23F_TCC1_WO7 _UINT32_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UINT32_(1) << 23) + +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _UINT32_(14) +#define MUX_PA14F_TCC2_WO0 _UINT32_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UINT32_(1) << 14) + +#define PIN_PA30F_TCC2_WO0 _UINT32_(30) +#define MUX_PA30F_TCC2_WO0 _UINT32_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UINT32_(1) << 30) + +#define PIN_PA15F_TCC2_WO1 _UINT32_(15) +#define MUX_PA15F_TCC2_WO1 _UINT32_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UINT32_(1) << 15) + +#define PIN_PA31F_TCC2_WO1 _UINT32_(31) +#define MUX_PA31F_TCC2_WO1 _UINT32_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UINT32_(1) << 31) + +#define PIN_PA24F_TCC2_WO2 _UINT32_(24) +#define MUX_PA24F_TCC2_WO2 _UINT32_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UINT32_(1) << 24) + +#define PIN_PB02F_TCC2_WO2 _UINT32_(34) +#define MUX_PB02F_TCC2_WO2 _UINT32_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UINT32_(1) << 2) + +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _UINT32_(44) +#define MUX_PB12F_TCC3_WO0 _UINT32_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UINT32_(1) << 12) + +#define PIN_PB16F_TCC3_WO0 _UINT32_(48) +#define MUX_PB16F_TCC3_WO0 _UINT32_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UINT32_(1) << 16) + +#define PIN_PB13F_TCC3_WO1 _UINT32_(45) +#define MUX_PB13F_TCC3_WO1 _UINT32_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UINT32_(1) << 13) + +#define PIN_PB17F_TCC3_WO1 _UINT32_(49) +#define MUX_PB17F_TCC3_WO1 _UINT32_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _UINT32_(46) +#define MUX_PB14F_TCC4_WO0 _UINT32_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UINT32_(1) << 14) + +#define PIN_PB30F_TCC4_WO0 _UINT32_(62) +#define MUX_PB30F_TCC4_WO0 _UINT32_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UINT32_(1) << 30) + +#define PIN_PB15F_TCC4_WO1 _UINT32_(47) +#define MUX_PB15F_TCC4_WO1 _UINT32_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UINT32_(1) << 15) + +#define PIN_PB31F_TCC4_WO1 _UINT32_(63) +#define MUX_PB31F_TCC4_WO1 _UINT32_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UINT32_(1) << 31) + +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _UINT32_(24) +#define MUX_PA24H_USB_DM _UINT32_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UINT32_(1) << 24) + +#define PIN_PA25H_USB_DP _UINT32_(25) +#define MUX_PA25H_USB_DP _UINT32_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UINT32_(1) << 25) + +#define PIN_PA23H_USB_SOF_1KHZ _UINT32_(23) +#define MUX_PA23H_USB_SOF_1KHZ _UINT32_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UINT32_(1) << 23) + +#define PIN_PB22H_USB_SOF_1KHZ _UINT32_(54) +#define MUX_PB22H_USB_SOF_1KHZ _UINT32_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UINT32_(1) << 22) + +/* ========== PORT definition for TPIU peripheral ========== */ +#define PIN_PC27H_TPIU_TRACECLK _UINT32_(91) +#define MUX_PC27H_TPIU_TRACECLK _UINT32_(7) +#define PINMUX_PC27H_TPIU_TRACECLK ((PIN_PC27H_TPIU_TRACECLK << 16) | MUX_PC27H_TPIU_TRACECLK) +#define PORT_PC27H_TPIU_TRACECLK (_UINT32_(1) << 27) + +#define PIN_PC28H_TPIU_TRACED0 _UINT32_(92) +#define MUX_PC28H_TPIU_TRACED0 _UINT32_(7) +#define PINMUX_PC28H_TPIU_TRACED0 ((PIN_PC28H_TPIU_TRACED0 << 16) | MUX_PC28H_TPIU_TRACED0) +#define PORT_PC28H_TPIU_TRACED0 (_UINT32_(1) << 28) + +#define PIN_PC26H_TPIU_TRACED1 _UINT32_(90) +#define MUX_PC26H_TPIU_TRACED1 _UINT32_(7) +#define PINMUX_PC26H_TPIU_TRACED1 ((PIN_PC26H_TPIU_TRACED1 << 16) | MUX_PC26H_TPIU_TRACED1) +#define PORT_PC26H_TPIU_TRACED1 (_UINT32_(1) << 26) + +#define PIN_PC25H_TPIU_TRACED2 _UINT32_(89) +#define MUX_PC25H_TPIU_TRACED2 _UINT32_(7) +#define PINMUX_PC25H_TPIU_TRACED2 ((PIN_PC25H_TPIU_TRACED2 << 16) | MUX_PC25H_TPIU_TRACED2) +#define PORT_PC25H_TPIU_TRACED2 (_UINT32_(1) << 25) + +#define PIN_PC24H_TPIU_TRACED3 _UINT32_(88) +#define MUX_PC24H_TPIU_TRACED3 _UINT32_(7) +#define PINMUX_PC24H_TPIU_TRACED3 ((PIN_PC24H_TPIU_TRACED3 << 16) | MUX_PC24H_TPIU_TRACED3) +#define PORT_PC24H_TPIU_TRACED3 (_UINT32_(1) << 24) + + + +#endif /* _SAME54N20A_GPIO_H_ */ + diff --git a/os/common/ext/Microchip/SAME54/pio/same54p19a.h b/os/common/ext/Microchip/SAME54/pio/same54p19a.h new file mode 100644 index 0000000000..f5ca40429e --- /dev/null +++ b/os/common/ext/Microchip/SAME54/pio/same54p19a.h @@ -0,0 +1,3651 @@ +/* + * Peripheral I/O description for SAME54P19A + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:07Z */ +#ifndef _SAME54P19A_GPIO_H_ +#define _SAME54P19A_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA00 ( 0) /**< Pin Number for PA00 */ +#define PIN_PA01 ( 1) /**< Pin Number for PA01 */ +#define PIN_PA02 ( 2) /**< Pin Number for PA02 */ +#define PIN_PA03 ( 3) /**< Pin Number for PA03 */ +#define PIN_PA04 ( 4) /**< Pin Number for PA04 */ +#define PIN_PA05 ( 5) /**< Pin Number for PA05 */ +#define PIN_PA06 ( 6) /**< Pin Number for PA06 */ +#define PIN_PA07 ( 7) /**< Pin Number for PA07 */ +#define PIN_PA08 ( 8) /**< Pin Number for PA08 */ +#define PIN_PA09 ( 9) /**< Pin Number for PA09 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB00 ( 32) /**< Pin Number for PB00 */ +#define PIN_PB01 ( 33) /**< Pin Number for PB01 */ +#define PIN_PB02 ( 34) /**< Pin Number for PB02 */ +#define PIN_PB03 ( 35) /**< Pin Number for PB03 */ +#define PIN_PB04 ( 36) /**< Pin Number for PB04 */ +#define PIN_PB05 ( 37) /**< Pin Number for PB05 */ +#define PIN_PB06 ( 38) /**< Pin Number for PB06 */ +#define PIN_PB07 ( 39) /**< Pin Number for PB07 */ +#define PIN_PB08 ( 40) /**< Pin Number for PB08 */ +#define PIN_PB09 ( 41) /**< Pin Number for PB09 */ +#define PIN_PB10 ( 42) /**< Pin Number for PB10 */ +#define PIN_PB11 ( 43) /**< Pin Number for PB11 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PB14 ( 46) /**< Pin Number for PB14 */ +#define PIN_PB15 ( 47) /**< Pin Number for PB15 */ +#define PIN_PB16 ( 48) /**< Pin Number for PB16 */ +#define PIN_PB17 ( 49) /**< Pin Number for PB17 */ +#define PIN_PB18 ( 50) /**< Pin Number for PB18 */ +#define PIN_PB19 ( 51) /**< Pin Number for PB19 */ +#define PIN_PB20 ( 52) /**< Pin Number for PB20 */ +#define PIN_PB21 ( 53) /**< Pin Number for PB21 */ +#define PIN_PB22 ( 54) /**< Pin Number for PB22 */ +#define PIN_PB23 ( 55) /**< Pin Number for PB23 */ +#define PIN_PB24 ( 56) /**< Pin Number for PB24 */ +#define PIN_PB25 ( 57) /**< Pin Number for PB25 */ +#define PIN_PB26 ( 58) /**< Pin Number for PB26 */ +#define PIN_PB27 ( 59) /**< Pin Number for PB27 */ +#define PIN_PB28 ( 60) /**< Pin Number for PB28 */ +#define PIN_PB29 ( 61) /**< Pin Number for PB29 */ +#define PIN_PB30 ( 62) /**< Pin Number for PB30 */ +#define PIN_PB31 ( 63) /**< Pin Number for PB31 */ +#define PIN_PC00 ( 64) /**< Pin Number for PC00 */ +#define PIN_PC01 ( 65) /**< Pin Number for PC01 */ +#define PIN_PC02 ( 66) /**< Pin Number for PC02 */ +#define PIN_PC03 ( 67) /**< Pin Number for PC03 */ +#define PIN_PC04 ( 68) /**< Pin Number for PC04 */ +#define PIN_PC05 ( 69) /**< Pin Number for PC05 */ +#define PIN_PC06 ( 70) /**< Pin Number for PC06 */ +#define PIN_PC07 ( 71) /**< Pin Number for PC07 */ +#define PIN_PC10 ( 74) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85) /**< Pin Number for PC21 */ +#define PIN_PC22 ( 86) /**< Pin Number for PC22 */ +#define PIN_PC23 ( 87) /**< Pin Number for PC23 */ +#define PIN_PC24 ( 88) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92) /**< Pin Number for PC28 */ +#define PIN_PC30 ( 94) /**< Pin Number for PC30 */ +#define PIN_PC31 ( 95) /**< Pin Number for PC31 */ +#define PIN_PD00 ( 96) /**< Pin Number for PD00 */ +#define PIN_PD01 ( 97) /**< Pin Number for PD01 */ +#define PIN_PD08 ( 104) /**< Pin Number for PD08 */ +#define PIN_PD09 ( 105) /**< Pin Number for PD09 */ +#define PIN_PD10 ( 106) /**< Pin Number for PD10 */ +#define PIN_PD11 ( 107) /**< Pin Number for PD11 */ +#define PIN_PD12 ( 108) /**< Pin Number for PD12 */ +#define PIN_PD20 ( 116) /**< Pin Number for PD20 */ +#define PIN_PD21 ( 117) /**< Pin Number for PD21 */ + +/* ========== Peripheral I/O masks ========== */ +#define PORT_PA00 (_UINT32_(1) << 0) /**< PORT mask for PA00 */ +#define PORT_PA01 (_UINT32_(1) << 1) /**< PORT mask for PA01 */ +#define PORT_PA02 (_UINT32_(1) << 2) /**< PORT mask for PA02 */ +#define PORT_PA03 (_UINT32_(1) << 3) /**< PORT mask for PA03 */ +#define PORT_PA04 (_UINT32_(1) << 4) /**< PORT mask for PA04 */ +#define PORT_PA05 (_UINT32_(1) << 5) /**< PORT mask for PA05 */ +#define PORT_PA06 (_UINT32_(1) << 6) /**< PORT mask for PA06 */ +#define PORT_PA07 (_UINT32_(1) << 7) /**< PORT mask for PA07 */ +#define PORT_PA08 (_UINT32_(1) << 8) /**< PORT mask for PA08 */ +#define PORT_PA09 (_UINT32_(1) << 9) /**< PORT mask for PA09 */ +#define PORT_PA10 (_UINT32_(1) << 10) /**< PORT mask for PA10 */ +#define PORT_PA11 (_UINT32_(1) << 11) /**< PORT mask for PA11 */ +#define PORT_PA12 (_UINT32_(1) << 12) /**< PORT mask for PA12 */ +#define PORT_PA13 (_UINT32_(1) << 13) /**< PORT mask for PA13 */ +#define PORT_PA14 (_UINT32_(1) << 14) /**< PORT mask for PA14 */ +#define PORT_PA15 (_UINT32_(1) << 15) /**< PORT mask for PA15 */ +#define PORT_PA16 (_UINT32_(1) << 16) /**< PORT mask for PA16 */ +#define PORT_PA17 (_UINT32_(1) << 17) /**< PORT mask for PA17 */ +#define PORT_PA18 (_UINT32_(1) << 18) /**< PORT mask for PA18 */ +#define PORT_PA19 (_UINT32_(1) << 19) /**< PORT mask for PA19 */ +#define PORT_PA20 (_UINT32_(1) << 20) /**< PORT mask for PA20 */ +#define PORT_PA21 (_UINT32_(1) << 21) /**< PORT mask for PA21 */ +#define PORT_PA22 (_UINT32_(1) << 22) /**< PORT mask for PA22 */ +#define PORT_PA23 (_UINT32_(1) << 23) /**< PORT mask for PA23 */ +#define PORT_PA24 (_UINT32_(1) << 24) /**< PORT mask for PA24 */ +#define PORT_PA25 (_UINT32_(1) << 25) /**< PORT mask for PA25 */ +#define PORT_PA27 (_UINT32_(1) << 27) /**< PORT mask for PA27 */ +#define PORT_PA30 (_UINT32_(1) << 30) /**< PORT mask for PA30 */ +#define PORT_PA31 (_UINT32_(1) << 31) /**< PORT mask for PA31 */ +#define PORT_PB00 (_UINT32_(1) << 0) /**< PORT mask for PB00 */ +#define PORT_PB01 (_UINT32_(1) << 1) /**< PORT mask for PB01 */ +#define PORT_PB02 (_UINT32_(1) << 2) /**< PORT mask for PB02 */ +#define PORT_PB03 (_UINT32_(1) << 3) /**< PORT mask for PB03 */ +#define PORT_PB04 (_UINT32_(1) << 4) /**< PORT mask for PB04 */ +#define PORT_PB05 (_UINT32_(1) << 5) /**< PORT mask for PB05 */ +#define PORT_PB06 (_UINT32_(1) << 6) /**< PORT mask for PB06 */ +#define PORT_PB07 (_UINT32_(1) << 7) /**< PORT mask for PB07 */ +#define PORT_PB08 (_UINT32_(1) << 8) /**< PORT mask for PB08 */ +#define PORT_PB09 (_UINT32_(1) << 9) /**< PORT mask for PB09 */ +#define PORT_PB10 (_UINT32_(1) << 10) /**< PORT mask for PB10 */ +#define PORT_PB11 (_UINT32_(1) << 11) /**< PORT mask for PB11 */ +#define PORT_PB12 (_UINT32_(1) << 12) /**< PORT mask for PB12 */ +#define PORT_PB13 (_UINT32_(1) << 13) /**< PORT mask for PB13 */ +#define PORT_PB14 (_UINT32_(1) << 14) /**< PORT mask for PB14 */ +#define PORT_PB15 (_UINT32_(1) << 15) /**< PORT mask for PB15 */ +#define PORT_PB16 (_UINT32_(1) << 16) /**< PORT mask for PB16 */ +#define PORT_PB17 (_UINT32_(1) << 17) /**< PORT mask for PB17 */ +#define PORT_PB18 (_UINT32_(1) << 18) /**< PORT mask for PB18 */ +#define PORT_PB19 (_UINT32_(1) << 19) /**< PORT mask for PB19 */ +#define PORT_PB20 (_UINT32_(1) << 20) /**< PORT mask for PB20 */ +#define PORT_PB21 (_UINT32_(1) << 21) /**< PORT mask for PB21 */ +#define PORT_PB22 (_UINT32_(1) << 22) /**< PORT mask for PB22 */ +#define PORT_PB23 (_UINT32_(1) << 23) /**< PORT mask for PB23 */ +#define PORT_PB24 (_UINT32_(1) << 24) /**< PORT mask for PB24 */ +#define PORT_PB25 (_UINT32_(1) << 25) /**< PORT mask for PB25 */ +#define PORT_PB26 (_UINT32_(1) << 26) /**< PORT mask for PB26 */ +#define PORT_PB27 (_UINT32_(1) << 27) /**< PORT mask for PB27 */ +#define PORT_PB28 (_UINT32_(1) << 28) /**< PORT mask for PB28 */ +#define PORT_PB29 (_UINT32_(1) << 29) /**< PORT mask for PB29 */ +#define PORT_PB30 (_UINT32_(1) << 30) /**< PORT mask for PB30 */ +#define PORT_PB31 (_UINT32_(1) << 31) /**< PORT mask for PB31 */ +#define PORT_PC00 (_UINT32_(1) << 0) /**< PORT mask for PC00 */ +#define PORT_PC01 (_UINT32_(1) << 1) /**< PORT mask for PC01 */ +#define PORT_PC02 (_UINT32_(1) << 2) /**< PORT mask for PC02 */ +#define PORT_PC03 (_UINT32_(1) << 3) /**< PORT mask for PC03 */ +#define PORT_PC04 (_UINT32_(1) << 4) /**< PORT mask for PC04 */ +#define PORT_PC05 (_UINT32_(1) << 5) /**< PORT mask for PC05 */ +#define PORT_PC06 (_UINT32_(1) << 6) /**< PORT mask for PC06 */ +#define PORT_PC07 (_UINT32_(1) << 7) /**< PORT mask for PC07 */ +#define PORT_PC10 (_UINT32_(1) << 10) /**< PORT mask for PC10 */ +#define PORT_PC11 (_UINT32_(1) << 11) /**< PORT mask for PC11 */ +#define PORT_PC12 (_UINT32_(1) << 12) /**< PORT mask for PC12 */ +#define PORT_PC13 (_UINT32_(1) << 13) /**< PORT mask for PC13 */ +#define PORT_PC14 (_UINT32_(1) << 14) /**< PORT mask for PC14 */ +#define PORT_PC15 (_UINT32_(1) << 15) /**< PORT mask for PC15 */ +#define PORT_PC16 (_UINT32_(1) << 16) /**< PORT mask for PC16 */ +#define PORT_PC17 (_UINT32_(1) << 17) /**< PORT mask for PC17 */ +#define PORT_PC18 (_UINT32_(1) << 18) /**< PORT mask for PC18 */ +#define PORT_PC19 (_UINT32_(1) << 19) /**< PORT mask for PC19 */ +#define PORT_PC20 (_UINT32_(1) << 20) /**< PORT mask for PC20 */ +#define PORT_PC21 (_UINT32_(1) << 21) /**< PORT mask for PC21 */ +#define PORT_PC22 (_UINT32_(1) << 22) /**< PORT mask for PC22 */ +#define PORT_PC23 (_UINT32_(1) << 23) /**< PORT mask for PC23 */ +#define PORT_PC24 (_UINT32_(1) << 24) /**< PORT mask for PC24 */ +#define PORT_PC25 (_UINT32_(1) << 25) /**< PORT mask for PC25 */ +#define PORT_PC26 (_UINT32_(1) << 26) /**< PORT mask for PC26 */ +#define PORT_PC27 (_UINT32_(1) << 27) /**< PORT mask for PC27 */ +#define PORT_PC28 (_UINT32_(1) << 28) /**< PORT mask for PC28 */ +#define PORT_PC30 (_UINT32_(1) << 30) /**< PORT mask for PC30 */ +#define PORT_PC31 (_UINT32_(1) << 31) /**< PORT mask for PC31 */ +#define PORT_PD00 (_UINT32_(1) << 0) /**< PORT mask for PD00 */ +#define PORT_PD01 (_UINT32_(1) << 1) /**< PORT mask for PD01 */ +#define PORT_PD08 (_UINT32_(1) << 8) /**< PORT mask for PD08 */ +#define PORT_PD09 (_UINT32_(1) << 9) /**< PORT mask for PD09 */ +#define PORT_PD10 (_UINT32_(1) << 10) /**< PORT mask for PD10 */ +#define PORT_PD11 (_UINT32_(1) << 11) /**< PORT mask for PD11 */ +#define PORT_PD12 (_UINT32_(1) << 12) /**< PORT mask for PD12 */ +#define PORT_PD20 (_UINT32_(1) << 20) /**< PORT mask for PD20 */ +#define PORT_PD21 (_UINT32_(1) << 21) /**< PORT mask for PD21 */ + +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _UINT32_(4) +#define MUX_PA04B_AC_AIN0 _UINT32_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UINT32_(1) << 4) + +#define PIN_PA05B_AC_AIN1 _UINT32_(5) +#define MUX_PA05B_AC_AIN1 _UINT32_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UINT32_(1) << 5) + +#define PIN_PA06B_AC_AIN2 _UINT32_(6) +#define MUX_PA06B_AC_AIN2 _UINT32_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UINT32_(1) << 6) + +#define PIN_PA07B_AC_AIN3 _UINT32_(7) +#define MUX_PA07B_AC_AIN3 _UINT32_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UINT32_(1) << 7) + +#define PIN_PA12M_AC_CMP0 _UINT32_(12) +#define MUX_PA12M_AC_CMP0 _UINT32_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UINT32_(1) << 12) + +#define PIN_PA18M_AC_CMP0 _UINT32_(18) +#define MUX_PA18M_AC_CMP0 _UINT32_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UINT32_(1) << 18) + +#define PIN_PB24M_AC_CMP0 _UINT32_(56) +#define MUX_PB24M_AC_CMP0 _UINT32_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UINT32_(1) << 24) + +#define PIN_PA13M_AC_CMP1 _UINT32_(13) +#define MUX_PA13M_AC_CMP1 _UINT32_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UINT32_(1) << 13) + +#define PIN_PA19M_AC_CMP1 _UINT32_(19) +#define MUX_PA19M_AC_CMP1 _UINT32_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UINT32_(1) << 19) + +#define PIN_PB25M_AC_CMP1 _UINT32_(57) +#define MUX_PB25M_AC_CMP1 _UINT32_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UINT32_(1) << 25) + +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _UINT32_(2) +#define MUX_PA02B_ADC0_AIN0 _UINT32_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UINT32_(1) << 2) + +#define PIN_PA03B_ADC0_AIN1 _UINT32_(3) +#define MUX_PA03B_ADC0_AIN1 _UINT32_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_AIN2 _UINT32_(40) +#define MUX_PB08B_ADC0_AIN2 _UINT32_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_AIN3 _UINT32_(41) +#define MUX_PB09B_ADC0_AIN3 _UINT32_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_AIN4 _UINT32_(4) +#define MUX_PA04B_ADC0_AIN4 _UINT32_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UINT32_(1) << 4) + +#define PIN_PA05B_ADC0_AIN5 _UINT32_(5) +#define MUX_PA05B_ADC0_AIN5 _UINT32_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UINT32_(1) << 5) + +#define PIN_PA06B_ADC0_AIN6 _UINT32_(6) +#define MUX_PA06B_ADC0_AIN6 _UINT32_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_AIN7 _UINT32_(7) +#define MUX_PA07B_ADC0_AIN7 _UINT32_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_AIN8 _UINT32_(8) +#define MUX_PA08B_ADC0_AIN8 _UINT32_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_AIN9 _UINT32_(9) +#define MUX_PA09B_ADC0_AIN9 _UINT32_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_AIN10 _UINT32_(10) +#define MUX_PA10B_ADC0_AIN10 _UINT32_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_AIN11 _UINT32_(11) +#define MUX_PA11B_ADC0_AIN11 _UINT32_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UINT32_(1) << 11) + +#define PIN_PB00B_ADC0_AIN12 _UINT32_(32) +#define MUX_PB00B_ADC0_AIN12 _UINT32_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_AIN13 _UINT32_(33) +#define MUX_PB01B_ADC0_AIN13 _UINT32_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UINT32_(1) << 1) + +#define PIN_PB02B_ADC0_AIN14 _UINT32_(34) +#define MUX_PB02B_ADC0_AIN14 _UINT32_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_AIN15 _UINT32_(35) +#define MUX_PB03B_ADC0_AIN15 _UINT32_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UINT32_(1) << 3) + +#define PIN_PA03B_ADC0_VREFA _UINT32_(3) +#define MUX_PA03B_ADC0_VREFA _UINT32_(1) +#define PINMUX_PA03B_ADC0_VREFA ((PIN_PA03B_ADC0_VREFA << 16) | MUX_PA03B_ADC0_VREFA) +#define PORT_PA03B_ADC0_VREFA (_UINT32_(1) << 3) + +#define PIN_PA04B_ADC0_VREFB _UINT32_(4) +#define MUX_PA04B_ADC0_VREFB _UINT32_(1) +#define PINMUX_PA04B_ADC0_VREFB ((PIN_PA04B_ADC0_VREFB << 16) | MUX_PA04B_ADC0_VREFB) +#define PORT_PA04B_ADC0_VREFB (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_VREFC _UINT32_(6) +#define MUX_PA06B_ADC0_VREFC _UINT32_(1) +#define PINMUX_PA06B_ADC0_VREFC ((PIN_PA06B_ADC0_VREFC << 16) | MUX_PA06B_ADC0_VREFC) +#define PORT_PA06B_ADC0_VREFC (_UINT32_(1) << 6) + +#define PIN_PA03B_ADC0_X0 _UINT32_(3) +#define MUX_PA03B_ADC0_X0 _UINT32_(1) +#define PINMUX_PA03B_ADC0_X0 ((PIN_PA03B_ADC0_X0 << 16) | MUX_PA03B_ADC0_X0) +#define PORT_PA03B_ADC0_X0 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_X1 _UINT32_(40) +#define MUX_PB08B_ADC0_X1 _UINT32_(1) +#define PINMUX_PB08B_ADC0_X1 ((PIN_PB08B_ADC0_X1 << 16) | MUX_PB08B_ADC0_X1) +#define PORT_PB08B_ADC0_X1 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_X2 _UINT32_(41) +#define MUX_PB09B_ADC0_X2 _UINT32_(1) +#define PINMUX_PB09B_ADC0_X2 ((PIN_PB09B_ADC0_X2 << 16) | MUX_PB09B_ADC0_X2) +#define PORT_PB09B_ADC0_X2 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_X3 _UINT32_(4) +#define MUX_PA04B_ADC0_X3 _UINT32_(1) +#define PINMUX_PA04B_ADC0_X3 ((PIN_PA04B_ADC0_X3 << 16) | MUX_PA04B_ADC0_X3) +#define PORT_PA04B_ADC0_X3 (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_X4 _UINT32_(6) +#define MUX_PA06B_ADC0_X4 _UINT32_(1) +#define PINMUX_PA06B_ADC0_X4 ((PIN_PA06B_ADC0_X4 << 16) | MUX_PA06B_ADC0_X4) +#define PORT_PA06B_ADC0_X4 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_X5 _UINT32_(7) +#define MUX_PA07B_ADC0_X5 _UINT32_(1) +#define PINMUX_PA07B_ADC0_X5 ((PIN_PA07B_ADC0_X5 << 16) | MUX_PA07B_ADC0_X5) +#define PORT_PA07B_ADC0_X5 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_X6 _UINT32_(8) +#define MUX_PA08B_ADC0_X6 _UINT32_(1) +#define PINMUX_PA08B_ADC0_X6 ((PIN_PA08B_ADC0_X6 << 16) | MUX_PA08B_ADC0_X6) +#define PORT_PA08B_ADC0_X6 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_X7 _UINT32_(9) +#define MUX_PA09B_ADC0_X7 _UINT32_(1) +#define PINMUX_PA09B_ADC0_X7 ((PIN_PA09B_ADC0_X7 << 16) | MUX_PA09B_ADC0_X7) +#define PORT_PA09B_ADC0_X7 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_X8 _UINT32_(10) +#define MUX_PA10B_ADC0_X8 _UINT32_(1) +#define PINMUX_PA10B_ADC0_X8 ((PIN_PA10B_ADC0_X8 << 16) | MUX_PA10B_ADC0_X8) +#define PORT_PA10B_ADC0_X8 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_X9 _UINT32_(11) +#define MUX_PA11B_ADC0_X9 _UINT32_(1) +#define PINMUX_PA11B_ADC0_X9 ((PIN_PA11B_ADC0_X9 << 16) | MUX_PA11B_ADC0_X9) +#define PORT_PA11B_ADC0_X9 (_UINT32_(1) << 11) + +#define PIN_PA16B_ADC0_X10 _UINT32_(16) +#define MUX_PA16B_ADC0_X10 _UINT32_(1) +#define PINMUX_PA16B_ADC0_X10 ((PIN_PA16B_ADC0_X10 << 16) | MUX_PA16B_ADC0_X10) +#define PORT_PA16B_ADC0_X10 (_UINT32_(1) << 16) + +#define PIN_PA17B_ADC0_X11 _UINT32_(17) +#define MUX_PA17B_ADC0_X11 _UINT32_(1) +#define PINMUX_PA17B_ADC0_X11 ((PIN_PA17B_ADC0_X11 << 16) | MUX_PA17B_ADC0_X11) +#define PORT_PA17B_ADC0_X11 (_UINT32_(1) << 17) + +#define PIN_PA18B_ADC0_X12 _UINT32_(18) +#define MUX_PA18B_ADC0_X12 _UINT32_(1) +#define PINMUX_PA18B_ADC0_X12 ((PIN_PA18B_ADC0_X12 << 16) | MUX_PA18B_ADC0_X12) +#define PORT_PA18B_ADC0_X12 (_UINT32_(1) << 18) + +#define PIN_PA19B_ADC0_X13 _UINT32_(19) +#define MUX_PA19B_ADC0_X13 _UINT32_(1) +#define PINMUX_PA19B_ADC0_X13 ((PIN_PA19B_ADC0_X13 << 16) | MUX_PA19B_ADC0_X13) +#define PORT_PA19B_ADC0_X13 (_UINT32_(1) << 19) + +#define PIN_PA20B_ADC0_X14 _UINT32_(20) +#define MUX_PA20B_ADC0_X14 _UINT32_(1) +#define PINMUX_PA20B_ADC0_X14 ((PIN_PA20B_ADC0_X14 << 16) | MUX_PA20B_ADC0_X14) +#define PORT_PA20B_ADC0_X14 (_UINT32_(1) << 20) + +#define PIN_PA21B_ADC0_X15 _UINT32_(21) +#define MUX_PA21B_ADC0_X15 _UINT32_(1) +#define PINMUX_PA21B_ADC0_X15 ((PIN_PA21B_ADC0_X15 << 16) | MUX_PA21B_ADC0_X15) +#define PORT_PA21B_ADC0_X15 (_UINT32_(1) << 21) + +#define PIN_PA22B_ADC0_X16 _UINT32_(22) +#define MUX_PA22B_ADC0_X16 _UINT32_(1) +#define PINMUX_PA22B_ADC0_X16 ((PIN_PA22B_ADC0_X16 << 16) | MUX_PA22B_ADC0_X16) +#define PORT_PA22B_ADC0_X16 (_UINT32_(1) << 22) + +#define PIN_PA23B_ADC0_X17 _UINT32_(23) +#define MUX_PA23B_ADC0_X17 _UINT32_(1) +#define PINMUX_PA23B_ADC0_X17 ((PIN_PA23B_ADC0_X17 << 16) | MUX_PA23B_ADC0_X17) +#define PORT_PA23B_ADC0_X17 (_UINT32_(1) << 23) + +#define PIN_PA27B_ADC0_X18 _UINT32_(27) +#define MUX_PA27B_ADC0_X18 _UINT32_(1) +#define PINMUX_PA27B_ADC0_X18 ((PIN_PA27B_ADC0_X18 << 16) | MUX_PA27B_ADC0_X18) +#define PORT_PA27B_ADC0_X18 (_UINT32_(1) << 27) + +#define PIN_PA30B_ADC0_X19 _UINT32_(30) +#define MUX_PA30B_ADC0_X19 _UINT32_(1) +#define PINMUX_PA30B_ADC0_X19 ((PIN_PA30B_ADC0_X19 << 16) | MUX_PA30B_ADC0_X19) +#define PORT_PA30B_ADC0_X19 (_UINT32_(1) << 30) + +#define PIN_PB02B_ADC0_X20 _UINT32_(34) +#define MUX_PB02B_ADC0_X20 _UINT32_(1) +#define PINMUX_PB02B_ADC0_X20 ((PIN_PB02B_ADC0_X20 << 16) | MUX_PB02B_ADC0_X20) +#define PORT_PB02B_ADC0_X20 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_X21 _UINT32_(35) +#define MUX_PB03B_ADC0_X21 _UINT32_(1) +#define PINMUX_PB03B_ADC0_X21 ((PIN_PB03B_ADC0_X21 << 16) | MUX_PB03B_ADC0_X21) +#define PORT_PB03B_ADC0_X21 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC0_X22 _UINT32_(36) +#define MUX_PB04B_ADC0_X22 _UINT32_(1) +#define PINMUX_PB04B_ADC0_X22 ((PIN_PB04B_ADC0_X22 << 16) | MUX_PB04B_ADC0_X22) +#define PORT_PB04B_ADC0_X22 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC0_X23 _UINT32_(37) +#define MUX_PB05B_ADC0_X23 _UINT32_(1) +#define PINMUX_PB05B_ADC0_X23 ((PIN_PB05B_ADC0_X23 << 16) | MUX_PB05B_ADC0_X23) +#define PORT_PB05B_ADC0_X23 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC0_X24 _UINT32_(38) +#define MUX_PB06B_ADC0_X24 _UINT32_(1) +#define PINMUX_PB06B_ADC0_X24 ((PIN_PB06B_ADC0_X24 << 16) | MUX_PB06B_ADC0_X24) +#define PORT_PB06B_ADC0_X24 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC0_X25 _UINT32_(39) +#define MUX_PB07B_ADC0_X25 _UINT32_(1) +#define PINMUX_PB07B_ADC0_X25 ((PIN_PB07B_ADC0_X25 << 16) | MUX_PB07B_ADC0_X25) +#define PORT_PB07B_ADC0_X25 (_UINT32_(1) << 7) + +#define PIN_PB12B_ADC0_X26 _UINT32_(44) +#define MUX_PB12B_ADC0_X26 _UINT32_(1) +#define PINMUX_PB12B_ADC0_X26 ((PIN_PB12B_ADC0_X26 << 16) | MUX_PB12B_ADC0_X26) +#define PORT_PB12B_ADC0_X26 (_UINT32_(1) << 12) + +#define PIN_PB13B_ADC0_X27 _UINT32_(45) +#define MUX_PB13B_ADC0_X27 _UINT32_(1) +#define PINMUX_PB13B_ADC0_X27 ((PIN_PB13B_ADC0_X27 << 16) | MUX_PB13B_ADC0_X27) +#define PORT_PB13B_ADC0_X27 (_UINT32_(1) << 13) + +#define PIN_PB14B_ADC0_X28 _UINT32_(46) +#define MUX_PB14B_ADC0_X28 _UINT32_(1) +#define PINMUX_PB14B_ADC0_X28 ((PIN_PB14B_ADC0_X28 << 16) | MUX_PB14B_ADC0_X28) +#define PORT_PB14B_ADC0_X28 (_UINT32_(1) << 14) + +#define PIN_PB15B_ADC0_X29 _UINT32_(47) +#define MUX_PB15B_ADC0_X29 _UINT32_(1) +#define PINMUX_PB15B_ADC0_X29 ((PIN_PB15B_ADC0_X29 << 16) | MUX_PB15B_ADC0_X29) +#define PORT_PB15B_ADC0_X29 (_UINT32_(1) << 15) + +#define PIN_PB00B_ADC0_X30 _UINT32_(32) +#define MUX_PB00B_ADC0_X30 _UINT32_(1) +#define PINMUX_PB00B_ADC0_X30 ((PIN_PB00B_ADC0_X30 << 16) | MUX_PB00B_ADC0_X30) +#define PORT_PB00B_ADC0_X30 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_X31 _UINT32_(33) +#define MUX_PB01B_ADC0_X31 _UINT32_(1) +#define PINMUX_PB01B_ADC0_X31 ((PIN_PB01B_ADC0_X31 << 16) | MUX_PB01B_ADC0_X31) +#define PORT_PB01B_ADC0_X31 (_UINT32_(1) << 1) + +#define PIN_PA03B_ADC0_Y0 _UINT32_(3) +#define MUX_PA03B_ADC0_Y0 _UINT32_(1) +#define PINMUX_PA03B_ADC0_Y0 ((PIN_PA03B_ADC0_Y0 << 16) | MUX_PA03B_ADC0_Y0) +#define PORT_PA03B_ADC0_Y0 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_Y1 _UINT32_(40) +#define MUX_PB08B_ADC0_Y1 _UINT32_(1) +#define PINMUX_PB08B_ADC0_Y1 ((PIN_PB08B_ADC0_Y1 << 16) | MUX_PB08B_ADC0_Y1) +#define PORT_PB08B_ADC0_Y1 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_Y2 _UINT32_(41) +#define MUX_PB09B_ADC0_Y2 _UINT32_(1) +#define PINMUX_PB09B_ADC0_Y2 ((PIN_PB09B_ADC0_Y2 << 16) | MUX_PB09B_ADC0_Y2) +#define PORT_PB09B_ADC0_Y2 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_Y3 _UINT32_(4) +#define MUX_PA04B_ADC0_Y3 _UINT32_(1) +#define PINMUX_PA04B_ADC0_Y3 ((PIN_PA04B_ADC0_Y3 << 16) | MUX_PA04B_ADC0_Y3) +#define PORT_PA04B_ADC0_Y3 (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_Y4 _UINT32_(6) +#define MUX_PA06B_ADC0_Y4 _UINT32_(1) +#define PINMUX_PA06B_ADC0_Y4 ((PIN_PA06B_ADC0_Y4 << 16) | MUX_PA06B_ADC0_Y4) +#define PORT_PA06B_ADC0_Y4 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_Y5 _UINT32_(7) +#define MUX_PA07B_ADC0_Y5 _UINT32_(1) +#define PINMUX_PA07B_ADC0_Y5 ((PIN_PA07B_ADC0_Y5 << 16) | MUX_PA07B_ADC0_Y5) +#define PORT_PA07B_ADC0_Y5 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_Y6 _UINT32_(8) +#define MUX_PA08B_ADC0_Y6 _UINT32_(1) +#define PINMUX_PA08B_ADC0_Y6 ((PIN_PA08B_ADC0_Y6 << 16) | MUX_PA08B_ADC0_Y6) +#define PORT_PA08B_ADC0_Y6 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_Y7 _UINT32_(9) +#define MUX_PA09B_ADC0_Y7 _UINT32_(1) +#define PINMUX_PA09B_ADC0_Y7 ((PIN_PA09B_ADC0_Y7 << 16) | MUX_PA09B_ADC0_Y7) +#define PORT_PA09B_ADC0_Y7 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_Y8 _UINT32_(10) +#define MUX_PA10B_ADC0_Y8 _UINT32_(1) +#define PINMUX_PA10B_ADC0_Y8 ((PIN_PA10B_ADC0_Y8 << 16) | MUX_PA10B_ADC0_Y8) +#define PORT_PA10B_ADC0_Y8 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_Y9 _UINT32_(11) +#define MUX_PA11B_ADC0_Y9 _UINT32_(1) +#define PINMUX_PA11B_ADC0_Y9 ((PIN_PA11B_ADC0_Y9 << 16) | MUX_PA11B_ADC0_Y9) +#define PORT_PA11B_ADC0_Y9 (_UINT32_(1) << 11) + +#define PIN_PA16B_ADC0_Y10 _UINT32_(16) +#define MUX_PA16B_ADC0_Y10 _UINT32_(1) +#define PINMUX_PA16B_ADC0_Y10 ((PIN_PA16B_ADC0_Y10 << 16) | MUX_PA16B_ADC0_Y10) +#define PORT_PA16B_ADC0_Y10 (_UINT32_(1) << 16) + +#define PIN_PA17B_ADC0_Y11 _UINT32_(17) +#define MUX_PA17B_ADC0_Y11 _UINT32_(1) +#define PINMUX_PA17B_ADC0_Y11 ((PIN_PA17B_ADC0_Y11 << 16) | MUX_PA17B_ADC0_Y11) +#define PORT_PA17B_ADC0_Y11 (_UINT32_(1) << 17) + +#define PIN_PA18B_ADC0_Y12 _UINT32_(18) +#define MUX_PA18B_ADC0_Y12 _UINT32_(1) +#define PINMUX_PA18B_ADC0_Y12 ((PIN_PA18B_ADC0_Y12 << 16) | MUX_PA18B_ADC0_Y12) +#define PORT_PA18B_ADC0_Y12 (_UINT32_(1) << 18) + +#define PIN_PA19B_ADC0_Y13 _UINT32_(19) +#define MUX_PA19B_ADC0_Y13 _UINT32_(1) +#define PINMUX_PA19B_ADC0_Y13 ((PIN_PA19B_ADC0_Y13 << 16) | MUX_PA19B_ADC0_Y13) +#define PORT_PA19B_ADC0_Y13 (_UINT32_(1) << 19) + +#define PIN_PA20B_ADC0_Y14 _UINT32_(20) +#define MUX_PA20B_ADC0_Y14 _UINT32_(1) +#define PINMUX_PA20B_ADC0_Y14 ((PIN_PA20B_ADC0_Y14 << 16) | MUX_PA20B_ADC0_Y14) +#define PORT_PA20B_ADC0_Y14 (_UINT32_(1) << 20) + +#define PIN_PA21B_ADC0_Y15 _UINT32_(21) +#define MUX_PA21B_ADC0_Y15 _UINT32_(1) +#define PINMUX_PA21B_ADC0_Y15 ((PIN_PA21B_ADC0_Y15 << 16) | MUX_PA21B_ADC0_Y15) +#define PORT_PA21B_ADC0_Y15 (_UINT32_(1) << 21) + +#define PIN_PA22B_ADC0_Y16 _UINT32_(22) +#define MUX_PA22B_ADC0_Y16 _UINT32_(1) +#define PINMUX_PA22B_ADC0_Y16 ((PIN_PA22B_ADC0_Y16 << 16) | MUX_PA22B_ADC0_Y16) +#define PORT_PA22B_ADC0_Y16 (_UINT32_(1) << 22) + +#define PIN_PA23B_ADC0_Y17 _UINT32_(23) +#define MUX_PA23B_ADC0_Y17 _UINT32_(1) +#define PINMUX_PA23B_ADC0_Y17 ((PIN_PA23B_ADC0_Y17 << 16) | MUX_PA23B_ADC0_Y17) +#define PORT_PA23B_ADC0_Y17 (_UINT32_(1) << 23) + +#define PIN_PA27B_ADC0_Y18 _UINT32_(27) +#define MUX_PA27B_ADC0_Y18 _UINT32_(1) +#define PINMUX_PA27B_ADC0_Y18 ((PIN_PA27B_ADC0_Y18 << 16) | MUX_PA27B_ADC0_Y18) +#define PORT_PA27B_ADC0_Y18 (_UINT32_(1) << 27) + +#define PIN_PA30B_ADC0_Y19 _UINT32_(30) +#define MUX_PA30B_ADC0_Y19 _UINT32_(1) +#define PINMUX_PA30B_ADC0_Y19 ((PIN_PA30B_ADC0_Y19 << 16) | MUX_PA30B_ADC0_Y19) +#define PORT_PA30B_ADC0_Y19 (_UINT32_(1) << 30) + +#define PIN_PB02B_ADC0_Y20 _UINT32_(34) +#define MUX_PB02B_ADC0_Y20 _UINT32_(1) +#define PINMUX_PB02B_ADC0_Y20 ((PIN_PB02B_ADC0_Y20 << 16) | MUX_PB02B_ADC0_Y20) +#define PORT_PB02B_ADC0_Y20 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_Y21 _UINT32_(35) +#define MUX_PB03B_ADC0_Y21 _UINT32_(1) +#define PINMUX_PB03B_ADC0_Y21 ((PIN_PB03B_ADC0_Y21 << 16) | MUX_PB03B_ADC0_Y21) +#define PORT_PB03B_ADC0_Y21 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC0_Y22 _UINT32_(36) +#define MUX_PB04B_ADC0_Y22 _UINT32_(1) +#define PINMUX_PB04B_ADC0_Y22 ((PIN_PB04B_ADC0_Y22 << 16) | MUX_PB04B_ADC0_Y22) +#define PORT_PB04B_ADC0_Y22 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC0_Y23 _UINT32_(37) +#define MUX_PB05B_ADC0_Y23 _UINT32_(1) +#define PINMUX_PB05B_ADC0_Y23 ((PIN_PB05B_ADC0_Y23 << 16) | MUX_PB05B_ADC0_Y23) +#define PORT_PB05B_ADC0_Y23 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC0_Y24 _UINT32_(38) +#define MUX_PB06B_ADC0_Y24 _UINT32_(1) +#define PINMUX_PB06B_ADC0_Y24 ((PIN_PB06B_ADC0_Y24 << 16) | MUX_PB06B_ADC0_Y24) +#define PORT_PB06B_ADC0_Y24 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC0_Y25 _UINT32_(39) +#define MUX_PB07B_ADC0_Y25 _UINT32_(1) +#define PINMUX_PB07B_ADC0_Y25 ((PIN_PB07B_ADC0_Y25 << 16) | MUX_PB07B_ADC0_Y25) +#define PORT_PB07B_ADC0_Y25 (_UINT32_(1) << 7) + +#define PIN_PB12B_ADC0_Y26 _UINT32_(44) +#define MUX_PB12B_ADC0_Y26 _UINT32_(1) +#define PINMUX_PB12B_ADC0_Y26 ((PIN_PB12B_ADC0_Y26 << 16) | MUX_PB12B_ADC0_Y26) +#define PORT_PB12B_ADC0_Y26 (_UINT32_(1) << 12) + +#define PIN_PB13B_ADC0_Y27 _UINT32_(45) +#define MUX_PB13B_ADC0_Y27 _UINT32_(1) +#define PINMUX_PB13B_ADC0_Y27 ((PIN_PB13B_ADC0_Y27 << 16) | MUX_PB13B_ADC0_Y27) +#define PORT_PB13B_ADC0_Y27 (_UINT32_(1) << 13) + +#define PIN_PB14B_ADC0_Y28 _UINT32_(46) +#define MUX_PB14B_ADC0_Y28 _UINT32_(1) +#define PINMUX_PB14B_ADC0_Y28 ((PIN_PB14B_ADC0_Y28 << 16) | MUX_PB14B_ADC0_Y28) +#define PORT_PB14B_ADC0_Y28 (_UINT32_(1) << 14) + +#define PIN_PB15B_ADC0_Y29 _UINT32_(47) +#define MUX_PB15B_ADC0_Y29 _UINT32_(1) +#define PINMUX_PB15B_ADC0_Y29 ((PIN_PB15B_ADC0_Y29 << 16) | MUX_PB15B_ADC0_Y29) +#define PORT_PB15B_ADC0_Y29 (_UINT32_(1) << 15) + +#define PIN_PB00B_ADC0_Y30 _UINT32_(32) +#define MUX_PB00B_ADC0_Y30 _UINT32_(1) +#define PINMUX_PB00B_ADC0_Y30 ((PIN_PB00B_ADC0_Y30 << 16) | MUX_PB00B_ADC0_Y30) +#define PORT_PB00B_ADC0_Y30 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_Y31 _UINT32_(33) +#define MUX_PB01B_ADC0_Y31 _UINT32_(1) +#define PINMUX_PB01B_ADC0_Y31 ((PIN_PB01B_ADC0_Y31 << 16) | MUX_PB01B_ADC0_Y31) +#define PORT_PB01B_ADC0_Y31 (_UINT32_(1) << 1) + +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _UINT32_(40) +#define MUX_PB08B_ADC1_AIN0 _UINT32_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC1_AIN1 _UINT32_(41) +#define MUX_PB09B_ADC1_AIN1 _UINT32_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UINT32_(1) << 9) + +#define PIN_PA08B_ADC1_AIN2 _UINT32_(8) +#define MUX_PA08B_ADC1_AIN2 _UINT32_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC1_AIN3 _UINT32_(9) +#define MUX_PA09B_ADC1_AIN3 _UINT32_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UINT32_(1) << 9) + +#define PIN_PC02B_ADC1_AIN4 _UINT32_(66) +#define MUX_PC02B_ADC1_AIN4 _UINT32_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UINT32_(1) << 2) + +#define PIN_PC03B_ADC1_AIN5 _UINT32_(67) +#define MUX_PC03B_ADC1_AIN5 _UINT32_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC1_AIN6 _UINT32_(36) +#define MUX_PB04B_ADC1_AIN6 _UINT32_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC1_AIN7 _UINT32_(37) +#define MUX_PB05B_ADC1_AIN7 _UINT32_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC1_AIN8 _UINT32_(38) +#define MUX_PB06B_ADC1_AIN8 _UINT32_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC1_AIN9 _UINT32_(39) +#define MUX_PB07B_ADC1_AIN9 _UINT32_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UINT32_(1) << 7) + +#define PIN_PC00B_ADC1_AIN10 _UINT32_(64) +#define MUX_PC00B_ADC1_AIN10 _UINT32_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UINT32_(1) << 0) + +#define PIN_PC01B_ADC1_AIN11 _UINT32_(65) +#define MUX_PC01B_ADC1_AIN11 _UINT32_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UINT32_(1) << 1) + +#define PIN_PC30B_ADC1_AIN12 _UINT32_(94) +#define MUX_PC30B_ADC1_AIN12 _UINT32_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UINT32_(1) << 30) + +#define PIN_PC31B_ADC1_AIN13 _UINT32_(95) +#define MUX_PC31B_ADC1_AIN13 _UINT32_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UINT32_(1) << 31) + +#define PIN_PD00B_ADC1_AIN14 _UINT32_(96) +#define MUX_PD00B_ADC1_AIN14 _UINT32_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UINT32_(1) << 0) + +#define PIN_PD01B_ADC1_AIN15 _UINT32_(97) +#define MUX_PD01B_ADC1_AIN15 _UINT32_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UINT32_(1) << 1) + +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _UINT32_(23) +#define MUX_PA23I_CAN0_RX _UINT32_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UINT32_(1) << 23) + +#define PIN_PA25I_CAN0_RX _UINT32_(25) +#define MUX_PA25I_CAN0_RX _UINT32_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UINT32_(1) << 25) + +#define PIN_PA22I_CAN0_TX _UINT32_(22) +#define MUX_PA22I_CAN0_TX _UINT32_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UINT32_(1) << 22) + +#define PIN_PA24I_CAN0_TX _UINT32_(24) +#define MUX_PA24I_CAN0_TX _UINT32_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UINT32_(1) << 24) + +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _UINT32_(45) +#define MUX_PB13H_CAN1_RX _UINT32_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UINT32_(1) << 13) + +#define PIN_PB15H_CAN1_RX _UINT32_(47) +#define MUX_PB15H_CAN1_RX _UINT32_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UINT32_(1) << 15) + +#define PIN_PB12H_CAN1_TX _UINT32_(44) +#define MUX_PB12H_CAN1_TX _UINT32_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UINT32_(1) << 12) + +#define PIN_PB14H_CAN1_TX _UINT32_(46) +#define MUX_PB14H_CAN1_TX _UINT32_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UINT32_(1) << 14) + +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _UINT32_(4) +#define MUX_PA04N_CCL_IN0 _UINT32_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UINT32_(1) << 4) + +#define PIN_PA16N_CCL_IN0 _UINT32_(16) +#define MUX_PA16N_CCL_IN0 _UINT32_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UINT32_(1) << 16) + +#define PIN_PB22N_CCL_IN0 _UINT32_(54) +#define MUX_PB22N_CCL_IN0 _UINT32_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UINT32_(1) << 22) + +#define PIN_PA05N_CCL_IN1 _UINT32_(5) +#define MUX_PA05N_CCL_IN1 _UINT32_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UINT32_(1) << 5) + +#define PIN_PA17N_CCL_IN1 _UINT32_(17) +#define MUX_PA17N_CCL_IN1 _UINT32_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UINT32_(1) << 17) + +#define PIN_PB00N_CCL_IN1 _UINT32_(32) +#define MUX_PB00N_CCL_IN1 _UINT32_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UINT32_(1) << 0) + +#define PIN_PA06N_CCL_IN2 _UINT32_(6) +#define MUX_PA06N_CCL_IN2 _UINT32_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UINT32_(1) << 6) + +#define PIN_PA18N_CCL_IN2 _UINT32_(18) +#define MUX_PA18N_CCL_IN2 _UINT32_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UINT32_(1) << 18) + +#define PIN_PB01N_CCL_IN2 _UINT32_(33) +#define MUX_PB01N_CCL_IN2 _UINT32_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UINT32_(1) << 1) + +#define PIN_PA08N_CCL_IN3 _UINT32_(8) +#define MUX_PA08N_CCL_IN3 _UINT32_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UINT32_(1) << 8) + +#define PIN_PA30N_CCL_IN3 _UINT32_(30) +#define MUX_PA30N_CCL_IN3 _UINT32_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UINT32_(1) << 30) + +#define PIN_PA09N_CCL_IN4 _UINT32_(9) +#define MUX_PA09N_CCL_IN4 _UINT32_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UINT32_(1) << 9) + +#define PIN_PC27N_CCL_IN4 _UINT32_(91) +#define MUX_PC27N_CCL_IN4 _UINT32_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UINT32_(1) << 27) + +#define PIN_PA10N_CCL_IN5 _UINT32_(10) +#define MUX_PA10N_CCL_IN5 _UINT32_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UINT32_(1) << 10) + +#define PIN_PC28N_CCL_IN5 _UINT32_(92) +#define MUX_PC28N_CCL_IN5 _UINT32_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UINT32_(1) << 28) + +#define PIN_PA22N_CCL_IN6 _UINT32_(22) +#define MUX_PA22N_CCL_IN6 _UINT32_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UINT32_(1) << 22) + +#define PIN_PB06N_CCL_IN6 _UINT32_(38) +#define MUX_PB06N_CCL_IN6 _UINT32_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UINT32_(1) << 6) + +#define PIN_PA23N_CCL_IN7 _UINT32_(23) +#define MUX_PA23N_CCL_IN7 _UINT32_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UINT32_(1) << 23) + +#define PIN_PB07N_CCL_IN7 _UINT32_(39) +#define MUX_PB07N_CCL_IN7 _UINT32_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UINT32_(1) << 7) + +#define PIN_PA24N_CCL_IN8 _UINT32_(24) +#define MUX_PA24N_CCL_IN8 _UINT32_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UINT32_(1) << 24) + +#define PIN_PB08N_CCL_IN8 _UINT32_(40) +#define MUX_PB08N_CCL_IN8 _UINT32_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UINT32_(1) << 8) + +#define PIN_PB14N_CCL_IN9 _UINT32_(46) +#define MUX_PB14N_CCL_IN9 _UINT32_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UINT32_(1) << 14) + +#define PIN_PC20N_CCL_IN9 _UINT32_(84) +#define MUX_PC20N_CCL_IN9 _UINT32_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UINT32_(1) << 20) + +#define PIN_PB15N_CCL_IN10 _UINT32_(47) +#define MUX_PB15N_CCL_IN10 _UINT32_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UINT32_(1) << 15) + +#define PIN_PC21N_CCL_IN10 _UINT32_(85) +#define MUX_PC21N_CCL_IN10 _UINT32_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UINT32_(1) << 21) + +#define PIN_PB10N_CCL_IN11 _UINT32_(42) +#define MUX_PB10N_CCL_IN11 _UINT32_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UINT32_(1) << 10) + +#define PIN_PB16N_CCL_IN11 _UINT32_(48) +#define MUX_PB16N_CCL_IN11 _UINT32_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UINT32_(1) << 16) + +#define PIN_PA07N_CCL_OUT0 _UINT32_(7) +#define MUX_PA07N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UINT32_(1) << 7) + +#define PIN_PA19N_CCL_OUT0 _UINT32_(19) +#define MUX_PA19N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UINT32_(1) << 19) + +#define PIN_PB02N_CCL_OUT0 _UINT32_(34) +#define MUX_PB02N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UINT32_(1) << 2) + +#define PIN_PB23N_CCL_OUT0 _UINT32_(55) +#define MUX_PB23N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UINT32_(1) << 23) + +#define PIN_PA11N_CCL_OUT1 _UINT32_(11) +#define MUX_PA11N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UINT32_(1) << 11) + +#define PIN_PA31N_CCL_OUT1 _UINT32_(31) +#define MUX_PA31N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UINT32_(1) << 31) + +#define PIN_PB11N_CCL_OUT1 _UINT32_(43) +#define MUX_PB11N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UINT32_(1) << 11) + +#define PIN_PA25N_CCL_OUT2 _UINT32_(25) +#define MUX_PA25N_CCL_OUT2 _UINT32_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UINT32_(1) << 25) + +#define PIN_PB09N_CCL_OUT2 _UINT32_(41) +#define MUX_PB09N_CCL_OUT2 _UINT32_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UINT32_(1) << 9) + +#define PIN_PB17N_CCL_OUT3 _UINT32_(49) +#define MUX_PB17N_CCL_OUT3 _UINT32_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UINT32_(1) << 17) + +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _UINT32_(2) +#define MUX_PA02B_DAC_VOUT0 _UINT32_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UINT32_(1) << 2) + +#define PIN_PA05B_DAC_VOUT1 _UINT32_(5) +#define MUX_PA05B_DAC_VOUT1 _UINT32_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UINT32_(1) << 5) + +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _UINT32_(0) +#define MUX_PA00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA00 External Interrupt Line */ + +#define PIN_PA16A_EIC_EXTINT0 _UINT32_(16) +#define MUX_PA16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA16 External Interrupt Line */ + +#define PIN_PB00A_EIC_EXTINT0 _UINT32_(32) +#define MUX_PB00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB00 External Interrupt Line */ + +#define PIN_PB16A_EIC_EXTINT0 _UINT32_(48) +#define MUX_PB16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB16 External Interrupt Line */ + +#define PIN_PC00A_EIC_EXTINT0 _UINT32_(64) +#define MUX_PC00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PC00 External Interrupt Line */ + +#define PIN_PC16A_EIC_EXTINT0 _UINT32_(80) +#define MUX_PC16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PC16 External Interrupt Line */ + +#define PIN_PD00A_EIC_EXTINT0 _UINT32_(96) +#define MUX_PD00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PD00 External Interrupt Line */ + +#define PIN_PA01A_EIC_EXTINT1 _UINT32_(1) +#define MUX_PA01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA01 External Interrupt Line */ + +#define PIN_PA17A_EIC_EXTINT1 _UINT32_(17) +#define MUX_PA17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA17 External Interrupt Line */ + +#define PIN_PB01A_EIC_EXTINT1 _UINT32_(33) +#define MUX_PB01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB01 External Interrupt Line */ + +#define PIN_PB17A_EIC_EXTINT1 _UINT32_(49) +#define MUX_PB17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB17 External Interrupt Line */ + +#define PIN_PC01A_EIC_EXTINT1 _UINT32_(65) +#define MUX_PC01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PC01 External Interrupt Line */ + +#define PIN_PC17A_EIC_EXTINT1 _UINT32_(81) +#define MUX_PC17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PC17 External Interrupt Line */ + +#define PIN_PD01A_EIC_EXTINT1 _UINT32_(97) +#define MUX_PD01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PD01 External Interrupt Line */ + +#define PIN_PA02A_EIC_EXTINT2 _UINT32_(2) +#define MUX_PA02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA02 External Interrupt Line */ + +#define PIN_PA18A_EIC_EXTINT2 _UINT32_(18) +#define MUX_PA18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA18 External Interrupt Line */ + +#define PIN_PB02A_EIC_EXTINT2 _UINT32_(34) +#define MUX_PB02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB02 External Interrupt Line */ + +#define PIN_PB18A_EIC_EXTINT2 _UINT32_(50) +#define MUX_PB18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB18 External Interrupt Line */ + +#define PIN_PC02A_EIC_EXTINT2 _UINT32_(66) +#define MUX_PC02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PC02 External Interrupt Line */ + +#define PIN_PC18A_EIC_EXTINT2 _UINT32_(82) +#define MUX_PC18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PC18 External Interrupt Line */ + +#define PIN_PA03A_EIC_EXTINT3 _UINT32_(3) +#define MUX_PA03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA03 External Interrupt Line */ + +#define PIN_PA19A_EIC_EXTINT3 _UINT32_(19) +#define MUX_PA19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA19 External Interrupt Line */ + +#define PIN_PB03A_EIC_EXTINT3 _UINT32_(35) +#define MUX_PB03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB03 External Interrupt Line */ + +#define PIN_PB19A_EIC_EXTINT3 _UINT32_(51) +#define MUX_PB19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB19 External Interrupt Line */ + +#define PIN_PC03A_EIC_EXTINT3 _UINT32_(67) +#define MUX_PC03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PC03 External Interrupt Line */ + +#define PIN_PC19A_EIC_EXTINT3 _UINT32_(83) +#define MUX_PC19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PC19 External Interrupt Line */ + +#define PIN_PD08A_EIC_EXTINT3 _UINT32_(104) +#define MUX_PD08A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UINT32_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PD08 External Interrupt Line */ + +#define PIN_PA04A_EIC_EXTINT4 _UINT32_(4) +#define MUX_PA04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA04 External Interrupt Line */ + +#define PIN_PA20A_EIC_EXTINT4 _UINT32_(20) +#define MUX_PA20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA20 External Interrupt Line */ + +#define PIN_PB04A_EIC_EXTINT4 _UINT32_(36) +#define MUX_PB04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB04 External Interrupt Line */ + +#define PIN_PB20A_EIC_EXTINT4 _UINT32_(52) +#define MUX_PB20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB20 External Interrupt Line */ + +#define PIN_PC04A_EIC_EXTINT4 _UINT32_(68) +#define MUX_PC04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PC04 External Interrupt Line */ + +#define PIN_PC20A_EIC_EXTINT4 _UINT32_(84) +#define MUX_PC20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PC20 External Interrupt Line */ + +#define PIN_PD09A_EIC_EXTINT4 _UINT32_(105) +#define MUX_PD09A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UINT32_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PD09 External Interrupt Line */ + +#define PIN_PA05A_EIC_EXTINT5 _UINT32_(5) +#define MUX_PA05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA05 External Interrupt Line */ + +#define PIN_PA21A_EIC_EXTINT5 _UINT32_(21) +#define MUX_PA21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA21 External Interrupt Line */ + +#define PIN_PB05A_EIC_EXTINT5 _UINT32_(37) +#define MUX_PB05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB05 External Interrupt Line */ + +#define PIN_PB21A_EIC_EXTINT5 _UINT32_(53) +#define MUX_PB21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB21 External Interrupt Line */ + +#define PIN_PC05A_EIC_EXTINT5 _UINT32_(69) +#define MUX_PC05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PC05 External Interrupt Line */ + +#define PIN_PC21A_EIC_EXTINT5 _UINT32_(85) +#define MUX_PC21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PC21 External Interrupt Line */ + +#define PIN_PD10A_EIC_EXTINT5 _UINT32_(106) +#define MUX_PD10A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UINT32_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PD10 External Interrupt Line */ + +#define PIN_PA06A_EIC_EXTINT6 _UINT32_(6) +#define MUX_PA06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA06 External Interrupt Line */ + +#define PIN_PA22A_EIC_EXTINT6 _UINT32_(22) +#define MUX_PA22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA22 External Interrupt Line */ + +#define PIN_PB06A_EIC_EXTINT6 _UINT32_(38) +#define MUX_PB06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB06 External Interrupt Line */ + +#define PIN_PB22A_EIC_EXTINT6 _UINT32_(54) +#define MUX_PB22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB22 External Interrupt Line */ + +#define PIN_PC06A_EIC_EXTINT6 _UINT32_(70) +#define MUX_PC06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PC06 External Interrupt Line */ + +#define PIN_PC22A_EIC_EXTINT6 _UINT32_(86) +#define MUX_PC22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PC22 External Interrupt Line */ + +#define PIN_PD11A_EIC_EXTINT6 _UINT32_(107) +#define MUX_PD11A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UINT32_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PD11 External Interrupt Line */ + +#define PIN_PA07A_EIC_EXTINT7 _UINT32_(7) +#define MUX_PA07A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UINT32_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA07 External Interrupt Line */ + +#define PIN_PA23A_EIC_EXTINT7 _UINT32_(23) +#define MUX_PA23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA23 External Interrupt Line */ + +#define PIN_PB07A_EIC_EXTINT7 _UINT32_(39) +#define MUX_PB07A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UINT32_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB07 External Interrupt Line */ + +#define PIN_PB23A_EIC_EXTINT7 _UINT32_(55) +#define MUX_PB23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB23 External Interrupt Line */ + +#define PIN_PC23A_EIC_EXTINT7 _UINT32_(87) +#define MUX_PC23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PC23 External Interrupt Line */ + +#define PIN_PD12A_EIC_EXTINT7 _UINT32_(108) +#define MUX_PD12A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UINT32_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PD12 External Interrupt Line */ + +#define PIN_PA24A_EIC_EXTINT8 _UINT32_(24) +#define MUX_PA24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PA24 External Interrupt Line */ + +#define PIN_PB08A_EIC_EXTINT8 _UINT32_(40) +#define MUX_PB08A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UINT32_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PB08 External Interrupt Line */ + +#define PIN_PB24A_EIC_EXTINT8 _UINT32_(56) +#define MUX_PB24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PB24 External Interrupt Line */ + +#define PIN_PC24A_EIC_EXTINT8 _UINT32_(88) +#define MUX_PC24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PC24 External Interrupt Line */ + +#define PIN_PA09A_EIC_EXTINT9 _UINT32_(9) +#define MUX_PA09A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UINT32_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA09 External Interrupt Line */ + +#define PIN_PA25A_EIC_EXTINT9 _UINT32_(25) +#define MUX_PA25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA25 External Interrupt Line */ + +#define PIN_PB09A_EIC_EXTINT9 _UINT32_(41) +#define MUX_PB09A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UINT32_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PB09 External Interrupt Line */ + +#define PIN_PB25A_EIC_EXTINT9 _UINT32_(57) +#define MUX_PB25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PB25 External Interrupt Line */ + +#define PIN_PC07A_EIC_EXTINT9 _UINT32_(71) +#define MUX_PC07A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UINT32_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PC07 External Interrupt Line */ + +#define PIN_PC25A_EIC_EXTINT9 _UINT32_(89) +#define MUX_PC25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PC25 External Interrupt Line */ + +#define PIN_PA10A_EIC_EXTINT10 _UINT32_(10) +#define MUX_PA10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PA10 External Interrupt Line */ + +#define PIN_PB10A_EIC_EXTINT10 _UINT32_(42) +#define MUX_PB10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PB10 External Interrupt Line */ + +#define PIN_PC10A_EIC_EXTINT10 _UINT32_(74) +#define MUX_PC10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PC10 External Interrupt Line */ + +#define PIN_PC26A_EIC_EXTINT10 _UINT32_(90) +#define MUX_PC26A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UINT32_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PC26 External Interrupt Line */ + +#define PIN_PD20A_EIC_EXTINT10 _UINT32_(116) +#define MUX_PD20A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UINT32_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PD20 External Interrupt Line */ + +#define PIN_PA11A_EIC_EXTINT11 _UINT32_(11) +#define MUX_PA11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA11 External Interrupt Line */ + +#define PIN_PA27A_EIC_EXTINT11 _UINT32_(27) +#define MUX_PA27A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UINT32_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA27 External Interrupt Line */ + +#define PIN_PB11A_EIC_EXTINT11 _UINT32_(43) +#define MUX_PB11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PB11 External Interrupt Line */ + +#define PIN_PC11A_EIC_EXTINT11 _UINT32_(75) +#define MUX_PC11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PC11 External Interrupt Line */ + +#define PIN_PC27A_EIC_EXTINT11 _UINT32_(91) +#define MUX_PC27A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UINT32_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PC27 External Interrupt Line */ + +#define PIN_PD21A_EIC_EXTINT11 _UINT32_(117) +#define MUX_PD21A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UINT32_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PD21 External Interrupt Line */ + +#define PIN_PA12A_EIC_EXTINT12 _UINT32_(12) +#define MUX_PA12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PA12 External Interrupt Line */ + +#define PIN_PB12A_EIC_EXTINT12 _UINT32_(44) +#define MUX_PB12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PB12 External Interrupt Line */ + +#define PIN_PB26A_EIC_EXTINT12 _UINT32_(58) +#define MUX_PB26A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UINT32_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PB26 External Interrupt Line */ + +#define PIN_PC12A_EIC_EXTINT12 _UINT32_(76) +#define MUX_PC12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PC12 External Interrupt Line */ + +#define PIN_PC28A_EIC_EXTINT12 _UINT32_(92) +#define MUX_PC28A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UINT32_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PC28 External Interrupt Line */ + +#define PIN_PA13A_EIC_EXTINT13 _UINT32_(13) +#define MUX_PA13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PA13 External Interrupt Line */ + +#define PIN_PB13A_EIC_EXTINT13 _UINT32_(45) +#define MUX_PB13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PB13 External Interrupt Line */ + +#define PIN_PB27A_EIC_EXTINT13 _UINT32_(59) +#define MUX_PB27A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UINT32_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PB27 External Interrupt Line */ + +#define PIN_PC13A_EIC_EXTINT13 _UINT32_(77) +#define MUX_PC13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PC13 External Interrupt Line */ + +#define PIN_PA30A_EIC_EXTINT14 _UINT32_(30) +#define MUX_PA30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA30 External Interrupt Line */ + +#define PIN_PB14A_EIC_EXTINT14 _UINT32_(46) +#define MUX_PB14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB14 External Interrupt Line */ + +#define PIN_PB28A_EIC_EXTINT14 _UINT32_(60) +#define MUX_PB28A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UINT32_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB28 External Interrupt Line */ + +#define PIN_PB30A_EIC_EXTINT14 _UINT32_(62) +#define MUX_PB30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB30 External Interrupt Line */ + +#define PIN_PC14A_EIC_EXTINT14 _UINT32_(78) +#define MUX_PC14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PC14 External Interrupt Line */ + +#define PIN_PC30A_EIC_EXTINT14 _UINT32_(94) +#define MUX_PC30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PC30 External Interrupt Line */ + +#define PIN_PA14A_EIC_EXTINT14 _UINT32_(14) +#define MUX_PA14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA14 External Interrupt Line */ + +#define PIN_PA15A_EIC_EXTINT15 _UINT32_(15) +#define MUX_PA15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA15 External Interrupt Line */ + +#define PIN_PA31A_EIC_EXTINT15 _UINT32_(31) +#define MUX_PA31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA31 External Interrupt Line */ + +#define PIN_PB15A_EIC_EXTINT15 _UINT32_(47) +#define MUX_PB15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB15 External Interrupt Line */ + +#define PIN_PB29A_EIC_EXTINT15 _UINT32_(61) +#define MUX_PB29A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UINT32_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB29 External Interrupt Line */ + +#define PIN_PB31A_EIC_EXTINT15 _UINT32_(63) +#define MUX_PB31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB31 External Interrupt Line */ + +#define PIN_PC15A_EIC_EXTINT15 _UINT32_(79) +#define MUX_PC15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PC15 External Interrupt Line */ + +#define PIN_PC31A_EIC_EXTINT15 _UINT32_(95) +#define MUX_PC31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PC31 External Interrupt Line */ + +#define PIN_PA08A_EIC_NMI _UINT32_(8) +#define MUX_PA08A_EIC_NMI _UINT32_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UINT32_(1) << 8) + +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _UINT32_(30) +#define MUX_PA30M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UINT32_(1) << 30) + +#define PIN_PB14M_GCLK_IO0 _UINT32_(46) +#define MUX_PB14M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UINT32_(1) << 14) + +#define PIN_PA14M_GCLK_IO0 _UINT32_(14) +#define MUX_PA14M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UINT32_(1) << 14) + +#define PIN_PB22M_GCLK_IO0 _UINT32_(54) +#define MUX_PB22M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UINT32_(1) << 22) + +#define PIN_PB15M_GCLK_IO1 _UINT32_(47) +#define MUX_PB15M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UINT32_(1) << 15) + +#define PIN_PA15M_GCLK_IO1 _UINT32_(15) +#define MUX_PA15M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UINT32_(1) << 15) + +#define PIN_PB23M_GCLK_IO1 _UINT32_(55) +#define MUX_PB23M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UINT32_(1) << 23) + +#define PIN_PA27M_GCLK_IO1 _UINT32_(27) +#define MUX_PA27M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UINT32_(1) << 27) + +#define PIN_PA16M_GCLK_IO2 _UINT32_(16) +#define MUX_PA16M_GCLK_IO2 _UINT32_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UINT32_(1) << 16) + +#define PIN_PB16M_GCLK_IO2 _UINT32_(48) +#define MUX_PB16M_GCLK_IO2 _UINT32_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UINT32_(1) << 16) + +#define PIN_PA17M_GCLK_IO3 _UINT32_(17) +#define MUX_PA17M_GCLK_IO3 _UINT32_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UINT32_(1) << 17) + +#define PIN_PB17M_GCLK_IO3 _UINT32_(49) +#define MUX_PB17M_GCLK_IO3 _UINT32_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UINT32_(1) << 17) + +#define PIN_PA10M_GCLK_IO4 _UINT32_(10) +#define MUX_PA10M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UINT32_(1) << 10) + +#define PIN_PB10M_GCLK_IO4 _UINT32_(42) +#define MUX_PB10M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UINT32_(1) << 10) + +#define PIN_PB18M_GCLK_IO4 _UINT32_(50) +#define MUX_PB18M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UINT32_(1) << 18) + +#define PIN_PA11M_GCLK_IO5 _UINT32_(11) +#define MUX_PA11M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UINT32_(1) << 11) + +#define PIN_PB11M_GCLK_IO5 _UINT32_(43) +#define MUX_PB11M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UINT32_(1) << 11) + +#define PIN_PB19M_GCLK_IO5 _UINT32_(51) +#define MUX_PB19M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UINT32_(1) << 19) + +#define PIN_PB12M_GCLK_IO6 _UINT32_(44) +#define MUX_PB12M_GCLK_IO6 _UINT32_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UINT32_(1) << 12) + +#define PIN_PB20M_GCLK_IO6 _UINT32_(52) +#define MUX_PB20M_GCLK_IO6 _UINT32_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UINT32_(1) << 20) + +#define PIN_PB13M_GCLK_IO7 _UINT32_(45) +#define MUX_PB13M_GCLK_IO7 _UINT32_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UINT32_(1) << 13) + +#define PIN_PB21M_GCLK_IO7 _UINT32_(53) +#define MUX_PB21M_GCLK_IO7 _UINT32_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UINT32_(1) << 21) + +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _UINT32_(85) +#define MUX_PC21L_GMAC_GCOL _UINT32_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UINT32_(1) << 21) + +#define PIN_PA16L_GMAC_GCRS _UINT32_(16) +#define MUX_PA16L_GMAC_GCRS _UINT32_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UINT32_(1) << 16) + +#define PIN_PA20L_GMAC_GMDC _UINT32_(20) +#define MUX_PA20L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UINT32_(1) << 20) + +#define PIN_PB14L_GMAC_GMDC _UINT32_(46) +#define MUX_PB14L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UINT32_(1) << 14) + +#define PIN_PC11L_GMAC_GMDC _UINT32_(75) +#define MUX_PC11L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UINT32_(1) << 11) + +#define PIN_PC22L_GMAC_GMDC _UINT32_(86) +#define MUX_PC22L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) +#define PORT_PC22L_GMAC_GMDC (_UINT32_(1) << 22) + +#define PIN_PA21L_GMAC_GMDIO _UINT32_(21) +#define MUX_PA21L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UINT32_(1) << 21) + +#define PIN_PB15L_GMAC_GMDIO _UINT32_(47) +#define MUX_PB15L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UINT32_(1) << 15) + +#define PIN_PC12L_GMAC_GMDIO _UINT32_(76) +#define MUX_PC12L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UINT32_(1) << 12) + +#define PIN_PC23L_GMAC_GMDIO _UINT32_(87) +#define MUX_PC23L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) +#define PORT_PC23L_GMAC_GMDIO (_UINT32_(1) << 23) + +#define PIN_PA13L_GMAC_GRX0 _UINT32_(13) +#define MUX_PA13L_GMAC_GRX0 _UINT32_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UINT32_(1) << 13) + +#define PIN_PA12L_GMAC_GRX1 _UINT32_(12) +#define MUX_PA12L_GMAC_GRX1 _UINT32_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UINT32_(1) << 12) + +#define PIN_PC15L_GMAC_GRX2 _UINT32_(79) +#define MUX_PC15L_GMAC_GRX2 _UINT32_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UINT32_(1) << 15) + +#define PIN_PC14L_GMAC_GRX3 _UINT32_(78) +#define MUX_PC14L_GMAC_GRX3 _UINT32_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UINT32_(1) << 14) + +#define PIN_PC18L_GMAC_GRXCK _UINT32_(82) +#define MUX_PC18L_GMAC_GRXCK _UINT32_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UINT32_(1) << 18) + +#define PIN_PC20L_GMAC_GRXDV _UINT32_(84) +#define MUX_PC20L_GMAC_GRXDV _UINT32_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UINT32_(1) << 20) + +#define PIN_PA15L_GMAC_GRXER _UINT32_(15) +#define MUX_PA15L_GMAC_GRXER _UINT32_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UINT32_(1) << 15) + +#define PIN_PA18L_GMAC_GTX0 _UINT32_(18) +#define MUX_PA18L_GMAC_GTX0 _UINT32_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UINT32_(1) << 18) + +#define PIN_PA19L_GMAC_GTX1 _UINT32_(19) +#define MUX_PA19L_GMAC_GTX1 _UINT32_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UINT32_(1) << 19) + +#define PIN_PC16L_GMAC_GTX2 _UINT32_(80) +#define MUX_PC16L_GMAC_GTX2 _UINT32_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UINT32_(1) << 16) + +#define PIN_PC17L_GMAC_GTX3 _UINT32_(81) +#define MUX_PC17L_GMAC_GTX3 _UINT32_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UINT32_(1) << 17) + +#define PIN_PA14L_GMAC_GTXCK _UINT32_(14) +#define MUX_PA14L_GMAC_GTXCK _UINT32_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UINT32_(1) << 14) + +#define PIN_PA17L_GMAC_GTXEN _UINT32_(17) +#define MUX_PA17L_GMAC_GTXEN _UINT32_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UINT32_(1) << 17) + +#define PIN_PC19L_GMAC_GTXER _UINT32_(83) +#define MUX_PC19L_GMAC_GTXER _UINT32_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UINT32_(1) << 19) + +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _UINT32_(9) +#define MUX_PA09J_I2S_FS0 _UINT32_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UINT32_(1) << 9) + +#define PIN_PA20J_I2S_FS0 _UINT32_(20) +#define MUX_PA20J_I2S_FS0 _UINT32_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UINT32_(1) << 20) + +#define PIN_PA23J_I2S_FS1 _UINT32_(23) +#define MUX_PA23J_I2S_FS1 _UINT32_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UINT32_(1) << 23) + +#define PIN_PB11J_I2S_FS1 _UINT32_(43) +#define MUX_PB11J_I2S_FS1 _UINT32_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UINT32_(1) << 11) + +#define PIN_PA08J_I2S_MCK0 _UINT32_(8) +#define MUX_PA08J_I2S_MCK0 _UINT32_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UINT32_(1) << 8) + +#define PIN_PB17J_I2S_MCK0 _UINT32_(49) +#define MUX_PB17J_I2S_MCK0 _UINT32_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UINT32_(1) << 17) + +#define PIN_PB29J_I2S_MCK1 _UINT32_(61) +#define MUX_PB29J_I2S_MCK1 _UINT32_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UINT32_(1) << 29) + +#define PIN_PB13J_I2S_MCK1 _UINT32_(45) +#define MUX_PB13J_I2S_MCK1 _UINT32_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UINT32_(1) << 13) + +#define PIN_PA10J_I2S_SCK0 _UINT32_(10) +#define MUX_PA10J_I2S_SCK0 _UINT32_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UINT32_(1) << 10) + +#define PIN_PB16J_I2S_SCK0 _UINT32_(48) +#define MUX_PB16J_I2S_SCK0 _UINT32_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UINT32_(1) << 16) + +#define PIN_PB28J_I2S_SCK1 _UINT32_(60) +#define MUX_PB28J_I2S_SCK1 _UINT32_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UINT32_(1) << 28) + +#define PIN_PB12J_I2S_SCK1 _UINT32_(44) +#define MUX_PB12J_I2S_SCK1 _UINT32_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UINT32_(1) << 12) + +#define PIN_PA22J_I2S_SDI _UINT32_(22) +#define MUX_PA22J_I2S_SDI _UINT32_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UINT32_(1) << 22) + +#define PIN_PB10J_I2S_SDI _UINT32_(42) +#define MUX_PB10J_I2S_SDI _UINT32_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UINT32_(1) << 10) + +#define PIN_PA11J_I2S_SDO _UINT32_(11) +#define MUX_PA11J_I2S_SDO _UINT32_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UINT32_(1) << 11) + +#define PIN_PA21J_I2S_SDO _UINT32_(21) +#define MUX_PA21J_I2S_SDO _UINT32_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UINT32_(1) << 21) + +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _UINT32_(14) +#define MUX_PA14K_PCC_CLK _UINT32_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UINT32_(1) << 14) + +#define PIN_PA16K_PCC_DATA0 _UINT32_(16) +#define MUX_PA16K_PCC_DATA0 _UINT32_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UINT32_(1) << 16) + +#define PIN_PA17K_PCC_DATA1 _UINT32_(17) +#define MUX_PA17K_PCC_DATA1 _UINT32_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UINT32_(1) << 17) + +#define PIN_PA18K_PCC_DATA2 _UINT32_(18) +#define MUX_PA18K_PCC_DATA2 _UINT32_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UINT32_(1) << 18) + +#define PIN_PA19K_PCC_DATA3 _UINT32_(19) +#define MUX_PA19K_PCC_DATA3 _UINT32_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UINT32_(1) << 19) + +#define PIN_PA20K_PCC_DATA4 _UINT32_(20) +#define MUX_PA20K_PCC_DATA4 _UINT32_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UINT32_(1) << 20) + +#define PIN_PA21K_PCC_DATA5 _UINT32_(21) +#define MUX_PA21K_PCC_DATA5 _UINT32_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UINT32_(1) << 21) + +#define PIN_PA22K_PCC_DATA6 _UINT32_(22) +#define MUX_PA22K_PCC_DATA6 _UINT32_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UINT32_(1) << 22) + +#define PIN_PA23K_PCC_DATA7 _UINT32_(23) +#define MUX_PA23K_PCC_DATA7 _UINT32_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UINT32_(1) << 23) + +#define PIN_PB14K_PCC_DATA8 _UINT32_(46) +#define MUX_PB14K_PCC_DATA8 _UINT32_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UINT32_(1) << 14) + +#define PIN_PB15K_PCC_DATA9 _UINT32_(47) +#define MUX_PB15K_PCC_DATA9 _UINT32_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UINT32_(1) << 15) + +#define PIN_PC12K_PCC_DATA10 _UINT32_(76) +#define MUX_PC12K_PCC_DATA10 _UINT32_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UINT32_(1) << 12) + +#define PIN_PC13K_PCC_DATA11 _UINT32_(77) +#define MUX_PC13K_PCC_DATA11 _UINT32_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UINT32_(1) << 13) + +#define PIN_PC14K_PCC_DATA12 _UINT32_(78) +#define MUX_PC14K_PCC_DATA12 _UINT32_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UINT32_(1) << 14) + +#define PIN_PC15K_PCC_DATA13 _UINT32_(79) +#define MUX_PC15K_PCC_DATA13 _UINT32_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UINT32_(1) << 15) + +#define PIN_PA12K_PCC_DEN1 _UINT32_(12) +#define MUX_PA12K_PCC_DEN1 _UINT32_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UINT32_(1) << 12) + +#define PIN_PA13K_PCC_DEN2 _UINT32_(13) +#define MUX_PA13K_PCC_DEN2 _UINT32_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UINT32_(1) << 13) + +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _UINT32_(50) +#define MUX_PB18G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UINT32_(1) << 18) + +#define PIN_PB23G_PDEC_QDI0 _UINT32_(55) +#define MUX_PB23G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UINT32_(1) << 23) + +#define PIN_PC16G_PDEC_QDI0 _UINT32_(80) +#define MUX_PC16G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UINT32_(1) << 16) + +#define PIN_PA24G_PDEC_QDI0 _UINT32_(24) +#define MUX_PA24G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UINT32_(1) << 24) + +#define PIN_PB19G_PDEC_QDI1 _UINT32_(51) +#define MUX_PB19G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UINT32_(1) << 19) + +#define PIN_PB24G_PDEC_QDI1 _UINT32_(56) +#define MUX_PB24G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UINT32_(1) << 24) + +#define PIN_PC17G_PDEC_QDI1 _UINT32_(81) +#define MUX_PC17G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UINT32_(1) << 17) + +#define PIN_PA25G_PDEC_QDI1 _UINT32_(25) +#define MUX_PA25G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UINT32_(1) << 25) + +#define PIN_PB20G_PDEC_QDI2 _UINT32_(52) +#define MUX_PB20G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UINT32_(1) << 20) + +#define PIN_PB25G_PDEC_QDI2 _UINT32_(57) +#define MUX_PB25G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UINT32_(1) << 25) + +#define PIN_PC18G_PDEC_QDI2 _UINT32_(82) +#define MUX_PC18G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UINT32_(1) << 18) + +#define PIN_PB22G_PDEC_QDI2 _UINT32_(54) +#define MUX_PB22G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UINT32_(1) << 22) + +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _UINT32_(43) +#define MUX_PB11H_QSPI_CS _UINT32_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UINT32_(1) << 11) + +#define PIN_PA08H_QSPI_DATA0 _UINT32_(8) +#define MUX_PA08H_QSPI_DATA0 _UINT32_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UINT32_(1) << 8) + +#define PIN_PA09H_QSPI_DATA1 _UINT32_(9) +#define MUX_PA09H_QSPI_DATA1 _UINT32_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UINT32_(1) << 9) + +#define PIN_PA10H_QSPI_DATA2 _UINT32_(10) +#define MUX_PA10H_QSPI_DATA2 _UINT32_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UINT32_(1) << 10) + +#define PIN_PA11H_QSPI_DATA3 _UINT32_(11) +#define MUX_PA11H_QSPI_DATA3 _UINT32_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UINT32_(1) << 11) + +#define PIN_PB10H_QSPI_SCK _UINT32_(42) +#define MUX_PB10H_QSPI_SCK _UINT32_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UINT32_(1) << 10) + +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _UINT32_(6) +#define MUX_PA06I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UINT32_(1) << 6) + +#define PIN_PA12I_SDHC0_SDCD _UINT32_(12) +#define MUX_PA12I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UINT32_(1) << 12) + +#define PIN_PB12I_SDHC0_SDCD _UINT32_(44) +#define MUX_PB12I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UINT32_(1) << 12) + +#define PIN_PC06I_SDHC0_SDCD _UINT32_(70) +#define MUX_PC06I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UINT32_(1) << 6) + +#define PIN_PB11I_SDHC0_SDCK _UINT32_(43) +#define MUX_PB11I_SDHC0_SDCK _UINT32_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UINT32_(1) << 11) + +#define PIN_PA08I_SDHC0_SDCMD _UINT32_(8) +#define MUX_PA08I_SDHC0_SDCMD _UINT32_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UINT32_(1) << 8) + +#define PIN_PA09I_SDHC0_SDDAT0 _UINT32_(9) +#define MUX_PA09I_SDHC0_SDDAT0 _UINT32_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UINT32_(1) << 9) + +#define PIN_PA10I_SDHC0_SDDAT1 _UINT32_(10) +#define MUX_PA10I_SDHC0_SDDAT1 _UINT32_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UINT32_(1) << 10) + +#define PIN_PA11I_SDHC0_SDDAT2 _UINT32_(11) +#define MUX_PA11I_SDHC0_SDDAT2 _UINT32_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UINT32_(1) << 11) + +#define PIN_PB10I_SDHC0_SDDAT3 _UINT32_(42) +#define MUX_PB10I_SDHC0_SDDAT3 _UINT32_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UINT32_(1) << 10) + +#define PIN_PA07I_SDHC0_SDWP _UINT32_(7) +#define MUX_PA07I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UINT32_(1) << 7) + +#define PIN_PA13I_SDHC0_SDWP _UINT32_(13) +#define MUX_PA13I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UINT32_(1) << 13) + +#define PIN_PB13I_SDHC0_SDWP _UINT32_(45) +#define MUX_PB13I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UINT32_(1) << 13) + +#define PIN_PC07I_SDHC0_SDWP _UINT32_(71) +#define MUX_PC07I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UINT32_(1) << 7) + +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _UINT32_(48) +#define MUX_PB16I_SDHC1_SDCD _UINT32_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UINT32_(1) << 16) + +#define PIN_PC20I_SDHC1_SDCD _UINT32_(84) +#define MUX_PC20I_SDHC1_SDCD _UINT32_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UINT32_(1) << 20) + +#define PIN_PD20I_SDHC1_SDCD _UINT32_(116) +#define MUX_PD20I_SDHC1_SDCD _UINT32_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UINT32_(1) << 20) + +#define PIN_PA21I_SDHC1_SDCK _UINT32_(21) +#define MUX_PA21I_SDHC1_SDCK _UINT32_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UINT32_(1) << 21) + +#define PIN_PA20I_SDHC1_SDCMD _UINT32_(20) +#define MUX_PA20I_SDHC1_SDCMD _UINT32_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UINT32_(1) << 20) + +#define PIN_PB18I_SDHC1_SDDAT0 _UINT32_(50) +#define MUX_PB18I_SDHC1_SDDAT0 _UINT32_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UINT32_(1) << 18) + +#define PIN_PB19I_SDHC1_SDDAT1 _UINT32_(51) +#define MUX_PB19I_SDHC1_SDDAT1 _UINT32_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UINT32_(1) << 19) + +#define PIN_PB20I_SDHC1_SDDAT2 _UINT32_(52) +#define MUX_PB20I_SDHC1_SDDAT2 _UINT32_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UINT32_(1) << 20) + +#define PIN_PB21I_SDHC1_SDDAT3 _UINT32_(53) +#define MUX_PB21I_SDHC1_SDDAT3 _UINT32_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UINT32_(1) << 21) + +#define PIN_PB17I_SDHC1_SDWP _UINT32_(49) +#define MUX_PB17I_SDHC1_SDWP _UINT32_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UINT32_(1) << 17) + +#define PIN_PC21I_SDHC1_SDWP _UINT32_(85) +#define MUX_PC21I_SDHC1_SDWP _UINT32_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UINT32_(1) << 21) + +#define PIN_PD21I_SDHC1_SDWP _UINT32_(117) +#define MUX_PD21I_SDHC1_SDWP _UINT32_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UINT32_(1) << 21) + +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _UINT32_(4) +#define MUX_PA04D_SERCOM0_PAD0 _UINT32_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UINT32_(1) << 4) + +#define PIN_PC17D_SERCOM0_PAD0 _UINT32_(81) +#define MUX_PC17D_SERCOM0_PAD0 _UINT32_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UINT32_(1) << 17) + +#define PIN_PA08C_SERCOM0_PAD0 _UINT32_(8) +#define MUX_PA08C_SERCOM0_PAD0 _UINT32_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UINT32_(1) << 8) + +#define PIN_PB24C_SERCOM0_PAD0 _UINT32_(56) +#define MUX_PB24C_SERCOM0_PAD0 _UINT32_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UINT32_(1) << 24) + +#define PIN_PA05D_SERCOM0_PAD1 _UINT32_(5) +#define MUX_PA05D_SERCOM0_PAD1 _UINT32_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UINT32_(1) << 5) + +#define PIN_PC16D_SERCOM0_PAD1 _UINT32_(80) +#define MUX_PC16D_SERCOM0_PAD1 _UINT32_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UINT32_(1) << 16) + +#define PIN_PA09C_SERCOM0_PAD1 _UINT32_(9) +#define MUX_PA09C_SERCOM0_PAD1 _UINT32_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UINT32_(1) << 9) + +#define PIN_PB25C_SERCOM0_PAD1 _UINT32_(57) +#define MUX_PB25C_SERCOM0_PAD1 _UINT32_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UINT32_(1) << 25) + +#define PIN_PA06D_SERCOM0_PAD2 _UINT32_(6) +#define MUX_PA06D_SERCOM0_PAD2 _UINT32_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UINT32_(1) << 6) + +#define PIN_PC18D_SERCOM0_PAD2 _UINT32_(82) +#define MUX_PC18D_SERCOM0_PAD2 _UINT32_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA10C_SERCOM0_PAD2 _UINT32_(10) +#define MUX_PA10C_SERCOM0_PAD2 _UINT32_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC24C_SERCOM0_PAD2 _UINT32_(88) +#define MUX_PC24C_SERCOM0_PAD2 _UINT32_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UINT32_(1) << 24) + +#define PIN_PA07D_SERCOM0_PAD3 _UINT32_(7) +#define MUX_PA07D_SERCOM0_PAD3 _UINT32_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UINT32_(1) << 7) + +#define PIN_PC19D_SERCOM0_PAD3 _UINT32_(83) +#define MUX_PC19D_SERCOM0_PAD3 _UINT32_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UINT32_(1) << 19) + +#define PIN_PA11C_SERCOM0_PAD3 _UINT32_(11) +#define MUX_PA11C_SERCOM0_PAD3 _UINT32_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC25C_SERCOM0_PAD3 _UINT32_(89) +#define MUX_PC25C_SERCOM0_PAD3 _UINT32_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UINT32_(1) << 25) + +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _UINT32_(0) +#define MUX_PA00D_SERCOM1_PAD0 _UINT32_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UINT32_(1) << 0) + +#define PIN_PA16C_SERCOM1_PAD0 _UINT32_(16) +#define MUX_PA16C_SERCOM1_PAD0 _UINT32_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UINT32_(1) << 16) + +#define PIN_PC22C_SERCOM1_PAD0 _UINT32_(86) +#define MUX_PC22C_SERCOM1_PAD0 _UINT32_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UINT32_(1) << 22) + +#define PIN_PC27C_SERCOM1_PAD0 _UINT32_(91) +#define MUX_PC27C_SERCOM1_PAD0 _UINT32_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UINT32_(1) << 27) + +#define PIN_PA01D_SERCOM1_PAD1 _UINT32_(1) +#define MUX_PA01D_SERCOM1_PAD1 _UINT32_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UINT32_(1) << 1) + +#define PIN_PA17C_SERCOM1_PAD1 _UINT32_(17) +#define MUX_PA17C_SERCOM1_PAD1 _UINT32_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UINT32_(1) << 17) + +#define PIN_PC23C_SERCOM1_PAD1 _UINT32_(87) +#define MUX_PC23C_SERCOM1_PAD1 _UINT32_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UINT32_(1) << 23) + +#define PIN_PC28C_SERCOM1_PAD1 _UINT32_(92) +#define MUX_PC28C_SERCOM1_PAD1 _UINT32_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UINT32_(1) << 28) + +#define PIN_PA30D_SERCOM1_PAD2 _UINT32_(30) +#define MUX_PA30D_SERCOM1_PAD2 _UINT32_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UINT32_(1) << 30) + +#define PIN_PA18C_SERCOM1_PAD2 _UINT32_(18) +#define MUX_PA18C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UINT32_(1) << 18) + +#define PIN_PB22C_SERCOM1_PAD2 _UINT32_(54) +#define MUX_PB22C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UINT32_(1) << 22) + +#define PIN_PD20C_SERCOM1_PAD2 _UINT32_(116) +#define MUX_PD20C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UINT32_(1) << 20) + +#define PIN_PA31D_SERCOM1_PAD3 _UINT32_(31) +#define MUX_PA31D_SERCOM1_PAD3 _UINT32_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UINT32_(1) << 31) + +#define PIN_PA19C_SERCOM1_PAD3 _UINT32_(19) +#define MUX_PA19C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UINT32_(1) << 19) + +#define PIN_PB23C_SERCOM1_PAD3 _UINT32_(55) +#define MUX_PB23C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UINT32_(1) << 23) + +#define PIN_PD21C_SERCOM1_PAD3 _UINT32_(117) +#define MUX_PD21C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UINT32_(1) << 21) + +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _UINT32_(9) +#define MUX_PA09D_SERCOM2_PAD0 _UINT32_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UINT32_(1) << 9) + +#define PIN_PB25D_SERCOM2_PAD0 _UINT32_(57) +#define MUX_PB25D_SERCOM2_PAD0 _UINT32_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UINT32_(1) << 25) + +#define PIN_PA12C_SERCOM2_PAD0 _UINT32_(12) +#define MUX_PA12C_SERCOM2_PAD0 _UINT32_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UINT32_(1) << 12) + +#define PIN_PB26C_SERCOM2_PAD0 _UINT32_(58) +#define MUX_PB26C_SERCOM2_PAD0 _UINT32_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UINT32_(1) << 26) + +#define PIN_PA08D_SERCOM2_PAD1 _UINT32_(8) +#define MUX_PA08D_SERCOM2_PAD1 _UINT32_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UINT32_(1) << 8) + +#define PIN_PB24D_SERCOM2_PAD1 _UINT32_(56) +#define MUX_PB24D_SERCOM2_PAD1 _UINT32_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UINT32_(1) << 24) + +#define PIN_PA13C_SERCOM2_PAD1 _UINT32_(13) +#define MUX_PA13C_SERCOM2_PAD1 _UINT32_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UINT32_(1) << 13) + +#define PIN_PB27C_SERCOM2_PAD1 _UINT32_(59) +#define MUX_PB27C_SERCOM2_PAD1 _UINT32_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UINT32_(1) << 27) + +#define PIN_PA10D_SERCOM2_PAD2 _UINT32_(10) +#define MUX_PA10D_SERCOM2_PAD2 _UINT32_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC24D_SERCOM2_PAD2 _UINT32_(88) +#define MUX_PC24D_SERCOM2_PAD2 _UINT32_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UINT32_(1) << 24) + +#define PIN_PB28C_SERCOM2_PAD2 _UINT32_(60) +#define MUX_PB28C_SERCOM2_PAD2 _UINT32_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UINT32_(1) << 28) + +#define PIN_PA14C_SERCOM2_PAD2 _UINT32_(14) +#define MUX_PA14C_SERCOM2_PAD2 _UINT32_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UINT32_(1) << 14) + +#define PIN_PA11D_SERCOM2_PAD3 _UINT32_(11) +#define MUX_PA11D_SERCOM2_PAD3 _UINT32_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC25D_SERCOM2_PAD3 _UINT32_(89) +#define MUX_PC25D_SERCOM2_PAD3 _UINT32_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UINT32_(1) << 25) + +#define PIN_PB29C_SERCOM2_PAD3 _UINT32_(61) +#define MUX_PB29C_SERCOM2_PAD3 _UINT32_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UINT32_(1) << 29) + +#define PIN_PA15C_SERCOM2_PAD3 _UINT32_(15) +#define MUX_PA15C_SERCOM2_PAD3 _UINT32_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UINT32_(1) << 15) + +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _UINT32_(17) +#define MUX_PA17D_SERCOM3_PAD0 _UINT32_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UINT32_(1) << 17) + +#define PIN_PC23D_SERCOM3_PAD0 _UINT32_(87) +#define MUX_PC23D_SERCOM3_PAD0 _UINT32_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UINT32_(1) << 23) + +#define PIN_PA22C_SERCOM3_PAD0 _UINT32_(22) +#define MUX_PA22C_SERCOM3_PAD0 _UINT32_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UINT32_(1) << 22) + +#define PIN_PB20C_SERCOM3_PAD0 _UINT32_(52) +#define MUX_PB20C_SERCOM3_PAD0 _UINT32_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UINT32_(1) << 20) + +#define PIN_PA16D_SERCOM3_PAD1 _UINT32_(16) +#define MUX_PA16D_SERCOM3_PAD1 _UINT32_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UINT32_(1) << 16) + +#define PIN_PC22D_SERCOM3_PAD1 _UINT32_(86) +#define MUX_PC22D_SERCOM3_PAD1 _UINT32_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UINT32_(1) << 22) + +#define PIN_PA23C_SERCOM3_PAD1 _UINT32_(23) +#define MUX_PA23C_SERCOM3_PAD1 _UINT32_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UINT32_(1) << 23) + +#define PIN_PB21C_SERCOM3_PAD1 _UINT32_(53) +#define MUX_PB21C_SERCOM3_PAD1 _UINT32_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UINT32_(1) << 21) + +#define PIN_PA18D_SERCOM3_PAD2 _UINT32_(18) +#define MUX_PA18D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA20D_SERCOM3_PAD2 _UINT32_(20) +#define MUX_PA20D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UINT32_(1) << 20) + +#define PIN_PD20D_SERCOM3_PAD2 _UINT32_(116) +#define MUX_PD20D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UINT32_(1) << 20) + +#define PIN_PA24C_SERCOM3_PAD2 _UINT32_(24) +#define MUX_PA24C_SERCOM3_PAD2 _UINT32_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UINT32_(1) << 24) + +#define PIN_PA19D_SERCOM3_PAD3 _UINT32_(19) +#define MUX_PA19D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UINT32_(1) << 19) + +#define PIN_PA21D_SERCOM3_PAD3 _UINT32_(21) +#define MUX_PA21D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UINT32_(1) << 21) + +#define PIN_PD21D_SERCOM3_PAD3 _UINT32_(117) +#define MUX_PD21D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UINT32_(1) << 21) + +#define PIN_PA25C_SERCOM3_PAD3 _UINT32_(25) +#define MUX_PA25C_SERCOM3_PAD3 _UINT32_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UINT32_(1) << 25) + +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _UINT32_(13) +#define MUX_PA13D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UINT32_(1) << 13) + +#define PIN_PB08D_SERCOM4_PAD0 _UINT32_(40) +#define MUX_PB08D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UINT32_(1) << 8) + +#define PIN_PB27D_SERCOM4_PAD0 _UINT32_(59) +#define MUX_PB27D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UINT32_(1) << 27) + +#define PIN_PB12C_SERCOM4_PAD0 _UINT32_(44) +#define MUX_PB12C_SERCOM4_PAD0 _UINT32_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UINT32_(1) << 12) + +#define PIN_PA12D_SERCOM4_PAD1 _UINT32_(12) +#define MUX_PA12D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UINT32_(1) << 12) + +#define PIN_PB09D_SERCOM4_PAD1 _UINT32_(41) +#define MUX_PB09D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UINT32_(1) << 9) + +#define PIN_PB26D_SERCOM4_PAD1 _UINT32_(58) +#define MUX_PB26D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UINT32_(1) << 26) + +#define PIN_PB13C_SERCOM4_PAD1 _UINT32_(45) +#define MUX_PB13C_SERCOM4_PAD1 _UINT32_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UINT32_(1) << 13) + +#define PIN_PA14D_SERCOM4_PAD2 _UINT32_(14) +#define MUX_PA14D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UINT32_(1) << 14) + +#define PIN_PB10D_SERCOM4_PAD2 _UINT32_(42) +#define MUX_PB10D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UINT32_(1) << 10) + +#define PIN_PB28D_SERCOM4_PAD2 _UINT32_(60) +#define MUX_PB28D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UINT32_(1) << 28) + +#define PIN_PB14C_SERCOM4_PAD2 _UINT32_(46) +#define MUX_PB14C_SERCOM4_PAD2 _UINT32_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UINT32_(1) << 14) + +#define PIN_PB11D_SERCOM4_PAD3 _UINT32_(43) +#define MUX_PB11D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UINT32_(1) << 11) + +#define PIN_PB29D_SERCOM4_PAD3 _UINT32_(61) +#define MUX_PB29D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UINT32_(1) << 29) + +#define PIN_PA15D_SERCOM4_PAD3 _UINT32_(15) +#define MUX_PA15D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UINT32_(1) << 15) + +#define PIN_PB15C_SERCOM4_PAD3 _UINT32_(47) +#define MUX_PB15C_SERCOM4_PAD3 _UINT32_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UINT32_(1) << 15) + +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _UINT32_(23) +#define MUX_PA23D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UINT32_(1) << 23) + +#define PIN_PB02D_SERCOM5_PAD0 _UINT32_(34) +#define MUX_PB02D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UINT32_(1) << 2) + +#define PIN_PB31D_SERCOM5_PAD0 _UINT32_(63) +#define MUX_PB31D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UINT32_(1) << 31) + +#define PIN_PB16C_SERCOM5_PAD0 _UINT32_(48) +#define MUX_PB16C_SERCOM5_PAD0 _UINT32_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UINT32_(1) << 16) + +#define PIN_PA22D_SERCOM5_PAD1 _UINT32_(22) +#define MUX_PA22D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UINT32_(1) << 22) + +#define PIN_PB03D_SERCOM5_PAD1 _UINT32_(35) +#define MUX_PB03D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UINT32_(1) << 3) + +#define PIN_PB30D_SERCOM5_PAD1 _UINT32_(62) +#define MUX_PB30D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UINT32_(1) << 30) + +#define PIN_PB17C_SERCOM5_PAD1 _UINT32_(49) +#define MUX_PB17C_SERCOM5_PAD1 _UINT32_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UINT32_(1) << 17) + +#define PIN_PA24D_SERCOM5_PAD2 _UINT32_(24) +#define MUX_PA24D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UINT32_(1) << 24) + +#define PIN_PB00D_SERCOM5_PAD2 _UINT32_(32) +#define MUX_PB00D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UINT32_(1) << 0) + +#define PIN_PB22D_SERCOM5_PAD2 _UINT32_(54) +#define MUX_PB22D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UINT32_(1) << 22) + +#define PIN_PA20C_SERCOM5_PAD2 _UINT32_(20) +#define MUX_PA20C_SERCOM5_PAD2 _UINT32_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UINT32_(1) << 20) + +#define PIN_PB18C_SERCOM5_PAD2 _UINT32_(50) +#define MUX_PB18C_SERCOM5_PAD2 _UINT32_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA25D_SERCOM5_PAD3 _UINT32_(25) +#define MUX_PA25D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UINT32_(1) << 25) + +#define PIN_PB01D_SERCOM5_PAD3 _UINT32_(33) +#define MUX_PB01D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UINT32_(1) << 1) + +#define PIN_PB23D_SERCOM5_PAD3 _UINT32_(55) +#define MUX_PB23D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UINT32_(1) << 23) + +#define PIN_PA21C_SERCOM5_PAD3 _UINT32_(21) +#define MUX_PA21C_SERCOM5_PAD3 _UINT32_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UINT32_(1) << 21) + +#define PIN_PB19C_SERCOM5_PAD3 _UINT32_(51) +#define MUX_PB19C_SERCOM5_PAD3 _UINT32_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UINT32_(1) << 19) + +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _UINT32_(105) +#define MUX_PD09D_SERCOM6_PAD0 _UINT32_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UINT32_(1) << 9) + +#define PIN_PC13D_SERCOM6_PAD0 _UINT32_(77) +#define MUX_PC13D_SERCOM6_PAD0 _UINT32_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UINT32_(1) << 13) + +#define PIN_PC04C_SERCOM6_PAD0 _UINT32_(68) +#define MUX_PC04C_SERCOM6_PAD0 _UINT32_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UINT32_(1) << 4) + +#define PIN_PC16C_SERCOM6_PAD0 _UINT32_(80) +#define MUX_PC16C_SERCOM6_PAD0 _UINT32_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UINT32_(1) << 16) + +#define PIN_PD08D_SERCOM6_PAD1 _UINT32_(104) +#define MUX_PD08D_SERCOM6_PAD1 _UINT32_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UINT32_(1) << 8) + +#define PIN_PC12D_SERCOM6_PAD1 _UINT32_(76) +#define MUX_PC12D_SERCOM6_PAD1 _UINT32_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UINT32_(1) << 12) + +#define PIN_PC05C_SERCOM6_PAD1 _UINT32_(69) +#define MUX_PC05C_SERCOM6_PAD1 _UINT32_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UINT32_(1) << 5) + +#define PIN_PC17C_SERCOM6_PAD1 _UINT32_(81) +#define MUX_PC17C_SERCOM6_PAD1 _UINT32_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UINT32_(1) << 17) + +#define PIN_PC14D_SERCOM6_PAD2 _UINT32_(78) +#define MUX_PC14D_SERCOM6_PAD2 _UINT32_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UINT32_(1) << 14) + +#define PIN_PD10D_SERCOM6_PAD2 _UINT32_(106) +#define MUX_PD10D_SERCOM6_PAD2 _UINT32_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC06C_SERCOM6_PAD2 _UINT32_(70) +#define MUX_PC06C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UINT32_(1) << 6) + +#define PIN_PC10C_SERCOM6_PAD2 _UINT32_(74) +#define MUX_PC10C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC18C_SERCOM6_PAD2 _UINT32_(82) +#define MUX_PC18C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UINT32_(1) << 18) + +#define PIN_PC15D_SERCOM6_PAD3 _UINT32_(79) +#define MUX_PC15D_SERCOM6_PAD3 _UINT32_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UINT32_(1) << 15) + +#define PIN_PD11D_SERCOM6_PAD3 _UINT32_(107) +#define MUX_PD11D_SERCOM6_PAD3 _UINT32_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC07C_SERCOM6_PAD3 _UINT32_(71) +#define MUX_PC07C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UINT32_(1) << 7) + +#define PIN_PC11C_SERCOM6_PAD3 _UINT32_(75) +#define MUX_PC11C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC19C_SERCOM6_PAD3 _UINT32_(83) +#define MUX_PC19C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UINT32_(1) << 19) + +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _UINT32_(53) +#define MUX_PB21D_SERCOM7_PAD0 _UINT32_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UINT32_(1) << 21) + +#define PIN_PD08C_SERCOM7_PAD0 _UINT32_(104) +#define MUX_PD08C_SERCOM7_PAD0 _UINT32_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UINT32_(1) << 8) + +#define PIN_PB30C_SERCOM7_PAD0 _UINT32_(62) +#define MUX_PB30C_SERCOM7_PAD0 _UINT32_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UINT32_(1) << 30) + +#define PIN_PC12C_SERCOM7_PAD0 _UINT32_(76) +#define MUX_PC12C_SERCOM7_PAD0 _UINT32_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UINT32_(1) << 12) + +#define PIN_PB20D_SERCOM7_PAD1 _UINT32_(52) +#define MUX_PB20D_SERCOM7_PAD1 _UINT32_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UINT32_(1) << 20) + +#define PIN_PD09C_SERCOM7_PAD1 _UINT32_(105) +#define MUX_PD09C_SERCOM7_PAD1 _UINT32_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UINT32_(1) << 9) + +#define PIN_PB31C_SERCOM7_PAD1 _UINT32_(63) +#define MUX_PB31C_SERCOM7_PAD1 _UINT32_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UINT32_(1) << 31) + +#define PIN_PC13C_SERCOM7_PAD1 _UINT32_(77) +#define MUX_PC13C_SERCOM7_PAD1 _UINT32_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UINT32_(1) << 13) + +#define PIN_PB18D_SERCOM7_PAD2 _UINT32_(50) +#define MUX_PB18D_SERCOM7_PAD2 _UINT32_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UINT32_(1) << 18) + +#define PIN_PC10D_SERCOM7_PAD2 _UINT32_(74) +#define MUX_PC10D_SERCOM7_PAD2 _UINT32_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC14C_SERCOM7_PAD2 _UINT32_(78) +#define MUX_PC14C_SERCOM7_PAD2 _UINT32_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UINT32_(1) << 14) + +#define PIN_PD10C_SERCOM7_PAD2 _UINT32_(106) +#define MUX_PD10C_SERCOM7_PAD2 _UINT32_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UINT32_(1) << 10) + +#define PIN_PA30C_SERCOM7_PAD2 _UINT32_(30) +#define MUX_PA30C_SERCOM7_PAD2 _UINT32_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UINT32_(1) << 30) + +#define PIN_PB19D_SERCOM7_PAD3 _UINT32_(51) +#define MUX_PB19D_SERCOM7_PAD3 _UINT32_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UINT32_(1) << 19) + +#define PIN_PC11D_SERCOM7_PAD3 _UINT32_(75) +#define MUX_PC11D_SERCOM7_PAD3 _UINT32_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC15C_SERCOM7_PAD3 _UINT32_(79) +#define MUX_PC15C_SERCOM7_PAD3 _UINT32_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UINT32_(1) << 15) + +#define PIN_PD11C_SERCOM7_PAD3 _UINT32_(107) +#define MUX_PD11C_SERCOM7_PAD3 _UINT32_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UINT32_(1) << 11) + +#define PIN_PA31C_SERCOM7_PAD3 _UINT32_(31) +#define MUX_PA31C_SERCOM7_PAD3 _UINT32_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UINT32_(1) << 31) + +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _UINT32_(4) +#define MUX_PA04E_TC0_WO0 _UINT32_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UINT32_(1) << 4) + +#define PIN_PA08E_TC0_WO0 _UINT32_(8) +#define MUX_PA08E_TC0_WO0 _UINT32_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UINT32_(1) << 8) + +#define PIN_PB30E_TC0_WO0 _UINT32_(62) +#define MUX_PB30E_TC0_WO0 _UINT32_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UINT32_(1) << 30) + +#define PIN_PA05E_TC0_WO1 _UINT32_(5) +#define MUX_PA05E_TC0_WO1 _UINT32_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UINT32_(1) << 5) + +#define PIN_PA09E_TC0_WO1 _UINT32_(9) +#define MUX_PA09E_TC0_WO1 _UINT32_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UINT32_(1) << 9) + +#define PIN_PB31E_TC0_WO1 _UINT32_(63) +#define MUX_PB31E_TC0_WO1 _UINT32_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UINT32_(1) << 31) + +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _UINT32_(6) +#define MUX_PA06E_TC1_WO0 _UINT32_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UINT32_(1) << 6) + +#define PIN_PA10E_TC1_WO0 _UINT32_(10) +#define MUX_PA10E_TC1_WO0 _UINT32_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UINT32_(1) << 10) + +#define PIN_PA07E_TC1_WO1 _UINT32_(7) +#define MUX_PA07E_TC1_WO1 _UINT32_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UINT32_(1) << 7) + +#define PIN_PA11E_TC1_WO1 _UINT32_(11) +#define MUX_PA11E_TC1_WO1 _UINT32_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UINT32_(1) << 11) + +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _UINT32_(12) +#define MUX_PA12E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UINT32_(1) << 12) + +#define PIN_PA16E_TC2_WO0 _UINT32_(16) +#define MUX_PA16E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UINT32_(1) << 16) + +#define PIN_PA00E_TC2_WO0 _UINT32_(0) +#define MUX_PA00E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UINT32_(1) << 0) + +#define PIN_PA01E_TC2_WO1 _UINT32_(1) +#define MUX_PA01E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UINT32_(1) << 1) + +#define PIN_PA13E_TC2_WO1 _UINT32_(13) +#define MUX_PA13E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UINT32_(1) << 13) + +#define PIN_PA17E_TC2_WO1 _UINT32_(17) +#define MUX_PA17E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _UINT32_(18) +#define MUX_PA18E_TC3_WO0 _UINT32_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UINT32_(1) << 18) + +#define PIN_PA14E_TC3_WO0 _UINT32_(14) +#define MUX_PA14E_TC3_WO0 _UINT32_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UINT32_(1) << 14) + +#define PIN_PA15E_TC3_WO1 _UINT32_(15) +#define MUX_PA15E_TC3_WO1 _UINT32_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UINT32_(1) << 15) + +#define PIN_PA19E_TC3_WO1 _UINT32_(19) +#define MUX_PA19E_TC3_WO1 _UINT32_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UINT32_(1) << 19) + +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _UINT32_(22) +#define MUX_PA22E_TC4_WO0 _UINT32_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UINT32_(1) << 22) + +#define PIN_PB08E_TC4_WO0 _UINT32_(40) +#define MUX_PB08E_TC4_WO0 _UINT32_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UINT32_(1) << 8) + +#define PIN_PB12E_TC4_WO0 _UINT32_(44) +#define MUX_PB12E_TC4_WO0 _UINT32_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UINT32_(1) << 12) + +#define PIN_PA23E_TC4_WO1 _UINT32_(23) +#define MUX_PA23E_TC4_WO1 _UINT32_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UINT32_(1) << 23) + +#define PIN_PB09E_TC4_WO1 _UINT32_(41) +#define MUX_PB09E_TC4_WO1 _UINT32_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UINT32_(1) << 9) + +#define PIN_PB13E_TC4_WO1 _UINT32_(45) +#define MUX_PB13E_TC4_WO1 _UINT32_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UINT32_(1) << 13) + +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _UINT32_(24) +#define MUX_PA24E_TC5_WO0 _UINT32_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UINT32_(1) << 24) + +#define PIN_PB10E_TC5_WO0 _UINT32_(42) +#define MUX_PB10E_TC5_WO0 _UINT32_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UINT32_(1) << 10) + +#define PIN_PB14E_TC5_WO0 _UINT32_(46) +#define MUX_PB14E_TC5_WO0 _UINT32_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UINT32_(1) << 14) + +#define PIN_PA25E_TC5_WO1 _UINT32_(25) +#define MUX_PA25E_TC5_WO1 _UINT32_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UINT32_(1) << 25) + +#define PIN_PB11E_TC5_WO1 _UINT32_(43) +#define MUX_PB11E_TC5_WO1 _UINT32_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UINT32_(1) << 11) + +#define PIN_PB15E_TC5_WO1 _UINT32_(47) +#define MUX_PB15E_TC5_WO1 _UINT32_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UINT32_(1) << 15) + +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _UINT32_(30) +#define MUX_PA30E_TC6_WO0 _UINT32_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UINT32_(1) << 30) + +#define PIN_PB02E_TC6_WO0 _UINT32_(34) +#define MUX_PB02E_TC6_WO0 _UINT32_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UINT32_(1) << 2) + +#define PIN_PB16E_TC6_WO0 _UINT32_(48) +#define MUX_PB16E_TC6_WO0 _UINT32_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UINT32_(1) << 16) + +#define PIN_PA31E_TC6_WO1 _UINT32_(31) +#define MUX_PA31E_TC6_WO1 _UINT32_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UINT32_(1) << 31) + +#define PIN_PB03E_TC6_WO1 _UINT32_(35) +#define MUX_PB03E_TC6_WO1 _UINT32_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UINT32_(1) << 3) + +#define PIN_PB17E_TC6_WO1 _UINT32_(49) +#define MUX_PB17E_TC6_WO1 _UINT32_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _UINT32_(20) +#define MUX_PA20E_TC7_WO0 _UINT32_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UINT32_(1) << 20) + +#define PIN_PB00E_TC7_WO0 _UINT32_(32) +#define MUX_PB00E_TC7_WO0 _UINT32_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UINT32_(1) << 0) + +#define PIN_PB22E_TC7_WO0 _UINT32_(54) +#define MUX_PB22E_TC7_WO0 _UINT32_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UINT32_(1) << 22) + +#define PIN_PA21E_TC7_WO1 _UINT32_(21) +#define MUX_PA21E_TC7_WO1 _UINT32_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UINT32_(1) << 21) + +#define PIN_PB01E_TC7_WO1 _UINT32_(33) +#define MUX_PB01E_TC7_WO1 _UINT32_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UINT32_(1) << 1) + +#define PIN_PB23E_TC7_WO1 _UINT32_(55) +#define MUX_PB23E_TC7_WO1 _UINT32_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UINT32_(1) << 23) + +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _UINT32_(20) +#define MUX_PA20G_TCC0_WO0 _UINT32_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UINT32_(1) << 20) + +#define PIN_PB12G_TCC0_WO0 _UINT32_(44) +#define MUX_PB12G_TCC0_WO0 _UINT32_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UINT32_(1) << 12) + +#define PIN_PA08F_TCC0_WO0 _UINT32_(8) +#define MUX_PA08F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UINT32_(1) << 8) + +#define PIN_PC04F_TCC0_WO0 _UINT32_(68) +#define MUX_PC04F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UINT32_(1) << 4) + +#define PIN_PC10F_TCC0_WO0 _UINT32_(74) +#define MUX_PC10F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UINT32_(1) << 10) + +#define PIN_PC16F_TCC0_WO0 _UINT32_(80) +#define MUX_PC16F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UINT32_(1) << 16) + +#define PIN_PA21G_TCC0_WO1 _UINT32_(21) +#define MUX_PA21G_TCC0_WO1 _UINT32_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UINT32_(1) << 21) + +#define PIN_PB13G_TCC0_WO1 _UINT32_(45) +#define MUX_PB13G_TCC0_WO1 _UINT32_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UINT32_(1) << 13) + +#define PIN_PA09F_TCC0_WO1 _UINT32_(9) +#define MUX_PA09F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UINT32_(1) << 9) + +#define PIN_PC11F_TCC0_WO1 _UINT32_(75) +#define MUX_PC11F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UINT32_(1) << 11) + +#define PIN_PC17F_TCC0_WO1 _UINT32_(81) +#define MUX_PC17F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UINT32_(1) << 17) + +#define PIN_PD08F_TCC0_WO1 _UINT32_(104) +#define MUX_PD08F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UINT32_(1) << 8) + +#define PIN_PA22G_TCC0_WO2 _UINT32_(22) +#define MUX_PA22G_TCC0_WO2 _UINT32_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UINT32_(1) << 22) + +#define PIN_PB14G_TCC0_WO2 _UINT32_(46) +#define MUX_PB14G_TCC0_WO2 _UINT32_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UINT32_(1) << 14) + +#define PIN_PA10F_TCC0_WO2 _UINT32_(10) +#define MUX_PA10F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UINT32_(1) << 10) + +#define PIN_PC12F_TCC0_WO2 _UINT32_(76) +#define MUX_PC12F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UINT32_(1) << 12) + +#define PIN_PC18F_TCC0_WO2 _UINT32_(82) +#define MUX_PC18F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UINT32_(1) << 18) + +#define PIN_PD09F_TCC0_WO2 _UINT32_(105) +#define MUX_PD09F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UINT32_(1) << 9) + +#define PIN_PA23G_TCC0_WO3 _UINT32_(23) +#define MUX_PA23G_TCC0_WO3 _UINT32_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UINT32_(1) << 23) + +#define PIN_PB15G_TCC0_WO3 _UINT32_(47) +#define MUX_PB15G_TCC0_WO3 _UINT32_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UINT32_(1) << 15) + +#define PIN_PA11F_TCC0_WO3 _UINT32_(11) +#define MUX_PA11F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UINT32_(1) << 11) + +#define PIN_PC13F_TCC0_WO3 _UINT32_(77) +#define MUX_PC13F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UINT32_(1) << 13) + +#define PIN_PC19F_TCC0_WO3 _UINT32_(83) +#define MUX_PC19F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UINT32_(1) << 19) + +#define PIN_PD10F_TCC0_WO3 _UINT32_(106) +#define MUX_PD10F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UINT32_(1) << 10) + +#define PIN_PA16G_TCC0_WO4 _UINT32_(16) +#define MUX_PA16G_TCC0_WO4 _UINT32_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UINT32_(1) << 16) + +#define PIN_PB16G_TCC0_WO4 _UINT32_(48) +#define MUX_PB16G_TCC0_WO4 _UINT32_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UINT32_(1) << 16) + +#define PIN_PB10F_TCC0_WO4 _UINT32_(42) +#define MUX_PB10F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UINT32_(1) << 10) + +#define PIN_PC14F_TCC0_WO4 _UINT32_(78) +#define MUX_PC14F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UINT32_(1) << 14) + +#define PIN_PC20F_TCC0_WO4 _UINT32_(84) +#define MUX_PC20F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UINT32_(1) << 20) + +#define PIN_PD11F_TCC0_WO4 _UINT32_(107) +#define MUX_PD11F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UINT32_(1) << 11) + +#define PIN_PA17G_TCC0_WO5 _UINT32_(17) +#define MUX_PA17G_TCC0_WO5 _UINT32_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UINT32_(1) << 17) + +#define PIN_PB17G_TCC0_WO5 _UINT32_(49) +#define MUX_PB17G_TCC0_WO5 _UINT32_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UINT32_(1) << 17) + +#define PIN_PB11F_TCC0_WO5 _UINT32_(43) +#define MUX_PB11F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UINT32_(1) << 11) + +#define PIN_PC15F_TCC0_WO5 _UINT32_(79) +#define MUX_PC15F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UINT32_(1) << 15) + +#define PIN_PC21F_TCC0_WO5 _UINT32_(85) +#define MUX_PC21F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UINT32_(1) << 21) + +#define PIN_PD12F_TCC0_WO5 _UINT32_(108) +#define MUX_PD12F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UINT32_(1) << 12) + +#define PIN_PA18G_TCC0_WO6 _UINT32_(18) +#define MUX_PA18G_TCC0_WO6 _UINT32_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UINT32_(1) << 18) + +#define PIN_PB30G_TCC0_WO6 _UINT32_(62) +#define MUX_PB30G_TCC0_WO6 _UINT32_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UINT32_(1) << 30) + +#define PIN_PA12F_TCC0_WO6 _UINT32_(12) +#define MUX_PA12F_TCC0_WO6 _UINT32_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UINT32_(1) << 12) + +#define PIN_PC22F_TCC0_WO6 _UINT32_(86) +#define MUX_PC22F_TCC0_WO6 _UINT32_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UINT32_(1) << 22) + +#define PIN_PA19G_TCC0_WO7 _UINT32_(19) +#define MUX_PA19G_TCC0_WO7 _UINT32_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UINT32_(1) << 19) + +#define PIN_PB31G_TCC0_WO7 _UINT32_(63) +#define MUX_PB31G_TCC0_WO7 _UINT32_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UINT32_(1) << 31) + +#define PIN_PA13F_TCC0_WO7 _UINT32_(13) +#define MUX_PA13F_TCC0_WO7 _UINT32_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UINT32_(1) << 13) + +#define PIN_PC23F_TCC0_WO7 _UINT32_(87) +#define MUX_PC23F_TCC0_WO7 _UINT32_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UINT32_(1) << 23) + +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _UINT32_(42) +#define MUX_PB10G_TCC1_WO0 _UINT32_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UINT32_(1) << 10) + +#define PIN_PC14G_TCC1_WO0 _UINT32_(78) +#define MUX_PC14G_TCC1_WO0 _UINT32_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UINT32_(1) << 14) + +#define PIN_PA16F_TCC1_WO0 _UINT32_(16) +#define MUX_PA16F_TCC1_WO0 _UINT32_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UINT32_(1) << 16) + +#define PIN_PB18F_TCC1_WO0 _UINT32_(50) +#define MUX_PB18F_TCC1_WO0 _UINT32_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UINT32_(1) << 18) + +#define PIN_PD20F_TCC1_WO0 _UINT32_(116) +#define MUX_PD20F_TCC1_WO0 _UINT32_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UINT32_(1) << 20) + +#define PIN_PB11G_TCC1_WO1 _UINT32_(43) +#define MUX_PB11G_TCC1_WO1 _UINT32_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UINT32_(1) << 11) + +#define PIN_PC15G_TCC1_WO1 _UINT32_(79) +#define MUX_PC15G_TCC1_WO1 _UINT32_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UINT32_(1) << 15) + +#define PIN_PA17F_TCC1_WO1 _UINT32_(17) +#define MUX_PA17F_TCC1_WO1 _UINT32_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UINT32_(1) << 17) + +#define PIN_PB19F_TCC1_WO1 _UINT32_(51) +#define MUX_PB19F_TCC1_WO1 _UINT32_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UINT32_(1) << 19) + +#define PIN_PD21F_TCC1_WO1 _UINT32_(117) +#define MUX_PD21F_TCC1_WO1 _UINT32_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UINT32_(1) << 21) + +#define PIN_PA12G_TCC1_WO2 _UINT32_(12) +#define MUX_PA12G_TCC1_WO2 _UINT32_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UINT32_(1) << 12) + +#define PIN_PA14G_TCC1_WO2 _UINT32_(14) +#define MUX_PA14G_TCC1_WO2 _UINT32_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UINT32_(1) << 14) + +#define PIN_PA18F_TCC1_WO2 _UINT32_(18) +#define MUX_PA18F_TCC1_WO2 _UINT32_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UINT32_(1) << 18) + +#define PIN_PB20F_TCC1_WO2 _UINT32_(52) +#define MUX_PB20F_TCC1_WO2 _UINT32_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UINT32_(1) << 20) + +#define PIN_PB26F_TCC1_WO2 _UINT32_(58) +#define MUX_PB26F_TCC1_WO2 _UINT32_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UINT32_(1) << 26) + +#define PIN_PA13G_TCC1_WO3 _UINT32_(13) +#define MUX_PA13G_TCC1_WO3 _UINT32_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UINT32_(1) << 13) + +#define PIN_PA15G_TCC1_WO3 _UINT32_(15) +#define MUX_PA15G_TCC1_WO3 _UINT32_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UINT32_(1) << 15) + +#define PIN_PA19F_TCC1_WO3 _UINT32_(19) +#define MUX_PA19F_TCC1_WO3 _UINT32_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UINT32_(1) << 19) + +#define PIN_PB21F_TCC1_WO3 _UINT32_(53) +#define MUX_PB21F_TCC1_WO3 _UINT32_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UINT32_(1) << 21) + +#define PIN_PB27F_TCC1_WO3 _UINT32_(59) +#define MUX_PB27F_TCC1_WO3 _UINT32_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UINT32_(1) << 27) + +#define PIN_PA08G_TCC1_WO4 _UINT32_(8) +#define MUX_PA08G_TCC1_WO4 _UINT32_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UINT32_(1) << 8) + +#define PIN_PC10G_TCC1_WO4 _UINT32_(74) +#define MUX_PC10G_TCC1_WO4 _UINT32_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UINT32_(1) << 10) + +#define PIN_PA20F_TCC1_WO4 _UINT32_(20) +#define MUX_PA20F_TCC1_WO4 _UINT32_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UINT32_(1) << 20) + +#define PIN_PB28F_TCC1_WO4 _UINT32_(60) +#define MUX_PB28F_TCC1_WO4 _UINT32_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UINT32_(1) << 28) + +#define PIN_PA09G_TCC1_WO5 _UINT32_(9) +#define MUX_PA09G_TCC1_WO5 _UINT32_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UINT32_(1) << 9) + +#define PIN_PC11G_TCC1_WO5 _UINT32_(75) +#define MUX_PC11G_TCC1_WO5 _UINT32_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UINT32_(1) << 11) + +#define PIN_PA21F_TCC1_WO5 _UINT32_(21) +#define MUX_PA21F_TCC1_WO5 _UINT32_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UINT32_(1) << 21) + +#define PIN_PB29F_TCC1_WO5 _UINT32_(61) +#define MUX_PB29F_TCC1_WO5 _UINT32_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UINT32_(1) << 29) + +#define PIN_PA10G_TCC1_WO6 _UINT32_(10) +#define MUX_PA10G_TCC1_WO6 _UINT32_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UINT32_(1) << 10) + +#define PIN_PC12G_TCC1_WO6 _UINT32_(76) +#define MUX_PC12G_TCC1_WO6 _UINT32_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UINT32_(1) << 12) + +#define PIN_PA22F_TCC1_WO6 _UINT32_(22) +#define MUX_PA22F_TCC1_WO6 _UINT32_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UINT32_(1) << 22) + +#define PIN_PA11G_TCC1_WO7 _UINT32_(11) +#define MUX_PA11G_TCC1_WO7 _UINT32_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UINT32_(1) << 11) + +#define PIN_PC13G_TCC1_WO7 _UINT32_(77) +#define MUX_PC13G_TCC1_WO7 _UINT32_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UINT32_(1) << 13) + +#define PIN_PA23F_TCC1_WO7 _UINT32_(23) +#define MUX_PA23F_TCC1_WO7 _UINT32_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UINT32_(1) << 23) + +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _UINT32_(14) +#define MUX_PA14F_TCC2_WO0 _UINT32_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UINT32_(1) << 14) + +#define PIN_PA30F_TCC2_WO0 _UINT32_(30) +#define MUX_PA30F_TCC2_WO0 _UINT32_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UINT32_(1) << 30) + +#define PIN_PA15F_TCC2_WO1 _UINT32_(15) +#define MUX_PA15F_TCC2_WO1 _UINT32_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UINT32_(1) << 15) + +#define PIN_PA31F_TCC2_WO1 _UINT32_(31) +#define MUX_PA31F_TCC2_WO1 _UINT32_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UINT32_(1) << 31) + +#define PIN_PA24F_TCC2_WO2 _UINT32_(24) +#define MUX_PA24F_TCC2_WO2 _UINT32_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UINT32_(1) << 24) + +#define PIN_PB02F_TCC2_WO2 _UINT32_(34) +#define MUX_PB02F_TCC2_WO2 _UINT32_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UINT32_(1) << 2) + +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _UINT32_(44) +#define MUX_PB12F_TCC3_WO0 _UINT32_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UINT32_(1) << 12) + +#define PIN_PB16F_TCC3_WO0 _UINT32_(48) +#define MUX_PB16F_TCC3_WO0 _UINT32_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UINT32_(1) << 16) + +#define PIN_PB13F_TCC3_WO1 _UINT32_(45) +#define MUX_PB13F_TCC3_WO1 _UINT32_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UINT32_(1) << 13) + +#define PIN_PB17F_TCC3_WO1 _UINT32_(49) +#define MUX_PB17F_TCC3_WO1 _UINT32_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _UINT32_(46) +#define MUX_PB14F_TCC4_WO0 _UINT32_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UINT32_(1) << 14) + +#define PIN_PB30F_TCC4_WO0 _UINT32_(62) +#define MUX_PB30F_TCC4_WO0 _UINT32_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UINT32_(1) << 30) + +#define PIN_PB15F_TCC4_WO1 _UINT32_(47) +#define MUX_PB15F_TCC4_WO1 _UINT32_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UINT32_(1) << 15) + +#define PIN_PB31F_TCC4_WO1 _UINT32_(63) +#define MUX_PB31F_TCC4_WO1 _UINT32_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UINT32_(1) << 31) + +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _UINT32_(24) +#define MUX_PA24H_USB_DM _UINT32_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UINT32_(1) << 24) + +#define PIN_PA25H_USB_DP _UINT32_(25) +#define MUX_PA25H_USB_DP _UINT32_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UINT32_(1) << 25) + +#define PIN_PA23H_USB_SOF_1KHZ _UINT32_(23) +#define MUX_PA23H_USB_SOF_1KHZ _UINT32_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UINT32_(1) << 23) + +#define PIN_PB22H_USB_SOF_1KHZ _UINT32_(54) +#define MUX_PB22H_USB_SOF_1KHZ _UINT32_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UINT32_(1) << 22) + +/* ========== PORT definition for TPIU peripheral ========== */ +#define PIN_PC27H_TPIU_TRACECLK _UINT32_(91) +#define MUX_PC27H_TPIU_TRACECLK _UINT32_(7) +#define PINMUX_PC27H_TPIU_TRACECLK ((PIN_PC27H_TPIU_TRACECLK << 16) | MUX_PC27H_TPIU_TRACECLK) +#define PORT_PC27H_TPIU_TRACECLK (_UINT32_(1) << 27) + +#define PIN_PC28H_TPIU_TRACED0 _UINT32_(92) +#define MUX_PC28H_TPIU_TRACED0 _UINT32_(7) +#define PINMUX_PC28H_TPIU_TRACED0 ((PIN_PC28H_TPIU_TRACED0 << 16) | MUX_PC28H_TPIU_TRACED0) +#define PORT_PC28H_TPIU_TRACED0 (_UINT32_(1) << 28) + +#define PIN_PC26H_TPIU_TRACED1 _UINT32_(90) +#define MUX_PC26H_TPIU_TRACED1 _UINT32_(7) +#define PINMUX_PC26H_TPIU_TRACED1 ((PIN_PC26H_TPIU_TRACED1 << 16) | MUX_PC26H_TPIU_TRACED1) +#define PORT_PC26H_TPIU_TRACED1 (_UINT32_(1) << 26) + +#define PIN_PC25H_TPIU_TRACED2 _UINT32_(89) +#define MUX_PC25H_TPIU_TRACED2 _UINT32_(7) +#define PINMUX_PC25H_TPIU_TRACED2 ((PIN_PC25H_TPIU_TRACED2 << 16) | MUX_PC25H_TPIU_TRACED2) +#define PORT_PC25H_TPIU_TRACED2 (_UINT32_(1) << 25) + +#define PIN_PC24H_TPIU_TRACED3 _UINT32_(88) +#define MUX_PC24H_TPIU_TRACED3 _UINT32_(7) +#define PINMUX_PC24H_TPIU_TRACED3 ((PIN_PC24H_TPIU_TRACED3 << 16) | MUX_PC24H_TPIU_TRACED3) +#define PORT_PC24H_TPIU_TRACED3 (_UINT32_(1) << 24) + + + +#endif /* _SAME54P19A_GPIO_H_ */ + diff --git a/os/common/ext/Microchip/SAME54/pio/same54p20a.h b/os/common/ext/Microchip/SAME54/pio/same54p20a.h new file mode 100644 index 0000000000..b8cb8388b1 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/pio/same54p20a.h @@ -0,0 +1,3651 @@ +/* + * Peripheral I/O description for SAME54P20A + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* file generated from device description file (ATDF) version 2023-03-17T09:50:08Z */ +#ifndef _SAME54P20A_GPIO_H_ +#define _SAME54P20A_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA00 ( 0) /**< Pin Number for PA00 */ +#define PIN_PA01 ( 1) /**< Pin Number for PA01 */ +#define PIN_PA02 ( 2) /**< Pin Number for PA02 */ +#define PIN_PA03 ( 3) /**< Pin Number for PA03 */ +#define PIN_PA04 ( 4) /**< Pin Number for PA04 */ +#define PIN_PA05 ( 5) /**< Pin Number for PA05 */ +#define PIN_PA06 ( 6) /**< Pin Number for PA06 */ +#define PIN_PA07 ( 7) /**< Pin Number for PA07 */ +#define PIN_PA08 ( 8) /**< Pin Number for PA08 */ +#define PIN_PA09 ( 9) /**< Pin Number for PA09 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB00 ( 32) /**< Pin Number for PB00 */ +#define PIN_PB01 ( 33) /**< Pin Number for PB01 */ +#define PIN_PB02 ( 34) /**< Pin Number for PB02 */ +#define PIN_PB03 ( 35) /**< Pin Number for PB03 */ +#define PIN_PB04 ( 36) /**< Pin Number for PB04 */ +#define PIN_PB05 ( 37) /**< Pin Number for PB05 */ +#define PIN_PB06 ( 38) /**< Pin Number for PB06 */ +#define PIN_PB07 ( 39) /**< Pin Number for PB07 */ +#define PIN_PB08 ( 40) /**< Pin Number for PB08 */ +#define PIN_PB09 ( 41) /**< Pin Number for PB09 */ +#define PIN_PB10 ( 42) /**< Pin Number for PB10 */ +#define PIN_PB11 ( 43) /**< Pin Number for PB11 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PB14 ( 46) /**< Pin Number for PB14 */ +#define PIN_PB15 ( 47) /**< Pin Number for PB15 */ +#define PIN_PB16 ( 48) /**< Pin Number for PB16 */ +#define PIN_PB17 ( 49) /**< Pin Number for PB17 */ +#define PIN_PB18 ( 50) /**< Pin Number for PB18 */ +#define PIN_PB19 ( 51) /**< Pin Number for PB19 */ +#define PIN_PB20 ( 52) /**< Pin Number for PB20 */ +#define PIN_PB21 ( 53) /**< Pin Number for PB21 */ +#define PIN_PB22 ( 54) /**< Pin Number for PB22 */ +#define PIN_PB23 ( 55) /**< Pin Number for PB23 */ +#define PIN_PB24 ( 56) /**< Pin Number for PB24 */ +#define PIN_PB25 ( 57) /**< Pin Number for PB25 */ +#define PIN_PB26 ( 58) /**< Pin Number for PB26 */ +#define PIN_PB27 ( 59) /**< Pin Number for PB27 */ +#define PIN_PB28 ( 60) /**< Pin Number for PB28 */ +#define PIN_PB29 ( 61) /**< Pin Number for PB29 */ +#define PIN_PB30 ( 62) /**< Pin Number for PB30 */ +#define PIN_PB31 ( 63) /**< Pin Number for PB31 */ +#define PIN_PC00 ( 64) /**< Pin Number for PC00 */ +#define PIN_PC01 ( 65) /**< Pin Number for PC01 */ +#define PIN_PC02 ( 66) /**< Pin Number for PC02 */ +#define PIN_PC03 ( 67) /**< Pin Number for PC03 */ +#define PIN_PC04 ( 68) /**< Pin Number for PC04 */ +#define PIN_PC05 ( 69) /**< Pin Number for PC05 */ +#define PIN_PC06 ( 70) /**< Pin Number for PC06 */ +#define PIN_PC07 ( 71) /**< Pin Number for PC07 */ +#define PIN_PC10 ( 74) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85) /**< Pin Number for PC21 */ +#define PIN_PC22 ( 86) /**< Pin Number for PC22 */ +#define PIN_PC23 ( 87) /**< Pin Number for PC23 */ +#define PIN_PC24 ( 88) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92) /**< Pin Number for PC28 */ +#define PIN_PC30 ( 94) /**< Pin Number for PC30 */ +#define PIN_PC31 ( 95) /**< Pin Number for PC31 */ +#define PIN_PD00 ( 96) /**< Pin Number for PD00 */ +#define PIN_PD01 ( 97) /**< Pin Number for PD01 */ +#define PIN_PD08 ( 104) /**< Pin Number for PD08 */ +#define PIN_PD09 ( 105) /**< Pin Number for PD09 */ +#define PIN_PD10 ( 106) /**< Pin Number for PD10 */ +#define PIN_PD11 ( 107) /**< Pin Number for PD11 */ +#define PIN_PD12 ( 108) /**< Pin Number for PD12 */ +#define PIN_PD20 ( 116) /**< Pin Number for PD20 */ +#define PIN_PD21 ( 117) /**< Pin Number for PD21 */ + +/* ========== Peripheral I/O masks ========== */ +#define PORT_PA00 (_UINT32_(1) << 0) /**< PORT mask for PA00 */ +#define PORT_PA01 (_UINT32_(1) << 1) /**< PORT mask for PA01 */ +#define PORT_PA02 (_UINT32_(1) << 2) /**< PORT mask for PA02 */ +#define PORT_PA03 (_UINT32_(1) << 3) /**< PORT mask for PA03 */ +#define PORT_PA04 (_UINT32_(1) << 4) /**< PORT mask for PA04 */ +#define PORT_PA05 (_UINT32_(1) << 5) /**< PORT mask for PA05 */ +#define PORT_PA06 (_UINT32_(1) << 6) /**< PORT mask for PA06 */ +#define PORT_PA07 (_UINT32_(1) << 7) /**< PORT mask for PA07 */ +#define PORT_PA08 (_UINT32_(1) << 8) /**< PORT mask for PA08 */ +#define PORT_PA09 (_UINT32_(1) << 9) /**< PORT mask for PA09 */ +#define PORT_PA10 (_UINT32_(1) << 10) /**< PORT mask for PA10 */ +#define PORT_PA11 (_UINT32_(1) << 11) /**< PORT mask for PA11 */ +#define PORT_PA12 (_UINT32_(1) << 12) /**< PORT mask for PA12 */ +#define PORT_PA13 (_UINT32_(1) << 13) /**< PORT mask for PA13 */ +#define PORT_PA14 (_UINT32_(1) << 14) /**< PORT mask for PA14 */ +#define PORT_PA15 (_UINT32_(1) << 15) /**< PORT mask for PA15 */ +#define PORT_PA16 (_UINT32_(1) << 16) /**< PORT mask for PA16 */ +#define PORT_PA17 (_UINT32_(1) << 17) /**< PORT mask for PA17 */ +#define PORT_PA18 (_UINT32_(1) << 18) /**< PORT mask for PA18 */ +#define PORT_PA19 (_UINT32_(1) << 19) /**< PORT mask for PA19 */ +#define PORT_PA20 (_UINT32_(1) << 20) /**< PORT mask for PA20 */ +#define PORT_PA21 (_UINT32_(1) << 21) /**< PORT mask for PA21 */ +#define PORT_PA22 (_UINT32_(1) << 22) /**< PORT mask for PA22 */ +#define PORT_PA23 (_UINT32_(1) << 23) /**< PORT mask for PA23 */ +#define PORT_PA24 (_UINT32_(1) << 24) /**< PORT mask for PA24 */ +#define PORT_PA25 (_UINT32_(1) << 25) /**< PORT mask for PA25 */ +#define PORT_PA27 (_UINT32_(1) << 27) /**< PORT mask for PA27 */ +#define PORT_PA30 (_UINT32_(1) << 30) /**< PORT mask for PA30 */ +#define PORT_PA31 (_UINT32_(1) << 31) /**< PORT mask for PA31 */ +#define PORT_PB00 (_UINT32_(1) << 0) /**< PORT mask for PB00 */ +#define PORT_PB01 (_UINT32_(1) << 1) /**< PORT mask for PB01 */ +#define PORT_PB02 (_UINT32_(1) << 2) /**< PORT mask for PB02 */ +#define PORT_PB03 (_UINT32_(1) << 3) /**< PORT mask for PB03 */ +#define PORT_PB04 (_UINT32_(1) << 4) /**< PORT mask for PB04 */ +#define PORT_PB05 (_UINT32_(1) << 5) /**< PORT mask for PB05 */ +#define PORT_PB06 (_UINT32_(1) << 6) /**< PORT mask for PB06 */ +#define PORT_PB07 (_UINT32_(1) << 7) /**< PORT mask for PB07 */ +#define PORT_PB08 (_UINT32_(1) << 8) /**< PORT mask for PB08 */ +#define PORT_PB09 (_UINT32_(1) << 9) /**< PORT mask for PB09 */ +#define PORT_PB10 (_UINT32_(1) << 10) /**< PORT mask for PB10 */ +#define PORT_PB11 (_UINT32_(1) << 11) /**< PORT mask for PB11 */ +#define PORT_PB12 (_UINT32_(1) << 12) /**< PORT mask for PB12 */ +#define PORT_PB13 (_UINT32_(1) << 13) /**< PORT mask for PB13 */ +#define PORT_PB14 (_UINT32_(1) << 14) /**< PORT mask for PB14 */ +#define PORT_PB15 (_UINT32_(1) << 15) /**< PORT mask for PB15 */ +#define PORT_PB16 (_UINT32_(1) << 16) /**< PORT mask for PB16 */ +#define PORT_PB17 (_UINT32_(1) << 17) /**< PORT mask for PB17 */ +#define PORT_PB18 (_UINT32_(1) << 18) /**< PORT mask for PB18 */ +#define PORT_PB19 (_UINT32_(1) << 19) /**< PORT mask for PB19 */ +#define PORT_PB20 (_UINT32_(1) << 20) /**< PORT mask for PB20 */ +#define PORT_PB21 (_UINT32_(1) << 21) /**< PORT mask for PB21 */ +#define PORT_PB22 (_UINT32_(1) << 22) /**< PORT mask for PB22 */ +#define PORT_PB23 (_UINT32_(1) << 23) /**< PORT mask for PB23 */ +#define PORT_PB24 (_UINT32_(1) << 24) /**< PORT mask for PB24 */ +#define PORT_PB25 (_UINT32_(1) << 25) /**< PORT mask for PB25 */ +#define PORT_PB26 (_UINT32_(1) << 26) /**< PORT mask for PB26 */ +#define PORT_PB27 (_UINT32_(1) << 27) /**< PORT mask for PB27 */ +#define PORT_PB28 (_UINT32_(1) << 28) /**< PORT mask for PB28 */ +#define PORT_PB29 (_UINT32_(1) << 29) /**< PORT mask for PB29 */ +#define PORT_PB30 (_UINT32_(1) << 30) /**< PORT mask for PB30 */ +#define PORT_PB31 (_UINT32_(1) << 31) /**< PORT mask for PB31 */ +#define PORT_PC00 (_UINT32_(1) << 0) /**< PORT mask for PC00 */ +#define PORT_PC01 (_UINT32_(1) << 1) /**< PORT mask for PC01 */ +#define PORT_PC02 (_UINT32_(1) << 2) /**< PORT mask for PC02 */ +#define PORT_PC03 (_UINT32_(1) << 3) /**< PORT mask for PC03 */ +#define PORT_PC04 (_UINT32_(1) << 4) /**< PORT mask for PC04 */ +#define PORT_PC05 (_UINT32_(1) << 5) /**< PORT mask for PC05 */ +#define PORT_PC06 (_UINT32_(1) << 6) /**< PORT mask for PC06 */ +#define PORT_PC07 (_UINT32_(1) << 7) /**< PORT mask for PC07 */ +#define PORT_PC10 (_UINT32_(1) << 10) /**< PORT mask for PC10 */ +#define PORT_PC11 (_UINT32_(1) << 11) /**< PORT mask for PC11 */ +#define PORT_PC12 (_UINT32_(1) << 12) /**< PORT mask for PC12 */ +#define PORT_PC13 (_UINT32_(1) << 13) /**< PORT mask for PC13 */ +#define PORT_PC14 (_UINT32_(1) << 14) /**< PORT mask for PC14 */ +#define PORT_PC15 (_UINT32_(1) << 15) /**< PORT mask for PC15 */ +#define PORT_PC16 (_UINT32_(1) << 16) /**< PORT mask for PC16 */ +#define PORT_PC17 (_UINT32_(1) << 17) /**< PORT mask for PC17 */ +#define PORT_PC18 (_UINT32_(1) << 18) /**< PORT mask for PC18 */ +#define PORT_PC19 (_UINT32_(1) << 19) /**< PORT mask for PC19 */ +#define PORT_PC20 (_UINT32_(1) << 20) /**< PORT mask for PC20 */ +#define PORT_PC21 (_UINT32_(1) << 21) /**< PORT mask for PC21 */ +#define PORT_PC22 (_UINT32_(1) << 22) /**< PORT mask for PC22 */ +#define PORT_PC23 (_UINT32_(1) << 23) /**< PORT mask for PC23 */ +#define PORT_PC24 (_UINT32_(1) << 24) /**< PORT mask for PC24 */ +#define PORT_PC25 (_UINT32_(1) << 25) /**< PORT mask for PC25 */ +#define PORT_PC26 (_UINT32_(1) << 26) /**< PORT mask for PC26 */ +#define PORT_PC27 (_UINT32_(1) << 27) /**< PORT mask for PC27 */ +#define PORT_PC28 (_UINT32_(1) << 28) /**< PORT mask for PC28 */ +#define PORT_PC30 (_UINT32_(1) << 30) /**< PORT mask for PC30 */ +#define PORT_PC31 (_UINT32_(1) << 31) /**< PORT mask for PC31 */ +#define PORT_PD00 (_UINT32_(1) << 0) /**< PORT mask for PD00 */ +#define PORT_PD01 (_UINT32_(1) << 1) /**< PORT mask for PD01 */ +#define PORT_PD08 (_UINT32_(1) << 8) /**< PORT mask for PD08 */ +#define PORT_PD09 (_UINT32_(1) << 9) /**< PORT mask for PD09 */ +#define PORT_PD10 (_UINT32_(1) << 10) /**< PORT mask for PD10 */ +#define PORT_PD11 (_UINT32_(1) << 11) /**< PORT mask for PD11 */ +#define PORT_PD12 (_UINT32_(1) << 12) /**< PORT mask for PD12 */ +#define PORT_PD20 (_UINT32_(1) << 20) /**< PORT mask for PD20 */ +#define PORT_PD21 (_UINT32_(1) << 21) /**< PORT mask for PD21 */ + +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _UINT32_(4) +#define MUX_PA04B_AC_AIN0 _UINT32_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UINT32_(1) << 4) + +#define PIN_PA05B_AC_AIN1 _UINT32_(5) +#define MUX_PA05B_AC_AIN1 _UINT32_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UINT32_(1) << 5) + +#define PIN_PA06B_AC_AIN2 _UINT32_(6) +#define MUX_PA06B_AC_AIN2 _UINT32_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UINT32_(1) << 6) + +#define PIN_PA07B_AC_AIN3 _UINT32_(7) +#define MUX_PA07B_AC_AIN3 _UINT32_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UINT32_(1) << 7) + +#define PIN_PA12M_AC_CMP0 _UINT32_(12) +#define MUX_PA12M_AC_CMP0 _UINT32_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UINT32_(1) << 12) + +#define PIN_PA18M_AC_CMP0 _UINT32_(18) +#define MUX_PA18M_AC_CMP0 _UINT32_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UINT32_(1) << 18) + +#define PIN_PB24M_AC_CMP0 _UINT32_(56) +#define MUX_PB24M_AC_CMP0 _UINT32_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UINT32_(1) << 24) + +#define PIN_PA13M_AC_CMP1 _UINT32_(13) +#define MUX_PA13M_AC_CMP1 _UINT32_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UINT32_(1) << 13) + +#define PIN_PA19M_AC_CMP1 _UINT32_(19) +#define MUX_PA19M_AC_CMP1 _UINT32_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UINT32_(1) << 19) + +#define PIN_PB25M_AC_CMP1 _UINT32_(57) +#define MUX_PB25M_AC_CMP1 _UINT32_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UINT32_(1) << 25) + +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _UINT32_(2) +#define MUX_PA02B_ADC0_AIN0 _UINT32_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UINT32_(1) << 2) + +#define PIN_PA03B_ADC0_AIN1 _UINT32_(3) +#define MUX_PA03B_ADC0_AIN1 _UINT32_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_AIN2 _UINT32_(40) +#define MUX_PB08B_ADC0_AIN2 _UINT32_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_AIN3 _UINT32_(41) +#define MUX_PB09B_ADC0_AIN3 _UINT32_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_AIN4 _UINT32_(4) +#define MUX_PA04B_ADC0_AIN4 _UINT32_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UINT32_(1) << 4) + +#define PIN_PA05B_ADC0_AIN5 _UINT32_(5) +#define MUX_PA05B_ADC0_AIN5 _UINT32_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UINT32_(1) << 5) + +#define PIN_PA06B_ADC0_AIN6 _UINT32_(6) +#define MUX_PA06B_ADC0_AIN6 _UINT32_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_AIN7 _UINT32_(7) +#define MUX_PA07B_ADC0_AIN7 _UINT32_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_AIN8 _UINT32_(8) +#define MUX_PA08B_ADC0_AIN8 _UINT32_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_AIN9 _UINT32_(9) +#define MUX_PA09B_ADC0_AIN9 _UINT32_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_AIN10 _UINT32_(10) +#define MUX_PA10B_ADC0_AIN10 _UINT32_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_AIN11 _UINT32_(11) +#define MUX_PA11B_ADC0_AIN11 _UINT32_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UINT32_(1) << 11) + +#define PIN_PB00B_ADC0_AIN12 _UINT32_(32) +#define MUX_PB00B_ADC0_AIN12 _UINT32_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_AIN13 _UINT32_(33) +#define MUX_PB01B_ADC0_AIN13 _UINT32_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UINT32_(1) << 1) + +#define PIN_PB02B_ADC0_AIN14 _UINT32_(34) +#define MUX_PB02B_ADC0_AIN14 _UINT32_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_AIN15 _UINT32_(35) +#define MUX_PB03B_ADC0_AIN15 _UINT32_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UINT32_(1) << 3) + +#define PIN_PA03B_ADC0_VREFA _UINT32_(3) +#define MUX_PA03B_ADC0_VREFA _UINT32_(1) +#define PINMUX_PA03B_ADC0_VREFA ((PIN_PA03B_ADC0_VREFA << 16) | MUX_PA03B_ADC0_VREFA) +#define PORT_PA03B_ADC0_VREFA (_UINT32_(1) << 3) + +#define PIN_PA04B_ADC0_VREFB _UINT32_(4) +#define MUX_PA04B_ADC0_VREFB _UINT32_(1) +#define PINMUX_PA04B_ADC0_VREFB ((PIN_PA04B_ADC0_VREFB << 16) | MUX_PA04B_ADC0_VREFB) +#define PORT_PA04B_ADC0_VREFB (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_VREFC _UINT32_(6) +#define MUX_PA06B_ADC0_VREFC _UINT32_(1) +#define PINMUX_PA06B_ADC0_VREFC ((PIN_PA06B_ADC0_VREFC << 16) | MUX_PA06B_ADC0_VREFC) +#define PORT_PA06B_ADC0_VREFC (_UINT32_(1) << 6) + +#define PIN_PA03B_ADC0_X0 _UINT32_(3) +#define MUX_PA03B_ADC0_X0 _UINT32_(1) +#define PINMUX_PA03B_ADC0_X0 ((PIN_PA03B_ADC0_X0 << 16) | MUX_PA03B_ADC0_X0) +#define PORT_PA03B_ADC0_X0 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_X1 _UINT32_(40) +#define MUX_PB08B_ADC0_X1 _UINT32_(1) +#define PINMUX_PB08B_ADC0_X1 ((PIN_PB08B_ADC0_X1 << 16) | MUX_PB08B_ADC0_X1) +#define PORT_PB08B_ADC0_X1 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_X2 _UINT32_(41) +#define MUX_PB09B_ADC0_X2 _UINT32_(1) +#define PINMUX_PB09B_ADC0_X2 ((PIN_PB09B_ADC0_X2 << 16) | MUX_PB09B_ADC0_X2) +#define PORT_PB09B_ADC0_X2 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_X3 _UINT32_(4) +#define MUX_PA04B_ADC0_X3 _UINT32_(1) +#define PINMUX_PA04B_ADC0_X3 ((PIN_PA04B_ADC0_X3 << 16) | MUX_PA04B_ADC0_X3) +#define PORT_PA04B_ADC0_X3 (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_X4 _UINT32_(6) +#define MUX_PA06B_ADC0_X4 _UINT32_(1) +#define PINMUX_PA06B_ADC0_X4 ((PIN_PA06B_ADC0_X4 << 16) | MUX_PA06B_ADC0_X4) +#define PORT_PA06B_ADC0_X4 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_X5 _UINT32_(7) +#define MUX_PA07B_ADC0_X5 _UINT32_(1) +#define PINMUX_PA07B_ADC0_X5 ((PIN_PA07B_ADC0_X5 << 16) | MUX_PA07B_ADC0_X5) +#define PORT_PA07B_ADC0_X5 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_X6 _UINT32_(8) +#define MUX_PA08B_ADC0_X6 _UINT32_(1) +#define PINMUX_PA08B_ADC0_X6 ((PIN_PA08B_ADC0_X6 << 16) | MUX_PA08B_ADC0_X6) +#define PORT_PA08B_ADC0_X6 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_X7 _UINT32_(9) +#define MUX_PA09B_ADC0_X7 _UINT32_(1) +#define PINMUX_PA09B_ADC0_X7 ((PIN_PA09B_ADC0_X7 << 16) | MUX_PA09B_ADC0_X7) +#define PORT_PA09B_ADC0_X7 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_X8 _UINT32_(10) +#define MUX_PA10B_ADC0_X8 _UINT32_(1) +#define PINMUX_PA10B_ADC0_X8 ((PIN_PA10B_ADC0_X8 << 16) | MUX_PA10B_ADC0_X8) +#define PORT_PA10B_ADC0_X8 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_X9 _UINT32_(11) +#define MUX_PA11B_ADC0_X9 _UINT32_(1) +#define PINMUX_PA11B_ADC0_X9 ((PIN_PA11B_ADC0_X9 << 16) | MUX_PA11B_ADC0_X9) +#define PORT_PA11B_ADC0_X9 (_UINT32_(1) << 11) + +#define PIN_PA16B_ADC0_X10 _UINT32_(16) +#define MUX_PA16B_ADC0_X10 _UINT32_(1) +#define PINMUX_PA16B_ADC0_X10 ((PIN_PA16B_ADC0_X10 << 16) | MUX_PA16B_ADC0_X10) +#define PORT_PA16B_ADC0_X10 (_UINT32_(1) << 16) + +#define PIN_PA17B_ADC0_X11 _UINT32_(17) +#define MUX_PA17B_ADC0_X11 _UINT32_(1) +#define PINMUX_PA17B_ADC0_X11 ((PIN_PA17B_ADC0_X11 << 16) | MUX_PA17B_ADC0_X11) +#define PORT_PA17B_ADC0_X11 (_UINT32_(1) << 17) + +#define PIN_PA18B_ADC0_X12 _UINT32_(18) +#define MUX_PA18B_ADC0_X12 _UINT32_(1) +#define PINMUX_PA18B_ADC0_X12 ((PIN_PA18B_ADC0_X12 << 16) | MUX_PA18B_ADC0_X12) +#define PORT_PA18B_ADC0_X12 (_UINT32_(1) << 18) + +#define PIN_PA19B_ADC0_X13 _UINT32_(19) +#define MUX_PA19B_ADC0_X13 _UINT32_(1) +#define PINMUX_PA19B_ADC0_X13 ((PIN_PA19B_ADC0_X13 << 16) | MUX_PA19B_ADC0_X13) +#define PORT_PA19B_ADC0_X13 (_UINT32_(1) << 19) + +#define PIN_PA20B_ADC0_X14 _UINT32_(20) +#define MUX_PA20B_ADC0_X14 _UINT32_(1) +#define PINMUX_PA20B_ADC0_X14 ((PIN_PA20B_ADC0_X14 << 16) | MUX_PA20B_ADC0_X14) +#define PORT_PA20B_ADC0_X14 (_UINT32_(1) << 20) + +#define PIN_PA21B_ADC0_X15 _UINT32_(21) +#define MUX_PA21B_ADC0_X15 _UINT32_(1) +#define PINMUX_PA21B_ADC0_X15 ((PIN_PA21B_ADC0_X15 << 16) | MUX_PA21B_ADC0_X15) +#define PORT_PA21B_ADC0_X15 (_UINT32_(1) << 21) + +#define PIN_PA22B_ADC0_X16 _UINT32_(22) +#define MUX_PA22B_ADC0_X16 _UINT32_(1) +#define PINMUX_PA22B_ADC0_X16 ((PIN_PA22B_ADC0_X16 << 16) | MUX_PA22B_ADC0_X16) +#define PORT_PA22B_ADC0_X16 (_UINT32_(1) << 22) + +#define PIN_PA23B_ADC0_X17 _UINT32_(23) +#define MUX_PA23B_ADC0_X17 _UINT32_(1) +#define PINMUX_PA23B_ADC0_X17 ((PIN_PA23B_ADC0_X17 << 16) | MUX_PA23B_ADC0_X17) +#define PORT_PA23B_ADC0_X17 (_UINT32_(1) << 23) + +#define PIN_PA27B_ADC0_X18 _UINT32_(27) +#define MUX_PA27B_ADC0_X18 _UINT32_(1) +#define PINMUX_PA27B_ADC0_X18 ((PIN_PA27B_ADC0_X18 << 16) | MUX_PA27B_ADC0_X18) +#define PORT_PA27B_ADC0_X18 (_UINT32_(1) << 27) + +#define PIN_PA30B_ADC0_X19 _UINT32_(30) +#define MUX_PA30B_ADC0_X19 _UINT32_(1) +#define PINMUX_PA30B_ADC0_X19 ((PIN_PA30B_ADC0_X19 << 16) | MUX_PA30B_ADC0_X19) +#define PORT_PA30B_ADC0_X19 (_UINT32_(1) << 30) + +#define PIN_PB02B_ADC0_X20 _UINT32_(34) +#define MUX_PB02B_ADC0_X20 _UINT32_(1) +#define PINMUX_PB02B_ADC0_X20 ((PIN_PB02B_ADC0_X20 << 16) | MUX_PB02B_ADC0_X20) +#define PORT_PB02B_ADC0_X20 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_X21 _UINT32_(35) +#define MUX_PB03B_ADC0_X21 _UINT32_(1) +#define PINMUX_PB03B_ADC0_X21 ((PIN_PB03B_ADC0_X21 << 16) | MUX_PB03B_ADC0_X21) +#define PORT_PB03B_ADC0_X21 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC0_X22 _UINT32_(36) +#define MUX_PB04B_ADC0_X22 _UINT32_(1) +#define PINMUX_PB04B_ADC0_X22 ((PIN_PB04B_ADC0_X22 << 16) | MUX_PB04B_ADC0_X22) +#define PORT_PB04B_ADC0_X22 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC0_X23 _UINT32_(37) +#define MUX_PB05B_ADC0_X23 _UINT32_(1) +#define PINMUX_PB05B_ADC0_X23 ((PIN_PB05B_ADC0_X23 << 16) | MUX_PB05B_ADC0_X23) +#define PORT_PB05B_ADC0_X23 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC0_X24 _UINT32_(38) +#define MUX_PB06B_ADC0_X24 _UINT32_(1) +#define PINMUX_PB06B_ADC0_X24 ((PIN_PB06B_ADC0_X24 << 16) | MUX_PB06B_ADC0_X24) +#define PORT_PB06B_ADC0_X24 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC0_X25 _UINT32_(39) +#define MUX_PB07B_ADC0_X25 _UINT32_(1) +#define PINMUX_PB07B_ADC0_X25 ((PIN_PB07B_ADC0_X25 << 16) | MUX_PB07B_ADC0_X25) +#define PORT_PB07B_ADC0_X25 (_UINT32_(1) << 7) + +#define PIN_PB12B_ADC0_X26 _UINT32_(44) +#define MUX_PB12B_ADC0_X26 _UINT32_(1) +#define PINMUX_PB12B_ADC0_X26 ((PIN_PB12B_ADC0_X26 << 16) | MUX_PB12B_ADC0_X26) +#define PORT_PB12B_ADC0_X26 (_UINT32_(1) << 12) + +#define PIN_PB13B_ADC0_X27 _UINT32_(45) +#define MUX_PB13B_ADC0_X27 _UINT32_(1) +#define PINMUX_PB13B_ADC0_X27 ((PIN_PB13B_ADC0_X27 << 16) | MUX_PB13B_ADC0_X27) +#define PORT_PB13B_ADC0_X27 (_UINT32_(1) << 13) + +#define PIN_PB14B_ADC0_X28 _UINT32_(46) +#define MUX_PB14B_ADC0_X28 _UINT32_(1) +#define PINMUX_PB14B_ADC0_X28 ((PIN_PB14B_ADC0_X28 << 16) | MUX_PB14B_ADC0_X28) +#define PORT_PB14B_ADC0_X28 (_UINT32_(1) << 14) + +#define PIN_PB15B_ADC0_X29 _UINT32_(47) +#define MUX_PB15B_ADC0_X29 _UINT32_(1) +#define PINMUX_PB15B_ADC0_X29 ((PIN_PB15B_ADC0_X29 << 16) | MUX_PB15B_ADC0_X29) +#define PORT_PB15B_ADC0_X29 (_UINT32_(1) << 15) + +#define PIN_PB00B_ADC0_X30 _UINT32_(32) +#define MUX_PB00B_ADC0_X30 _UINT32_(1) +#define PINMUX_PB00B_ADC0_X30 ((PIN_PB00B_ADC0_X30 << 16) | MUX_PB00B_ADC0_X30) +#define PORT_PB00B_ADC0_X30 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_X31 _UINT32_(33) +#define MUX_PB01B_ADC0_X31 _UINT32_(1) +#define PINMUX_PB01B_ADC0_X31 ((PIN_PB01B_ADC0_X31 << 16) | MUX_PB01B_ADC0_X31) +#define PORT_PB01B_ADC0_X31 (_UINT32_(1) << 1) + +#define PIN_PA03B_ADC0_Y0 _UINT32_(3) +#define MUX_PA03B_ADC0_Y0 _UINT32_(1) +#define PINMUX_PA03B_ADC0_Y0 ((PIN_PA03B_ADC0_Y0 << 16) | MUX_PA03B_ADC0_Y0) +#define PORT_PA03B_ADC0_Y0 (_UINT32_(1) << 3) + +#define PIN_PB08B_ADC0_Y1 _UINT32_(40) +#define MUX_PB08B_ADC0_Y1 _UINT32_(1) +#define PINMUX_PB08B_ADC0_Y1 ((PIN_PB08B_ADC0_Y1 << 16) | MUX_PB08B_ADC0_Y1) +#define PORT_PB08B_ADC0_Y1 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC0_Y2 _UINT32_(41) +#define MUX_PB09B_ADC0_Y2 _UINT32_(1) +#define PINMUX_PB09B_ADC0_Y2 ((PIN_PB09B_ADC0_Y2 << 16) | MUX_PB09B_ADC0_Y2) +#define PORT_PB09B_ADC0_Y2 (_UINT32_(1) << 9) + +#define PIN_PA04B_ADC0_Y3 _UINT32_(4) +#define MUX_PA04B_ADC0_Y3 _UINT32_(1) +#define PINMUX_PA04B_ADC0_Y3 ((PIN_PA04B_ADC0_Y3 << 16) | MUX_PA04B_ADC0_Y3) +#define PORT_PA04B_ADC0_Y3 (_UINT32_(1) << 4) + +#define PIN_PA06B_ADC0_Y4 _UINT32_(6) +#define MUX_PA06B_ADC0_Y4 _UINT32_(1) +#define PINMUX_PA06B_ADC0_Y4 ((PIN_PA06B_ADC0_Y4 << 16) | MUX_PA06B_ADC0_Y4) +#define PORT_PA06B_ADC0_Y4 (_UINT32_(1) << 6) + +#define PIN_PA07B_ADC0_Y5 _UINT32_(7) +#define MUX_PA07B_ADC0_Y5 _UINT32_(1) +#define PINMUX_PA07B_ADC0_Y5 ((PIN_PA07B_ADC0_Y5 << 16) | MUX_PA07B_ADC0_Y5) +#define PORT_PA07B_ADC0_Y5 (_UINT32_(1) << 7) + +#define PIN_PA08B_ADC0_Y6 _UINT32_(8) +#define MUX_PA08B_ADC0_Y6 _UINT32_(1) +#define PINMUX_PA08B_ADC0_Y6 ((PIN_PA08B_ADC0_Y6 << 16) | MUX_PA08B_ADC0_Y6) +#define PORT_PA08B_ADC0_Y6 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC0_Y7 _UINT32_(9) +#define MUX_PA09B_ADC0_Y7 _UINT32_(1) +#define PINMUX_PA09B_ADC0_Y7 ((PIN_PA09B_ADC0_Y7 << 16) | MUX_PA09B_ADC0_Y7) +#define PORT_PA09B_ADC0_Y7 (_UINT32_(1) << 9) + +#define PIN_PA10B_ADC0_Y8 _UINT32_(10) +#define MUX_PA10B_ADC0_Y8 _UINT32_(1) +#define PINMUX_PA10B_ADC0_Y8 ((PIN_PA10B_ADC0_Y8 << 16) | MUX_PA10B_ADC0_Y8) +#define PORT_PA10B_ADC0_Y8 (_UINT32_(1) << 10) + +#define PIN_PA11B_ADC0_Y9 _UINT32_(11) +#define MUX_PA11B_ADC0_Y9 _UINT32_(1) +#define PINMUX_PA11B_ADC0_Y9 ((PIN_PA11B_ADC0_Y9 << 16) | MUX_PA11B_ADC0_Y9) +#define PORT_PA11B_ADC0_Y9 (_UINT32_(1) << 11) + +#define PIN_PA16B_ADC0_Y10 _UINT32_(16) +#define MUX_PA16B_ADC0_Y10 _UINT32_(1) +#define PINMUX_PA16B_ADC0_Y10 ((PIN_PA16B_ADC0_Y10 << 16) | MUX_PA16B_ADC0_Y10) +#define PORT_PA16B_ADC0_Y10 (_UINT32_(1) << 16) + +#define PIN_PA17B_ADC0_Y11 _UINT32_(17) +#define MUX_PA17B_ADC0_Y11 _UINT32_(1) +#define PINMUX_PA17B_ADC0_Y11 ((PIN_PA17B_ADC0_Y11 << 16) | MUX_PA17B_ADC0_Y11) +#define PORT_PA17B_ADC0_Y11 (_UINT32_(1) << 17) + +#define PIN_PA18B_ADC0_Y12 _UINT32_(18) +#define MUX_PA18B_ADC0_Y12 _UINT32_(1) +#define PINMUX_PA18B_ADC0_Y12 ((PIN_PA18B_ADC0_Y12 << 16) | MUX_PA18B_ADC0_Y12) +#define PORT_PA18B_ADC0_Y12 (_UINT32_(1) << 18) + +#define PIN_PA19B_ADC0_Y13 _UINT32_(19) +#define MUX_PA19B_ADC0_Y13 _UINT32_(1) +#define PINMUX_PA19B_ADC0_Y13 ((PIN_PA19B_ADC0_Y13 << 16) | MUX_PA19B_ADC0_Y13) +#define PORT_PA19B_ADC0_Y13 (_UINT32_(1) << 19) + +#define PIN_PA20B_ADC0_Y14 _UINT32_(20) +#define MUX_PA20B_ADC0_Y14 _UINT32_(1) +#define PINMUX_PA20B_ADC0_Y14 ((PIN_PA20B_ADC0_Y14 << 16) | MUX_PA20B_ADC0_Y14) +#define PORT_PA20B_ADC0_Y14 (_UINT32_(1) << 20) + +#define PIN_PA21B_ADC0_Y15 _UINT32_(21) +#define MUX_PA21B_ADC0_Y15 _UINT32_(1) +#define PINMUX_PA21B_ADC0_Y15 ((PIN_PA21B_ADC0_Y15 << 16) | MUX_PA21B_ADC0_Y15) +#define PORT_PA21B_ADC0_Y15 (_UINT32_(1) << 21) + +#define PIN_PA22B_ADC0_Y16 _UINT32_(22) +#define MUX_PA22B_ADC0_Y16 _UINT32_(1) +#define PINMUX_PA22B_ADC0_Y16 ((PIN_PA22B_ADC0_Y16 << 16) | MUX_PA22B_ADC0_Y16) +#define PORT_PA22B_ADC0_Y16 (_UINT32_(1) << 22) + +#define PIN_PA23B_ADC0_Y17 _UINT32_(23) +#define MUX_PA23B_ADC0_Y17 _UINT32_(1) +#define PINMUX_PA23B_ADC0_Y17 ((PIN_PA23B_ADC0_Y17 << 16) | MUX_PA23B_ADC0_Y17) +#define PORT_PA23B_ADC0_Y17 (_UINT32_(1) << 23) + +#define PIN_PA27B_ADC0_Y18 _UINT32_(27) +#define MUX_PA27B_ADC0_Y18 _UINT32_(1) +#define PINMUX_PA27B_ADC0_Y18 ((PIN_PA27B_ADC0_Y18 << 16) | MUX_PA27B_ADC0_Y18) +#define PORT_PA27B_ADC0_Y18 (_UINT32_(1) << 27) + +#define PIN_PA30B_ADC0_Y19 _UINT32_(30) +#define MUX_PA30B_ADC0_Y19 _UINT32_(1) +#define PINMUX_PA30B_ADC0_Y19 ((PIN_PA30B_ADC0_Y19 << 16) | MUX_PA30B_ADC0_Y19) +#define PORT_PA30B_ADC0_Y19 (_UINT32_(1) << 30) + +#define PIN_PB02B_ADC0_Y20 _UINT32_(34) +#define MUX_PB02B_ADC0_Y20 _UINT32_(1) +#define PINMUX_PB02B_ADC0_Y20 ((PIN_PB02B_ADC0_Y20 << 16) | MUX_PB02B_ADC0_Y20) +#define PORT_PB02B_ADC0_Y20 (_UINT32_(1) << 2) + +#define PIN_PB03B_ADC0_Y21 _UINT32_(35) +#define MUX_PB03B_ADC0_Y21 _UINT32_(1) +#define PINMUX_PB03B_ADC0_Y21 ((PIN_PB03B_ADC0_Y21 << 16) | MUX_PB03B_ADC0_Y21) +#define PORT_PB03B_ADC0_Y21 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC0_Y22 _UINT32_(36) +#define MUX_PB04B_ADC0_Y22 _UINT32_(1) +#define PINMUX_PB04B_ADC0_Y22 ((PIN_PB04B_ADC0_Y22 << 16) | MUX_PB04B_ADC0_Y22) +#define PORT_PB04B_ADC0_Y22 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC0_Y23 _UINT32_(37) +#define MUX_PB05B_ADC0_Y23 _UINT32_(1) +#define PINMUX_PB05B_ADC0_Y23 ((PIN_PB05B_ADC0_Y23 << 16) | MUX_PB05B_ADC0_Y23) +#define PORT_PB05B_ADC0_Y23 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC0_Y24 _UINT32_(38) +#define MUX_PB06B_ADC0_Y24 _UINT32_(1) +#define PINMUX_PB06B_ADC0_Y24 ((PIN_PB06B_ADC0_Y24 << 16) | MUX_PB06B_ADC0_Y24) +#define PORT_PB06B_ADC0_Y24 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC0_Y25 _UINT32_(39) +#define MUX_PB07B_ADC0_Y25 _UINT32_(1) +#define PINMUX_PB07B_ADC0_Y25 ((PIN_PB07B_ADC0_Y25 << 16) | MUX_PB07B_ADC0_Y25) +#define PORT_PB07B_ADC0_Y25 (_UINT32_(1) << 7) + +#define PIN_PB12B_ADC0_Y26 _UINT32_(44) +#define MUX_PB12B_ADC0_Y26 _UINT32_(1) +#define PINMUX_PB12B_ADC0_Y26 ((PIN_PB12B_ADC0_Y26 << 16) | MUX_PB12B_ADC0_Y26) +#define PORT_PB12B_ADC0_Y26 (_UINT32_(1) << 12) + +#define PIN_PB13B_ADC0_Y27 _UINT32_(45) +#define MUX_PB13B_ADC0_Y27 _UINT32_(1) +#define PINMUX_PB13B_ADC0_Y27 ((PIN_PB13B_ADC0_Y27 << 16) | MUX_PB13B_ADC0_Y27) +#define PORT_PB13B_ADC0_Y27 (_UINT32_(1) << 13) + +#define PIN_PB14B_ADC0_Y28 _UINT32_(46) +#define MUX_PB14B_ADC0_Y28 _UINT32_(1) +#define PINMUX_PB14B_ADC0_Y28 ((PIN_PB14B_ADC0_Y28 << 16) | MUX_PB14B_ADC0_Y28) +#define PORT_PB14B_ADC0_Y28 (_UINT32_(1) << 14) + +#define PIN_PB15B_ADC0_Y29 _UINT32_(47) +#define MUX_PB15B_ADC0_Y29 _UINT32_(1) +#define PINMUX_PB15B_ADC0_Y29 ((PIN_PB15B_ADC0_Y29 << 16) | MUX_PB15B_ADC0_Y29) +#define PORT_PB15B_ADC0_Y29 (_UINT32_(1) << 15) + +#define PIN_PB00B_ADC0_Y30 _UINT32_(32) +#define MUX_PB00B_ADC0_Y30 _UINT32_(1) +#define PINMUX_PB00B_ADC0_Y30 ((PIN_PB00B_ADC0_Y30 << 16) | MUX_PB00B_ADC0_Y30) +#define PORT_PB00B_ADC0_Y30 (_UINT32_(1) << 0) + +#define PIN_PB01B_ADC0_Y31 _UINT32_(33) +#define MUX_PB01B_ADC0_Y31 _UINT32_(1) +#define PINMUX_PB01B_ADC0_Y31 ((PIN_PB01B_ADC0_Y31 << 16) | MUX_PB01B_ADC0_Y31) +#define PORT_PB01B_ADC0_Y31 (_UINT32_(1) << 1) + +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _UINT32_(40) +#define MUX_PB08B_ADC1_AIN0 _UINT32_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UINT32_(1) << 8) + +#define PIN_PB09B_ADC1_AIN1 _UINT32_(41) +#define MUX_PB09B_ADC1_AIN1 _UINT32_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UINT32_(1) << 9) + +#define PIN_PA08B_ADC1_AIN2 _UINT32_(8) +#define MUX_PA08B_ADC1_AIN2 _UINT32_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UINT32_(1) << 8) + +#define PIN_PA09B_ADC1_AIN3 _UINT32_(9) +#define MUX_PA09B_ADC1_AIN3 _UINT32_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UINT32_(1) << 9) + +#define PIN_PC02B_ADC1_AIN4 _UINT32_(66) +#define MUX_PC02B_ADC1_AIN4 _UINT32_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UINT32_(1) << 2) + +#define PIN_PC03B_ADC1_AIN5 _UINT32_(67) +#define MUX_PC03B_ADC1_AIN5 _UINT32_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UINT32_(1) << 3) + +#define PIN_PB04B_ADC1_AIN6 _UINT32_(36) +#define MUX_PB04B_ADC1_AIN6 _UINT32_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UINT32_(1) << 4) + +#define PIN_PB05B_ADC1_AIN7 _UINT32_(37) +#define MUX_PB05B_ADC1_AIN7 _UINT32_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UINT32_(1) << 5) + +#define PIN_PB06B_ADC1_AIN8 _UINT32_(38) +#define MUX_PB06B_ADC1_AIN8 _UINT32_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UINT32_(1) << 6) + +#define PIN_PB07B_ADC1_AIN9 _UINT32_(39) +#define MUX_PB07B_ADC1_AIN9 _UINT32_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UINT32_(1) << 7) + +#define PIN_PC00B_ADC1_AIN10 _UINT32_(64) +#define MUX_PC00B_ADC1_AIN10 _UINT32_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UINT32_(1) << 0) + +#define PIN_PC01B_ADC1_AIN11 _UINT32_(65) +#define MUX_PC01B_ADC1_AIN11 _UINT32_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UINT32_(1) << 1) + +#define PIN_PC30B_ADC1_AIN12 _UINT32_(94) +#define MUX_PC30B_ADC1_AIN12 _UINT32_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UINT32_(1) << 30) + +#define PIN_PC31B_ADC1_AIN13 _UINT32_(95) +#define MUX_PC31B_ADC1_AIN13 _UINT32_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UINT32_(1) << 31) + +#define PIN_PD00B_ADC1_AIN14 _UINT32_(96) +#define MUX_PD00B_ADC1_AIN14 _UINT32_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UINT32_(1) << 0) + +#define PIN_PD01B_ADC1_AIN15 _UINT32_(97) +#define MUX_PD01B_ADC1_AIN15 _UINT32_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UINT32_(1) << 1) + +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _UINT32_(23) +#define MUX_PA23I_CAN0_RX _UINT32_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UINT32_(1) << 23) + +#define PIN_PA25I_CAN0_RX _UINT32_(25) +#define MUX_PA25I_CAN0_RX _UINT32_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UINT32_(1) << 25) + +#define PIN_PA22I_CAN0_TX _UINT32_(22) +#define MUX_PA22I_CAN0_TX _UINT32_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UINT32_(1) << 22) + +#define PIN_PA24I_CAN0_TX _UINT32_(24) +#define MUX_PA24I_CAN0_TX _UINT32_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UINT32_(1) << 24) + +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _UINT32_(45) +#define MUX_PB13H_CAN1_RX _UINT32_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UINT32_(1) << 13) + +#define PIN_PB15H_CAN1_RX _UINT32_(47) +#define MUX_PB15H_CAN1_RX _UINT32_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UINT32_(1) << 15) + +#define PIN_PB12H_CAN1_TX _UINT32_(44) +#define MUX_PB12H_CAN1_TX _UINT32_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UINT32_(1) << 12) + +#define PIN_PB14H_CAN1_TX _UINT32_(46) +#define MUX_PB14H_CAN1_TX _UINT32_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UINT32_(1) << 14) + +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _UINT32_(4) +#define MUX_PA04N_CCL_IN0 _UINT32_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UINT32_(1) << 4) + +#define PIN_PA16N_CCL_IN0 _UINT32_(16) +#define MUX_PA16N_CCL_IN0 _UINT32_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UINT32_(1) << 16) + +#define PIN_PB22N_CCL_IN0 _UINT32_(54) +#define MUX_PB22N_CCL_IN0 _UINT32_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UINT32_(1) << 22) + +#define PIN_PA05N_CCL_IN1 _UINT32_(5) +#define MUX_PA05N_CCL_IN1 _UINT32_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UINT32_(1) << 5) + +#define PIN_PA17N_CCL_IN1 _UINT32_(17) +#define MUX_PA17N_CCL_IN1 _UINT32_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UINT32_(1) << 17) + +#define PIN_PB00N_CCL_IN1 _UINT32_(32) +#define MUX_PB00N_CCL_IN1 _UINT32_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UINT32_(1) << 0) + +#define PIN_PA06N_CCL_IN2 _UINT32_(6) +#define MUX_PA06N_CCL_IN2 _UINT32_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UINT32_(1) << 6) + +#define PIN_PA18N_CCL_IN2 _UINT32_(18) +#define MUX_PA18N_CCL_IN2 _UINT32_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UINT32_(1) << 18) + +#define PIN_PB01N_CCL_IN2 _UINT32_(33) +#define MUX_PB01N_CCL_IN2 _UINT32_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UINT32_(1) << 1) + +#define PIN_PA08N_CCL_IN3 _UINT32_(8) +#define MUX_PA08N_CCL_IN3 _UINT32_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UINT32_(1) << 8) + +#define PIN_PA30N_CCL_IN3 _UINT32_(30) +#define MUX_PA30N_CCL_IN3 _UINT32_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UINT32_(1) << 30) + +#define PIN_PA09N_CCL_IN4 _UINT32_(9) +#define MUX_PA09N_CCL_IN4 _UINT32_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UINT32_(1) << 9) + +#define PIN_PC27N_CCL_IN4 _UINT32_(91) +#define MUX_PC27N_CCL_IN4 _UINT32_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UINT32_(1) << 27) + +#define PIN_PA10N_CCL_IN5 _UINT32_(10) +#define MUX_PA10N_CCL_IN5 _UINT32_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UINT32_(1) << 10) + +#define PIN_PC28N_CCL_IN5 _UINT32_(92) +#define MUX_PC28N_CCL_IN5 _UINT32_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UINT32_(1) << 28) + +#define PIN_PA22N_CCL_IN6 _UINT32_(22) +#define MUX_PA22N_CCL_IN6 _UINT32_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UINT32_(1) << 22) + +#define PIN_PB06N_CCL_IN6 _UINT32_(38) +#define MUX_PB06N_CCL_IN6 _UINT32_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UINT32_(1) << 6) + +#define PIN_PA23N_CCL_IN7 _UINT32_(23) +#define MUX_PA23N_CCL_IN7 _UINT32_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UINT32_(1) << 23) + +#define PIN_PB07N_CCL_IN7 _UINT32_(39) +#define MUX_PB07N_CCL_IN7 _UINT32_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UINT32_(1) << 7) + +#define PIN_PA24N_CCL_IN8 _UINT32_(24) +#define MUX_PA24N_CCL_IN8 _UINT32_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UINT32_(1) << 24) + +#define PIN_PB08N_CCL_IN8 _UINT32_(40) +#define MUX_PB08N_CCL_IN8 _UINT32_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UINT32_(1) << 8) + +#define PIN_PB14N_CCL_IN9 _UINT32_(46) +#define MUX_PB14N_CCL_IN9 _UINT32_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UINT32_(1) << 14) + +#define PIN_PC20N_CCL_IN9 _UINT32_(84) +#define MUX_PC20N_CCL_IN9 _UINT32_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UINT32_(1) << 20) + +#define PIN_PB15N_CCL_IN10 _UINT32_(47) +#define MUX_PB15N_CCL_IN10 _UINT32_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UINT32_(1) << 15) + +#define PIN_PC21N_CCL_IN10 _UINT32_(85) +#define MUX_PC21N_CCL_IN10 _UINT32_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UINT32_(1) << 21) + +#define PIN_PB10N_CCL_IN11 _UINT32_(42) +#define MUX_PB10N_CCL_IN11 _UINT32_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UINT32_(1) << 10) + +#define PIN_PB16N_CCL_IN11 _UINT32_(48) +#define MUX_PB16N_CCL_IN11 _UINT32_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UINT32_(1) << 16) + +#define PIN_PA07N_CCL_OUT0 _UINT32_(7) +#define MUX_PA07N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UINT32_(1) << 7) + +#define PIN_PA19N_CCL_OUT0 _UINT32_(19) +#define MUX_PA19N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UINT32_(1) << 19) + +#define PIN_PB02N_CCL_OUT0 _UINT32_(34) +#define MUX_PB02N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UINT32_(1) << 2) + +#define PIN_PB23N_CCL_OUT0 _UINT32_(55) +#define MUX_PB23N_CCL_OUT0 _UINT32_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UINT32_(1) << 23) + +#define PIN_PA11N_CCL_OUT1 _UINT32_(11) +#define MUX_PA11N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UINT32_(1) << 11) + +#define PIN_PA31N_CCL_OUT1 _UINT32_(31) +#define MUX_PA31N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UINT32_(1) << 31) + +#define PIN_PB11N_CCL_OUT1 _UINT32_(43) +#define MUX_PB11N_CCL_OUT1 _UINT32_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UINT32_(1) << 11) + +#define PIN_PA25N_CCL_OUT2 _UINT32_(25) +#define MUX_PA25N_CCL_OUT2 _UINT32_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UINT32_(1) << 25) + +#define PIN_PB09N_CCL_OUT2 _UINT32_(41) +#define MUX_PB09N_CCL_OUT2 _UINT32_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UINT32_(1) << 9) + +#define PIN_PB17N_CCL_OUT3 _UINT32_(49) +#define MUX_PB17N_CCL_OUT3 _UINT32_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UINT32_(1) << 17) + +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _UINT32_(2) +#define MUX_PA02B_DAC_VOUT0 _UINT32_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UINT32_(1) << 2) + +#define PIN_PA05B_DAC_VOUT1 _UINT32_(5) +#define MUX_PA05B_DAC_VOUT1 _UINT32_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UINT32_(1) << 5) + +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _UINT32_(0) +#define MUX_PA00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA00 External Interrupt Line */ + +#define PIN_PA16A_EIC_EXTINT0 _UINT32_(16) +#define MUX_PA16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA16 External Interrupt Line */ + +#define PIN_PB00A_EIC_EXTINT0 _UINT32_(32) +#define MUX_PB00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB00 External Interrupt Line */ + +#define PIN_PB16A_EIC_EXTINT0 _UINT32_(48) +#define MUX_PB16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB16 External Interrupt Line */ + +#define PIN_PC00A_EIC_EXTINT0 _UINT32_(64) +#define MUX_PC00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PC00 External Interrupt Line */ + +#define PIN_PC16A_EIC_EXTINT0 _UINT32_(80) +#define MUX_PC16A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UINT32_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PC16 External Interrupt Line */ + +#define PIN_PD00A_EIC_EXTINT0 _UINT32_(96) +#define MUX_PD00A_EIC_EXTINT0 _UINT32_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UINT32_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PD00 External Interrupt Line */ + +#define PIN_PA01A_EIC_EXTINT1 _UINT32_(1) +#define MUX_PA01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA01 External Interrupt Line */ + +#define PIN_PA17A_EIC_EXTINT1 _UINT32_(17) +#define MUX_PA17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA17 External Interrupt Line */ + +#define PIN_PB01A_EIC_EXTINT1 _UINT32_(33) +#define MUX_PB01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB01 External Interrupt Line */ + +#define PIN_PB17A_EIC_EXTINT1 _UINT32_(49) +#define MUX_PB17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB17 External Interrupt Line */ + +#define PIN_PC01A_EIC_EXTINT1 _UINT32_(65) +#define MUX_PC01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PC01 External Interrupt Line */ + +#define PIN_PC17A_EIC_EXTINT1 _UINT32_(81) +#define MUX_PC17A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UINT32_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PC17 External Interrupt Line */ + +#define PIN_PD01A_EIC_EXTINT1 _UINT32_(97) +#define MUX_PD01A_EIC_EXTINT1 _UINT32_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UINT32_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PD01 External Interrupt Line */ + +#define PIN_PA02A_EIC_EXTINT2 _UINT32_(2) +#define MUX_PA02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA02 External Interrupt Line */ + +#define PIN_PA18A_EIC_EXTINT2 _UINT32_(18) +#define MUX_PA18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA18 External Interrupt Line */ + +#define PIN_PB02A_EIC_EXTINT2 _UINT32_(34) +#define MUX_PB02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB02 External Interrupt Line */ + +#define PIN_PB18A_EIC_EXTINT2 _UINT32_(50) +#define MUX_PB18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB18 External Interrupt Line */ + +#define PIN_PC02A_EIC_EXTINT2 _UINT32_(66) +#define MUX_PC02A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UINT32_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PC02 External Interrupt Line */ + +#define PIN_PC18A_EIC_EXTINT2 _UINT32_(82) +#define MUX_PC18A_EIC_EXTINT2 _UINT32_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UINT32_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PC18 External Interrupt Line */ + +#define PIN_PA03A_EIC_EXTINT3 _UINT32_(3) +#define MUX_PA03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA03 External Interrupt Line */ + +#define PIN_PA19A_EIC_EXTINT3 _UINT32_(19) +#define MUX_PA19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA19 External Interrupt Line */ + +#define PIN_PB03A_EIC_EXTINT3 _UINT32_(35) +#define MUX_PB03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB03 External Interrupt Line */ + +#define PIN_PB19A_EIC_EXTINT3 _UINT32_(51) +#define MUX_PB19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB19 External Interrupt Line */ + +#define PIN_PC03A_EIC_EXTINT3 _UINT32_(67) +#define MUX_PC03A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UINT32_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PC03 External Interrupt Line */ + +#define PIN_PC19A_EIC_EXTINT3 _UINT32_(83) +#define MUX_PC19A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UINT32_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PC19 External Interrupt Line */ + +#define PIN_PD08A_EIC_EXTINT3 _UINT32_(104) +#define MUX_PD08A_EIC_EXTINT3 _UINT32_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UINT32_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PD08 External Interrupt Line */ + +#define PIN_PA04A_EIC_EXTINT4 _UINT32_(4) +#define MUX_PA04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA04 External Interrupt Line */ + +#define PIN_PA20A_EIC_EXTINT4 _UINT32_(20) +#define MUX_PA20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA20 External Interrupt Line */ + +#define PIN_PB04A_EIC_EXTINT4 _UINT32_(36) +#define MUX_PB04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB04 External Interrupt Line */ + +#define PIN_PB20A_EIC_EXTINT4 _UINT32_(52) +#define MUX_PB20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB20 External Interrupt Line */ + +#define PIN_PC04A_EIC_EXTINT4 _UINT32_(68) +#define MUX_PC04A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UINT32_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PC04 External Interrupt Line */ + +#define PIN_PC20A_EIC_EXTINT4 _UINT32_(84) +#define MUX_PC20A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UINT32_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PC20 External Interrupt Line */ + +#define PIN_PD09A_EIC_EXTINT4 _UINT32_(105) +#define MUX_PD09A_EIC_EXTINT4 _UINT32_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UINT32_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PD09 External Interrupt Line */ + +#define PIN_PA05A_EIC_EXTINT5 _UINT32_(5) +#define MUX_PA05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA05 External Interrupt Line */ + +#define PIN_PA21A_EIC_EXTINT5 _UINT32_(21) +#define MUX_PA21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA21 External Interrupt Line */ + +#define PIN_PB05A_EIC_EXTINT5 _UINT32_(37) +#define MUX_PB05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB05 External Interrupt Line */ + +#define PIN_PB21A_EIC_EXTINT5 _UINT32_(53) +#define MUX_PB21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB21 External Interrupt Line */ + +#define PIN_PC05A_EIC_EXTINT5 _UINT32_(69) +#define MUX_PC05A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UINT32_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PC05 External Interrupt Line */ + +#define PIN_PC21A_EIC_EXTINT5 _UINT32_(85) +#define MUX_PC21A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UINT32_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PC21 External Interrupt Line */ + +#define PIN_PD10A_EIC_EXTINT5 _UINT32_(106) +#define MUX_PD10A_EIC_EXTINT5 _UINT32_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UINT32_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PD10 External Interrupt Line */ + +#define PIN_PA06A_EIC_EXTINT6 _UINT32_(6) +#define MUX_PA06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA06 External Interrupt Line */ + +#define PIN_PA22A_EIC_EXTINT6 _UINT32_(22) +#define MUX_PA22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA22 External Interrupt Line */ + +#define PIN_PB06A_EIC_EXTINT6 _UINT32_(38) +#define MUX_PB06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB06 External Interrupt Line */ + +#define PIN_PB22A_EIC_EXTINT6 _UINT32_(54) +#define MUX_PB22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB22 External Interrupt Line */ + +#define PIN_PC06A_EIC_EXTINT6 _UINT32_(70) +#define MUX_PC06A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UINT32_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PC06 External Interrupt Line */ + +#define PIN_PC22A_EIC_EXTINT6 _UINT32_(86) +#define MUX_PC22A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UINT32_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PC22 External Interrupt Line */ + +#define PIN_PD11A_EIC_EXTINT6 _UINT32_(107) +#define MUX_PD11A_EIC_EXTINT6 _UINT32_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UINT32_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PD11 External Interrupt Line */ + +#define PIN_PA07A_EIC_EXTINT7 _UINT32_(7) +#define MUX_PA07A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UINT32_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA07 External Interrupt Line */ + +#define PIN_PA23A_EIC_EXTINT7 _UINT32_(23) +#define MUX_PA23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA23 External Interrupt Line */ + +#define PIN_PB07A_EIC_EXTINT7 _UINT32_(39) +#define MUX_PB07A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UINT32_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB07 External Interrupt Line */ + +#define PIN_PB23A_EIC_EXTINT7 _UINT32_(55) +#define MUX_PB23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB23 External Interrupt Line */ + +#define PIN_PC23A_EIC_EXTINT7 _UINT32_(87) +#define MUX_PC23A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UINT32_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PC23 External Interrupt Line */ + +#define PIN_PD12A_EIC_EXTINT7 _UINT32_(108) +#define MUX_PD12A_EIC_EXTINT7 _UINT32_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UINT32_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PD12 External Interrupt Line */ + +#define PIN_PA24A_EIC_EXTINT8 _UINT32_(24) +#define MUX_PA24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PA24 External Interrupt Line */ + +#define PIN_PB08A_EIC_EXTINT8 _UINT32_(40) +#define MUX_PB08A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UINT32_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PB08 External Interrupt Line */ + +#define PIN_PB24A_EIC_EXTINT8 _UINT32_(56) +#define MUX_PB24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PB24 External Interrupt Line */ + +#define PIN_PC24A_EIC_EXTINT8 _UINT32_(88) +#define MUX_PC24A_EIC_EXTINT8 _UINT32_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UINT32_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PC24 External Interrupt Line */ + +#define PIN_PA09A_EIC_EXTINT9 _UINT32_(9) +#define MUX_PA09A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UINT32_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA09 External Interrupt Line */ + +#define PIN_PA25A_EIC_EXTINT9 _UINT32_(25) +#define MUX_PA25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA25 External Interrupt Line */ + +#define PIN_PB09A_EIC_EXTINT9 _UINT32_(41) +#define MUX_PB09A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UINT32_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PB09 External Interrupt Line */ + +#define PIN_PB25A_EIC_EXTINT9 _UINT32_(57) +#define MUX_PB25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PB25 External Interrupt Line */ + +#define PIN_PC07A_EIC_EXTINT9 _UINT32_(71) +#define MUX_PC07A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UINT32_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PC07 External Interrupt Line */ + +#define PIN_PC25A_EIC_EXTINT9 _UINT32_(89) +#define MUX_PC25A_EIC_EXTINT9 _UINT32_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UINT32_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PC25 External Interrupt Line */ + +#define PIN_PA10A_EIC_EXTINT10 _UINT32_(10) +#define MUX_PA10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PA10 External Interrupt Line */ + +#define PIN_PB10A_EIC_EXTINT10 _UINT32_(42) +#define MUX_PB10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PB10 External Interrupt Line */ + +#define PIN_PC10A_EIC_EXTINT10 _UINT32_(74) +#define MUX_PC10A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UINT32_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PC10 External Interrupt Line */ + +#define PIN_PC26A_EIC_EXTINT10 _UINT32_(90) +#define MUX_PC26A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UINT32_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PC26 External Interrupt Line */ + +#define PIN_PD20A_EIC_EXTINT10 _UINT32_(116) +#define MUX_PD20A_EIC_EXTINT10 _UINT32_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UINT32_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PD20 External Interrupt Line */ + +#define PIN_PA11A_EIC_EXTINT11 _UINT32_(11) +#define MUX_PA11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA11 External Interrupt Line */ + +#define PIN_PA27A_EIC_EXTINT11 _UINT32_(27) +#define MUX_PA27A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UINT32_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA27 External Interrupt Line */ + +#define PIN_PB11A_EIC_EXTINT11 _UINT32_(43) +#define MUX_PB11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PB11 External Interrupt Line */ + +#define PIN_PC11A_EIC_EXTINT11 _UINT32_(75) +#define MUX_PC11A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UINT32_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PC11 External Interrupt Line */ + +#define PIN_PC27A_EIC_EXTINT11 _UINT32_(91) +#define MUX_PC27A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UINT32_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PC27 External Interrupt Line */ + +#define PIN_PD21A_EIC_EXTINT11 _UINT32_(117) +#define MUX_PD21A_EIC_EXTINT11 _UINT32_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UINT32_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PD21 External Interrupt Line */ + +#define PIN_PA12A_EIC_EXTINT12 _UINT32_(12) +#define MUX_PA12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PA12 External Interrupt Line */ + +#define PIN_PB12A_EIC_EXTINT12 _UINT32_(44) +#define MUX_PB12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PB12 External Interrupt Line */ + +#define PIN_PB26A_EIC_EXTINT12 _UINT32_(58) +#define MUX_PB26A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UINT32_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PB26 External Interrupt Line */ + +#define PIN_PC12A_EIC_EXTINT12 _UINT32_(76) +#define MUX_PC12A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UINT32_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PC12 External Interrupt Line */ + +#define PIN_PC28A_EIC_EXTINT12 _UINT32_(92) +#define MUX_PC28A_EIC_EXTINT12 _UINT32_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UINT32_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PC28 External Interrupt Line */ + +#define PIN_PA13A_EIC_EXTINT13 _UINT32_(13) +#define MUX_PA13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PA13 External Interrupt Line */ + +#define PIN_PB13A_EIC_EXTINT13 _UINT32_(45) +#define MUX_PB13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PB13 External Interrupt Line */ + +#define PIN_PB27A_EIC_EXTINT13 _UINT32_(59) +#define MUX_PB27A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UINT32_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PB27 External Interrupt Line */ + +#define PIN_PC13A_EIC_EXTINT13 _UINT32_(77) +#define MUX_PC13A_EIC_EXTINT13 _UINT32_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UINT32_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PC13 External Interrupt Line */ + +#define PIN_PA30A_EIC_EXTINT14 _UINT32_(30) +#define MUX_PA30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA30 External Interrupt Line */ + +#define PIN_PB14A_EIC_EXTINT14 _UINT32_(46) +#define MUX_PB14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB14 External Interrupt Line */ + +#define PIN_PB28A_EIC_EXTINT14 _UINT32_(60) +#define MUX_PB28A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UINT32_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB28 External Interrupt Line */ + +#define PIN_PB30A_EIC_EXTINT14 _UINT32_(62) +#define MUX_PB30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB30 External Interrupt Line */ + +#define PIN_PC14A_EIC_EXTINT14 _UINT32_(78) +#define MUX_PC14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PC14 External Interrupt Line */ + +#define PIN_PC30A_EIC_EXTINT14 _UINT32_(94) +#define MUX_PC30A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UINT32_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PC30 External Interrupt Line */ + +#define PIN_PA14A_EIC_EXTINT14 _UINT32_(14) +#define MUX_PA14A_EIC_EXTINT14 _UINT32_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UINT32_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA14 External Interrupt Line */ + +#define PIN_PA15A_EIC_EXTINT15 _UINT32_(15) +#define MUX_PA15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA15 External Interrupt Line */ + +#define PIN_PA31A_EIC_EXTINT15 _UINT32_(31) +#define MUX_PA31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA31 External Interrupt Line */ + +#define PIN_PB15A_EIC_EXTINT15 _UINT32_(47) +#define MUX_PB15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB15 External Interrupt Line */ + +#define PIN_PB29A_EIC_EXTINT15 _UINT32_(61) +#define MUX_PB29A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UINT32_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB29 External Interrupt Line */ + +#define PIN_PB31A_EIC_EXTINT15 _UINT32_(63) +#define MUX_PB31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB31 External Interrupt Line */ + +#define PIN_PC15A_EIC_EXTINT15 _UINT32_(79) +#define MUX_PC15A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UINT32_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PC15 External Interrupt Line */ + +#define PIN_PC31A_EIC_EXTINT15 _UINT32_(95) +#define MUX_PC31A_EIC_EXTINT15 _UINT32_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UINT32_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PC31 External Interrupt Line */ + +#define PIN_PA08A_EIC_NMI _UINT32_(8) +#define MUX_PA08A_EIC_NMI _UINT32_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UINT32_(1) << 8) + +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _UINT32_(30) +#define MUX_PA30M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UINT32_(1) << 30) + +#define PIN_PB14M_GCLK_IO0 _UINT32_(46) +#define MUX_PB14M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UINT32_(1) << 14) + +#define PIN_PA14M_GCLK_IO0 _UINT32_(14) +#define MUX_PA14M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UINT32_(1) << 14) + +#define PIN_PB22M_GCLK_IO0 _UINT32_(54) +#define MUX_PB22M_GCLK_IO0 _UINT32_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UINT32_(1) << 22) + +#define PIN_PB15M_GCLK_IO1 _UINT32_(47) +#define MUX_PB15M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UINT32_(1) << 15) + +#define PIN_PA15M_GCLK_IO1 _UINT32_(15) +#define MUX_PA15M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UINT32_(1) << 15) + +#define PIN_PB23M_GCLK_IO1 _UINT32_(55) +#define MUX_PB23M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UINT32_(1) << 23) + +#define PIN_PA27M_GCLK_IO1 _UINT32_(27) +#define MUX_PA27M_GCLK_IO1 _UINT32_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UINT32_(1) << 27) + +#define PIN_PA16M_GCLK_IO2 _UINT32_(16) +#define MUX_PA16M_GCLK_IO2 _UINT32_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UINT32_(1) << 16) + +#define PIN_PB16M_GCLK_IO2 _UINT32_(48) +#define MUX_PB16M_GCLK_IO2 _UINT32_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UINT32_(1) << 16) + +#define PIN_PA17M_GCLK_IO3 _UINT32_(17) +#define MUX_PA17M_GCLK_IO3 _UINT32_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UINT32_(1) << 17) + +#define PIN_PB17M_GCLK_IO3 _UINT32_(49) +#define MUX_PB17M_GCLK_IO3 _UINT32_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UINT32_(1) << 17) + +#define PIN_PA10M_GCLK_IO4 _UINT32_(10) +#define MUX_PA10M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UINT32_(1) << 10) + +#define PIN_PB10M_GCLK_IO4 _UINT32_(42) +#define MUX_PB10M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UINT32_(1) << 10) + +#define PIN_PB18M_GCLK_IO4 _UINT32_(50) +#define MUX_PB18M_GCLK_IO4 _UINT32_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UINT32_(1) << 18) + +#define PIN_PA11M_GCLK_IO5 _UINT32_(11) +#define MUX_PA11M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UINT32_(1) << 11) + +#define PIN_PB11M_GCLK_IO5 _UINT32_(43) +#define MUX_PB11M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UINT32_(1) << 11) + +#define PIN_PB19M_GCLK_IO5 _UINT32_(51) +#define MUX_PB19M_GCLK_IO5 _UINT32_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UINT32_(1) << 19) + +#define PIN_PB12M_GCLK_IO6 _UINT32_(44) +#define MUX_PB12M_GCLK_IO6 _UINT32_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UINT32_(1) << 12) + +#define PIN_PB20M_GCLK_IO6 _UINT32_(52) +#define MUX_PB20M_GCLK_IO6 _UINT32_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UINT32_(1) << 20) + +#define PIN_PB13M_GCLK_IO7 _UINT32_(45) +#define MUX_PB13M_GCLK_IO7 _UINT32_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UINT32_(1) << 13) + +#define PIN_PB21M_GCLK_IO7 _UINT32_(53) +#define MUX_PB21M_GCLK_IO7 _UINT32_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UINT32_(1) << 21) + +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _UINT32_(85) +#define MUX_PC21L_GMAC_GCOL _UINT32_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UINT32_(1) << 21) + +#define PIN_PA16L_GMAC_GCRS _UINT32_(16) +#define MUX_PA16L_GMAC_GCRS _UINT32_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UINT32_(1) << 16) + +#define PIN_PA20L_GMAC_GMDC _UINT32_(20) +#define MUX_PA20L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UINT32_(1) << 20) + +#define PIN_PB14L_GMAC_GMDC _UINT32_(46) +#define MUX_PB14L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UINT32_(1) << 14) + +#define PIN_PC11L_GMAC_GMDC _UINT32_(75) +#define MUX_PC11L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UINT32_(1) << 11) + +#define PIN_PC22L_GMAC_GMDC _UINT32_(86) +#define MUX_PC22L_GMAC_GMDC _UINT32_(11) +#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) +#define PORT_PC22L_GMAC_GMDC (_UINT32_(1) << 22) + +#define PIN_PA21L_GMAC_GMDIO _UINT32_(21) +#define MUX_PA21L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UINT32_(1) << 21) + +#define PIN_PB15L_GMAC_GMDIO _UINT32_(47) +#define MUX_PB15L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UINT32_(1) << 15) + +#define PIN_PC12L_GMAC_GMDIO _UINT32_(76) +#define MUX_PC12L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UINT32_(1) << 12) + +#define PIN_PC23L_GMAC_GMDIO _UINT32_(87) +#define MUX_PC23L_GMAC_GMDIO _UINT32_(11) +#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) +#define PORT_PC23L_GMAC_GMDIO (_UINT32_(1) << 23) + +#define PIN_PA13L_GMAC_GRX0 _UINT32_(13) +#define MUX_PA13L_GMAC_GRX0 _UINT32_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UINT32_(1) << 13) + +#define PIN_PA12L_GMAC_GRX1 _UINT32_(12) +#define MUX_PA12L_GMAC_GRX1 _UINT32_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UINT32_(1) << 12) + +#define PIN_PC15L_GMAC_GRX2 _UINT32_(79) +#define MUX_PC15L_GMAC_GRX2 _UINT32_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UINT32_(1) << 15) + +#define PIN_PC14L_GMAC_GRX3 _UINT32_(78) +#define MUX_PC14L_GMAC_GRX3 _UINT32_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UINT32_(1) << 14) + +#define PIN_PC18L_GMAC_GRXCK _UINT32_(82) +#define MUX_PC18L_GMAC_GRXCK _UINT32_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UINT32_(1) << 18) + +#define PIN_PC20L_GMAC_GRXDV _UINT32_(84) +#define MUX_PC20L_GMAC_GRXDV _UINT32_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UINT32_(1) << 20) + +#define PIN_PA15L_GMAC_GRXER _UINT32_(15) +#define MUX_PA15L_GMAC_GRXER _UINT32_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UINT32_(1) << 15) + +#define PIN_PA18L_GMAC_GTX0 _UINT32_(18) +#define MUX_PA18L_GMAC_GTX0 _UINT32_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UINT32_(1) << 18) + +#define PIN_PA19L_GMAC_GTX1 _UINT32_(19) +#define MUX_PA19L_GMAC_GTX1 _UINT32_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UINT32_(1) << 19) + +#define PIN_PC16L_GMAC_GTX2 _UINT32_(80) +#define MUX_PC16L_GMAC_GTX2 _UINT32_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UINT32_(1) << 16) + +#define PIN_PC17L_GMAC_GTX3 _UINT32_(81) +#define MUX_PC17L_GMAC_GTX3 _UINT32_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UINT32_(1) << 17) + +#define PIN_PA14L_GMAC_GTXCK _UINT32_(14) +#define MUX_PA14L_GMAC_GTXCK _UINT32_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UINT32_(1) << 14) + +#define PIN_PA17L_GMAC_GTXEN _UINT32_(17) +#define MUX_PA17L_GMAC_GTXEN _UINT32_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UINT32_(1) << 17) + +#define PIN_PC19L_GMAC_GTXER _UINT32_(83) +#define MUX_PC19L_GMAC_GTXER _UINT32_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UINT32_(1) << 19) + +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _UINT32_(9) +#define MUX_PA09J_I2S_FS0 _UINT32_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UINT32_(1) << 9) + +#define PIN_PA20J_I2S_FS0 _UINT32_(20) +#define MUX_PA20J_I2S_FS0 _UINT32_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UINT32_(1) << 20) + +#define PIN_PA23J_I2S_FS1 _UINT32_(23) +#define MUX_PA23J_I2S_FS1 _UINT32_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UINT32_(1) << 23) + +#define PIN_PB11J_I2S_FS1 _UINT32_(43) +#define MUX_PB11J_I2S_FS1 _UINT32_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UINT32_(1) << 11) + +#define PIN_PA08J_I2S_MCK0 _UINT32_(8) +#define MUX_PA08J_I2S_MCK0 _UINT32_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UINT32_(1) << 8) + +#define PIN_PB17J_I2S_MCK0 _UINT32_(49) +#define MUX_PB17J_I2S_MCK0 _UINT32_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UINT32_(1) << 17) + +#define PIN_PB29J_I2S_MCK1 _UINT32_(61) +#define MUX_PB29J_I2S_MCK1 _UINT32_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UINT32_(1) << 29) + +#define PIN_PB13J_I2S_MCK1 _UINT32_(45) +#define MUX_PB13J_I2S_MCK1 _UINT32_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UINT32_(1) << 13) + +#define PIN_PA10J_I2S_SCK0 _UINT32_(10) +#define MUX_PA10J_I2S_SCK0 _UINT32_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UINT32_(1) << 10) + +#define PIN_PB16J_I2S_SCK0 _UINT32_(48) +#define MUX_PB16J_I2S_SCK0 _UINT32_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UINT32_(1) << 16) + +#define PIN_PB28J_I2S_SCK1 _UINT32_(60) +#define MUX_PB28J_I2S_SCK1 _UINT32_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UINT32_(1) << 28) + +#define PIN_PB12J_I2S_SCK1 _UINT32_(44) +#define MUX_PB12J_I2S_SCK1 _UINT32_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UINT32_(1) << 12) + +#define PIN_PA22J_I2S_SDI _UINT32_(22) +#define MUX_PA22J_I2S_SDI _UINT32_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UINT32_(1) << 22) + +#define PIN_PB10J_I2S_SDI _UINT32_(42) +#define MUX_PB10J_I2S_SDI _UINT32_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UINT32_(1) << 10) + +#define PIN_PA11J_I2S_SDO _UINT32_(11) +#define MUX_PA11J_I2S_SDO _UINT32_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UINT32_(1) << 11) + +#define PIN_PA21J_I2S_SDO _UINT32_(21) +#define MUX_PA21J_I2S_SDO _UINT32_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UINT32_(1) << 21) + +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _UINT32_(14) +#define MUX_PA14K_PCC_CLK _UINT32_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UINT32_(1) << 14) + +#define PIN_PA16K_PCC_DATA0 _UINT32_(16) +#define MUX_PA16K_PCC_DATA0 _UINT32_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UINT32_(1) << 16) + +#define PIN_PA17K_PCC_DATA1 _UINT32_(17) +#define MUX_PA17K_PCC_DATA1 _UINT32_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UINT32_(1) << 17) + +#define PIN_PA18K_PCC_DATA2 _UINT32_(18) +#define MUX_PA18K_PCC_DATA2 _UINT32_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UINT32_(1) << 18) + +#define PIN_PA19K_PCC_DATA3 _UINT32_(19) +#define MUX_PA19K_PCC_DATA3 _UINT32_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UINT32_(1) << 19) + +#define PIN_PA20K_PCC_DATA4 _UINT32_(20) +#define MUX_PA20K_PCC_DATA4 _UINT32_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UINT32_(1) << 20) + +#define PIN_PA21K_PCC_DATA5 _UINT32_(21) +#define MUX_PA21K_PCC_DATA5 _UINT32_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UINT32_(1) << 21) + +#define PIN_PA22K_PCC_DATA6 _UINT32_(22) +#define MUX_PA22K_PCC_DATA6 _UINT32_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UINT32_(1) << 22) + +#define PIN_PA23K_PCC_DATA7 _UINT32_(23) +#define MUX_PA23K_PCC_DATA7 _UINT32_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UINT32_(1) << 23) + +#define PIN_PB14K_PCC_DATA8 _UINT32_(46) +#define MUX_PB14K_PCC_DATA8 _UINT32_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UINT32_(1) << 14) + +#define PIN_PB15K_PCC_DATA9 _UINT32_(47) +#define MUX_PB15K_PCC_DATA9 _UINT32_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UINT32_(1) << 15) + +#define PIN_PC12K_PCC_DATA10 _UINT32_(76) +#define MUX_PC12K_PCC_DATA10 _UINT32_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UINT32_(1) << 12) + +#define PIN_PC13K_PCC_DATA11 _UINT32_(77) +#define MUX_PC13K_PCC_DATA11 _UINT32_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UINT32_(1) << 13) + +#define PIN_PC14K_PCC_DATA12 _UINT32_(78) +#define MUX_PC14K_PCC_DATA12 _UINT32_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UINT32_(1) << 14) + +#define PIN_PC15K_PCC_DATA13 _UINT32_(79) +#define MUX_PC15K_PCC_DATA13 _UINT32_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UINT32_(1) << 15) + +#define PIN_PA12K_PCC_DEN1 _UINT32_(12) +#define MUX_PA12K_PCC_DEN1 _UINT32_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UINT32_(1) << 12) + +#define PIN_PA13K_PCC_DEN2 _UINT32_(13) +#define MUX_PA13K_PCC_DEN2 _UINT32_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UINT32_(1) << 13) + +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _UINT32_(50) +#define MUX_PB18G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UINT32_(1) << 18) + +#define PIN_PB23G_PDEC_QDI0 _UINT32_(55) +#define MUX_PB23G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UINT32_(1) << 23) + +#define PIN_PC16G_PDEC_QDI0 _UINT32_(80) +#define MUX_PC16G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UINT32_(1) << 16) + +#define PIN_PA24G_PDEC_QDI0 _UINT32_(24) +#define MUX_PA24G_PDEC_QDI0 _UINT32_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UINT32_(1) << 24) + +#define PIN_PB19G_PDEC_QDI1 _UINT32_(51) +#define MUX_PB19G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UINT32_(1) << 19) + +#define PIN_PB24G_PDEC_QDI1 _UINT32_(56) +#define MUX_PB24G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UINT32_(1) << 24) + +#define PIN_PC17G_PDEC_QDI1 _UINT32_(81) +#define MUX_PC17G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UINT32_(1) << 17) + +#define PIN_PA25G_PDEC_QDI1 _UINT32_(25) +#define MUX_PA25G_PDEC_QDI1 _UINT32_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UINT32_(1) << 25) + +#define PIN_PB20G_PDEC_QDI2 _UINT32_(52) +#define MUX_PB20G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UINT32_(1) << 20) + +#define PIN_PB25G_PDEC_QDI2 _UINT32_(57) +#define MUX_PB25G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UINT32_(1) << 25) + +#define PIN_PC18G_PDEC_QDI2 _UINT32_(82) +#define MUX_PC18G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UINT32_(1) << 18) + +#define PIN_PB22G_PDEC_QDI2 _UINT32_(54) +#define MUX_PB22G_PDEC_QDI2 _UINT32_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UINT32_(1) << 22) + +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _UINT32_(43) +#define MUX_PB11H_QSPI_CS _UINT32_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UINT32_(1) << 11) + +#define PIN_PA08H_QSPI_DATA0 _UINT32_(8) +#define MUX_PA08H_QSPI_DATA0 _UINT32_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UINT32_(1) << 8) + +#define PIN_PA09H_QSPI_DATA1 _UINT32_(9) +#define MUX_PA09H_QSPI_DATA1 _UINT32_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UINT32_(1) << 9) + +#define PIN_PA10H_QSPI_DATA2 _UINT32_(10) +#define MUX_PA10H_QSPI_DATA2 _UINT32_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UINT32_(1) << 10) + +#define PIN_PA11H_QSPI_DATA3 _UINT32_(11) +#define MUX_PA11H_QSPI_DATA3 _UINT32_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UINT32_(1) << 11) + +#define PIN_PB10H_QSPI_SCK _UINT32_(42) +#define MUX_PB10H_QSPI_SCK _UINT32_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UINT32_(1) << 10) + +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _UINT32_(6) +#define MUX_PA06I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UINT32_(1) << 6) + +#define PIN_PA12I_SDHC0_SDCD _UINT32_(12) +#define MUX_PA12I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UINT32_(1) << 12) + +#define PIN_PB12I_SDHC0_SDCD _UINT32_(44) +#define MUX_PB12I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UINT32_(1) << 12) + +#define PIN_PC06I_SDHC0_SDCD _UINT32_(70) +#define MUX_PC06I_SDHC0_SDCD _UINT32_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UINT32_(1) << 6) + +#define PIN_PB11I_SDHC0_SDCK _UINT32_(43) +#define MUX_PB11I_SDHC0_SDCK _UINT32_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UINT32_(1) << 11) + +#define PIN_PA08I_SDHC0_SDCMD _UINT32_(8) +#define MUX_PA08I_SDHC0_SDCMD _UINT32_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UINT32_(1) << 8) + +#define PIN_PA09I_SDHC0_SDDAT0 _UINT32_(9) +#define MUX_PA09I_SDHC0_SDDAT0 _UINT32_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UINT32_(1) << 9) + +#define PIN_PA10I_SDHC0_SDDAT1 _UINT32_(10) +#define MUX_PA10I_SDHC0_SDDAT1 _UINT32_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UINT32_(1) << 10) + +#define PIN_PA11I_SDHC0_SDDAT2 _UINT32_(11) +#define MUX_PA11I_SDHC0_SDDAT2 _UINT32_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UINT32_(1) << 11) + +#define PIN_PB10I_SDHC0_SDDAT3 _UINT32_(42) +#define MUX_PB10I_SDHC0_SDDAT3 _UINT32_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UINT32_(1) << 10) + +#define PIN_PA07I_SDHC0_SDWP _UINT32_(7) +#define MUX_PA07I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UINT32_(1) << 7) + +#define PIN_PA13I_SDHC0_SDWP _UINT32_(13) +#define MUX_PA13I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UINT32_(1) << 13) + +#define PIN_PB13I_SDHC0_SDWP _UINT32_(45) +#define MUX_PB13I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UINT32_(1) << 13) + +#define PIN_PC07I_SDHC0_SDWP _UINT32_(71) +#define MUX_PC07I_SDHC0_SDWP _UINT32_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UINT32_(1) << 7) + +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _UINT32_(48) +#define MUX_PB16I_SDHC1_SDCD _UINT32_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UINT32_(1) << 16) + +#define PIN_PC20I_SDHC1_SDCD _UINT32_(84) +#define MUX_PC20I_SDHC1_SDCD _UINT32_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UINT32_(1) << 20) + +#define PIN_PD20I_SDHC1_SDCD _UINT32_(116) +#define MUX_PD20I_SDHC1_SDCD _UINT32_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UINT32_(1) << 20) + +#define PIN_PA21I_SDHC1_SDCK _UINT32_(21) +#define MUX_PA21I_SDHC1_SDCK _UINT32_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UINT32_(1) << 21) + +#define PIN_PA20I_SDHC1_SDCMD _UINT32_(20) +#define MUX_PA20I_SDHC1_SDCMD _UINT32_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UINT32_(1) << 20) + +#define PIN_PB18I_SDHC1_SDDAT0 _UINT32_(50) +#define MUX_PB18I_SDHC1_SDDAT0 _UINT32_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UINT32_(1) << 18) + +#define PIN_PB19I_SDHC1_SDDAT1 _UINT32_(51) +#define MUX_PB19I_SDHC1_SDDAT1 _UINT32_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UINT32_(1) << 19) + +#define PIN_PB20I_SDHC1_SDDAT2 _UINT32_(52) +#define MUX_PB20I_SDHC1_SDDAT2 _UINT32_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UINT32_(1) << 20) + +#define PIN_PB21I_SDHC1_SDDAT3 _UINT32_(53) +#define MUX_PB21I_SDHC1_SDDAT3 _UINT32_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UINT32_(1) << 21) + +#define PIN_PB17I_SDHC1_SDWP _UINT32_(49) +#define MUX_PB17I_SDHC1_SDWP _UINT32_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UINT32_(1) << 17) + +#define PIN_PC21I_SDHC1_SDWP _UINT32_(85) +#define MUX_PC21I_SDHC1_SDWP _UINT32_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UINT32_(1) << 21) + +#define PIN_PD21I_SDHC1_SDWP _UINT32_(117) +#define MUX_PD21I_SDHC1_SDWP _UINT32_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UINT32_(1) << 21) + +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _UINT32_(4) +#define MUX_PA04D_SERCOM0_PAD0 _UINT32_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UINT32_(1) << 4) + +#define PIN_PC17D_SERCOM0_PAD0 _UINT32_(81) +#define MUX_PC17D_SERCOM0_PAD0 _UINT32_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UINT32_(1) << 17) + +#define PIN_PA08C_SERCOM0_PAD0 _UINT32_(8) +#define MUX_PA08C_SERCOM0_PAD0 _UINT32_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UINT32_(1) << 8) + +#define PIN_PB24C_SERCOM0_PAD0 _UINT32_(56) +#define MUX_PB24C_SERCOM0_PAD0 _UINT32_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UINT32_(1) << 24) + +#define PIN_PA05D_SERCOM0_PAD1 _UINT32_(5) +#define MUX_PA05D_SERCOM0_PAD1 _UINT32_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UINT32_(1) << 5) + +#define PIN_PC16D_SERCOM0_PAD1 _UINT32_(80) +#define MUX_PC16D_SERCOM0_PAD1 _UINT32_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UINT32_(1) << 16) + +#define PIN_PA09C_SERCOM0_PAD1 _UINT32_(9) +#define MUX_PA09C_SERCOM0_PAD1 _UINT32_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UINT32_(1) << 9) + +#define PIN_PB25C_SERCOM0_PAD1 _UINT32_(57) +#define MUX_PB25C_SERCOM0_PAD1 _UINT32_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UINT32_(1) << 25) + +#define PIN_PA06D_SERCOM0_PAD2 _UINT32_(6) +#define MUX_PA06D_SERCOM0_PAD2 _UINT32_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UINT32_(1) << 6) + +#define PIN_PC18D_SERCOM0_PAD2 _UINT32_(82) +#define MUX_PC18D_SERCOM0_PAD2 _UINT32_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA10C_SERCOM0_PAD2 _UINT32_(10) +#define MUX_PA10C_SERCOM0_PAD2 _UINT32_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC24C_SERCOM0_PAD2 _UINT32_(88) +#define MUX_PC24C_SERCOM0_PAD2 _UINT32_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UINT32_(1) << 24) + +#define PIN_PA07D_SERCOM0_PAD3 _UINT32_(7) +#define MUX_PA07D_SERCOM0_PAD3 _UINT32_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UINT32_(1) << 7) + +#define PIN_PC19D_SERCOM0_PAD3 _UINT32_(83) +#define MUX_PC19D_SERCOM0_PAD3 _UINT32_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UINT32_(1) << 19) + +#define PIN_PA11C_SERCOM0_PAD3 _UINT32_(11) +#define MUX_PA11C_SERCOM0_PAD3 _UINT32_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC25C_SERCOM0_PAD3 _UINT32_(89) +#define MUX_PC25C_SERCOM0_PAD3 _UINT32_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UINT32_(1) << 25) + +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _UINT32_(0) +#define MUX_PA00D_SERCOM1_PAD0 _UINT32_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UINT32_(1) << 0) + +#define PIN_PA16C_SERCOM1_PAD0 _UINT32_(16) +#define MUX_PA16C_SERCOM1_PAD0 _UINT32_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UINT32_(1) << 16) + +#define PIN_PC22C_SERCOM1_PAD0 _UINT32_(86) +#define MUX_PC22C_SERCOM1_PAD0 _UINT32_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UINT32_(1) << 22) + +#define PIN_PC27C_SERCOM1_PAD0 _UINT32_(91) +#define MUX_PC27C_SERCOM1_PAD0 _UINT32_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UINT32_(1) << 27) + +#define PIN_PA01D_SERCOM1_PAD1 _UINT32_(1) +#define MUX_PA01D_SERCOM1_PAD1 _UINT32_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UINT32_(1) << 1) + +#define PIN_PA17C_SERCOM1_PAD1 _UINT32_(17) +#define MUX_PA17C_SERCOM1_PAD1 _UINT32_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UINT32_(1) << 17) + +#define PIN_PC23C_SERCOM1_PAD1 _UINT32_(87) +#define MUX_PC23C_SERCOM1_PAD1 _UINT32_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UINT32_(1) << 23) + +#define PIN_PC28C_SERCOM1_PAD1 _UINT32_(92) +#define MUX_PC28C_SERCOM1_PAD1 _UINT32_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UINT32_(1) << 28) + +#define PIN_PA30D_SERCOM1_PAD2 _UINT32_(30) +#define MUX_PA30D_SERCOM1_PAD2 _UINT32_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UINT32_(1) << 30) + +#define PIN_PA18C_SERCOM1_PAD2 _UINT32_(18) +#define MUX_PA18C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UINT32_(1) << 18) + +#define PIN_PB22C_SERCOM1_PAD2 _UINT32_(54) +#define MUX_PB22C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UINT32_(1) << 22) + +#define PIN_PD20C_SERCOM1_PAD2 _UINT32_(116) +#define MUX_PD20C_SERCOM1_PAD2 _UINT32_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UINT32_(1) << 20) + +#define PIN_PA31D_SERCOM1_PAD3 _UINT32_(31) +#define MUX_PA31D_SERCOM1_PAD3 _UINT32_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UINT32_(1) << 31) + +#define PIN_PA19C_SERCOM1_PAD3 _UINT32_(19) +#define MUX_PA19C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UINT32_(1) << 19) + +#define PIN_PB23C_SERCOM1_PAD3 _UINT32_(55) +#define MUX_PB23C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UINT32_(1) << 23) + +#define PIN_PD21C_SERCOM1_PAD3 _UINT32_(117) +#define MUX_PD21C_SERCOM1_PAD3 _UINT32_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UINT32_(1) << 21) + +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _UINT32_(9) +#define MUX_PA09D_SERCOM2_PAD0 _UINT32_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UINT32_(1) << 9) + +#define PIN_PB25D_SERCOM2_PAD0 _UINT32_(57) +#define MUX_PB25D_SERCOM2_PAD0 _UINT32_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UINT32_(1) << 25) + +#define PIN_PA12C_SERCOM2_PAD0 _UINT32_(12) +#define MUX_PA12C_SERCOM2_PAD0 _UINT32_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UINT32_(1) << 12) + +#define PIN_PB26C_SERCOM2_PAD0 _UINT32_(58) +#define MUX_PB26C_SERCOM2_PAD0 _UINT32_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UINT32_(1) << 26) + +#define PIN_PA08D_SERCOM2_PAD1 _UINT32_(8) +#define MUX_PA08D_SERCOM2_PAD1 _UINT32_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UINT32_(1) << 8) + +#define PIN_PB24D_SERCOM2_PAD1 _UINT32_(56) +#define MUX_PB24D_SERCOM2_PAD1 _UINT32_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UINT32_(1) << 24) + +#define PIN_PA13C_SERCOM2_PAD1 _UINT32_(13) +#define MUX_PA13C_SERCOM2_PAD1 _UINT32_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UINT32_(1) << 13) + +#define PIN_PB27C_SERCOM2_PAD1 _UINT32_(59) +#define MUX_PB27C_SERCOM2_PAD1 _UINT32_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UINT32_(1) << 27) + +#define PIN_PA10D_SERCOM2_PAD2 _UINT32_(10) +#define MUX_PA10D_SERCOM2_PAD2 _UINT32_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC24D_SERCOM2_PAD2 _UINT32_(88) +#define MUX_PC24D_SERCOM2_PAD2 _UINT32_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UINT32_(1) << 24) + +#define PIN_PB28C_SERCOM2_PAD2 _UINT32_(60) +#define MUX_PB28C_SERCOM2_PAD2 _UINT32_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UINT32_(1) << 28) + +#define PIN_PA14C_SERCOM2_PAD2 _UINT32_(14) +#define MUX_PA14C_SERCOM2_PAD2 _UINT32_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UINT32_(1) << 14) + +#define PIN_PA11D_SERCOM2_PAD3 _UINT32_(11) +#define MUX_PA11D_SERCOM2_PAD3 _UINT32_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC25D_SERCOM2_PAD3 _UINT32_(89) +#define MUX_PC25D_SERCOM2_PAD3 _UINT32_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UINT32_(1) << 25) + +#define PIN_PB29C_SERCOM2_PAD3 _UINT32_(61) +#define MUX_PB29C_SERCOM2_PAD3 _UINT32_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UINT32_(1) << 29) + +#define PIN_PA15C_SERCOM2_PAD3 _UINT32_(15) +#define MUX_PA15C_SERCOM2_PAD3 _UINT32_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UINT32_(1) << 15) + +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _UINT32_(17) +#define MUX_PA17D_SERCOM3_PAD0 _UINT32_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UINT32_(1) << 17) + +#define PIN_PC23D_SERCOM3_PAD0 _UINT32_(87) +#define MUX_PC23D_SERCOM3_PAD0 _UINT32_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UINT32_(1) << 23) + +#define PIN_PA22C_SERCOM3_PAD0 _UINT32_(22) +#define MUX_PA22C_SERCOM3_PAD0 _UINT32_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UINT32_(1) << 22) + +#define PIN_PB20C_SERCOM3_PAD0 _UINT32_(52) +#define MUX_PB20C_SERCOM3_PAD0 _UINT32_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UINT32_(1) << 20) + +#define PIN_PA16D_SERCOM3_PAD1 _UINT32_(16) +#define MUX_PA16D_SERCOM3_PAD1 _UINT32_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UINT32_(1) << 16) + +#define PIN_PC22D_SERCOM3_PAD1 _UINT32_(86) +#define MUX_PC22D_SERCOM3_PAD1 _UINT32_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UINT32_(1) << 22) + +#define PIN_PA23C_SERCOM3_PAD1 _UINT32_(23) +#define MUX_PA23C_SERCOM3_PAD1 _UINT32_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UINT32_(1) << 23) + +#define PIN_PB21C_SERCOM3_PAD1 _UINT32_(53) +#define MUX_PB21C_SERCOM3_PAD1 _UINT32_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UINT32_(1) << 21) + +#define PIN_PA18D_SERCOM3_PAD2 _UINT32_(18) +#define MUX_PA18D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA20D_SERCOM3_PAD2 _UINT32_(20) +#define MUX_PA20D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UINT32_(1) << 20) + +#define PIN_PD20D_SERCOM3_PAD2 _UINT32_(116) +#define MUX_PD20D_SERCOM3_PAD2 _UINT32_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UINT32_(1) << 20) + +#define PIN_PA24C_SERCOM3_PAD2 _UINT32_(24) +#define MUX_PA24C_SERCOM3_PAD2 _UINT32_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UINT32_(1) << 24) + +#define PIN_PA19D_SERCOM3_PAD3 _UINT32_(19) +#define MUX_PA19D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UINT32_(1) << 19) + +#define PIN_PA21D_SERCOM3_PAD3 _UINT32_(21) +#define MUX_PA21D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UINT32_(1) << 21) + +#define PIN_PD21D_SERCOM3_PAD3 _UINT32_(117) +#define MUX_PD21D_SERCOM3_PAD3 _UINT32_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UINT32_(1) << 21) + +#define PIN_PA25C_SERCOM3_PAD3 _UINT32_(25) +#define MUX_PA25C_SERCOM3_PAD3 _UINT32_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UINT32_(1) << 25) + +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _UINT32_(13) +#define MUX_PA13D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UINT32_(1) << 13) + +#define PIN_PB08D_SERCOM4_PAD0 _UINT32_(40) +#define MUX_PB08D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UINT32_(1) << 8) + +#define PIN_PB27D_SERCOM4_PAD0 _UINT32_(59) +#define MUX_PB27D_SERCOM4_PAD0 _UINT32_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UINT32_(1) << 27) + +#define PIN_PB12C_SERCOM4_PAD0 _UINT32_(44) +#define MUX_PB12C_SERCOM4_PAD0 _UINT32_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UINT32_(1) << 12) + +#define PIN_PA12D_SERCOM4_PAD1 _UINT32_(12) +#define MUX_PA12D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UINT32_(1) << 12) + +#define PIN_PB09D_SERCOM4_PAD1 _UINT32_(41) +#define MUX_PB09D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UINT32_(1) << 9) + +#define PIN_PB26D_SERCOM4_PAD1 _UINT32_(58) +#define MUX_PB26D_SERCOM4_PAD1 _UINT32_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UINT32_(1) << 26) + +#define PIN_PB13C_SERCOM4_PAD1 _UINT32_(45) +#define MUX_PB13C_SERCOM4_PAD1 _UINT32_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UINT32_(1) << 13) + +#define PIN_PA14D_SERCOM4_PAD2 _UINT32_(14) +#define MUX_PA14D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UINT32_(1) << 14) + +#define PIN_PB10D_SERCOM4_PAD2 _UINT32_(42) +#define MUX_PB10D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UINT32_(1) << 10) + +#define PIN_PB28D_SERCOM4_PAD2 _UINT32_(60) +#define MUX_PB28D_SERCOM4_PAD2 _UINT32_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UINT32_(1) << 28) + +#define PIN_PB14C_SERCOM4_PAD2 _UINT32_(46) +#define MUX_PB14C_SERCOM4_PAD2 _UINT32_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UINT32_(1) << 14) + +#define PIN_PB11D_SERCOM4_PAD3 _UINT32_(43) +#define MUX_PB11D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UINT32_(1) << 11) + +#define PIN_PB29D_SERCOM4_PAD3 _UINT32_(61) +#define MUX_PB29D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UINT32_(1) << 29) + +#define PIN_PA15D_SERCOM4_PAD3 _UINT32_(15) +#define MUX_PA15D_SERCOM4_PAD3 _UINT32_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UINT32_(1) << 15) + +#define PIN_PB15C_SERCOM4_PAD3 _UINT32_(47) +#define MUX_PB15C_SERCOM4_PAD3 _UINT32_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UINT32_(1) << 15) + +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _UINT32_(23) +#define MUX_PA23D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UINT32_(1) << 23) + +#define PIN_PB02D_SERCOM5_PAD0 _UINT32_(34) +#define MUX_PB02D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UINT32_(1) << 2) + +#define PIN_PB31D_SERCOM5_PAD0 _UINT32_(63) +#define MUX_PB31D_SERCOM5_PAD0 _UINT32_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UINT32_(1) << 31) + +#define PIN_PB16C_SERCOM5_PAD0 _UINT32_(48) +#define MUX_PB16C_SERCOM5_PAD0 _UINT32_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UINT32_(1) << 16) + +#define PIN_PA22D_SERCOM5_PAD1 _UINT32_(22) +#define MUX_PA22D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UINT32_(1) << 22) + +#define PIN_PB03D_SERCOM5_PAD1 _UINT32_(35) +#define MUX_PB03D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UINT32_(1) << 3) + +#define PIN_PB30D_SERCOM5_PAD1 _UINT32_(62) +#define MUX_PB30D_SERCOM5_PAD1 _UINT32_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UINT32_(1) << 30) + +#define PIN_PB17C_SERCOM5_PAD1 _UINT32_(49) +#define MUX_PB17C_SERCOM5_PAD1 _UINT32_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UINT32_(1) << 17) + +#define PIN_PA24D_SERCOM5_PAD2 _UINT32_(24) +#define MUX_PA24D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UINT32_(1) << 24) + +#define PIN_PB00D_SERCOM5_PAD2 _UINT32_(32) +#define MUX_PB00D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UINT32_(1) << 0) + +#define PIN_PB22D_SERCOM5_PAD2 _UINT32_(54) +#define MUX_PB22D_SERCOM5_PAD2 _UINT32_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UINT32_(1) << 22) + +#define PIN_PA20C_SERCOM5_PAD2 _UINT32_(20) +#define MUX_PA20C_SERCOM5_PAD2 _UINT32_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UINT32_(1) << 20) + +#define PIN_PB18C_SERCOM5_PAD2 _UINT32_(50) +#define MUX_PB18C_SERCOM5_PAD2 _UINT32_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UINT32_(1) << 18) + +#define PIN_PA25D_SERCOM5_PAD3 _UINT32_(25) +#define MUX_PA25D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UINT32_(1) << 25) + +#define PIN_PB01D_SERCOM5_PAD3 _UINT32_(33) +#define MUX_PB01D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UINT32_(1) << 1) + +#define PIN_PB23D_SERCOM5_PAD3 _UINT32_(55) +#define MUX_PB23D_SERCOM5_PAD3 _UINT32_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UINT32_(1) << 23) + +#define PIN_PA21C_SERCOM5_PAD3 _UINT32_(21) +#define MUX_PA21C_SERCOM5_PAD3 _UINT32_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UINT32_(1) << 21) + +#define PIN_PB19C_SERCOM5_PAD3 _UINT32_(51) +#define MUX_PB19C_SERCOM5_PAD3 _UINT32_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UINT32_(1) << 19) + +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _UINT32_(105) +#define MUX_PD09D_SERCOM6_PAD0 _UINT32_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UINT32_(1) << 9) + +#define PIN_PC13D_SERCOM6_PAD0 _UINT32_(77) +#define MUX_PC13D_SERCOM6_PAD0 _UINT32_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UINT32_(1) << 13) + +#define PIN_PC04C_SERCOM6_PAD0 _UINT32_(68) +#define MUX_PC04C_SERCOM6_PAD0 _UINT32_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UINT32_(1) << 4) + +#define PIN_PC16C_SERCOM6_PAD0 _UINT32_(80) +#define MUX_PC16C_SERCOM6_PAD0 _UINT32_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UINT32_(1) << 16) + +#define PIN_PD08D_SERCOM6_PAD1 _UINT32_(104) +#define MUX_PD08D_SERCOM6_PAD1 _UINT32_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UINT32_(1) << 8) + +#define PIN_PC12D_SERCOM6_PAD1 _UINT32_(76) +#define MUX_PC12D_SERCOM6_PAD1 _UINT32_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UINT32_(1) << 12) + +#define PIN_PC05C_SERCOM6_PAD1 _UINT32_(69) +#define MUX_PC05C_SERCOM6_PAD1 _UINT32_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UINT32_(1) << 5) + +#define PIN_PC17C_SERCOM6_PAD1 _UINT32_(81) +#define MUX_PC17C_SERCOM6_PAD1 _UINT32_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UINT32_(1) << 17) + +#define PIN_PC14D_SERCOM6_PAD2 _UINT32_(78) +#define MUX_PC14D_SERCOM6_PAD2 _UINT32_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UINT32_(1) << 14) + +#define PIN_PD10D_SERCOM6_PAD2 _UINT32_(106) +#define MUX_PD10D_SERCOM6_PAD2 _UINT32_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC06C_SERCOM6_PAD2 _UINT32_(70) +#define MUX_PC06C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UINT32_(1) << 6) + +#define PIN_PC10C_SERCOM6_PAD2 _UINT32_(74) +#define MUX_PC10C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC18C_SERCOM6_PAD2 _UINT32_(82) +#define MUX_PC18C_SERCOM6_PAD2 _UINT32_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UINT32_(1) << 18) + +#define PIN_PC15D_SERCOM6_PAD3 _UINT32_(79) +#define MUX_PC15D_SERCOM6_PAD3 _UINT32_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UINT32_(1) << 15) + +#define PIN_PD11D_SERCOM6_PAD3 _UINT32_(107) +#define MUX_PD11D_SERCOM6_PAD3 _UINT32_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC07C_SERCOM6_PAD3 _UINT32_(71) +#define MUX_PC07C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UINT32_(1) << 7) + +#define PIN_PC11C_SERCOM6_PAD3 _UINT32_(75) +#define MUX_PC11C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC19C_SERCOM6_PAD3 _UINT32_(83) +#define MUX_PC19C_SERCOM6_PAD3 _UINT32_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UINT32_(1) << 19) + +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _UINT32_(53) +#define MUX_PB21D_SERCOM7_PAD0 _UINT32_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UINT32_(1) << 21) + +#define PIN_PD08C_SERCOM7_PAD0 _UINT32_(104) +#define MUX_PD08C_SERCOM7_PAD0 _UINT32_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UINT32_(1) << 8) + +#define PIN_PB30C_SERCOM7_PAD0 _UINT32_(62) +#define MUX_PB30C_SERCOM7_PAD0 _UINT32_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UINT32_(1) << 30) + +#define PIN_PC12C_SERCOM7_PAD0 _UINT32_(76) +#define MUX_PC12C_SERCOM7_PAD0 _UINT32_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UINT32_(1) << 12) + +#define PIN_PB20D_SERCOM7_PAD1 _UINT32_(52) +#define MUX_PB20D_SERCOM7_PAD1 _UINT32_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UINT32_(1) << 20) + +#define PIN_PD09C_SERCOM7_PAD1 _UINT32_(105) +#define MUX_PD09C_SERCOM7_PAD1 _UINT32_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UINT32_(1) << 9) + +#define PIN_PB31C_SERCOM7_PAD1 _UINT32_(63) +#define MUX_PB31C_SERCOM7_PAD1 _UINT32_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UINT32_(1) << 31) + +#define PIN_PC13C_SERCOM7_PAD1 _UINT32_(77) +#define MUX_PC13C_SERCOM7_PAD1 _UINT32_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UINT32_(1) << 13) + +#define PIN_PB18D_SERCOM7_PAD2 _UINT32_(50) +#define MUX_PB18D_SERCOM7_PAD2 _UINT32_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UINT32_(1) << 18) + +#define PIN_PC10D_SERCOM7_PAD2 _UINT32_(74) +#define MUX_PC10D_SERCOM7_PAD2 _UINT32_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UINT32_(1) << 10) + +#define PIN_PC14C_SERCOM7_PAD2 _UINT32_(78) +#define MUX_PC14C_SERCOM7_PAD2 _UINT32_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UINT32_(1) << 14) + +#define PIN_PD10C_SERCOM7_PAD2 _UINT32_(106) +#define MUX_PD10C_SERCOM7_PAD2 _UINT32_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UINT32_(1) << 10) + +#define PIN_PA30C_SERCOM7_PAD2 _UINT32_(30) +#define MUX_PA30C_SERCOM7_PAD2 _UINT32_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UINT32_(1) << 30) + +#define PIN_PB19D_SERCOM7_PAD3 _UINT32_(51) +#define MUX_PB19D_SERCOM7_PAD3 _UINT32_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UINT32_(1) << 19) + +#define PIN_PC11D_SERCOM7_PAD3 _UINT32_(75) +#define MUX_PC11D_SERCOM7_PAD3 _UINT32_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UINT32_(1) << 11) + +#define PIN_PC15C_SERCOM7_PAD3 _UINT32_(79) +#define MUX_PC15C_SERCOM7_PAD3 _UINT32_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UINT32_(1) << 15) + +#define PIN_PD11C_SERCOM7_PAD3 _UINT32_(107) +#define MUX_PD11C_SERCOM7_PAD3 _UINT32_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UINT32_(1) << 11) + +#define PIN_PA31C_SERCOM7_PAD3 _UINT32_(31) +#define MUX_PA31C_SERCOM7_PAD3 _UINT32_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UINT32_(1) << 31) + +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _UINT32_(4) +#define MUX_PA04E_TC0_WO0 _UINT32_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UINT32_(1) << 4) + +#define PIN_PA08E_TC0_WO0 _UINT32_(8) +#define MUX_PA08E_TC0_WO0 _UINT32_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UINT32_(1) << 8) + +#define PIN_PB30E_TC0_WO0 _UINT32_(62) +#define MUX_PB30E_TC0_WO0 _UINT32_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UINT32_(1) << 30) + +#define PIN_PA05E_TC0_WO1 _UINT32_(5) +#define MUX_PA05E_TC0_WO1 _UINT32_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UINT32_(1) << 5) + +#define PIN_PA09E_TC0_WO1 _UINT32_(9) +#define MUX_PA09E_TC0_WO1 _UINT32_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UINT32_(1) << 9) + +#define PIN_PB31E_TC0_WO1 _UINT32_(63) +#define MUX_PB31E_TC0_WO1 _UINT32_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UINT32_(1) << 31) + +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _UINT32_(6) +#define MUX_PA06E_TC1_WO0 _UINT32_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UINT32_(1) << 6) + +#define PIN_PA10E_TC1_WO0 _UINT32_(10) +#define MUX_PA10E_TC1_WO0 _UINT32_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UINT32_(1) << 10) + +#define PIN_PA07E_TC1_WO1 _UINT32_(7) +#define MUX_PA07E_TC1_WO1 _UINT32_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UINT32_(1) << 7) + +#define PIN_PA11E_TC1_WO1 _UINT32_(11) +#define MUX_PA11E_TC1_WO1 _UINT32_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UINT32_(1) << 11) + +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _UINT32_(12) +#define MUX_PA12E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UINT32_(1) << 12) + +#define PIN_PA16E_TC2_WO0 _UINT32_(16) +#define MUX_PA16E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UINT32_(1) << 16) + +#define PIN_PA00E_TC2_WO0 _UINT32_(0) +#define MUX_PA00E_TC2_WO0 _UINT32_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UINT32_(1) << 0) + +#define PIN_PA01E_TC2_WO1 _UINT32_(1) +#define MUX_PA01E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UINT32_(1) << 1) + +#define PIN_PA13E_TC2_WO1 _UINT32_(13) +#define MUX_PA13E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UINT32_(1) << 13) + +#define PIN_PA17E_TC2_WO1 _UINT32_(17) +#define MUX_PA17E_TC2_WO1 _UINT32_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _UINT32_(18) +#define MUX_PA18E_TC3_WO0 _UINT32_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UINT32_(1) << 18) + +#define PIN_PA14E_TC3_WO0 _UINT32_(14) +#define MUX_PA14E_TC3_WO0 _UINT32_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UINT32_(1) << 14) + +#define PIN_PA15E_TC3_WO1 _UINT32_(15) +#define MUX_PA15E_TC3_WO1 _UINT32_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UINT32_(1) << 15) + +#define PIN_PA19E_TC3_WO1 _UINT32_(19) +#define MUX_PA19E_TC3_WO1 _UINT32_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UINT32_(1) << 19) + +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _UINT32_(22) +#define MUX_PA22E_TC4_WO0 _UINT32_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UINT32_(1) << 22) + +#define PIN_PB08E_TC4_WO0 _UINT32_(40) +#define MUX_PB08E_TC4_WO0 _UINT32_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UINT32_(1) << 8) + +#define PIN_PB12E_TC4_WO0 _UINT32_(44) +#define MUX_PB12E_TC4_WO0 _UINT32_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UINT32_(1) << 12) + +#define PIN_PA23E_TC4_WO1 _UINT32_(23) +#define MUX_PA23E_TC4_WO1 _UINT32_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UINT32_(1) << 23) + +#define PIN_PB09E_TC4_WO1 _UINT32_(41) +#define MUX_PB09E_TC4_WO1 _UINT32_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UINT32_(1) << 9) + +#define PIN_PB13E_TC4_WO1 _UINT32_(45) +#define MUX_PB13E_TC4_WO1 _UINT32_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UINT32_(1) << 13) + +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _UINT32_(24) +#define MUX_PA24E_TC5_WO0 _UINT32_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UINT32_(1) << 24) + +#define PIN_PB10E_TC5_WO0 _UINT32_(42) +#define MUX_PB10E_TC5_WO0 _UINT32_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UINT32_(1) << 10) + +#define PIN_PB14E_TC5_WO0 _UINT32_(46) +#define MUX_PB14E_TC5_WO0 _UINT32_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UINT32_(1) << 14) + +#define PIN_PA25E_TC5_WO1 _UINT32_(25) +#define MUX_PA25E_TC5_WO1 _UINT32_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UINT32_(1) << 25) + +#define PIN_PB11E_TC5_WO1 _UINT32_(43) +#define MUX_PB11E_TC5_WO1 _UINT32_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UINT32_(1) << 11) + +#define PIN_PB15E_TC5_WO1 _UINT32_(47) +#define MUX_PB15E_TC5_WO1 _UINT32_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UINT32_(1) << 15) + +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _UINT32_(30) +#define MUX_PA30E_TC6_WO0 _UINT32_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UINT32_(1) << 30) + +#define PIN_PB02E_TC6_WO0 _UINT32_(34) +#define MUX_PB02E_TC6_WO0 _UINT32_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UINT32_(1) << 2) + +#define PIN_PB16E_TC6_WO0 _UINT32_(48) +#define MUX_PB16E_TC6_WO0 _UINT32_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UINT32_(1) << 16) + +#define PIN_PA31E_TC6_WO1 _UINT32_(31) +#define MUX_PA31E_TC6_WO1 _UINT32_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UINT32_(1) << 31) + +#define PIN_PB03E_TC6_WO1 _UINT32_(35) +#define MUX_PB03E_TC6_WO1 _UINT32_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UINT32_(1) << 3) + +#define PIN_PB17E_TC6_WO1 _UINT32_(49) +#define MUX_PB17E_TC6_WO1 _UINT32_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _UINT32_(20) +#define MUX_PA20E_TC7_WO0 _UINT32_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UINT32_(1) << 20) + +#define PIN_PB00E_TC7_WO0 _UINT32_(32) +#define MUX_PB00E_TC7_WO0 _UINT32_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UINT32_(1) << 0) + +#define PIN_PB22E_TC7_WO0 _UINT32_(54) +#define MUX_PB22E_TC7_WO0 _UINT32_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UINT32_(1) << 22) + +#define PIN_PA21E_TC7_WO1 _UINT32_(21) +#define MUX_PA21E_TC7_WO1 _UINT32_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UINT32_(1) << 21) + +#define PIN_PB01E_TC7_WO1 _UINT32_(33) +#define MUX_PB01E_TC7_WO1 _UINT32_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UINT32_(1) << 1) + +#define PIN_PB23E_TC7_WO1 _UINT32_(55) +#define MUX_PB23E_TC7_WO1 _UINT32_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UINT32_(1) << 23) + +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _UINT32_(20) +#define MUX_PA20G_TCC0_WO0 _UINT32_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UINT32_(1) << 20) + +#define PIN_PB12G_TCC0_WO0 _UINT32_(44) +#define MUX_PB12G_TCC0_WO0 _UINT32_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UINT32_(1) << 12) + +#define PIN_PA08F_TCC0_WO0 _UINT32_(8) +#define MUX_PA08F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UINT32_(1) << 8) + +#define PIN_PC04F_TCC0_WO0 _UINT32_(68) +#define MUX_PC04F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UINT32_(1) << 4) + +#define PIN_PC10F_TCC0_WO0 _UINT32_(74) +#define MUX_PC10F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UINT32_(1) << 10) + +#define PIN_PC16F_TCC0_WO0 _UINT32_(80) +#define MUX_PC16F_TCC0_WO0 _UINT32_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UINT32_(1) << 16) + +#define PIN_PA21G_TCC0_WO1 _UINT32_(21) +#define MUX_PA21G_TCC0_WO1 _UINT32_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UINT32_(1) << 21) + +#define PIN_PB13G_TCC0_WO1 _UINT32_(45) +#define MUX_PB13G_TCC0_WO1 _UINT32_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UINT32_(1) << 13) + +#define PIN_PA09F_TCC0_WO1 _UINT32_(9) +#define MUX_PA09F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UINT32_(1) << 9) + +#define PIN_PC11F_TCC0_WO1 _UINT32_(75) +#define MUX_PC11F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UINT32_(1) << 11) + +#define PIN_PC17F_TCC0_WO1 _UINT32_(81) +#define MUX_PC17F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UINT32_(1) << 17) + +#define PIN_PD08F_TCC0_WO1 _UINT32_(104) +#define MUX_PD08F_TCC0_WO1 _UINT32_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UINT32_(1) << 8) + +#define PIN_PA22G_TCC0_WO2 _UINT32_(22) +#define MUX_PA22G_TCC0_WO2 _UINT32_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UINT32_(1) << 22) + +#define PIN_PB14G_TCC0_WO2 _UINT32_(46) +#define MUX_PB14G_TCC0_WO2 _UINT32_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UINT32_(1) << 14) + +#define PIN_PA10F_TCC0_WO2 _UINT32_(10) +#define MUX_PA10F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UINT32_(1) << 10) + +#define PIN_PC12F_TCC0_WO2 _UINT32_(76) +#define MUX_PC12F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UINT32_(1) << 12) + +#define PIN_PC18F_TCC0_WO2 _UINT32_(82) +#define MUX_PC18F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UINT32_(1) << 18) + +#define PIN_PD09F_TCC0_WO2 _UINT32_(105) +#define MUX_PD09F_TCC0_WO2 _UINT32_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UINT32_(1) << 9) + +#define PIN_PA23G_TCC0_WO3 _UINT32_(23) +#define MUX_PA23G_TCC0_WO3 _UINT32_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UINT32_(1) << 23) + +#define PIN_PB15G_TCC0_WO3 _UINT32_(47) +#define MUX_PB15G_TCC0_WO3 _UINT32_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UINT32_(1) << 15) + +#define PIN_PA11F_TCC0_WO3 _UINT32_(11) +#define MUX_PA11F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UINT32_(1) << 11) + +#define PIN_PC13F_TCC0_WO3 _UINT32_(77) +#define MUX_PC13F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UINT32_(1) << 13) + +#define PIN_PC19F_TCC0_WO3 _UINT32_(83) +#define MUX_PC19F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UINT32_(1) << 19) + +#define PIN_PD10F_TCC0_WO3 _UINT32_(106) +#define MUX_PD10F_TCC0_WO3 _UINT32_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UINT32_(1) << 10) + +#define PIN_PA16G_TCC0_WO4 _UINT32_(16) +#define MUX_PA16G_TCC0_WO4 _UINT32_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UINT32_(1) << 16) + +#define PIN_PB16G_TCC0_WO4 _UINT32_(48) +#define MUX_PB16G_TCC0_WO4 _UINT32_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UINT32_(1) << 16) + +#define PIN_PB10F_TCC0_WO4 _UINT32_(42) +#define MUX_PB10F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UINT32_(1) << 10) + +#define PIN_PC14F_TCC0_WO4 _UINT32_(78) +#define MUX_PC14F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UINT32_(1) << 14) + +#define PIN_PC20F_TCC0_WO4 _UINT32_(84) +#define MUX_PC20F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UINT32_(1) << 20) + +#define PIN_PD11F_TCC0_WO4 _UINT32_(107) +#define MUX_PD11F_TCC0_WO4 _UINT32_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UINT32_(1) << 11) + +#define PIN_PA17G_TCC0_WO5 _UINT32_(17) +#define MUX_PA17G_TCC0_WO5 _UINT32_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UINT32_(1) << 17) + +#define PIN_PB17G_TCC0_WO5 _UINT32_(49) +#define MUX_PB17G_TCC0_WO5 _UINT32_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UINT32_(1) << 17) + +#define PIN_PB11F_TCC0_WO5 _UINT32_(43) +#define MUX_PB11F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UINT32_(1) << 11) + +#define PIN_PC15F_TCC0_WO5 _UINT32_(79) +#define MUX_PC15F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UINT32_(1) << 15) + +#define PIN_PC21F_TCC0_WO5 _UINT32_(85) +#define MUX_PC21F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UINT32_(1) << 21) + +#define PIN_PD12F_TCC0_WO5 _UINT32_(108) +#define MUX_PD12F_TCC0_WO5 _UINT32_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UINT32_(1) << 12) + +#define PIN_PA18G_TCC0_WO6 _UINT32_(18) +#define MUX_PA18G_TCC0_WO6 _UINT32_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UINT32_(1) << 18) + +#define PIN_PB30G_TCC0_WO6 _UINT32_(62) +#define MUX_PB30G_TCC0_WO6 _UINT32_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UINT32_(1) << 30) + +#define PIN_PA12F_TCC0_WO6 _UINT32_(12) +#define MUX_PA12F_TCC0_WO6 _UINT32_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UINT32_(1) << 12) + +#define PIN_PC22F_TCC0_WO6 _UINT32_(86) +#define MUX_PC22F_TCC0_WO6 _UINT32_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UINT32_(1) << 22) + +#define PIN_PA19G_TCC0_WO7 _UINT32_(19) +#define MUX_PA19G_TCC0_WO7 _UINT32_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UINT32_(1) << 19) + +#define PIN_PB31G_TCC0_WO7 _UINT32_(63) +#define MUX_PB31G_TCC0_WO7 _UINT32_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UINT32_(1) << 31) + +#define PIN_PA13F_TCC0_WO7 _UINT32_(13) +#define MUX_PA13F_TCC0_WO7 _UINT32_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UINT32_(1) << 13) + +#define PIN_PC23F_TCC0_WO7 _UINT32_(87) +#define MUX_PC23F_TCC0_WO7 _UINT32_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UINT32_(1) << 23) + +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _UINT32_(42) +#define MUX_PB10G_TCC1_WO0 _UINT32_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UINT32_(1) << 10) + +#define PIN_PC14G_TCC1_WO0 _UINT32_(78) +#define MUX_PC14G_TCC1_WO0 _UINT32_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UINT32_(1) << 14) + +#define PIN_PA16F_TCC1_WO0 _UINT32_(16) +#define MUX_PA16F_TCC1_WO0 _UINT32_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UINT32_(1) << 16) + +#define PIN_PB18F_TCC1_WO0 _UINT32_(50) +#define MUX_PB18F_TCC1_WO0 _UINT32_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UINT32_(1) << 18) + +#define PIN_PD20F_TCC1_WO0 _UINT32_(116) +#define MUX_PD20F_TCC1_WO0 _UINT32_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UINT32_(1) << 20) + +#define PIN_PB11G_TCC1_WO1 _UINT32_(43) +#define MUX_PB11G_TCC1_WO1 _UINT32_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UINT32_(1) << 11) + +#define PIN_PC15G_TCC1_WO1 _UINT32_(79) +#define MUX_PC15G_TCC1_WO1 _UINT32_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UINT32_(1) << 15) + +#define PIN_PA17F_TCC1_WO1 _UINT32_(17) +#define MUX_PA17F_TCC1_WO1 _UINT32_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UINT32_(1) << 17) + +#define PIN_PB19F_TCC1_WO1 _UINT32_(51) +#define MUX_PB19F_TCC1_WO1 _UINT32_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UINT32_(1) << 19) + +#define PIN_PD21F_TCC1_WO1 _UINT32_(117) +#define MUX_PD21F_TCC1_WO1 _UINT32_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UINT32_(1) << 21) + +#define PIN_PA12G_TCC1_WO2 _UINT32_(12) +#define MUX_PA12G_TCC1_WO2 _UINT32_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UINT32_(1) << 12) + +#define PIN_PA14G_TCC1_WO2 _UINT32_(14) +#define MUX_PA14G_TCC1_WO2 _UINT32_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UINT32_(1) << 14) + +#define PIN_PA18F_TCC1_WO2 _UINT32_(18) +#define MUX_PA18F_TCC1_WO2 _UINT32_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UINT32_(1) << 18) + +#define PIN_PB20F_TCC1_WO2 _UINT32_(52) +#define MUX_PB20F_TCC1_WO2 _UINT32_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UINT32_(1) << 20) + +#define PIN_PB26F_TCC1_WO2 _UINT32_(58) +#define MUX_PB26F_TCC1_WO2 _UINT32_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UINT32_(1) << 26) + +#define PIN_PA13G_TCC1_WO3 _UINT32_(13) +#define MUX_PA13G_TCC1_WO3 _UINT32_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UINT32_(1) << 13) + +#define PIN_PA15G_TCC1_WO3 _UINT32_(15) +#define MUX_PA15G_TCC1_WO3 _UINT32_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UINT32_(1) << 15) + +#define PIN_PA19F_TCC1_WO3 _UINT32_(19) +#define MUX_PA19F_TCC1_WO3 _UINT32_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UINT32_(1) << 19) + +#define PIN_PB21F_TCC1_WO3 _UINT32_(53) +#define MUX_PB21F_TCC1_WO3 _UINT32_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UINT32_(1) << 21) + +#define PIN_PB27F_TCC1_WO3 _UINT32_(59) +#define MUX_PB27F_TCC1_WO3 _UINT32_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UINT32_(1) << 27) + +#define PIN_PA08G_TCC1_WO4 _UINT32_(8) +#define MUX_PA08G_TCC1_WO4 _UINT32_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UINT32_(1) << 8) + +#define PIN_PC10G_TCC1_WO4 _UINT32_(74) +#define MUX_PC10G_TCC1_WO4 _UINT32_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UINT32_(1) << 10) + +#define PIN_PA20F_TCC1_WO4 _UINT32_(20) +#define MUX_PA20F_TCC1_WO4 _UINT32_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UINT32_(1) << 20) + +#define PIN_PB28F_TCC1_WO4 _UINT32_(60) +#define MUX_PB28F_TCC1_WO4 _UINT32_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UINT32_(1) << 28) + +#define PIN_PA09G_TCC1_WO5 _UINT32_(9) +#define MUX_PA09G_TCC1_WO5 _UINT32_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UINT32_(1) << 9) + +#define PIN_PC11G_TCC1_WO5 _UINT32_(75) +#define MUX_PC11G_TCC1_WO5 _UINT32_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UINT32_(1) << 11) + +#define PIN_PA21F_TCC1_WO5 _UINT32_(21) +#define MUX_PA21F_TCC1_WO5 _UINT32_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UINT32_(1) << 21) + +#define PIN_PB29F_TCC1_WO5 _UINT32_(61) +#define MUX_PB29F_TCC1_WO5 _UINT32_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UINT32_(1) << 29) + +#define PIN_PA10G_TCC1_WO6 _UINT32_(10) +#define MUX_PA10G_TCC1_WO6 _UINT32_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UINT32_(1) << 10) + +#define PIN_PC12G_TCC1_WO6 _UINT32_(76) +#define MUX_PC12G_TCC1_WO6 _UINT32_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UINT32_(1) << 12) + +#define PIN_PA22F_TCC1_WO6 _UINT32_(22) +#define MUX_PA22F_TCC1_WO6 _UINT32_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UINT32_(1) << 22) + +#define PIN_PA11G_TCC1_WO7 _UINT32_(11) +#define MUX_PA11G_TCC1_WO7 _UINT32_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UINT32_(1) << 11) + +#define PIN_PC13G_TCC1_WO7 _UINT32_(77) +#define MUX_PC13G_TCC1_WO7 _UINT32_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UINT32_(1) << 13) + +#define PIN_PA23F_TCC1_WO7 _UINT32_(23) +#define MUX_PA23F_TCC1_WO7 _UINT32_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UINT32_(1) << 23) + +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _UINT32_(14) +#define MUX_PA14F_TCC2_WO0 _UINT32_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UINT32_(1) << 14) + +#define PIN_PA30F_TCC2_WO0 _UINT32_(30) +#define MUX_PA30F_TCC2_WO0 _UINT32_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UINT32_(1) << 30) + +#define PIN_PA15F_TCC2_WO1 _UINT32_(15) +#define MUX_PA15F_TCC2_WO1 _UINT32_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UINT32_(1) << 15) + +#define PIN_PA31F_TCC2_WO1 _UINT32_(31) +#define MUX_PA31F_TCC2_WO1 _UINT32_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UINT32_(1) << 31) + +#define PIN_PA24F_TCC2_WO2 _UINT32_(24) +#define MUX_PA24F_TCC2_WO2 _UINT32_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UINT32_(1) << 24) + +#define PIN_PB02F_TCC2_WO2 _UINT32_(34) +#define MUX_PB02F_TCC2_WO2 _UINT32_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UINT32_(1) << 2) + +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _UINT32_(44) +#define MUX_PB12F_TCC3_WO0 _UINT32_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UINT32_(1) << 12) + +#define PIN_PB16F_TCC3_WO0 _UINT32_(48) +#define MUX_PB16F_TCC3_WO0 _UINT32_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UINT32_(1) << 16) + +#define PIN_PB13F_TCC3_WO1 _UINT32_(45) +#define MUX_PB13F_TCC3_WO1 _UINT32_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UINT32_(1) << 13) + +#define PIN_PB17F_TCC3_WO1 _UINT32_(49) +#define MUX_PB17F_TCC3_WO1 _UINT32_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UINT32_(1) << 17) + +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _UINT32_(46) +#define MUX_PB14F_TCC4_WO0 _UINT32_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UINT32_(1) << 14) + +#define PIN_PB30F_TCC4_WO0 _UINT32_(62) +#define MUX_PB30F_TCC4_WO0 _UINT32_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UINT32_(1) << 30) + +#define PIN_PB15F_TCC4_WO1 _UINT32_(47) +#define MUX_PB15F_TCC4_WO1 _UINT32_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UINT32_(1) << 15) + +#define PIN_PB31F_TCC4_WO1 _UINT32_(63) +#define MUX_PB31F_TCC4_WO1 _UINT32_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UINT32_(1) << 31) + +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _UINT32_(24) +#define MUX_PA24H_USB_DM _UINT32_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UINT32_(1) << 24) + +#define PIN_PA25H_USB_DP _UINT32_(25) +#define MUX_PA25H_USB_DP _UINT32_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UINT32_(1) << 25) + +#define PIN_PA23H_USB_SOF_1KHZ _UINT32_(23) +#define MUX_PA23H_USB_SOF_1KHZ _UINT32_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UINT32_(1) << 23) + +#define PIN_PB22H_USB_SOF_1KHZ _UINT32_(54) +#define MUX_PB22H_USB_SOF_1KHZ _UINT32_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UINT32_(1) << 22) + +/* ========== PORT definition for TPIU peripheral ========== */ +#define PIN_PC27H_TPIU_TRACECLK _UINT32_(91) +#define MUX_PC27H_TPIU_TRACECLK _UINT32_(7) +#define PINMUX_PC27H_TPIU_TRACECLK ((PIN_PC27H_TPIU_TRACECLK << 16) | MUX_PC27H_TPIU_TRACECLK) +#define PORT_PC27H_TPIU_TRACECLK (_UINT32_(1) << 27) + +#define PIN_PC28H_TPIU_TRACED0 _UINT32_(92) +#define MUX_PC28H_TPIU_TRACED0 _UINT32_(7) +#define PINMUX_PC28H_TPIU_TRACED0 ((PIN_PC28H_TPIU_TRACED0 << 16) | MUX_PC28H_TPIU_TRACED0) +#define PORT_PC28H_TPIU_TRACED0 (_UINT32_(1) << 28) + +#define PIN_PC26H_TPIU_TRACED1 _UINT32_(90) +#define MUX_PC26H_TPIU_TRACED1 _UINT32_(7) +#define PINMUX_PC26H_TPIU_TRACED1 ((PIN_PC26H_TPIU_TRACED1 << 16) | MUX_PC26H_TPIU_TRACED1) +#define PORT_PC26H_TPIU_TRACED1 (_UINT32_(1) << 26) + +#define PIN_PC25H_TPIU_TRACED2 _UINT32_(89) +#define MUX_PC25H_TPIU_TRACED2 _UINT32_(7) +#define PINMUX_PC25H_TPIU_TRACED2 ((PIN_PC25H_TPIU_TRACED2 << 16) | MUX_PC25H_TPIU_TRACED2) +#define PORT_PC25H_TPIU_TRACED2 (_UINT32_(1) << 25) + +#define PIN_PC24H_TPIU_TRACED3 _UINT32_(88) +#define MUX_PC24H_TPIU_TRACED3 _UINT32_(7) +#define PINMUX_PC24H_TPIU_TRACED3 ((PIN_PC24H_TPIU_TRACED3 << 16) | MUX_PC24H_TPIU_TRACED3) +#define PORT_PC24H_TPIU_TRACED3 (_UINT32_(1) << 24) + + + +#endif /* _SAME54P20A_GPIO_H_ */ + diff --git a/os/common/ext/Microchip/SAME54/sam.h b/os/common/ext/Microchip/SAME54/sam.h new file mode 100644 index 0000000000..bb4d128e4c --- /dev/null +++ b/os/common/ext/Microchip/SAME54/sam.h @@ -0,0 +1,36 @@ +/* + * Top level header file + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef _SAM_H_ +#define _SAM_H_ + +#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__) + #include "same54n19a.h" +#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__) + #include "same54n20a.h" +#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__) + #include "same54p19a.h" +#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__) + #include "same54p20a.h" +#else + #error Library does not support the specified device +#endif + +#endif /* _SAM_H_ */ + diff --git a/os/common/ext/Microchip/SAME54/same54n19a.h b/os/common/ext/Microchip/SAME54/same54n19a.h new file mode 100644 index 0000000000..9540e580b5 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/same54n19a.h @@ -0,0 +1,1135 @@ +/* + * Header file for ATSAME54N19A + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* File generated from device description file (ATDF) version 2023-03-17T09:50:05Z */ +#ifndef _SAME54N19A_H_ +#define _SAME54N19A_H_ + +/* Header version uses Semantic Versioning 2.0.0 (https://semver.org/) */ +#define HEADER_FORMAT_VERSION "2.1.1" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (1) +#define HEADER_FORMAT_VERSION_PATCH (1) + +/* SAME54N19A definitions + This file defines all structures and symbols for SAME54N19A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_) +# error "Integer constant value macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with sizes of integer constants for C/C++ */ +# define _UINT8_(x) ((uint8_t)(x)) /* C code: 8-bits unsigned integer constant value */ +# define _UINT16_(x) ((uint16_t)(x)) /* C code: 16-bits unsigned integer constant value */ +# define _UINT32_(x) ((uint32_t)(x)) /* C code: 32-bits unsigned integer constant value */ + +#else /* Assembler */ + +# define _UINT8_(x) x /* Assembler: 8-bits unsigned integer constant value */ +# define _UINT16_(x) x /* Assembler: 16-bits unsigned integer constant value */ +# define _UINT32_(x) x /* Assembler: 32-bits unsigned integer constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* -4 Debug Monitor */ + PendSV_IRQn = -2, /* -2 Pendable request for system service */ + SysTick_IRQn = -1, /* -1 System Tick Timer */ + +/****** SAME54N19A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /* 0 Power Manager (PM) */ + MCLK_IRQn = 1, /* 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /* 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /* 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /* 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /* 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /* 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /* 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /* 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /* 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /* 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /* 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /* 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /* 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /* 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /* 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /* 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /* 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /* 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /* 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /* 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /* 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /* 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /* 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /* 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /* 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /* 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /* 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /* 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /* 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /* 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /* 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /* 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /* 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /* 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /* 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /* 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /* 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /* 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /* 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /* 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /* 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /* 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /* 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /* 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /* 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /* 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /* 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /* 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /* 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /* 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /* 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /* 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /* 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /* 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /* 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /* 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /* 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /* 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /* 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /* 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /* 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /* 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /* 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /* 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /* 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /* 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /* 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /* 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /* 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /* 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /* 77 Serial Communication Interface (SERCOM7) */ + CAN0_IRQn = 78, /* 78 Control Area Network (CAN0) */ + CAN1_IRQn = 79, /* 79 Control Area Network (CAN1) */ + USB_OTHER_IRQn = 80, /* 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /* 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /* 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /* 83 Universal Serial Bus (USB) */ + GMAC_IRQn = 84, /* 84 Ethernet MAC (GMAC) */ + TCC0_OTHER_IRQn = 85, /* 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /* 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /* 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /* 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /* 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /* 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /* 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /* 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /* 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /* 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /* 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /* 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /* 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /* 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /* 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /* 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /* 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /* 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /* 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /* 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /* 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /* 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /* 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /* 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /* 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /* 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /* 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /* 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /* 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /* 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /* 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /* 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /* 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /* 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /* 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /* 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /* 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /* 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /* 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /* 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /* 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /* 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /* 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /* 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /* 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /* 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /* 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /* 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /* 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /* 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /* 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /* Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ + void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /* Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /* Debug Level */ +#define __FPU_PRESENT 1 /* FPU present or not */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /* Trace Level */ +#define __VTOR_PRESENT 1 /* Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* CMSIS includes */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_same54.h" +#endif /* USE_CMSIS_INIT */ + +/* ************************************************************************** */ +/* SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N19A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/fuses.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" + +/* ************************************************************************** */ +/* INSTANCE DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/fuses.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/i2s.h" +#include "instance/icm.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/oscctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /* Instance index for PAC (PAC) */ +#define ID_PM ( 1) /* Instance index for PM (PM) */ +#define ID_MCLK ( 2) /* Instance index for MCLK (MCLK) */ +#define ID_RSTC ( 3) /* Instance index for RSTC (RSTC) */ +#define ID_OSCCTRL ( 4) /* Instance index for OSCCTRL (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /* Instance index for OSC32KCTRL (OSC32KCTRL) */ +#define ID_SUPC ( 6) /* Instance index for SUPC (SUPC) */ +#define ID_GCLK ( 7) /* Instance index for GCLK (GCLK) */ +#define ID_WDT ( 8) /* Instance index for WDT (WDT) */ +#define ID_RTC ( 9) /* Instance index for RTC (RTC) */ +#define ID_EIC ( 10) /* Instance index for EIC (EIC) */ +#define ID_FREQM ( 11) /* Instance index for FREQM (FREQM) */ +#define ID_SERCOM0 ( 12) /* Instance index for SERCOM0 (SERCOM0) */ +#define ID_SERCOM1 ( 13) /* Instance index for SERCOM1 (SERCOM1) */ +#define ID_TC0 ( 14) /* Instance index for TC0 (TC0) */ +#define ID_TC1 ( 15) /* Instance index for TC1 (TC1) */ +#define ID_USB ( 32) /* Instance index for USB (USB) */ +#define ID_DSU ( 33) /* Instance index for DSU (DSU) */ +#define ID_NVMCTRL ( 34) /* Instance index for NVMCTRL (NVMCTRL) */ +#define ID_CMCC ( 35) /* Instance index for CMCC (CMCC) */ +#define ID_PORT ( 36) /* Instance index for PORT (PORT) */ +#define ID_DMAC ( 37) /* Instance index for DMAC (DMAC) */ +#define ID_HMATRIX ( 38) /* Instance index for HMATRIX (HMATRIX) */ +#define ID_EVSYS ( 39) /* Instance index for EVSYS (EVSYS) */ +#define ID_SERCOM2 ( 41) /* Instance index for SERCOM2 (SERCOM2) */ +#define ID_SERCOM3 ( 42) /* Instance index for SERCOM3 (SERCOM3) */ +#define ID_TCC0 ( 43) /* Instance index for TCC0 (TCC0) */ +#define ID_TCC1 ( 44) /* Instance index for TCC1 (TCC1) */ +#define ID_TC2 ( 45) /* Instance index for TC2 (TC2) */ +#define ID_TC3 ( 46) /* Instance index for TC3 (TC3) */ +#define ID_RAMECC ( 48) /* Instance index for RAMECC (RAMECC) */ +#define ID_CAN0 ( 64) /* Instance index for CAN0 (CAN0) */ +#define ID_CAN1 ( 65) /* Instance index for CAN1 (CAN1) */ +#define ID_GMAC ( 66) /* Instance index for GMAC (GMAC) */ +#define ID_TCC2 ( 67) /* Instance index for TCC2 (TCC2) */ +#define ID_TCC3 ( 68) /* Instance index for TCC3 (TCC3) */ +#define ID_TC4 ( 69) /* Instance index for TC4 (TC4) */ +#define ID_TC5 ( 70) /* Instance index for TC5 (TC5) */ +#define ID_PDEC ( 71) /* Instance index for PDEC (PDEC) */ +#define ID_AC ( 72) /* Instance index for AC (AC) */ +#define ID_AES ( 73) /* Instance index for AES (AES) */ +#define ID_TRNG ( 74) /* Instance index for TRNG (TRNG) */ +#define ID_ICM ( 75) /* Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /* Instance index for PUKCC (PUKCC) */ +#define ID_QSPI ( 77) /* Instance index for QSPI (QSPI) */ +#define ID_CCL ( 78) /* Instance index for CCL (CCL) */ +#define ID_SERCOM4 ( 96) /* Instance index for SERCOM4 (SERCOM4) */ +#define ID_SERCOM5 ( 97) /* Instance index for SERCOM5 (SERCOM5) */ +#define ID_SERCOM6 ( 98) /* Instance index for SERCOM6 (SERCOM6) */ +#define ID_SERCOM7 ( 99) /* Instance index for SERCOM7 (SERCOM7) */ +#define ID_TCC4 (100) /* Instance index for TCC4 (TCC4) */ +#define ID_TC6 (101) /* Instance index for TC6 (TC6) */ +#define ID_TC7 (102) /* Instance index for TC7 (TC7) */ +#define ID_ADC0 (103) /* Instance index for ADC0 (ADC0) */ +#define ID_ADC1 (104) /* Instance index for ADC1 (ADC1) */ +#define ID_DAC (105) /* Instance index for DAC (DAC) */ +#define ID_I2S (106) /* Instance index for I2S (I2S) */ +#define ID_PCC (107) /* Instance index for PCC (PCC) */ + +#define ID_PERIPH_MAX (107) /* Number of peripheral IDs */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /* AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /* ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /* ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /* AES Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42000000) /* CAN0 Registers Address */ +#define CAN1_REGS ((can_registers_t*)0x42000400) /* CAN1 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /* CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /* CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /* DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /* DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /* DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /* EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /* EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /* FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /* GCLK Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x42000800) /* GMAC Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /* HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /* ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /* I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /* MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /* NVMCTRL Registers Address */ +#define SW0_FUSES_REGS ((fuses_sw0_fuses_registers_t*)0x00800080) /* FUSES Registers Address */ +#define TEMP_LOG_FUSES_REGS ((fuses_temp_log_fuses_registers_t*)0x00800100) /* FUSES Registers Address */ +#define USER_FUSES_REGS ((fuses_user_fuses_registers_t*)0x00804000) /* FUSES Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /* OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /* OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /* PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /* PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /* PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /* PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /* PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /* QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /* RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /* RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /* RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /* SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /* SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /* SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /* SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /* SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /* SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /* SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /* SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /* SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /* SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /* SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /* TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /* TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /* TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /* TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /* TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /* TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /* TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /* TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /* TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /* TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /* TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /* TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /* TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /* TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /* USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /* WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UINT32_(0x42002000) /* AC Base Address */ +#define ADC0_BASE_ADDRESS _UINT32_(0x43001c00) /* ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UINT32_(0x43002000) /* ADC1 Base Address */ +#define AES_BASE_ADDRESS _UINT32_(0x42002400) /* AES Base Address */ +#define CAN0_BASE_ADDRESS _UINT32_(0x42000000) /* CAN0 Base Address */ +#define CAN1_BASE_ADDRESS _UINT32_(0x42000400) /* CAN1 Base Address */ +#define CCL_BASE_ADDRESS _UINT32_(0x42003800) /* CCL Base Address */ +#define CMCC_BASE_ADDRESS _UINT32_(0x41006000) /* CMCC Base Address */ +#define DAC_BASE_ADDRESS _UINT32_(0x43002400) /* DAC Base Address */ +#define DMAC_BASE_ADDRESS _UINT32_(0x4100a000) /* DMAC Base Address */ +#define DSU_BASE_ADDRESS _UINT32_(0x41002000) /* DSU Base Address */ +#define EIC_BASE_ADDRESS _UINT32_(0x40002800) /* EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UINT32_(0x4100e000) /* EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UINT32_(0x40002c00) /* FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UINT32_(0x40001c00) /* GCLK Base Address */ +#define GMAC_BASE_ADDRESS _UINT32_(0x42000800) /* GMAC Base Address */ +#define HMATRIX_BASE_ADDRESS _UINT32_(0x4100c000) /* HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UINT32_(0x42002c00) /* ICM Base Address */ +#define I2S_BASE_ADDRESS _UINT32_(0x43002800) /* I2S Base Address */ +#define MCLK_BASE_ADDRESS _UINT32_(0x40000800) /* MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UINT32_(0x41004000) /* NVMCTRL Base Address */ +#define SW0_FUSES_BASE_ADDRESS _UINT32_(0x00800080) /* FUSES Base Address */ +#define TEMP_LOG_FUSES_BASE_ADDRESS _UINT32_(0x00800100) /* FUSES Base Address */ +#define USER_FUSES_BASE_ADDRESS _UINT32_(0x00804000) /* FUSES Base Address */ +#define OSCCTRL_BASE_ADDRESS _UINT32_(0x40001000) /* OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UINT32_(0x40001400) /* OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UINT32_(0x40000000) /* PAC Base Address */ +#define PCC_BASE_ADDRESS _UINT32_(0x43002c00) /* PCC Base Address */ +#define PDEC_BASE_ADDRESS _UINT32_(0x42001c00) /* PDEC Base Address */ +#define PM_BASE_ADDRESS _UINT32_(0x40000400) /* PM Base Address */ +#define PORT_BASE_ADDRESS _UINT32_(0x41008000) /* PORT Base Address */ +#define QSPI_BASE_ADDRESS _UINT32_(0x42003400) /* QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UINT32_(0x41020000) /* RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UINT32_(0x40000c00) /* RSTC Base Address */ +#define RTC_BASE_ADDRESS _UINT32_(0x40002400) /* RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UINT32_(0x45000000) /* SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UINT32_(0x46000000) /* SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UINT32_(0x40003000) /* SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UINT32_(0x40003400) /* SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UINT32_(0x41012000) /* SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UINT32_(0x41014000) /* SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UINT32_(0x43000000) /* SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UINT32_(0x43000400) /* SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UINT32_(0x43000800) /* SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UINT32_(0x43000c00) /* SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UINT32_(0x40001800) /* SUPC Base Address */ +#define TC0_BASE_ADDRESS _UINT32_(0x40003800) /* TC0 Base Address */ +#define TC1_BASE_ADDRESS _UINT32_(0x40003c00) /* TC1 Base Address */ +#define TC2_BASE_ADDRESS _UINT32_(0x4101a000) /* TC2 Base Address */ +#define TC3_BASE_ADDRESS _UINT32_(0x4101c000) /* TC3 Base Address */ +#define TC4_BASE_ADDRESS _UINT32_(0x42001400) /* TC4 Base Address */ +#define TC5_BASE_ADDRESS _UINT32_(0x42001800) /* TC5 Base Address */ +#define TC6_BASE_ADDRESS _UINT32_(0x43001400) /* TC6 Base Address */ +#define TC7_BASE_ADDRESS _UINT32_(0x43001800) /* TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UINT32_(0x41016000) /* TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UINT32_(0x41018000) /* TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UINT32_(0x42000c00) /* TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UINT32_(0x42001000) /* TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UINT32_(0x43001000) /* TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UINT32_(0x42002800) /* TRNG Base Address */ +#define USB_BASE_ADDRESS _UINT32_(0x41000000) /* USB Base Address */ +#define WDT_BASE_ADDRESS _UINT32_(0x40002000) /* WDT Base Address */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#include "pio/same54n19a.h" + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +#define FLASH_SIZE _UINT32_(0x00080000) /* 512kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UINT32_( 512) +#define FLASH_NB_OF_PAGES _UINT32_( 1024) + +#define SW0_SIZE _UINT32_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UINT32_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UINT32_( 512) +#define TEMP_LOG_NB_OF_PAGES _UINT32_( 1) + +#define USER_PAGE_SIZE _UINT32_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UINT32_( 512) +#define USER_PAGE_NB_OF_PAGES _UINT32_( 1) + +#define CMCC_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UINT32_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UINT32_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UINT32_(0x00030000) /* 192kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UINT32_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UINT32_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UINT32_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UINT32_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UINT32_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UINT32_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UINT32_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UINT32_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UINT32_(0x00000000) /* FLASH base address (type: flash)*/ +#define SW0_ADDR _UINT32_(0x00800080) /* SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UINT32_(0x00800100) /* TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UINT32_(0x00804000) /* USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UINT32_(0x03000000) /* CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UINT32_(0x03000000) /* CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UINT32_(0x03001000) /* CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UINT32_(0x03002000) /* CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UINT32_(0x04000000) /* QSPI base address (type: other)*/ +#define HSRAM_ADDR _UINT32_(0x20000000) /* HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UINT32_(0x20000000) /* HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UINT32_(0x20000000) /* HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UINT32_(0x40000000) /* HPB0 base address (type: io)*/ +#define HPB1_ADDR _UINT32_(0x41000000) /* HPB1 base address (type: io)*/ +#define HPB2_ADDR _UINT32_(0x42000000) /* HPB2 base address (type: io)*/ +#define HPB3_ADDR _UINT32_(0x43000000) /* HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UINT32_(0x44000000) /* SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UINT32_(0x45000000) /* SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UINT32_(0x46000000) /* SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UINT32_(0x47000000) /* BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UINT32_(0xe0000000) /* PPB base address (type: io)*/ +#define SCS_ADDR _UINT32_(0xe000e000) /* SCS base address (type: io)*/ + +/* ************************************************************************** */ +/* DEVICE SIGNATURES FOR SAME54N19A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UINT32_(0X61840303) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Event Generator IDs for SAME54N19A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /* ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /* ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /* ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /* ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /* ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /* ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /* ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /* ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /* ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /* ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /* ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /* ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /* ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /* ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /* ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /* ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /* ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /* ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /* ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /* ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /* ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /* ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /* ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /* ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /* ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /* ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /* ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /* ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /* ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /* ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /* ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /* ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /* ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /* ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /* ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /* ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /* ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /* ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /* ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /* ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /* ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /* ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /* ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /* ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /* ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /* ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /* ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /* ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /* ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /* ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /* ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /* ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /* ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /* ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /* ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /* ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /* ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /* ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /* ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /* ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /* ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /* ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /* ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /* ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /* ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /* ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /* ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /* ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /* ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /* ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /* ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /* ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /* ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /* ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /* ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /* ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /* ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /* ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /* ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /* ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /* ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /* ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /* ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /* ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /* ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /* ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /* ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /* ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /* ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /* ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /* ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /* ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /* ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /* ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /* ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /* ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /* ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /* ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /* ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /* ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /* ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /* ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /* ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /* ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /* ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /* ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /* ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /* ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /* ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /* ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /* ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /* ID for GMAC event generator TSU_CMP */ +#define EVENT_ID_GEN_TRNG_READY 115 /* ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /* ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /* ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /* ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /* ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/* Event User IDs for SAME54N19A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /* ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /* ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /* ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /* ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /* ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /* ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /* ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /* ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /* ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /* ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /* ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /* ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /* ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /* ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /* ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /* ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /* ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /* ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /* ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /* ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /* ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /* ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /* ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /* ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /* ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /* ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /* ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /* ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /* ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /* ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /* ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /* ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /* ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /* ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /* ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /* ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /* ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /* ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /* ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /* ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /* ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /* ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /* ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /* ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /* ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /* ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /* ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /* ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /* ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /* ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /* ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /* ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /* ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /* ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /* ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /* ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /* ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /* ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /* ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /* ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /* ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /* ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /* ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /* ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /* ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /* ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SAME54N19A_H_ */ + diff --git a/os/common/ext/Microchip/SAME54/same54n20a.h b/os/common/ext/Microchip/SAME54/same54n20a.h new file mode 100644 index 0000000000..6ad2a5d2e3 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/same54n20a.h @@ -0,0 +1,1135 @@ +/* + * Header file for ATSAME54N20A + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* File generated from device description file (ATDF) version 2023-03-17T09:50:06Z */ +#ifndef _SAME54N20A_H_ +#define _SAME54N20A_H_ + +/* Header version uses Semantic Versioning 2.0.0 (https://semver.org/) */ +#define HEADER_FORMAT_VERSION "2.1.1" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (1) +#define HEADER_FORMAT_VERSION_PATCH (1) + +/* SAME54N20A definitions + This file defines all structures and symbols for SAME54N20A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_) +# error "Integer constant value macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with sizes of integer constants for C/C++ */ +# define _UINT8_(x) ((uint8_t)(x)) /* C code: 8-bits unsigned integer constant value */ +# define _UINT16_(x) ((uint16_t)(x)) /* C code: 16-bits unsigned integer constant value */ +# define _UINT32_(x) ((uint32_t)(x)) /* C code: 32-bits unsigned integer constant value */ + +#else /* Assembler */ + +# define _UINT8_(x) x /* Assembler: 8-bits unsigned integer constant value */ +# define _UINT16_(x) x /* Assembler: 16-bits unsigned integer constant value */ +# define _UINT32_(x) x /* Assembler: 32-bits unsigned integer constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* -4 Debug Monitor */ + PendSV_IRQn = -2, /* -2 Pendable request for system service */ + SysTick_IRQn = -1, /* -1 System Tick Timer */ + +/****** SAME54N20A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /* 0 Power Manager (PM) */ + MCLK_IRQn = 1, /* 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /* 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /* 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /* 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /* 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /* 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /* 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /* 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /* 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /* 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /* 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /* 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /* 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /* 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /* 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /* 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /* 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /* 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /* 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /* 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /* 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /* 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /* 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /* 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /* 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /* 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /* 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /* 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /* 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /* 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /* 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /* 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /* 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /* 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /* 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /* 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /* 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /* 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /* 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /* 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /* 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /* 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /* 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /* 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /* 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /* 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /* 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /* 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /* 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /* 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /* 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /* 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /* 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /* 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /* 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /* 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /* 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /* 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /* 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /* 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /* 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /* 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /* 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /* 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /* 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /* 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /* 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /* 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /* 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /* 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /* 77 Serial Communication Interface (SERCOM7) */ + CAN0_IRQn = 78, /* 78 Control Area Network (CAN0) */ + CAN1_IRQn = 79, /* 79 Control Area Network (CAN1) */ + USB_OTHER_IRQn = 80, /* 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /* 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /* 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /* 83 Universal Serial Bus (USB) */ + GMAC_IRQn = 84, /* 84 Ethernet MAC (GMAC) */ + TCC0_OTHER_IRQn = 85, /* 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /* 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /* 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /* 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /* 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /* 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /* 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /* 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /* 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /* 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /* 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /* 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /* 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /* 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /* 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /* 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /* 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /* 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /* 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /* 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /* 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /* 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /* 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /* 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /* 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /* 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /* 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /* 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /* 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /* 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /* 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /* 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /* 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /* 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /* 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /* 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /* 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /* 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /* 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /* 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /* 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /* 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /* 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /* 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /* 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /* 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /* 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /* 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /* 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /* 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /* 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /* Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ + void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /* Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /* Debug Level */ +#define __FPU_PRESENT 1 /* FPU present or not */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /* Trace Level */ +#define __VTOR_PRESENT 1 /* Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* CMSIS includes */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_same54.h" +#endif /* USE_CMSIS_INIT */ + +/* ************************************************************************** */ +/* SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N20A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/fuses.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" + +/* ************************************************************************** */ +/* INSTANCE DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/fuses.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/i2s.h" +#include "instance/icm.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/oscctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /* Instance index for PAC (PAC) */ +#define ID_PM ( 1) /* Instance index for PM (PM) */ +#define ID_MCLK ( 2) /* Instance index for MCLK (MCLK) */ +#define ID_RSTC ( 3) /* Instance index for RSTC (RSTC) */ +#define ID_OSCCTRL ( 4) /* Instance index for OSCCTRL (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /* Instance index for OSC32KCTRL (OSC32KCTRL) */ +#define ID_SUPC ( 6) /* Instance index for SUPC (SUPC) */ +#define ID_GCLK ( 7) /* Instance index for GCLK (GCLK) */ +#define ID_WDT ( 8) /* Instance index for WDT (WDT) */ +#define ID_RTC ( 9) /* Instance index for RTC (RTC) */ +#define ID_EIC ( 10) /* Instance index for EIC (EIC) */ +#define ID_FREQM ( 11) /* Instance index for FREQM (FREQM) */ +#define ID_SERCOM0 ( 12) /* Instance index for SERCOM0 (SERCOM0) */ +#define ID_SERCOM1 ( 13) /* Instance index for SERCOM1 (SERCOM1) */ +#define ID_TC0 ( 14) /* Instance index for TC0 (TC0) */ +#define ID_TC1 ( 15) /* Instance index for TC1 (TC1) */ +#define ID_USB ( 32) /* Instance index for USB (USB) */ +#define ID_DSU ( 33) /* Instance index for DSU (DSU) */ +#define ID_NVMCTRL ( 34) /* Instance index for NVMCTRL (NVMCTRL) */ +#define ID_CMCC ( 35) /* Instance index for CMCC (CMCC) */ +#define ID_PORT ( 36) /* Instance index for PORT (PORT) */ +#define ID_DMAC ( 37) /* Instance index for DMAC (DMAC) */ +#define ID_HMATRIX ( 38) /* Instance index for HMATRIX (HMATRIX) */ +#define ID_EVSYS ( 39) /* Instance index for EVSYS (EVSYS) */ +#define ID_SERCOM2 ( 41) /* Instance index for SERCOM2 (SERCOM2) */ +#define ID_SERCOM3 ( 42) /* Instance index for SERCOM3 (SERCOM3) */ +#define ID_TCC0 ( 43) /* Instance index for TCC0 (TCC0) */ +#define ID_TCC1 ( 44) /* Instance index for TCC1 (TCC1) */ +#define ID_TC2 ( 45) /* Instance index for TC2 (TC2) */ +#define ID_TC3 ( 46) /* Instance index for TC3 (TC3) */ +#define ID_RAMECC ( 48) /* Instance index for RAMECC (RAMECC) */ +#define ID_CAN0 ( 64) /* Instance index for CAN0 (CAN0) */ +#define ID_CAN1 ( 65) /* Instance index for CAN1 (CAN1) */ +#define ID_GMAC ( 66) /* Instance index for GMAC (GMAC) */ +#define ID_TCC2 ( 67) /* Instance index for TCC2 (TCC2) */ +#define ID_TCC3 ( 68) /* Instance index for TCC3 (TCC3) */ +#define ID_TC4 ( 69) /* Instance index for TC4 (TC4) */ +#define ID_TC5 ( 70) /* Instance index for TC5 (TC5) */ +#define ID_PDEC ( 71) /* Instance index for PDEC (PDEC) */ +#define ID_AC ( 72) /* Instance index for AC (AC) */ +#define ID_AES ( 73) /* Instance index for AES (AES) */ +#define ID_TRNG ( 74) /* Instance index for TRNG (TRNG) */ +#define ID_ICM ( 75) /* Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /* Instance index for PUKCC (PUKCC) */ +#define ID_QSPI ( 77) /* Instance index for QSPI (QSPI) */ +#define ID_CCL ( 78) /* Instance index for CCL (CCL) */ +#define ID_SERCOM4 ( 96) /* Instance index for SERCOM4 (SERCOM4) */ +#define ID_SERCOM5 ( 97) /* Instance index for SERCOM5 (SERCOM5) */ +#define ID_SERCOM6 ( 98) /* Instance index for SERCOM6 (SERCOM6) */ +#define ID_SERCOM7 ( 99) /* Instance index for SERCOM7 (SERCOM7) */ +#define ID_TCC4 (100) /* Instance index for TCC4 (TCC4) */ +#define ID_TC6 (101) /* Instance index for TC6 (TC6) */ +#define ID_TC7 (102) /* Instance index for TC7 (TC7) */ +#define ID_ADC0 (103) /* Instance index for ADC0 (ADC0) */ +#define ID_ADC1 (104) /* Instance index for ADC1 (ADC1) */ +#define ID_DAC (105) /* Instance index for DAC (DAC) */ +#define ID_I2S (106) /* Instance index for I2S (I2S) */ +#define ID_PCC (107) /* Instance index for PCC (PCC) */ + +#define ID_PERIPH_MAX (107) /* Number of peripheral IDs */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /* AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /* ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /* ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /* AES Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42000000) /* CAN0 Registers Address */ +#define CAN1_REGS ((can_registers_t*)0x42000400) /* CAN1 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /* CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /* CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /* DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /* DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /* DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /* EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /* EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /* FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /* GCLK Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x42000800) /* GMAC Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /* HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /* ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /* I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /* MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /* NVMCTRL Registers Address */ +#define SW0_FUSES_REGS ((fuses_sw0_fuses_registers_t*)0x00800080) /* FUSES Registers Address */ +#define TEMP_LOG_FUSES_REGS ((fuses_temp_log_fuses_registers_t*)0x00800100) /* FUSES Registers Address */ +#define USER_FUSES_REGS ((fuses_user_fuses_registers_t*)0x00804000) /* FUSES Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /* OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /* OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /* PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /* PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /* PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /* PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /* PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /* QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /* RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /* RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /* RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /* SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /* SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /* SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /* SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /* SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /* SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /* SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /* SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /* SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /* SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /* SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /* TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /* TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /* TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /* TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /* TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /* TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /* TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /* TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /* TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /* TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /* TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /* TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /* TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /* TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /* USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /* WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UINT32_(0x42002000) /* AC Base Address */ +#define ADC0_BASE_ADDRESS _UINT32_(0x43001c00) /* ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UINT32_(0x43002000) /* ADC1 Base Address */ +#define AES_BASE_ADDRESS _UINT32_(0x42002400) /* AES Base Address */ +#define CAN0_BASE_ADDRESS _UINT32_(0x42000000) /* CAN0 Base Address */ +#define CAN1_BASE_ADDRESS _UINT32_(0x42000400) /* CAN1 Base Address */ +#define CCL_BASE_ADDRESS _UINT32_(0x42003800) /* CCL Base Address */ +#define CMCC_BASE_ADDRESS _UINT32_(0x41006000) /* CMCC Base Address */ +#define DAC_BASE_ADDRESS _UINT32_(0x43002400) /* DAC Base Address */ +#define DMAC_BASE_ADDRESS _UINT32_(0x4100a000) /* DMAC Base Address */ +#define DSU_BASE_ADDRESS _UINT32_(0x41002000) /* DSU Base Address */ +#define EIC_BASE_ADDRESS _UINT32_(0x40002800) /* EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UINT32_(0x4100e000) /* EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UINT32_(0x40002c00) /* FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UINT32_(0x40001c00) /* GCLK Base Address */ +#define GMAC_BASE_ADDRESS _UINT32_(0x42000800) /* GMAC Base Address */ +#define HMATRIX_BASE_ADDRESS _UINT32_(0x4100c000) /* HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UINT32_(0x42002c00) /* ICM Base Address */ +#define I2S_BASE_ADDRESS _UINT32_(0x43002800) /* I2S Base Address */ +#define MCLK_BASE_ADDRESS _UINT32_(0x40000800) /* MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UINT32_(0x41004000) /* NVMCTRL Base Address */ +#define SW0_FUSES_BASE_ADDRESS _UINT32_(0x00800080) /* FUSES Base Address */ +#define TEMP_LOG_FUSES_BASE_ADDRESS _UINT32_(0x00800100) /* FUSES Base Address */ +#define USER_FUSES_BASE_ADDRESS _UINT32_(0x00804000) /* FUSES Base Address */ +#define OSCCTRL_BASE_ADDRESS _UINT32_(0x40001000) /* OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UINT32_(0x40001400) /* OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UINT32_(0x40000000) /* PAC Base Address */ +#define PCC_BASE_ADDRESS _UINT32_(0x43002c00) /* PCC Base Address */ +#define PDEC_BASE_ADDRESS _UINT32_(0x42001c00) /* PDEC Base Address */ +#define PM_BASE_ADDRESS _UINT32_(0x40000400) /* PM Base Address */ +#define PORT_BASE_ADDRESS _UINT32_(0x41008000) /* PORT Base Address */ +#define QSPI_BASE_ADDRESS _UINT32_(0x42003400) /* QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UINT32_(0x41020000) /* RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UINT32_(0x40000c00) /* RSTC Base Address */ +#define RTC_BASE_ADDRESS _UINT32_(0x40002400) /* RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UINT32_(0x45000000) /* SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UINT32_(0x46000000) /* SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UINT32_(0x40003000) /* SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UINT32_(0x40003400) /* SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UINT32_(0x41012000) /* SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UINT32_(0x41014000) /* SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UINT32_(0x43000000) /* SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UINT32_(0x43000400) /* SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UINT32_(0x43000800) /* SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UINT32_(0x43000c00) /* SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UINT32_(0x40001800) /* SUPC Base Address */ +#define TC0_BASE_ADDRESS _UINT32_(0x40003800) /* TC0 Base Address */ +#define TC1_BASE_ADDRESS _UINT32_(0x40003c00) /* TC1 Base Address */ +#define TC2_BASE_ADDRESS _UINT32_(0x4101a000) /* TC2 Base Address */ +#define TC3_BASE_ADDRESS _UINT32_(0x4101c000) /* TC3 Base Address */ +#define TC4_BASE_ADDRESS _UINT32_(0x42001400) /* TC4 Base Address */ +#define TC5_BASE_ADDRESS _UINT32_(0x42001800) /* TC5 Base Address */ +#define TC6_BASE_ADDRESS _UINT32_(0x43001400) /* TC6 Base Address */ +#define TC7_BASE_ADDRESS _UINT32_(0x43001800) /* TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UINT32_(0x41016000) /* TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UINT32_(0x41018000) /* TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UINT32_(0x42000c00) /* TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UINT32_(0x42001000) /* TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UINT32_(0x43001000) /* TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UINT32_(0x42002800) /* TRNG Base Address */ +#define USB_BASE_ADDRESS _UINT32_(0x41000000) /* USB Base Address */ +#define WDT_BASE_ADDRESS _UINT32_(0x40002000) /* WDT Base Address */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#include "pio/same54n20a.h" + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +#define FLASH_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UINT32_( 512) +#define FLASH_NB_OF_PAGES _UINT32_( 2048) + +#define SW0_SIZE _UINT32_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UINT32_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UINT32_( 512) +#define TEMP_LOG_NB_OF_PAGES _UINT32_( 1) + +#define USER_PAGE_SIZE _UINT32_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UINT32_( 512) +#define USER_PAGE_NB_OF_PAGES _UINT32_( 1) + +#define CMCC_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UINT32_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UINT32_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UINT32_(0x00040000) /* 256kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UINT32_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UINT32_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UINT32_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UINT32_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UINT32_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UINT32_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UINT32_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UINT32_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UINT32_(0x00000000) /* FLASH base address (type: flash)*/ +#define SW0_ADDR _UINT32_(0x00800080) /* SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UINT32_(0x00800100) /* TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UINT32_(0x00804000) /* USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UINT32_(0x03000000) /* CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UINT32_(0x03000000) /* CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UINT32_(0x03001000) /* CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UINT32_(0x03002000) /* CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UINT32_(0x04000000) /* QSPI base address (type: other)*/ +#define HSRAM_ADDR _UINT32_(0x20000000) /* HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UINT32_(0x20000000) /* HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UINT32_(0x20000000) /* HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UINT32_(0x40000000) /* HPB0 base address (type: io)*/ +#define HPB1_ADDR _UINT32_(0x41000000) /* HPB1 base address (type: io)*/ +#define HPB2_ADDR _UINT32_(0x42000000) /* HPB2 base address (type: io)*/ +#define HPB3_ADDR _UINT32_(0x43000000) /* HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UINT32_(0x44000000) /* SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UINT32_(0x45000000) /* SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UINT32_(0x46000000) /* SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UINT32_(0x47000000) /* BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UINT32_(0xe0000000) /* PPB base address (type: io)*/ +#define SCS_ADDR _UINT32_(0xe000e000) /* SCS base address (type: io)*/ + +/* ************************************************************************** */ +/* DEVICE SIGNATURES FOR SAME54N20A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UINT32_(0X61840302) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Event Generator IDs for SAME54N20A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /* ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /* ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /* ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /* ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /* ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /* ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /* ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /* ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /* ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /* ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /* ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /* ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /* ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /* ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /* ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /* ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /* ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /* ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /* ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /* ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /* ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /* ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /* ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /* ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /* ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /* ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /* ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /* ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /* ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /* ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /* ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /* ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /* ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /* ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /* ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /* ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /* ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /* ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /* ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /* ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /* ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /* ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /* ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /* ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /* ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /* ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /* ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /* ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /* ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /* ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /* ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /* ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /* ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /* ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /* ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /* ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /* ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /* ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /* ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /* ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /* ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /* ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /* ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /* ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /* ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /* ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /* ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /* ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /* ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /* ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /* ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /* ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /* ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /* ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /* ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /* ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /* ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /* ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /* ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /* ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /* ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /* ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /* ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /* ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /* ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /* ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /* ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /* ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /* ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /* ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /* ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /* ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /* ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /* ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /* ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /* ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /* ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /* ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /* ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /* ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /* ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /* ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /* ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /* ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /* ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /* ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /* ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /* ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /* ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /* ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /* ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /* ID for GMAC event generator TSU_CMP */ +#define EVENT_ID_GEN_TRNG_READY 115 /* ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /* ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /* ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /* ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /* ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/* Event User IDs for SAME54N20A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /* ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /* ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /* ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /* ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /* ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /* ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /* ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /* ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /* ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /* ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /* ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /* ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /* ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /* ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /* ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /* ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /* ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /* ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /* ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /* ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /* ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /* ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /* ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /* ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /* ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /* ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /* ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /* ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /* ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /* ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /* ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /* ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /* ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /* ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /* ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /* ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /* ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /* ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /* ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /* ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /* ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /* ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /* ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /* ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /* ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /* ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /* ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /* ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /* ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /* ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /* ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /* ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /* ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /* ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /* ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /* ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /* ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /* ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /* ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /* ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /* ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /* ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /* ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /* ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /* ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /* ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SAME54N20A_H_ */ + diff --git a/os/common/ext/Microchip/SAME54/same54p19a.h b/os/common/ext/Microchip/SAME54/same54p19a.h new file mode 100644 index 0000000000..31c08769e6 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/same54p19a.h @@ -0,0 +1,1135 @@ +/* + * Header file for ATSAME54P19A + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* File generated from device description file (ATDF) version 2023-03-17T09:50:07Z */ +#ifndef _SAME54P19A_H_ +#define _SAME54P19A_H_ + +/* Header version uses Semantic Versioning 2.0.0 (https://semver.org/) */ +#define HEADER_FORMAT_VERSION "2.1.1" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (1) +#define HEADER_FORMAT_VERSION_PATCH (1) + +/* SAME54P19A definitions + This file defines all structures and symbols for SAME54P19A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_) +# error "Integer constant value macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with sizes of integer constants for C/C++ */ +# define _UINT8_(x) ((uint8_t)(x)) /* C code: 8-bits unsigned integer constant value */ +# define _UINT16_(x) ((uint16_t)(x)) /* C code: 16-bits unsigned integer constant value */ +# define _UINT32_(x) ((uint32_t)(x)) /* C code: 32-bits unsigned integer constant value */ + +#else /* Assembler */ + +# define _UINT8_(x) x /* Assembler: 8-bits unsigned integer constant value */ +# define _UINT16_(x) x /* Assembler: 16-bits unsigned integer constant value */ +# define _UINT32_(x) x /* Assembler: 32-bits unsigned integer constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* -4 Debug Monitor */ + PendSV_IRQn = -2, /* -2 Pendable request for system service */ + SysTick_IRQn = -1, /* -1 System Tick Timer */ + +/****** SAME54P19A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /* 0 Power Manager (PM) */ + MCLK_IRQn = 1, /* 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /* 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /* 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /* 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /* 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /* 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /* 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /* 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /* 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /* 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /* 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /* 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /* 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /* 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /* 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /* 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /* 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /* 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /* 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /* 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /* 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /* 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /* 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /* 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /* 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /* 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /* 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /* 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /* 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /* 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /* 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /* 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /* 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /* 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /* 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /* 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /* 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /* 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /* 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /* 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /* 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /* 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /* 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /* 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /* 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /* 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /* 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /* 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /* 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /* 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /* 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /* 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /* 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /* 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /* 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /* 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /* 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /* 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /* 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /* 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /* 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /* 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /* 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /* 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /* 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /* 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /* 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /* 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /* 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /* 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /* 77 Serial Communication Interface (SERCOM7) */ + CAN0_IRQn = 78, /* 78 Control Area Network (CAN0) */ + CAN1_IRQn = 79, /* 79 Control Area Network (CAN1) */ + USB_OTHER_IRQn = 80, /* 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /* 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /* 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /* 83 Universal Serial Bus (USB) */ + GMAC_IRQn = 84, /* 84 Ethernet MAC (GMAC) */ + TCC0_OTHER_IRQn = 85, /* 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /* 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /* 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /* 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /* 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /* 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /* 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /* 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /* 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /* 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /* 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /* 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /* 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /* 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /* 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /* 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /* 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /* 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /* 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /* 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /* 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /* 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /* 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /* 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /* 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /* 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /* 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /* 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /* 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /* 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /* 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /* 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /* 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /* 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /* 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /* 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /* 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /* 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /* 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /* 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /* 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /* 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /* 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /* 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /* 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /* 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /* 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /* 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /* 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /* 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /* 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /* Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ + void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /* Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /* Debug Level */ +#define __FPU_PRESENT 1 /* FPU present or not */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /* Trace Level */ +#define __VTOR_PRESENT 1 /* Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* CMSIS includes */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_same54.h" +#endif /* USE_CMSIS_INIT */ + +/* ************************************************************************** */ +/* SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P19A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/fuses.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" + +/* ************************************************************************** */ +/* INSTANCE DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/fuses.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/i2s.h" +#include "instance/icm.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/oscctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /* Instance index for PAC (PAC) */ +#define ID_PM ( 1) /* Instance index for PM (PM) */ +#define ID_MCLK ( 2) /* Instance index for MCLK (MCLK) */ +#define ID_RSTC ( 3) /* Instance index for RSTC (RSTC) */ +#define ID_OSCCTRL ( 4) /* Instance index for OSCCTRL (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /* Instance index for OSC32KCTRL (OSC32KCTRL) */ +#define ID_SUPC ( 6) /* Instance index for SUPC (SUPC) */ +#define ID_GCLK ( 7) /* Instance index for GCLK (GCLK) */ +#define ID_WDT ( 8) /* Instance index for WDT (WDT) */ +#define ID_RTC ( 9) /* Instance index for RTC (RTC) */ +#define ID_EIC ( 10) /* Instance index for EIC (EIC) */ +#define ID_FREQM ( 11) /* Instance index for FREQM (FREQM) */ +#define ID_SERCOM0 ( 12) /* Instance index for SERCOM0 (SERCOM0) */ +#define ID_SERCOM1 ( 13) /* Instance index for SERCOM1 (SERCOM1) */ +#define ID_TC0 ( 14) /* Instance index for TC0 (TC0) */ +#define ID_TC1 ( 15) /* Instance index for TC1 (TC1) */ +#define ID_USB ( 32) /* Instance index for USB (USB) */ +#define ID_DSU ( 33) /* Instance index for DSU (DSU) */ +#define ID_NVMCTRL ( 34) /* Instance index for NVMCTRL (NVMCTRL) */ +#define ID_CMCC ( 35) /* Instance index for CMCC (CMCC) */ +#define ID_PORT ( 36) /* Instance index for PORT (PORT) */ +#define ID_DMAC ( 37) /* Instance index for DMAC (DMAC) */ +#define ID_HMATRIX ( 38) /* Instance index for HMATRIX (HMATRIX) */ +#define ID_EVSYS ( 39) /* Instance index for EVSYS (EVSYS) */ +#define ID_SERCOM2 ( 41) /* Instance index for SERCOM2 (SERCOM2) */ +#define ID_SERCOM3 ( 42) /* Instance index for SERCOM3 (SERCOM3) */ +#define ID_TCC0 ( 43) /* Instance index for TCC0 (TCC0) */ +#define ID_TCC1 ( 44) /* Instance index for TCC1 (TCC1) */ +#define ID_TC2 ( 45) /* Instance index for TC2 (TC2) */ +#define ID_TC3 ( 46) /* Instance index for TC3 (TC3) */ +#define ID_RAMECC ( 48) /* Instance index for RAMECC (RAMECC) */ +#define ID_CAN0 ( 64) /* Instance index for CAN0 (CAN0) */ +#define ID_CAN1 ( 65) /* Instance index for CAN1 (CAN1) */ +#define ID_GMAC ( 66) /* Instance index for GMAC (GMAC) */ +#define ID_TCC2 ( 67) /* Instance index for TCC2 (TCC2) */ +#define ID_TCC3 ( 68) /* Instance index for TCC3 (TCC3) */ +#define ID_TC4 ( 69) /* Instance index for TC4 (TC4) */ +#define ID_TC5 ( 70) /* Instance index for TC5 (TC5) */ +#define ID_PDEC ( 71) /* Instance index for PDEC (PDEC) */ +#define ID_AC ( 72) /* Instance index for AC (AC) */ +#define ID_AES ( 73) /* Instance index for AES (AES) */ +#define ID_TRNG ( 74) /* Instance index for TRNG (TRNG) */ +#define ID_ICM ( 75) /* Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /* Instance index for PUKCC (PUKCC) */ +#define ID_QSPI ( 77) /* Instance index for QSPI (QSPI) */ +#define ID_CCL ( 78) /* Instance index for CCL (CCL) */ +#define ID_SERCOM4 ( 96) /* Instance index for SERCOM4 (SERCOM4) */ +#define ID_SERCOM5 ( 97) /* Instance index for SERCOM5 (SERCOM5) */ +#define ID_SERCOM6 ( 98) /* Instance index for SERCOM6 (SERCOM6) */ +#define ID_SERCOM7 ( 99) /* Instance index for SERCOM7 (SERCOM7) */ +#define ID_TCC4 (100) /* Instance index for TCC4 (TCC4) */ +#define ID_TC6 (101) /* Instance index for TC6 (TC6) */ +#define ID_TC7 (102) /* Instance index for TC7 (TC7) */ +#define ID_ADC0 (103) /* Instance index for ADC0 (ADC0) */ +#define ID_ADC1 (104) /* Instance index for ADC1 (ADC1) */ +#define ID_DAC (105) /* Instance index for DAC (DAC) */ +#define ID_I2S (106) /* Instance index for I2S (I2S) */ +#define ID_PCC (107) /* Instance index for PCC (PCC) */ + +#define ID_PERIPH_MAX (107) /* Number of peripheral IDs */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /* AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /* ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /* ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /* AES Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42000000) /* CAN0 Registers Address */ +#define CAN1_REGS ((can_registers_t*)0x42000400) /* CAN1 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /* CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /* CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /* DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /* DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /* DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /* EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /* EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /* FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /* GCLK Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x42000800) /* GMAC Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /* HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /* ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /* I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /* MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /* NVMCTRL Registers Address */ +#define SW0_FUSES_REGS ((fuses_sw0_fuses_registers_t*)0x00800080) /* FUSES Registers Address */ +#define TEMP_LOG_FUSES_REGS ((fuses_temp_log_fuses_registers_t*)0x00800100) /* FUSES Registers Address */ +#define USER_FUSES_REGS ((fuses_user_fuses_registers_t*)0x00804000) /* FUSES Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /* OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /* OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /* PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /* PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /* PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /* PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /* PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /* QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /* RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /* RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /* RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /* SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /* SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /* SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /* SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /* SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /* SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /* SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /* SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /* SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /* SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /* SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /* TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /* TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /* TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /* TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /* TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /* TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /* TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /* TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /* TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /* TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /* TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /* TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /* TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /* TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /* USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /* WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UINT32_(0x42002000) /* AC Base Address */ +#define ADC0_BASE_ADDRESS _UINT32_(0x43001c00) /* ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UINT32_(0x43002000) /* ADC1 Base Address */ +#define AES_BASE_ADDRESS _UINT32_(0x42002400) /* AES Base Address */ +#define CAN0_BASE_ADDRESS _UINT32_(0x42000000) /* CAN0 Base Address */ +#define CAN1_BASE_ADDRESS _UINT32_(0x42000400) /* CAN1 Base Address */ +#define CCL_BASE_ADDRESS _UINT32_(0x42003800) /* CCL Base Address */ +#define CMCC_BASE_ADDRESS _UINT32_(0x41006000) /* CMCC Base Address */ +#define DAC_BASE_ADDRESS _UINT32_(0x43002400) /* DAC Base Address */ +#define DMAC_BASE_ADDRESS _UINT32_(0x4100a000) /* DMAC Base Address */ +#define DSU_BASE_ADDRESS _UINT32_(0x41002000) /* DSU Base Address */ +#define EIC_BASE_ADDRESS _UINT32_(0x40002800) /* EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UINT32_(0x4100e000) /* EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UINT32_(0x40002c00) /* FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UINT32_(0x40001c00) /* GCLK Base Address */ +#define GMAC_BASE_ADDRESS _UINT32_(0x42000800) /* GMAC Base Address */ +#define HMATRIX_BASE_ADDRESS _UINT32_(0x4100c000) /* HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UINT32_(0x42002c00) /* ICM Base Address */ +#define I2S_BASE_ADDRESS _UINT32_(0x43002800) /* I2S Base Address */ +#define MCLK_BASE_ADDRESS _UINT32_(0x40000800) /* MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UINT32_(0x41004000) /* NVMCTRL Base Address */ +#define SW0_FUSES_BASE_ADDRESS _UINT32_(0x00800080) /* FUSES Base Address */ +#define TEMP_LOG_FUSES_BASE_ADDRESS _UINT32_(0x00800100) /* FUSES Base Address */ +#define USER_FUSES_BASE_ADDRESS _UINT32_(0x00804000) /* FUSES Base Address */ +#define OSCCTRL_BASE_ADDRESS _UINT32_(0x40001000) /* OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UINT32_(0x40001400) /* OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UINT32_(0x40000000) /* PAC Base Address */ +#define PCC_BASE_ADDRESS _UINT32_(0x43002c00) /* PCC Base Address */ +#define PDEC_BASE_ADDRESS _UINT32_(0x42001c00) /* PDEC Base Address */ +#define PM_BASE_ADDRESS _UINT32_(0x40000400) /* PM Base Address */ +#define PORT_BASE_ADDRESS _UINT32_(0x41008000) /* PORT Base Address */ +#define QSPI_BASE_ADDRESS _UINT32_(0x42003400) /* QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UINT32_(0x41020000) /* RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UINT32_(0x40000c00) /* RSTC Base Address */ +#define RTC_BASE_ADDRESS _UINT32_(0x40002400) /* RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UINT32_(0x45000000) /* SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UINT32_(0x46000000) /* SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UINT32_(0x40003000) /* SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UINT32_(0x40003400) /* SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UINT32_(0x41012000) /* SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UINT32_(0x41014000) /* SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UINT32_(0x43000000) /* SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UINT32_(0x43000400) /* SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UINT32_(0x43000800) /* SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UINT32_(0x43000c00) /* SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UINT32_(0x40001800) /* SUPC Base Address */ +#define TC0_BASE_ADDRESS _UINT32_(0x40003800) /* TC0 Base Address */ +#define TC1_BASE_ADDRESS _UINT32_(0x40003c00) /* TC1 Base Address */ +#define TC2_BASE_ADDRESS _UINT32_(0x4101a000) /* TC2 Base Address */ +#define TC3_BASE_ADDRESS _UINT32_(0x4101c000) /* TC3 Base Address */ +#define TC4_BASE_ADDRESS _UINT32_(0x42001400) /* TC4 Base Address */ +#define TC5_BASE_ADDRESS _UINT32_(0x42001800) /* TC5 Base Address */ +#define TC6_BASE_ADDRESS _UINT32_(0x43001400) /* TC6 Base Address */ +#define TC7_BASE_ADDRESS _UINT32_(0x43001800) /* TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UINT32_(0x41016000) /* TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UINT32_(0x41018000) /* TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UINT32_(0x42000c00) /* TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UINT32_(0x42001000) /* TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UINT32_(0x43001000) /* TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UINT32_(0x42002800) /* TRNG Base Address */ +#define USB_BASE_ADDRESS _UINT32_(0x41000000) /* USB Base Address */ +#define WDT_BASE_ADDRESS _UINT32_(0x40002000) /* WDT Base Address */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#include "pio/same54p19a.h" + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +#define FLASH_SIZE _UINT32_(0x00080000) /* 512kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UINT32_( 512) +#define FLASH_NB_OF_PAGES _UINT32_( 1024) + +#define SW0_SIZE _UINT32_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UINT32_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UINT32_( 512) +#define TEMP_LOG_NB_OF_PAGES _UINT32_( 1) + +#define USER_PAGE_SIZE _UINT32_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UINT32_( 512) +#define USER_PAGE_NB_OF_PAGES _UINT32_( 1) + +#define CMCC_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UINT32_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UINT32_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UINT32_(0x00030000) /* 192kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UINT32_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UINT32_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UINT32_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UINT32_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UINT32_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UINT32_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UINT32_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UINT32_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UINT32_(0x00000000) /* FLASH base address (type: flash)*/ +#define SW0_ADDR _UINT32_(0x00800080) /* SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UINT32_(0x00800100) /* TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UINT32_(0x00804000) /* USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UINT32_(0x03000000) /* CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UINT32_(0x03000000) /* CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UINT32_(0x03001000) /* CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UINT32_(0x03002000) /* CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UINT32_(0x04000000) /* QSPI base address (type: other)*/ +#define HSRAM_ADDR _UINT32_(0x20000000) /* HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UINT32_(0x20000000) /* HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UINT32_(0x20000000) /* HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UINT32_(0x40000000) /* HPB0 base address (type: io)*/ +#define HPB1_ADDR _UINT32_(0x41000000) /* HPB1 base address (type: io)*/ +#define HPB2_ADDR _UINT32_(0x42000000) /* HPB2 base address (type: io)*/ +#define HPB3_ADDR _UINT32_(0x43000000) /* HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UINT32_(0x44000000) /* SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UINT32_(0x45000000) /* SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UINT32_(0x46000000) /* SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UINT32_(0x47000000) /* BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UINT32_(0xe0000000) /* PPB base address (type: io)*/ +#define SCS_ADDR _UINT32_(0xe000e000) /* SCS base address (type: io)*/ + +/* ************************************************************************** */ +/* DEVICE SIGNATURES FOR SAME54P19A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UINT32_(0X61840301) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Event Generator IDs for SAME54P19A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /* ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /* ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /* ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /* ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /* ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /* ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /* ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /* ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /* ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /* ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /* ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /* ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /* ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /* ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /* ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /* ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /* ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /* ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /* ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /* ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /* ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /* ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /* ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /* ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /* ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /* ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /* ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /* ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /* ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /* ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /* ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /* ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /* ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /* ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /* ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /* ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /* ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /* ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /* ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /* ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /* ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /* ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /* ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /* ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /* ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /* ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /* ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /* ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /* ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /* ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /* ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /* ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /* ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /* ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /* ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /* ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /* ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /* ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /* ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /* ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /* ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /* ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /* ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /* ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /* ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /* ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /* ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /* ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /* ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /* ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /* ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /* ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /* ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /* ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /* ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /* ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /* ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /* ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /* ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /* ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /* ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /* ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /* ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /* ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /* ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /* ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /* ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /* ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /* ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /* ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /* ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /* ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /* ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /* ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /* ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /* ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /* ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /* ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /* ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /* ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /* ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /* ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /* ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /* ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /* ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /* ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /* ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /* ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /* ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /* ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /* ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /* ID for GMAC event generator TSU_CMP */ +#define EVENT_ID_GEN_TRNG_READY 115 /* ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /* ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /* ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /* ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /* ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/* Event User IDs for SAME54P19A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /* ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /* ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /* ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /* ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /* ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /* ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /* ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /* ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /* ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /* ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /* ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /* ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /* ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /* ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /* ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /* ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /* ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /* ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /* ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /* ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /* ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /* ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /* ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /* ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /* ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /* ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /* ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /* ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /* ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /* ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /* ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /* ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /* ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /* ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /* ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /* ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /* ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /* ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /* ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /* ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /* ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /* ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /* ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /* ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /* ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /* ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /* ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /* ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /* ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /* ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /* ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /* ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /* ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /* ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /* ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /* ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /* ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /* ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /* ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /* ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /* ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /* ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /* ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /* ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /* ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /* ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SAME54P19A_H_ */ + diff --git a/os/common/ext/Microchip/SAME54/same54p20a.h b/os/common/ext/Microchip/SAME54/same54p20a.h new file mode 100644 index 0000000000..f1a5928e99 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/same54p20a.h @@ -0,0 +1,1135 @@ +/* + * Header file for ATSAME54P20A + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* File generated from device description file (ATDF) version 2023-03-17T09:50:08Z */ +#ifndef _SAME54P20A_H_ +#define _SAME54P20A_H_ + +/* Header version uses Semantic Versioning 2.0.0 (https://semver.org/) */ +#define HEADER_FORMAT_VERSION "2.1.1" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (1) +#define HEADER_FORMAT_VERSION_PATCH (1) + +/* SAME54P20A definitions + This file defines all structures and symbols for SAME54P20A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_UINT8_) || defined(_UINT16_) || defined(_UINT32_) +# error "Integer constant value macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with sizes of integer constants for C/C++ */ +# define _UINT8_(x) (x) /* C code: 8-bits unsigned integer constant value */ +# define _UINT16_(x) (x) /* C code: 16-bits unsigned integer constant value */ +# define _UINT32_(x) (x) /* C code: 32-bits unsigned integer constant value */ + +#else /* Assembler */ + +# define _UINT8_(x) x /* Assembler: 8-bits unsigned integer constant value */ +# define _UINT16_(x) x /* Assembler: 16-bits unsigned integer constant value */ +# define _UINT32_(x) x /* Assembler: 32-bits unsigned integer constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* -4 Debug Monitor */ + PendSV_IRQn = -2, /* -2 Pendable request for system service */ + SysTick_IRQn = -1, /* -1 System Tick Timer */ + +/****** SAME54P20A specific Interrupt Numbers ***********************************/ + PM_IRQn = 0, /* 0 Power Manager (PM) */ + MCLK_IRQn = 1, /* 1 Main Clock (MCLK) */ + OSCCTRL_XOSC0_IRQn = 2, /* 2 Oscillators Control (OSCCTRL) */ + OSCCTRL_XOSC1_IRQn = 3, /* 3 Oscillators Control (OSCCTRL) */ + OSCCTRL_DFLL_IRQn = 4, /* 4 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL0_IRQn = 5, /* 5 Oscillators Control (OSCCTRL) */ + OSCCTRL_DPLL1_IRQn = 6, /* 6 Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 7, /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_OTHER_IRQn = 8, /* 8 Supply Controller (SUPC) */ + SUPC_BODDET_IRQn = 9, /* 9 Supply Controller (SUPC) */ + WDT_IRQn = 10, /* 10 Watchdog Timer (WDT) */ + RTC_IRQn = 11, /* 11 Real-Time Counter (RTC) */ + EIC_EXTINT_0_IRQn = 12, /* 12 External Interrupt Controller (EIC) */ + EIC_EXTINT_1_IRQn = 13, /* 13 External Interrupt Controller (EIC) */ + EIC_EXTINT_2_IRQn = 14, /* 14 External Interrupt Controller (EIC) */ + EIC_EXTINT_3_IRQn = 15, /* 15 External Interrupt Controller (EIC) */ + EIC_EXTINT_4_IRQn = 16, /* 16 External Interrupt Controller (EIC) */ + EIC_EXTINT_5_IRQn = 17, /* 17 External Interrupt Controller (EIC) */ + EIC_EXTINT_6_IRQn = 18, /* 18 External Interrupt Controller (EIC) */ + EIC_EXTINT_7_IRQn = 19, /* 19 External Interrupt Controller (EIC) */ + EIC_EXTINT_8_IRQn = 20, /* 20 External Interrupt Controller (EIC) */ + EIC_EXTINT_9_IRQn = 21, /* 21 External Interrupt Controller (EIC) */ + EIC_EXTINT_10_IRQn = 22, /* 22 External Interrupt Controller (EIC) */ + EIC_EXTINT_11_IRQn = 23, /* 23 External Interrupt Controller (EIC) */ + EIC_EXTINT_12_IRQn = 24, /* 24 External Interrupt Controller (EIC) */ + EIC_EXTINT_13_IRQn = 25, /* 25 External Interrupt Controller (EIC) */ + EIC_EXTINT_14_IRQn = 26, /* 26 External Interrupt Controller (EIC) */ + EIC_EXTINT_15_IRQn = 27, /* 27 External Interrupt Controller (EIC) */ + FREQM_IRQn = 28, /* 28 Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + NVMCTRL_1_IRQn = 30, /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_0_IRQn = 31, /* 31 Direct Memory Access Controller (DMAC) */ + DMAC_1_IRQn = 32, /* 32 Direct Memory Access Controller (DMAC) */ + DMAC_2_IRQn = 33, /* 33 Direct Memory Access Controller (DMAC) */ + DMAC_3_IRQn = 34, /* 34 Direct Memory Access Controller (DMAC) */ + DMAC_OTHER_IRQn = 35, /* 35 Direct Memory Access Controller (DMAC) */ + EVSYS_0_IRQn = 36, /* 36 Event System Interface (EVSYS) */ + EVSYS_1_IRQn = 37, /* 37 Event System Interface (EVSYS) */ + EVSYS_2_IRQn = 38, /* 38 Event System Interface (EVSYS) */ + EVSYS_3_IRQn = 39, /* 39 Event System Interface (EVSYS) */ + EVSYS_OTHER_IRQn = 40, /* 40 Event System Interface (EVSYS) */ + PAC_IRQn = 41, /* 41 Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /* 45 RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /* 46 Serial Communication Interface (SERCOM0) */ + SERCOM0_1_IRQn = 47, /* 47 Serial Communication Interface (SERCOM0) */ + SERCOM0_2_IRQn = 48, /* 48 Serial Communication Interface (SERCOM0) */ + SERCOM0_OTHER_IRQn = 49, /* 49 Serial Communication Interface (SERCOM0) */ + SERCOM1_0_IRQn = 50, /* 50 Serial Communication Interface (SERCOM1) */ + SERCOM1_1_IRQn = 51, /* 51 Serial Communication Interface (SERCOM1) */ + SERCOM1_2_IRQn = 52, /* 52 Serial Communication Interface (SERCOM1) */ + SERCOM1_OTHER_IRQn = 53, /* 53 Serial Communication Interface (SERCOM1) */ + SERCOM2_0_IRQn = 54, /* 54 Serial Communication Interface (SERCOM2) */ + SERCOM2_1_IRQn = 55, /* 55 Serial Communication Interface (SERCOM2) */ + SERCOM2_2_IRQn = 56, /* 56 Serial Communication Interface (SERCOM2) */ + SERCOM2_OTHER_IRQn = 57, /* 57 Serial Communication Interface (SERCOM2) */ + SERCOM3_0_IRQn = 58, /* 58 Serial Communication Interface (SERCOM3) */ + SERCOM3_1_IRQn = 59, /* 59 Serial Communication Interface (SERCOM3) */ + SERCOM3_2_IRQn = 60, /* 60 Serial Communication Interface (SERCOM3) */ + SERCOM3_OTHER_IRQn = 61, /* 61 Serial Communication Interface (SERCOM3) */ + SERCOM4_0_IRQn = 62, /* 62 Serial Communication Interface (SERCOM4) */ + SERCOM4_1_IRQn = 63, /* 63 Serial Communication Interface (SERCOM4) */ + SERCOM4_2_IRQn = 64, /* 64 Serial Communication Interface (SERCOM4) */ + SERCOM4_OTHER_IRQn = 65, /* 65 Serial Communication Interface (SERCOM4) */ + SERCOM5_0_IRQn = 66, /* 66 Serial Communication Interface (SERCOM5) */ + SERCOM5_1_IRQn = 67, /* 67 Serial Communication Interface (SERCOM5) */ + SERCOM5_2_IRQn = 68, /* 68 Serial Communication Interface (SERCOM5) */ + SERCOM5_OTHER_IRQn = 69, /* 69 Serial Communication Interface (SERCOM5) */ + SERCOM6_0_IRQn = 70, /* 70 Serial Communication Interface (SERCOM6) */ + SERCOM6_1_IRQn = 71, /* 71 Serial Communication Interface (SERCOM6) */ + SERCOM6_2_IRQn = 72, /* 72 Serial Communication Interface (SERCOM6) */ + SERCOM6_OTHER_IRQn = 73, /* 73 Serial Communication Interface (SERCOM6) */ + SERCOM7_0_IRQn = 74, /* 74 Serial Communication Interface (SERCOM7) */ + SERCOM7_1_IRQn = 75, /* 75 Serial Communication Interface (SERCOM7) */ + SERCOM7_2_IRQn = 76, /* 76 Serial Communication Interface (SERCOM7) */ + SERCOM7_OTHER_IRQn = 77, /* 77 Serial Communication Interface (SERCOM7) */ + CAN0_IRQn = 78, /* 78 Control Area Network (CAN0) */ + CAN1_IRQn = 79, /* 79 Control Area Network (CAN1) */ + USB_OTHER_IRQn = 80, /* 80 Universal Serial Bus (USB) */ + USB_SOF_HSOF_IRQn = 81, /* 81 Universal Serial Bus (USB) */ + USB_TRCPT0_IRQn = 82, /* 82 Universal Serial Bus (USB) */ + USB_TRCPT1_IRQn = 83, /* 83 Universal Serial Bus (USB) */ + GMAC_IRQn = 84, /* 84 Ethernet MAC (GMAC) */ + TCC0_OTHER_IRQn = 85, /* 85 Timer Counter Control (TCC0) */ + TCC0_MC0_IRQn = 86, /* 86 Timer Counter Control (TCC0) */ + TCC0_MC1_IRQn = 87, /* 87 Timer Counter Control (TCC0) */ + TCC0_MC2_IRQn = 88, /* 88 Timer Counter Control (TCC0) */ + TCC0_MC3_IRQn = 89, /* 89 Timer Counter Control (TCC0) */ + TCC0_MC4_IRQn = 90, /* 90 Timer Counter Control (TCC0) */ + TCC0_MC5_IRQn = 91, /* 91 Timer Counter Control (TCC0) */ + TCC1_OTHER_IRQn = 92, /* 92 Timer Counter Control (TCC1) */ + TCC1_MC0_IRQn = 93, /* 93 Timer Counter Control (TCC1) */ + TCC1_MC1_IRQn = 94, /* 94 Timer Counter Control (TCC1) */ + TCC1_MC2_IRQn = 95, /* 95 Timer Counter Control (TCC1) */ + TCC1_MC3_IRQn = 96, /* 96 Timer Counter Control (TCC1) */ + TCC2_OTHER_IRQn = 97, /* 97 Timer Counter Control (TCC2) */ + TCC2_MC0_IRQn = 98, /* 98 Timer Counter Control (TCC2) */ + TCC2_MC1_IRQn = 99, /* 99 Timer Counter Control (TCC2) */ + TCC2_MC2_IRQn = 100, /* 100 Timer Counter Control (TCC2) */ + TCC3_OTHER_IRQn = 101, /* 101 Timer Counter Control (TCC3) */ + TCC3_MC0_IRQn = 102, /* 102 Timer Counter Control (TCC3) */ + TCC3_MC1_IRQn = 103, /* 103 Timer Counter Control (TCC3) */ + TCC4_OTHER_IRQn = 104, /* 104 Timer Counter Control (TCC4) */ + TCC4_MC0_IRQn = 105, /* 105 Timer Counter Control (TCC4) */ + TCC4_MC1_IRQn = 106, /* 106 Timer Counter Control (TCC4) */ + TC0_IRQn = 107, /* 107 Basic Timer Counter (TC0) */ + TC1_IRQn = 108, /* 108 Basic Timer Counter (TC1) */ + TC2_IRQn = 109, /* 109 Basic Timer Counter (TC2) */ + TC3_IRQn = 110, /* 110 Basic Timer Counter (TC3) */ + TC4_IRQn = 111, /* 111 Basic Timer Counter (TC4) */ + TC5_IRQn = 112, /* 112 Basic Timer Counter (TC5) */ + TC6_IRQn = 113, /* 113 Basic Timer Counter (TC6) */ + TC7_IRQn = 114, /* 114 Basic Timer Counter (TC7) */ + PDEC_OTHER_IRQn = 115, /* 115 Quadrature Decodeur (PDEC) */ + PDEC_MC0_IRQn = 116, /* 116 Quadrature Decodeur (PDEC) */ + PDEC_MC1_IRQn = 117, /* 117 Quadrature Decodeur (PDEC) */ + ADC0_OTHER_IRQn = 118, /* 118 Analog Digital Converter (ADC0) */ + ADC0_RESRDY_IRQn = 119, /* 119 Analog Digital Converter (ADC0) */ + ADC1_OTHER_IRQn = 120, /* 120 Analog Digital Converter (ADC1) */ + ADC1_RESRDY_IRQn = 121, /* 121 Analog Digital Converter (ADC1) */ + AC_IRQn = 122, /* 122 Analog Comparators (AC) */ + DAC_OTHER_IRQn = 123, /* 123 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_0_IRQn = 124, /* 124 Digital-to-Analog Converter (DAC) */ + DAC_EMPTY_1_IRQn = 125, /* 125 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_0_IRQn = 126, /* 126 Digital-to-Analog Converter (DAC) */ + DAC_RESRDY_1_IRQn = 127, /* 127 Digital-to-Analog Converter (DAC) */ + I2S_IRQn = 128, /* 128 Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /* 129 Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /* 130 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /* 131 True Random Generator (TRNG) */ + ICM_IRQn = 132, /* 132 Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /* 134 Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /* 135 SD/MMC Host Controller (SDHC0) */ + SDHC1_IRQn = 136, /* 136 SD/MMC Host Controller (SDHC1) */ + + PERIPH_MAX_IRQn = 136 /* Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M4 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager (PM) */ + void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ + void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ + void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ + void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ + void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ + void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ + void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ + void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ + void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ + void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ + void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ + void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ + void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ + void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ + void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ + void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ + void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ + void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ + void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ + void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ + void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ + void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ + void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ + void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ + void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ + void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ + void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ + void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ + void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ + void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ + void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ + void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ + void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ + void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ + void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ + void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ + void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M4 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_XOSC0_Handler ( void ); +void OSCCTRL_XOSC1_Handler ( void ); +void OSCCTRL_DFLL_Handler ( void ); +void OSCCTRL_DPLL0_Handler ( void ); +void OSCCTRL_DPLL1_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_OTHER_Handler ( void ); +void SUPC_BODDET_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_EXTINT_0_Handler ( void ); +void EIC_EXTINT_1_Handler ( void ); +void EIC_EXTINT_2_Handler ( void ); +void EIC_EXTINT_3_Handler ( void ); +void EIC_EXTINT_4_Handler ( void ); +void EIC_EXTINT_5_Handler ( void ); +void EIC_EXTINT_6_Handler ( void ); +void EIC_EXTINT_7_Handler ( void ); +void EIC_EXTINT_8_Handler ( void ); +void EIC_EXTINT_9_Handler ( void ); +void EIC_EXTINT_10_Handler ( void ); +void EIC_EXTINT_11_Handler ( void ); +void EIC_EXTINT_12_Handler ( void ); +void EIC_EXTINT_13_Handler ( void ); +void EIC_EXTINT_14_Handler ( void ); +void EIC_EXTINT_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_OTHER_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_OTHER_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_OTHER_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_OTHER_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_OTHER_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_OTHER_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_OTHER_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_OTHER_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_OTHER_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_OTHER_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_OTHER_Handler ( void ); +void USB_SOF_HSOF_Handler ( void ); +void USB_TRCPT0_Handler ( void ); +void USB_TRCPT1_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_OTHER_Handler ( void ); +void TCC0_MC0_Handler ( void ); +void TCC0_MC1_Handler ( void ); +void TCC0_MC2_Handler ( void ); +void TCC0_MC3_Handler ( void ); +void TCC0_MC4_Handler ( void ); +void TCC0_MC5_Handler ( void ); +void TCC1_OTHER_Handler ( void ); +void TCC1_MC0_Handler ( void ); +void TCC1_MC1_Handler ( void ); +void TCC1_MC2_Handler ( void ); +void TCC1_MC3_Handler ( void ); +void TCC2_OTHER_Handler ( void ); +void TCC2_MC0_Handler ( void ); +void TCC2_MC1_Handler ( void ); +void TCC2_MC2_Handler ( void ); +void TCC3_OTHER_Handler ( void ); +void TCC3_MC0_Handler ( void ); +void TCC3_MC1_Handler ( void ); +void TCC4_OTHER_Handler ( void ); +void TCC4_MC0_Handler ( void ); +void TCC4_MC1_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_OTHER_Handler ( void ); +void PDEC_MC0_Handler ( void ); +void PDEC_MC1_Handler ( void ); +void ADC0_OTHER_Handler ( void ); +void ADC0_RESRDY_Handler ( void ); +void ADC1_OTHER_Handler ( void ); +void ADC1_RESRDY_Handler ( void ); +void AC_Handler ( void ); +void DAC_OTHER_Handler ( void ); +void DAC_EMPTY_0_Handler ( void ); +void DAC_EMPTY_1_Handler ( void ); +void DAC_RESRDY_0_Handler ( void ); +void DAC_RESRDY_1_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* Configuration of the CORTEX-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /* Cortex-M4 Core Revision */ +#define __DEBUG_LVL 3 /* Debug Level */ +#define __FPU_PRESENT 1 /* FPU present or not */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ +#define __TRACE_LVL 2 /* Trace Level */ +#define __VTOR_PRESENT 1 /* Vector Table Offset Register present or not */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* CMSIS includes */ +#include "core_cm4.h" +#if defined USE_CMSIS_INIT +#include "system_same54.h" +#endif /* USE_CMSIS_INIT */ + +/* ************************************************************************** */ +/* SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P20A */ +/* ************************************************************************** */ +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/fuses.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/osc32kctrl.h" +#include "component/oscctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/pukcc.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" + +/* ************************************************************************** */ +/* INSTANCE DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/fuses.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/i2s.h" +#include "instance/icm.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/oscctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#define ID_PAC ( 0) /* Instance index for PAC (PAC) */ +#define ID_PM ( 1) /* Instance index for PM (PM) */ +#define ID_MCLK ( 2) /* Instance index for MCLK (MCLK) */ +#define ID_RSTC ( 3) /* Instance index for RSTC (RSTC) */ +#define ID_OSCCTRL ( 4) /* Instance index for OSCCTRL (OSCCTRL) */ +#define ID_OSC32KCTRL ( 5) /* Instance index for OSC32KCTRL (OSC32KCTRL) */ +#define ID_SUPC ( 6) /* Instance index for SUPC (SUPC) */ +#define ID_GCLK ( 7) /* Instance index for GCLK (GCLK) */ +#define ID_WDT ( 8) /* Instance index for WDT (WDT) */ +#define ID_RTC ( 9) /* Instance index for RTC (RTC) */ +#define ID_EIC ( 10) /* Instance index for EIC (EIC) */ +#define ID_FREQM ( 11) /* Instance index for FREQM (FREQM) */ +#define ID_SERCOM0 ( 12) /* Instance index for SERCOM0 (SERCOM0) */ +#define ID_SERCOM1 ( 13) /* Instance index for SERCOM1 (SERCOM1) */ +#define ID_TC0 ( 14) /* Instance index for TC0 (TC0) */ +#define ID_TC1 ( 15) /* Instance index for TC1 (TC1) */ +#define ID_USB ( 32) /* Instance index for USB (USB) */ +#define ID_DSU ( 33) /* Instance index for DSU (DSU) */ +#define ID_NVMCTRL ( 34) /* Instance index for NVMCTRL (NVMCTRL) */ +#define ID_CMCC ( 35) /* Instance index for CMCC (CMCC) */ +#define ID_PORT ( 36) /* Instance index for PORT (PORT) */ +#define ID_DMAC ( 37) /* Instance index for DMAC (DMAC) */ +#define ID_HMATRIX ( 38) /* Instance index for HMATRIX (HMATRIX) */ +#define ID_EVSYS ( 39) /* Instance index for EVSYS (EVSYS) */ +#define ID_SERCOM2 ( 41) /* Instance index for SERCOM2 (SERCOM2) */ +#define ID_SERCOM3 ( 42) /* Instance index for SERCOM3 (SERCOM3) */ +#define ID_TCC0 ( 43) /* Instance index for TCC0 (TCC0) */ +#define ID_TCC1 ( 44) /* Instance index for TCC1 (TCC1) */ +#define ID_TC2 ( 45) /* Instance index for TC2 (TC2) */ +#define ID_TC3 ( 46) /* Instance index for TC3 (TC3) */ +#define ID_RAMECC ( 48) /* Instance index for RAMECC (RAMECC) */ +#define ID_CAN0 ( 64) /* Instance index for CAN0 (CAN0) */ +#define ID_CAN1 ( 65) /* Instance index for CAN1 (CAN1) */ +#define ID_GMAC ( 66) /* Instance index for GMAC (GMAC) */ +#define ID_TCC2 ( 67) /* Instance index for TCC2 (TCC2) */ +#define ID_TCC3 ( 68) /* Instance index for TCC3 (TCC3) */ +#define ID_TC4 ( 69) /* Instance index for TC4 (TC4) */ +#define ID_TC5 ( 70) /* Instance index for TC5 (TC5) */ +#define ID_PDEC ( 71) /* Instance index for PDEC (PDEC) */ +#define ID_AC ( 72) /* Instance index for AC (AC) */ +#define ID_AES ( 73) /* Instance index for AES (AES) */ +#define ID_TRNG ( 74) /* Instance index for TRNG (TRNG) */ +#define ID_ICM ( 75) /* Integrity Check Monitor (ICM) */ +#define ID_PUKCC ( 76) /* Instance index for PUKCC (PUKCC) */ +#define ID_QSPI ( 77) /* Instance index for QSPI (QSPI) */ +#define ID_CCL ( 78) /* Instance index for CCL (CCL) */ +#define ID_SERCOM4 ( 96) /* Instance index for SERCOM4 (SERCOM4) */ +#define ID_SERCOM5 ( 97) /* Instance index for SERCOM5 (SERCOM5) */ +#define ID_SERCOM6 ( 98) /* Instance index for SERCOM6 (SERCOM6) */ +#define ID_SERCOM7 ( 99) /* Instance index for SERCOM7 (SERCOM7) */ +#define ID_TCC4 (100) /* Instance index for TCC4 (TCC4) */ +#define ID_TC6 (101) /* Instance index for TC6 (TC6) */ +#define ID_TC7 (102) /* Instance index for TC7 (TC7) */ +#define ID_ADC0 (103) /* Instance index for ADC0 (ADC0) */ +#define ID_ADC1 (104) /* Instance index for ADC1 (ADC1) */ +#define ID_DAC (105) /* Instance index for DAC (DAC) */ +#define ID_I2S (106) /* Instance index for I2S (I2S) */ +#define ID_PCC (107) /* Instance index for PCC (PCC) */ + +#define ID_PERIPH_MAX (107) /* Number of peripheral IDs */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define AC_REGS ((ac_registers_t*)0x42002000) /* AC Registers Address */ +#define ADC0_REGS ((adc_registers_t*)0x43001c00) /* ADC0 Registers Address */ +#define ADC1_REGS ((adc_registers_t*)0x43002000) /* ADC1 Registers Address */ +#define AES_REGS ((aes_registers_t*)0x42002400) /* AES Registers Address */ +#define CAN0_REGS ((can_registers_t*)0x42000000) /* CAN0 Registers Address */ +#define CAN1_REGS ((can_registers_t*)0x42000400) /* CAN1 Registers Address */ +#define CCL_REGS ((ccl_registers_t*)0x42003800) /* CCL Registers Address */ +#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /* CMCC Registers Address */ +#define DAC_REGS ((dac_registers_t*)0x43002400) /* DAC Registers Address */ +#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /* DMAC Registers Address */ +#define DSU_REGS ((dsu_registers_t*)0x41002000) /* DSU Registers Address */ +#define EIC_REGS ((eic_registers_t*)0x40002800) /* EIC Registers Address */ +#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /* EVSYS Registers Address */ +#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /* FREQM Registers Address */ +#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /* GCLK Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x42000800) /* GMAC Registers Address */ +#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /* HMATRIX Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x42002c00) /* ICM Registers Address */ +#define I2S_REGS ((i2s_registers_t*)0x43002800) /* I2S Registers Address */ +#define MCLK_REGS ((mclk_registers_t*)0x40000800) /* MCLK Registers Address */ +#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /* NVMCTRL Registers Address */ +#define SW0_FUSES_REGS ((fuses_sw0_fuses_registers_t*)0x00800080) /* FUSES Registers Address */ +#define TEMP_LOG_FUSES_REGS ((fuses_temp_log_fuses_registers_t*)0x00800100) /* FUSES Registers Address */ +#define USER_FUSES_REGS ((fuses_user_fuses_registers_t*)0x00804000) /* FUSES Registers Address */ +#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /* OSCCTRL Registers Address */ +#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /* OSC32KCTRL Registers Address */ +#define PAC_REGS ((pac_registers_t*)0x40000000) /* PAC Registers Address */ +#define PCC_REGS ((pcc_registers_t*)0x43002c00) /* PCC Registers Address */ +#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /* PDEC Registers Address */ +#define PM_REGS ((pm_registers_t*)0x40000400) /* PM Registers Address */ +#define PORT_REGS ((port_registers_t*)0x41008000) /* PORT Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x42003400) /* QSPI Registers Address */ +#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /* RAMECC Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /* RSTC Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x40002400) /* RTC Registers Address */ +#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /* SDHC0 Registers Address */ +#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /* SDHC1 Registers Address */ +#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /* SERCOM0 Registers Address */ +#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /* SERCOM1 Registers Address */ +#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /* SERCOM2 Registers Address */ +#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /* SERCOM3 Registers Address */ +#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /* SERCOM4 Registers Address */ +#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /* SERCOM5 Registers Address */ +#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /* SERCOM6 Registers Address */ +#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /* SERCOM7 Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x40001800) /* SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x40003800) /* TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40003c00) /* TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x4101a000) /* TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x4101c000) /* TC3 Registers Address */ +#define TC4_REGS ((tc_registers_t*)0x42001400) /* TC4 Registers Address */ +#define TC5_REGS ((tc_registers_t*)0x42001800) /* TC5 Registers Address */ +#define TC6_REGS ((tc_registers_t*)0x43001400) /* TC6 Registers Address */ +#define TC7_REGS ((tc_registers_t*)0x43001800) /* TC7 Registers Address */ +#define TCC0_REGS ((tcc_registers_t*)0x41016000) /* TCC0 Registers Address */ +#define TCC1_REGS ((tcc_registers_t*)0x41018000) /* TCC1 Registers Address */ +#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /* TCC2 Registers Address */ +#define TCC3_REGS ((tcc_registers_t*)0x42001000) /* TCC3 Registers Address */ +#define TCC4_REGS ((tcc_registers_t*)0x43001000) /* TCC4 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x42002800) /* TRNG Registers Address */ +#define USB_REGS ((usb_registers_t*)0x41000000) /* USB Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x40002000) /* WDT Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#define AC_BASE_ADDRESS _UINT32_(0x42002000) /* AC Base Address */ +#define ADC0_BASE_ADDRESS _UINT32_(0x43001c00) /* ADC0 Base Address */ +#define ADC1_BASE_ADDRESS _UINT32_(0x43002000) /* ADC1 Base Address */ +#define AES_BASE_ADDRESS _UINT32_(0x42002400) /* AES Base Address */ +#define CAN0_BASE_ADDRESS _UINT32_(0x42000000) /* CAN0 Base Address */ +#define CAN1_BASE_ADDRESS _UINT32_(0x42000400) /* CAN1 Base Address */ +#define CCL_BASE_ADDRESS _UINT32_(0x42003800) /* CCL Base Address */ +#define CMCC_BASE_ADDRESS _UINT32_(0x41006000) /* CMCC Base Address */ +#define DAC_BASE_ADDRESS _UINT32_(0x43002400) /* DAC Base Address */ +#define DMAC_BASE_ADDRESS _UINT32_(0x4100a000) /* DMAC Base Address */ +#define DSU_BASE_ADDRESS _UINT32_(0x41002000) /* DSU Base Address */ +#define EIC_BASE_ADDRESS _UINT32_(0x40002800) /* EIC Base Address */ +#define EVSYS_BASE_ADDRESS _UINT32_(0x4100e000) /* EVSYS Base Address */ +#define FREQM_BASE_ADDRESS _UINT32_(0x40002c00) /* FREQM Base Address */ +#define GCLK_BASE_ADDRESS _UINT32_(0x40001c00) /* GCLK Base Address */ +#define GMAC_BASE_ADDRESS _UINT32_(0x42000800) /* GMAC Base Address */ +#define HMATRIX_BASE_ADDRESS _UINT32_(0x4100c000) /* HMATRIX Base Address */ +#define ICM_BASE_ADDRESS _UINT32_(0x42002c00) /* ICM Base Address */ +#define I2S_BASE_ADDRESS _UINT32_(0x43002800) /* I2S Base Address */ +#define MCLK_BASE_ADDRESS _UINT32_(0x40000800) /* MCLK Base Address */ +#define NVMCTRL_BASE_ADDRESS _UINT32_(0x41004000) /* NVMCTRL Base Address */ +#define SW0_FUSES_BASE_ADDRESS _UINT32_(0x00800080) /* FUSES Base Address */ +#define TEMP_LOG_FUSES_BASE_ADDRESS _UINT32_(0x00800100) /* FUSES Base Address */ +#define USER_FUSES_BASE_ADDRESS _UINT32_(0x00804000) /* FUSES Base Address */ +#define OSCCTRL_BASE_ADDRESS _UINT32_(0x40001000) /* OSCCTRL Base Address */ +#define OSC32KCTRL_BASE_ADDRESS _UINT32_(0x40001400) /* OSC32KCTRL Base Address */ +#define PAC_BASE_ADDRESS _UINT32_(0x40000000) /* PAC Base Address */ +#define PCC_BASE_ADDRESS _UINT32_(0x43002c00) /* PCC Base Address */ +#define PDEC_BASE_ADDRESS _UINT32_(0x42001c00) /* PDEC Base Address */ +#define PM_BASE_ADDRESS _UINT32_(0x40000400) /* PM Base Address */ +#define PORT_BASE_ADDRESS _UINT32_(0x41008000) /* PORT Base Address */ +#define QSPI_BASE_ADDRESS _UINT32_(0x42003400) /* QSPI Base Address */ +#define RAMECC_BASE_ADDRESS _UINT32_(0x41020000) /* RAMECC Base Address */ +#define RSTC_BASE_ADDRESS _UINT32_(0x40000c00) /* RSTC Base Address */ +#define RTC_BASE_ADDRESS _UINT32_(0x40002400) /* RTC Base Address */ +#define SDHC0_BASE_ADDRESS _UINT32_(0x45000000) /* SDHC0 Base Address */ +#define SDHC1_BASE_ADDRESS _UINT32_(0x46000000) /* SDHC1 Base Address */ +#define SERCOM0_BASE_ADDRESS _UINT32_(0x40003000) /* SERCOM0 Base Address */ +#define SERCOM1_BASE_ADDRESS _UINT32_(0x40003400) /* SERCOM1 Base Address */ +#define SERCOM2_BASE_ADDRESS _UINT32_(0x41012000) /* SERCOM2 Base Address */ +#define SERCOM3_BASE_ADDRESS _UINT32_(0x41014000) /* SERCOM3 Base Address */ +#define SERCOM4_BASE_ADDRESS _UINT32_(0x43000000) /* SERCOM4 Base Address */ +#define SERCOM5_BASE_ADDRESS _UINT32_(0x43000400) /* SERCOM5 Base Address */ +#define SERCOM6_BASE_ADDRESS _UINT32_(0x43000800) /* SERCOM6 Base Address */ +#define SERCOM7_BASE_ADDRESS _UINT32_(0x43000c00) /* SERCOM7 Base Address */ +#define SUPC_BASE_ADDRESS _UINT32_(0x40001800) /* SUPC Base Address */ +#define TC0_BASE_ADDRESS _UINT32_(0x40003800) /* TC0 Base Address */ +#define TC1_BASE_ADDRESS _UINT32_(0x40003c00) /* TC1 Base Address */ +#define TC2_BASE_ADDRESS _UINT32_(0x4101a000) /* TC2 Base Address */ +#define TC3_BASE_ADDRESS _UINT32_(0x4101c000) /* TC3 Base Address */ +#define TC4_BASE_ADDRESS _UINT32_(0x42001400) /* TC4 Base Address */ +#define TC5_BASE_ADDRESS _UINT32_(0x42001800) /* TC5 Base Address */ +#define TC6_BASE_ADDRESS _UINT32_(0x43001400) /* TC6 Base Address */ +#define TC7_BASE_ADDRESS _UINT32_(0x43001800) /* TC7 Base Address */ +#define TCC0_BASE_ADDRESS _UINT32_(0x41016000) /* TCC0 Base Address */ +#define TCC1_BASE_ADDRESS _UINT32_(0x41018000) /* TCC1 Base Address */ +#define TCC2_BASE_ADDRESS _UINT32_(0x42000c00) /* TCC2 Base Address */ +#define TCC3_BASE_ADDRESS _UINT32_(0x42001000) /* TCC3 Base Address */ +#define TCC4_BASE_ADDRESS _UINT32_(0x43001000) /* TCC4 Base Address */ +#define TRNG_BASE_ADDRESS _UINT32_(0x42002800) /* TRNG Base Address */ +#define USB_BASE_ADDRESS _UINT32_(0x41000000) /* USB Base Address */ +#define WDT_BASE_ADDRESS _UINT32_(0x40002000) /* WDT Base Address */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#include "pio/same54p20a.h" + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +#define FLASH_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: flash */ +#define FLASH_PAGE_SIZE _UINT32_( 512) +#define FLASH_NB_OF_PAGES _UINT32_( 2048) + +#define SW0_SIZE _UINT32_(0x00000010) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_SIZE _UINT32_(0x00000200) /* 0kB Memory segment type: fuses */ +#define TEMP_LOG_PAGE_SIZE _UINT32_( 512) +#define TEMP_LOG_NB_OF_PAGES _UINT32_( 1) + +#define USER_PAGE_SIZE _UINT32_(0x00000200) /* 0kB Memory segment type: user_page */ +#define USER_PAGE_PAGE_SIZE _UINT32_( 512) +#define USER_PAGE_NB_OF_PAGES _UINT32_( 1) + +#define CMCC_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: io */ +#define CMCC_DATARAM_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ +#define CMCC_TAGRAM_SIZE _UINT32_(0x00000400) /* 1kB Memory segment type: io */ +#define CMCC_VALIDRAM_SIZE _UINT32_(0x00000040) /* 0kB Memory segment type: io */ +#define QSPI_SIZE _UINT32_(0x01000000) /* 16384kB Memory segment type: other */ +#define HSRAM_SIZE _UINT32_(0x00040000) /* 256kB Memory segment type: ram */ +#define HSRAM_ETB_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HSRAM_RET1_SIZE _UINT32_(0x00008000) /* 32kB Memory segment type: ram */ +#define HPB0_SIZE _UINT32_(0x00004400) /* 17kB Memory segment type: io */ +#define HPB1_SIZE _UINT32_(0x00022000) /* 136kB Memory segment type: io */ +#define HPB2_SIZE _UINT32_(0x00003c00) /* 15kB Memory segment type: io */ +#define HPB3_SIZE _UINT32_(0x00003000) /* 12kB Memory segment type: io */ +#define SEEPROM_SIZE _UINT32_(0x00020000) /* 128kB Memory segment type: io */ +#define SDHC0_SIZE _UINT32_(0x00000c00) /* 3kB Memory segment type: io */ +#define SDHC1_SIZE _UINT32_(0x00000c00) /* 3kB Memory segment type: io */ +#define BKUPRAM_SIZE _UINT32_(0x00002000) /* 8kB Memory segment type: ram */ +#define PPB_SIZE _UINT32_(0x00100000) /* 1024kB Memory segment type: io */ +#define SCS_SIZE _UINT32_(0x00001000) /* 4kB Memory segment type: io */ + +#define FLASH_ADDR _UINT32_(0x00000000) /* FLASH base address (type: flash)*/ +#define SW0_ADDR _UINT32_(0x00800080) /* SW0 base address (type: fuses)*/ +#define TEMP_LOG_ADDR _UINT32_(0x00800100) /* TEMP_LOG base address (type: fuses)*/ +#define USER_PAGE_ADDR _UINT32_(0x00804000) /* USER_PAGE base address (type: user_page)*/ +#define CMCC_ADDR _UINT32_(0x03000000) /* CMCC base address (type: io)*/ +#define CMCC_DATARAM_ADDR _UINT32_(0x03000000) /* CMCC_DATARAM base address (type: io)*/ +#define CMCC_TAGRAM_ADDR _UINT32_(0x03001000) /* CMCC_TAGRAM base address (type: io)*/ +#define CMCC_VALIDRAM_ADDR _UINT32_(0x03002000) /* CMCC_VALIDRAM base address (type: io)*/ +#define QSPI_ADDR _UINT32_(0x04000000) /* QSPI base address (type: other)*/ +#define HSRAM_ADDR _UINT32_(0x20000000) /* HSRAM base address (type: ram)*/ +#define HSRAM_ETB_ADDR _UINT32_(0x20000000) /* HSRAM_ETB base address (type: ram)*/ +#define HSRAM_RET1_ADDR _UINT32_(0x20000000) /* HSRAM_RET1 base address (type: ram)*/ +#define HPB0_ADDR _UINT32_(0x40000000) /* HPB0 base address (type: io)*/ +#define HPB1_ADDR _UINT32_(0x41000000) /* HPB1 base address (type: io)*/ +#define HPB2_ADDR _UINT32_(0x42000000) /* HPB2 base address (type: io)*/ +#define HPB3_ADDR _UINT32_(0x43000000) /* HPB3 base address (type: io)*/ +#define SEEPROM_ADDR _UINT32_(0x44000000) /* SEEPROM base address (type: io)*/ +#define SDHC0_ADDR _UINT32_(0x45000000) /* SDHC0 base address (type: io)*/ +#define SDHC1_ADDR _UINT32_(0x46000000) /* SDHC1 base address (type: io)*/ +#define BKUPRAM_ADDR _UINT32_(0x47000000) /* BKUPRAM base address (type: ram)*/ +#define PPB_ADDR _UINT32_(0xe0000000) /* PPB base address (type: io)*/ +#define SCS_ADDR _UINT32_(0xe000e000) /* SCS base address (type: io)*/ + +/* ************************************************************************** */ +/* DEVICE SIGNATURES FOR SAME54P20A */ +/* ************************************************************************** */ +#define CHIP_DSU_DID _UINT32_(0X61840300) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Event Generator IDs for SAME54P20A */ +/* ************************************************************************** */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /* ID for OSCCTRL event generator XOSC_FAIL_0 */ +#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /* ID for OSCCTRL event generator XOSC_FAIL_1 */ +#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /* ID for OSC32KCTRL event generator XOSC32K_FAIL */ +#define EVENT_ID_GEN_RTC_PER_0 4 /* ID for RTC event generator PER_0 */ +#define EVENT_ID_GEN_RTC_PER_1 5 /* ID for RTC event generator PER_1 */ +#define EVENT_ID_GEN_RTC_PER_2 6 /* ID for RTC event generator PER_2 */ +#define EVENT_ID_GEN_RTC_PER_3 7 /* ID for RTC event generator PER_3 */ +#define EVENT_ID_GEN_RTC_PER_4 8 /* ID for RTC event generator PER_4 */ +#define EVENT_ID_GEN_RTC_PER_5 9 /* ID for RTC event generator PER_5 */ +#define EVENT_ID_GEN_RTC_PER_6 10 /* ID for RTC event generator PER_6 */ +#define EVENT_ID_GEN_RTC_PER_7 11 /* ID for RTC event generator PER_7 */ +#define EVENT_ID_GEN_RTC_CMP_0 12 /* ID for RTC event generator CMP_0 */ +#define EVENT_ID_GEN_RTC_CMP_1 13 /* ID for RTC event generator CMP_1 */ +#define EVENT_ID_GEN_RTC_CMP_2 14 /* ID for RTC event generator CMP_2 */ +#define EVENT_ID_GEN_RTC_CMP_3 15 /* ID for RTC event generator CMP_3 */ +#define EVENT_ID_GEN_RTC_TAMPER 16 /* ID for RTC event generator TAMPER */ +#define EVENT_ID_GEN_RTC_OVF 17 /* ID for RTC event generator OVF */ +#define EVENT_ID_GEN_EIC_EXTINT_0 18 /* ID for EIC event generator EXTINT_0 */ +#define EVENT_ID_GEN_EIC_EXTINT_1 19 /* ID for EIC event generator EXTINT_1 */ +#define EVENT_ID_GEN_EIC_EXTINT_2 20 /* ID for EIC event generator EXTINT_2 */ +#define EVENT_ID_GEN_EIC_EXTINT_3 21 /* ID for EIC event generator EXTINT_3 */ +#define EVENT_ID_GEN_EIC_EXTINT_4 22 /* ID for EIC event generator EXTINT_4 */ +#define EVENT_ID_GEN_EIC_EXTINT_5 23 /* ID for EIC event generator EXTINT_5 */ +#define EVENT_ID_GEN_EIC_EXTINT_6 24 /* ID for EIC event generator EXTINT_6 */ +#define EVENT_ID_GEN_EIC_EXTINT_7 25 /* ID for EIC event generator EXTINT_7 */ +#define EVENT_ID_GEN_EIC_EXTINT_8 26 /* ID for EIC event generator EXTINT_8 */ +#define EVENT_ID_GEN_EIC_EXTINT_9 27 /* ID for EIC event generator EXTINT_9 */ +#define EVENT_ID_GEN_EIC_EXTINT_10 28 /* ID for EIC event generator EXTINT_10 */ +#define EVENT_ID_GEN_EIC_EXTINT_11 29 /* ID for EIC event generator EXTINT_11 */ +#define EVENT_ID_GEN_EIC_EXTINT_12 30 /* ID for EIC event generator EXTINT_12 */ +#define EVENT_ID_GEN_EIC_EXTINT_13 31 /* ID for EIC event generator EXTINT_13 */ +#define EVENT_ID_GEN_EIC_EXTINT_14 32 /* ID for EIC event generator EXTINT_14 */ +#define EVENT_ID_GEN_EIC_EXTINT_15 33 /* ID for EIC event generator EXTINT_15 */ +#define EVENT_ID_GEN_DMAC_CH_0 34 /* ID for DMAC event generator CH_0 */ +#define EVENT_ID_GEN_DMAC_CH_1 35 /* ID for DMAC event generator CH_1 */ +#define EVENT_ID_GEN_DMAC_CH_2 36 /* ID for DMAC event generator CH_2 */ +#define EVENT_ID_GEN_DMAC_CH_3 37 /* ID for DMAC event generator CH_3 */ +#define EVENT_ID_GEN_PAC_ACCERR 38 /* ID for PAC event generator ACCERR */ +#define EVENT_ID_GEN_TCC0_OVF 41 /* ID for TCC0 event generator OVF */ +#define EVENT_ID_GEN_TCC0_TRG 42 /* ID for TCC0 event generator TRG */ +#define EVENT_ID_GEN_TCC0_CNT 43 /* ID for TCC0 event generator CNT */ +#define EVENT_ID_GEN_TCC0_MC_0 44 /* ID for TCC0 event generator MC_0 */ +#define EVENT_ID_GEN_TCC0_MC_1 45 /* ID for TCC0 event generator MC_1 */ +#define EVENT_ID_GEN_TCC0_MC_2 46 /* ID for TCC0 event generator MC_2 */ +#define EVENT_ID_GEN_TCC0_MC_3 47 /* ID for TCC0 event generator MC_3 */ +#define EVENT_ID_GEN_TCC0_MC_4 48 /* ID for TCC0 event generator MC_4 */ +#define EVENT_ID_GEN_TCC0_MC_5 49 /* ID for TCC0 event generator MC_5 */ +#define EVENT_ID_GEN_TCC1_OVF 50 /* ID for TCC1 event generator OVF */ +#define EVENT_ID_GEN_TCC1_TRG 51 /* ID for TCC1 event generator TRG */ +#define EVENT_ID_GEN_TCC1_CNT 52 /* ID for TCC1 event generator CNT */ +#define EVENT_ID_GEN_TCC1_MC_0 53 /* ID for TCC1 event generator MC_0 */ +#define EVENT_ID_GEN_TCC1_MC_1 54 /* ID for TCC1 event generator MC_1 */ +#define EVENT_ID_GEN_TCC1_MC_2 55 /* ID for TCC1 event generator MC_2 */ +#define EVENT_ID_GEN_TCC1_MC_3 56 /* ID for TCC1 event generator MC_3 */ +#define EVENT_ID_GEN_TCC2_OVF 57 /* ID for TCC2 event generator OVF */ +#define EVENT_ID_GEN_TCC2_TRG 58 /* ID for TCC2 event generator TRG */ +#define EVENT_ID_GEN_TCC2_CNT 59 /* ID for TCC2 event generator CNT */ +#define EVENT_ID_GEN_TCC2_MC_0 60 /* ID for TCC2 event generator MC_0 */ +#define EVENT_ID_GEN_TCC2_MC_1 61 /* ID for TCC2 event generator MC_1 */ +#define EVENT_ID_GEN_TCC2_MC_2 62 /* ID for TCC2 event generator MC_2 */ +#define EVENT_ID_GEN_TCC3_OVF 63 /* ID for TCC3 event generator OVF */ +#define EVENT_ID_GEN_TCC3_TRG 64 /* ID for TCC3 event generator TRG */ +#define EVENT_ID_GEN_TCC3_CNT 65 /* ID for TCC3 event generator CNT */ +#define EVENT_ID_GEN_TCC3_MC_0 66 /* ID for TCC3 event generator MC_0 */ +#define EVENT_ID_GEN_TCC3_MC_1 67 /* ID for TCC3 event generator MC_1 */ +#define EVENT_ID_GEN_TCC4_OVF 68 /* ID for TCC4 event generator OVF */ +#define EVENT_ID_GEN_TCC4_TRG 69 /* ID for TCC4 event generator TRG */ +#define EVENT_ID_GEN_TCC4_CNT 70 /* ID for TCC4 event generator CNT */ +#define EVENT_ID_GEN_TCC4_MC_0 71 /* ID for TCC4 event generator MC_0 */ +#define EVENT_ID_GEN_TCC4_MC_1 72 /* ID for TCC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC0_OVF 73 /* ID for TC0 event generator OVF */ +#define EVENT_ID_GEN_TC0_MC_0 74 /* ID for TC0 event generator MC_0 */ +#define EVENT_ID_GEN_TC0_MC_1 75 /* ID for TC0 event generator MC_1 */ +#define EVENT_ID_GEN_TC1_OVF 76 /* ID for TC1 event generator OVF */ +#define EVENT_ID_GEN_TC1_MC_0 77 /* ID for TC1 event generator MC_0 */ +#define EVENT_ID_GEN_TC1_MC_1 78 /* ID for TC1 event generator MC_1 */ +#define EVENT_ID_GEN_TC2_OVF 79 /* ID for TC2 event generator OVF */ +#define EVENT_ID_GEN_TC2_MC_0 80 /* ID for TC2 event generator MC_0 */ +#define EVENT_ID_GEN_TC2_MC_1 81 /* ID for TC2 event generator MC_1 */ +#define EVENT_ID_GEN_TC3_OVF 82 /* ID for TC3 event generator OVF */ +#define EVENT_ID_GEN_TC3_MC_0 83 /* ID for TC3 event generator MC_0 */ +#define EVENT_ID_GEN_TC3_MC_1 84 /* ID for TC3 event generator MC_1 */ +#define EVENT_ID_GEN_TC4_OVF 85 /* ID for TC4 event generator OVF */ +#define EVENT_ID_GEN_TC4_MC_0 86 /* ID for TC4 event generator MC_0 */ +#define EVENT_ID_GEN_TC4_MC_1 87 /* ID for TC4 event generator MC_1 */ +#define EVENT_ID_GEN_TC5_OVF 88 /* ID for TC5 event generator OVF */ +#define EVENT_ID_GEN_TC5_MC_0 89 /* ID for TC5 event generator MC_0 */ +#define EVENT_ID_GEN_TC5_MC_1 90 /* ID for TC5 event generator MC_1 */ +#define EVENT_ID_GEN_TC6_OVF 91 /* ID for TC6 event generator OVF */ +#define EVENT_ID_GEN_TC6_MC_0 92 /* ID for TC6 event generator MC_0 */ +#define EVENT_ID_GEN_TC6_MC_1 93 /* ID for TC6 event generator MC_1 */ +#define EVENT_ID_GEN_TC7_OVF 94 /* ID for TC7 event generator OVF */ +#define EVENT_ID_GEN_TC7_MC_0 95 /* ID for TC7 event generator MC_0 */ +#define EVENT_ID_GEN_TC7_MC_1 96 /* ID for TC7 event generator MC_1 */ +#define EVENT_ID_GEN_PDEC_OVF 97 /* ID for PDEC event generator OVF */ +#define EVENT_ID_GEN_PDEC_ERR 98 /* ID for PDEC event generator ERR */ +#define EVENT_ID_GEN_PDEC_DIR 99 /* ID for PDEC event generator DIR */ +#define EVENT_ID_GEN_PDEC_VLC 100 /* ID for PDEC event generator VLC */ +#define EVENT_ID_GEN_PDEC_MC_0 101 /* ID for PDEC event generator MC_0 */ +#define EVENT_ID_GEN_PDEC_MC_1 102 /* ID for PDEC event generator MC_1 */ +#define EVENT_ID_GEN_ADC0_RESRDY 103 /* ID for ADC0 event generator RESRDY */ +#define EVENT_ID_GEN_ADC0_WINMON 104 /* ID for ADC0 event generator WINMON */ +#define EVENT_ID_GEN_ADC1_RESRDY 105 /* ID for ADC1 event generator RESRDY */ +#define EVENT_ID_GEN_ADC1_WINMON 106 /* ID for ADC1 event generator WINMON */ +#define EVENT_ID_GEN_AC_COMP_0 107 /* ID for AC event generator COMP_0 */ +#define EVENT_ID_GEN_AC_COMP_1 108 /* ID for AC event generator COMP_1 */ +#define EVENT_ID_GEN_AC_WIN_0 109 /* ID for AC event generator WIN_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_0 110 /* ID for DAC event generator EMPTY_0 */ +#define EVENT_ID_GEN_DAC_EMPTY_1 111 /* ID for DAC event generator EMPTY_1 */ +#define EVENT_ID_GEN_DAC_RESRDY_0 112 /* ID for DAC event generator RESRDY_0 */ +#define EVENT_ID_GEN_DAC_RESRDY_1 113 /* ID for DAC event generator RESRDY_1 */ +#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /* ID for GMAC event generator TSU_CMP */ +#define EVENT_ID_GEN_TRNG_READY 115 /* ID for TRNG event generator READY */ +#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /* ID for CCL event generator LUTOUT_0 */ +#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /* ID for CCL event generator LUTOUT_1 */ +#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /* ID for CCL event generator LUTOUT_2 */ +#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /* ID for CCL event generator LUTOUT_3 */ + +/* ************************************************************************** */ +/* Event User IDs for SAME54P20A */ +/* ************************************************************************** */ +#define EVENT_ID_USER_RTC_TAMPER 0 /* ID for RTC event user TAMPER */ +#define EVENT_ID_USER_PORT_EV_0 1 /* ID for PORT event user EV_0 */ +#define EVENT_ID_USER_PORT_EV_1 2 /* ID for PORT event user EV_1 */ +#define EVENT_ID_USER_PORT_EV_2 3 /* ID for PORT event user EV_2 */ +#define EVENT_ID_USER_PORT_EV_3 4 /* ID for PORT event user EV_3 */ +#define EVENT_ID_USER_DMAC_CH_0 5 /* ID for DMAC event user CH_0 */ +#define EVENT_ID_USER_DMAC_CH_1 6 /* ID for DMAC event user CH_1 */ +#define EVENT_ID_USER_DMAC_CH_2 7 /* ID for DMAC event user CH_2 */ +#define EVENT_ID_USER_DMAC_CH_3 8 /* ID for DMAC event user CH_3 */ +#define EVENT_ID_USER_DMAC_CH_4 9 /* ID for DMAC event user CH_4 */ +#define EVENT_ID_USER_DMAC_CH_5 10 /* ID for DMAC event user CH_5 */ +#define EVENT_ID_USER_DMAC_CH_6 11 /* ID for DMAC event user CH_6 */ +#define EVENT_ID_USER_DMAC_CH_7 12 /* ID for DMAC event user CH_7 */ +#define EVENT_ID_USER_CM4_TRACE_START 14 /* ID for CM4 event user TRACE_START */ +#define EVENT_ID_USER_CM4_TRACE_STOP 15 /* ID for CM4 event user TRACE_STOP */ +#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /* ID for CM4 event user TRACE_TRIG */ +#define EVENT_ID_USER_TCC0_EV_0 17 /* ID for TCC0 event user EV_0 */ +#define EVENT_ID_USER_TCC0_EV_1 18 /* ID for TCC0 event user EV_1 */ +#define EVENT_ID_USER_TCC0_MC_0 19 /* ID for TCC0 event user MC_0 */ +#define EVENT_ID_USER_TCC0_MC_1 20 /* ID for TCC0 event user MC_1 */ +#define EVENT_ID_USER_TCC0_MC_2 21 /* ID for TCC0 event user MC_2 */ +#define EVENT_ID_USER_TCC0_MC_3 22 /* ID for TCC0 event user MC_3 */ +#define EVENT_ID_USER_TCC0_MC_4 23 /* ID for TCC0 event user MC_4 */ +#define EVENT_ID_USER_TCC0_MC_5 24 /* ID for TCC0 event user MC_5 */ +#define EVENT_ID_USER_TCC1_EV_0 25 /* ID for TCC1 event user EV_0 */ +#define EVENT_ID_USER_TCC1_EV_1 26 /* ID for TCC1 event user EV_1 */ +#define EVENT_ID_USER_TCC1_MC_0 27 /* ID for TCC1 event user MC_0 */ +#define EVENT_ID_USER_TCC1_MC_1 28 /* ID for TCC1 event user MC_1 */ +#define EVENT_ID_USER_TCC1_MC_2 29 /* ID for TCC1 event user MC_2 */ +#define EVENT_ID_USER_TCC1_MC_3 30 /* ID for TCC1 event user MC_3 */ +#define EVENT_ID_USER_TCC2_EV_0 31 /* ID for TCC2 event user EV_0 */ +#define EVENT_ID_USER_TCC2_EV_1 32 /* ID for TCC2 event user EV_1 */ +#define EVENT_ID_USER_TCC2_MC_0 33 /* ID for TCC2 event user MC_0 */ +#define EVENT_ID_USER_TCC2_MC_1 34 /* ID for TCC2 event user MC_1 */ +#define EVENT_ID_USER_TCC2_MC_2 35 /* ID for TCC2 event user MC_2 */ +#define EVENT_ID_USER_TCC3_EV_0 36 /* ID for TCC3 event user EV_0 */ +#define EVENT_ID_USER_TCC3_EV_1 37 /* ID for TCC3 event user EV_1 */ +#define EVENT_ID_USER_TCC3_MC_0 38 /* ID for TCC3 event user MC_0 */ +#define EVENT_ID_USER_TCC3_MC_1 39 /* ID for TCC3 event user MC_1 */ +#define EVENT_ID_USER_TCC4_EV_0 40 /* ID for TCC4 event user EV_0 */ +#define EVENT_ID_USER_TCC4_EV_1 41 /* ID for TCC4 event user EV_1 */ +#define EVENT_ID_USER_TCC4_MC_0 42 /* ID for TCC4 event user MC_0 */ +#define EVENT_ID_USER_TCC4_MC_1 43 /* ID for TCC4 event user MC_1 */ +#define EVENT_ID_USER_TC0_EVU 44 /* ID for TC0 event user EVU */ +#define EVENT_ID_USER_TC1_EVU 45 /* ID for TC1 event user EVU */ +#define EVENT_ID_USER_TC2_EVU 46 /* ID for TC2 event user EVU */ +#define EVENT_ID_USER_TC3_EVU 47 /* ID for TC3 event user EVU */ +#define EVENT_ID_USER_TC4_EVU 48 /* ID for TC4 event user EVU */ +#define EVENT_ID_USER_TC5_EVU 49 /* ID for TC5 event user EVU */ +#define EVENT_ID_USER_TC6_EVU 50 /* ID for TC6 event user EVU */ +#define EVENT_ID_USER_TC7_EVU 51 /* ID for TC7 event user EVU */ +#define EVENT_ID_USER_PDEC_EVU_0 52 /* ID for PDEC event user EVU_0 */ +#define EVENT_ID_USER_PDEC_EVU_1 53 /* ID for PDEC event user EVU_1 */ +#define EVENT_ID_USER_PDEC_EVU_2 54 /* ID for PDEC event user EVU_2 */ +#define EVENT_ID_USER_ADC0_START 55 /* ID for ADC0 event user START */ +#define EVENT_ID_USER_ADC0_SYNC 56 /* ID for ADC0 event user SYNC */ +#define EVENT_ID_USER_ADC1_START 57 /* ID for ADC1 event user START */ +#define EVENT_ID_USER_ADC1_SYNC 58 /* ID for ADC1 event user SYNC */ +#define EVENT_ID_USER_AC_SOC_0 59 /* ID for AC event user SOC_0 */ +#define EVENT_ID_USER_AC_SOC_1 60 /* ID for AC event user SOC_1 */ +#define EVENT_ID_USER_DAC_START_0 61 /* ID for DAC event user START_0 */ +#define EVENT_ID_USER_DAC_START_1 62 /* ID for DAC event user START_1 */ +#define EVENT_ID_USER_CCL_LUTIN_0 63 /* ID for CCL event user LUTIN_0 */ +#define EVENT_ID_USER_CCL_LUTIN_1 64 /* ID for CCL event user LUTIN_1 */ +#define EVENT_ID_USER_CCL_LUTIN_2 65 /* ID for CCL event user LUTIN_2 */ +#define EVENT_ID_USER_CCL_LUTIN_3 66 /* ID for CCL event user LUTIN_3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SAME54P20A_H_ */ + diff --git a/os/common/ext/Microchip/SAME54/system_same54.h b/os/common/ext/Microchip/SAME54/system_same54.h new file mode 100644 index 0000000000..88083aa340 --- /dev/null +++ b/os/common/ext/Microchip/SAME54/system_same54.h @@ -0,0 +1,38 @@ +/* + * Low-level initialization functions called upon device startup + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef _SYSTEM_SAME54_H_INCLUDED_ +#define _SYSTEM_SAME54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_SAME54_H_INCLUDED */ diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/SAME54P20.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/SAME54P20.ld new file mode 100644 index 0000000000..28c9ac0416 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/SAME54P20.ld @@ -0,0 +1,86 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SAME54P20 memory setup. + * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 1M + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 256k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld \ No newline at end of file diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_same54.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_same54.mk new file mode 100644 index 0000000000..da51e58126 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_same54.mk @@ -0,0 +1,19 @@ +# List of the ChibiOS generic SAME54 startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SAME54 \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/Microchip/SAME54 + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) diff --git a/os/common/startup/ARMCMx/devices/SAME54/cmparams.h b/os/common/startup/ARMCMx/devices/SAME54/cmparams.h new file mode 100644 index 0000000000..268115b483 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/SAME54/cmparams.h @@ -0,0 +1,91 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/cmparams.h + * @brief ARM Cortex-M4 parameters for the STM32F4xx. + * + * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * STM32F4xx platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 4 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 1 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 3 + +/* If the device type is not externally defined, for example from the Makefile, + then a file named board.h is included. This file must contain a device + definition compatible with the vendor include file.*/ +#if !defined(__SAME54N19A__) && !defined(__ATSAME54N19A__) && \ + !defined(__SAME54N20A__) && !defined(__ATSAME54N20A__) && \ + !defined(__SAME54P19A__) && !defined(__ATSAME54P19A__) && \ + !defined(__SAME54P20A__) && !defined(__ATSAME54P20A__) +#include "board.h" +#endif + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 144 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "sam.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_HAS_FPU != __FPU_PRESENT +#error "CMSIS __FPU_PRESENT mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif +/*lint -restore*/ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ diff --git a/os/hal/boards/SAME54_XPlainedPro/board.c b/os/hal/boards/SAME54_XPlainedPro/board.c new file mode 100644 index 0000000000..9b72d5bb4a --- /dev/null +++ b/os/hal/boards/SAME54_XPlainedPro/board.c @@ -0,0 +1,6 @@ +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) {} + \ No newline at end of file diff --git a/os/hal/boards/SAME54_XPlainedPro/board.h b/os/hal/boards/SAME54_XPlainedPro/board.h new file mode 100644 index 0000000000..7587eb7e8a --- /dev/null +++ b/os/hal/boards/SAME54_XPlainedPro/board.h @@ -0,0 +1,24 @@ +#ifndef BOARD_H_ +#define BOARD_H_ + +#define __SAME54P20A__ +#define BOARD_NAME "SAME54-Xplained Pro" + +#define SAM_XOSC32K_FREQ 32768UL +#define SAM_HAS_GPIOA +#define SAM_HAS_GPIOB +#define SAM_HAS_GPIOC +#define SAM_HAS_GPIOD + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus +void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif + +#endif // BOARD_H_ + \ No newline at end of file diff --git a/os/hal/boards/SAME54_XPlainedPro/board.mk b/os/hal/boards/SAME54_XPlainedPro/board.mk new file mode 100644 index 0000000000..037b6e8304 --- /dev/null +++ b/os/hal/boards/SAME54_XPlainedPro/board.mk @@ -0,0 +1,8 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/SAME54_XPlainedPro/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/SAME54_XPlainedPro + +ALLINC += $(BOARDINC) +ALLCSRC += $(BOARDSRC) diff --git a/os/hal/lib/complex/serial_nor/devices/AT25FF321A/at25ff.h b/os/hal/lib/complex/serial_nor/devices/AT25FF321A/at25ff.h new file mode 100644 index 0000000000..34e59eb03d --- /dev/null +++ b/os/hal/lib/complex/serial_nor/devices/AT25FF321A/at25ff.h @@ -0,0 +1,165 @@ +#ifndef AT25FF_H +#define AT25FF_H + + +/** + * @name Device capabilities + * @{ + */ +#define SNOR_DEVICE_SUPPORTS_XIP TRUE +/** @} */ + +/** + * @name Device identification + * @{ + */ +#define AT25FF_SUPPORTED_MANUFACTURE_IDS {0x1F, 0x47, 0x46, 0x45, 0x44, 0x8, 0x1, 0x0} + +typedef enum +{ + SIZE_32MBIT = 0x7, + SIZE_16MBIT = 0x6, + SIZE_8MBIT = 0x5, + SIZE_4MBIT = 0x4, +} jedec_id_size_map; +/** @} */ + +#define SIZE_4MB 0x400000U +#define SIZE_2MB 0x200000U +#define SIZE_1MB 0x100000U +#define SIZE_500KB 0x80000U +/** + * @name Command codes + * @{ + */ +#define AT25FF_CMD_RESET_ENABLE 0x66 +#define AT25FF_CMD_RESET_MEMORY 0x99 +#define AT25FF_CMD_TERMINATE 0xF0 +#define AT25FF_CMD_CHIP_ERASE_1 0x60 +#define AT25FF_CMD_4KB_BLOCK_ERASE 0x20 +#define AT25FF_CMD_32KB_BLOCK_ERASE 0x52 +#define AT25FF_CMD_64KB_BLOCK_ERASE 0xD8 +#define AT25FF_CMD_PROGRAM_ERASE_RESUME 0x7A +#define AT25FF_CMD_PROGRAM_ERASE_SUSPEND 0x75 +#define AT25FF_CMD_SECTOR_ERASE AT25FF_CMD_64KB_BLOCK_ERASE +#define AT25FF_CMD_SUBSECTOR_ERASE AT25FF_CMD_4KB_BLOCK_ERASE +#define AT25FF_CMD_WRITE_ENABLE 0x06 +#define AT25FF_CMD_WRITE_DISABLE 0x04 +#define AT25FF_CMD_READ 0x03 +#define AT25FF_CMD_FAST_READ 0x0B +#define AT25FF_CMD_READ_DUAL 0x3B +#define AT25FF_CMD_READ_QUAD 0x6B +#define AT25FF_CMD_READ_DISCOVERY_PARAMETER 0x5A +#define AT25FF_CMD_READ_MFG_ID 0x90 +#define AT25FF_CMD_MULTIPLE_IO_READ_ID 0x94 +#define AT25FF_CMD_READ_JEDEC_ID 0x9F +#define AT25FF_CMD_READ_STATUS_REGISTERS 0x65 +#define AT25FF_CMD_WRITE_STATUS_REGISTERS 0x71 +#define AT25FF_CMD_READ_LOCK_REGISTER 0xE8 +#define AT25FF_CMD_WRITE_LOCK_REGISTER 0xE5 +#define AT25FF_CMD_PAGE_PROGRAM 0x02 +#define AT25FF_CMD_PAGE_PROGRAM_DUAL 0xA2 +#define AT25FF_CMD_PAGE_PROGRAM_QUAD 0x32 +#define AT25FF_CMD_SEQ_PROGRAM 0xAD +#define AT25FF_CMD_READ_OTP 0x4B +#define AT25FF_CMD_PROGRAM_OTP 0x9B + +// CFG REG 1 +#define AT25FF_REG_SRP0_POS 7U +#define AT25FF_REG_BPSIZE_POS 6U +#define AT25FF_REG_TB_POS 5U +#define AT25FF_REG_BP2_POS 4U +#define AT25FF_REG_BP1_POS 3U +#define AT25FF_REG_BP0_POS 2U +#define AT25FF_REG_WEL_POS 1U +#define AT25FF_REG_RDY_BSY_POS 0U + +#define AT25FF_REG_SRP0 (1U << AT25FF_REG_SRP0_POS) +#define AT25FF_REG_BPSIZE (1U << AT25FF_REG_BPSIZE_POS) +#define AT25FF_REG_TB (1U << AT25FF_REG_TB_POS) +#define AT25FF_REG_BP2 (1U << AT25FF_REG_BP2_POS) +#define AT25FF_REG_BP1 (1U << AT25FF_REG_BP1_POS) +#define AT25FF_REG_BP0 (1U << AT25FF_REG_BP0_POS) +#define AT25FF_REG_WEL (1U << AT25FF_REG_WEL_POS) +#define AT25FF_REG_RDY_BSY (1U << AT25FF_REG_RDY_BSY_POS) + +// CFG REG 2 +#define AT25FF_REG_SUSP_POS 7U +#define AT25FF_REG_CMPRT_POS 6U +#define AT25FF_REG_SL3_POS 5U +#define AT25FF_REG_SL2_POS 4U +#define AT25FF_REG_SL1_POS 3U +#define AT25FF_REG_RSVD_2_POS 2U +#define AT25FF_REG_QE_POS 1U +#define AT25FF_REG_SRP1_POS 0U + +#define AT25FF_REG_SUSP (1U << AT25FF_REG_SUSP_POS) +#define AT25FF_REG_CMPRT (1U << AT25FF_REG_CMPRT_POS) +#define AT25FF_REG_SL3 (1U << AT25FF_REG_SL3_POS) +#define AT25FF_REG_SL2 (1U << AT25FF_REG_SL2_POS) +#define AT25FF_REG_SL1 (1U << AT25FF_REG_SL1_POS) +#define AT25FF_REG_RSVD_2 (1U << AT25FF_REG_RSVD_2_POS) +#define AT25FF_REG_QE (1U << AT25FF_REG_QE_POS) +#define AT25FF_REG_SRP1 (1U << AT25FF_REG_SRP1_POS) + +// CFG REG 3 +#define AT25FF_REG_RST_POS 7U +#define AT25FF_REG_DRV1_POS 6U +#define AT25FF_REG_DRV0_POS 5U +#define AT25FF_REG_WPS_POS 2U + +#define AT25FF_REG_RST (1U << AT25FF_REG_RST_POS) +#define AT25FF_REG_DRV1 (1U << AT25FF_REG_DRV1_POS) +#define AT25FF_REG_DRV0 (1U << AT25FF_REG_DRV0_POS) +#define AT25FF_REG_WPS (1U << AT25FF_REG_WPS_POS) +#define AT25FF_REG_RSVD_3 ((1U << 0U) | (1U << 1U) | (1U << 3U) | (1U << 4U)) + +// CFG REG 4 +#define AT25FF_REG_PDM_POS 7U +#define AT25FF_REG_SPM_POS 6U +#define AT25FF_REG_XIP_POS 3U +#define AT25FF_REG_BWS2_POS 2U +#define AT25FF_REG_BWS1_POS 1U +#define AT25FF_REG_BWS0_POS 0U + +#define AT25FF_REG_PDM (1U << AT25FF_REG_PDM_POS) +#define AT25FF_REG_SPM (1U << AT25FF_REG_SPM_POS) +#define AT25FF_REG_XIP (1U << AT25FF_REG_XIP_POS) +#define AT25FF_REG_BWS2 (1U << AT25FF_REG_BWS2_POS) +#define AT25FF_REG_BWS1 (1U << AT25FF_REG_BWS1_POS) +#define AT25FF_REG_BWS0 (1U << AT25FF_REG_BWS0_POS) +#define AT25FF_REG_RSVD_4 ((1U << 4U) | (1U << 5U)) + +// CFG REG 5 +#define AT25FF_REG_SRLOCK_POS 7U +#define AT25FF_REG_DC2_POS 6U +#define AT25FF_REG_DC1_POS 5U +#define AT25FF_REG_DC0_POS 4U +#define AT25FF_REG_ES_POS 3U +#define AT25FF_REG_PS_POS 2U +#define AT25FF_REG_TERE_POS 1U +#define AT25FF_REG_DWA_POS 0U + +#define AT25FF_REG_SRLOCK (1U << AT25FF_REG_SRLOCK_POS) +#define AT25FF_REG_DC2 (1U << AT25FF_REG_DC2_POS) +#define AT25FF_REG_DC1 (1U << AT25FF_REG_DC1_POS) +#define AT25FF_REG_DC0 (1U << AT25FF_REG_DC0_POS) +#define AT25FF_REG_ES (1U << AT25FF_REG_ES_POS) +#define AT25FF_REG_PS (1U << AT25FF_REG_PS_POS) +#define AT25FF_REG_TERE (1U << AT25FF_REG_TERE_POS) +#define AT25FF_REG_DWA (1U << AT25FF_REG_DWA_POS) + + +/** + * @name Quad Enable Mode + * @{ + */ +#define AT25FF_QUAD_ENABLE_POS 1UL +#define AT25FF_QUAD_ENABLE_MSK (1UL << AT25FF_QUAD_ENABLE_POS) +#define AT25FF_QUAD_ENABLE(value) ((value << AT25FF_QUAD_ENABLE_POS) & AT25FF_QUAD_ENABLE_MSK) + +// /** useful macros */ +// #define BIT_POS(x) (__builtin_ctz(x)) + + +#endif // HAL_FLASH_DEVICE_H \ No newline at end of file diff --git a/os/hal/lib/complex/serial_nor/devices/AT25FF321A/at25ff321a.mk b/os/hal/lib/complex/serial_nor/devices/AT25FF321A/at25ff321a.mk new file mode 100644 index 0000000000..b7bf681c57 --- /dev/null +++ b/os/hal/lib/complex/serial_nor/devices/AT25FF321A/at25ff321a.mk @@ -0,0 +1,10 @@ +# List of all at25ff321a device files. +SNORSRC := $(CHIBIOS)/os/hal/lib/complex/serial_nor/hal_serial_nor.c \ + $(CHIBIOS_CONTRIB)/os/hal/lib/complex/serial_nor/devices/AT25FF321A/hal_flash_device.c + +# Required include directories +SNORINC := $(CHIBIOS)/os/hal/lib/complex/serial_nor \$(CHIBIOS_CONTRIB)/os/hal/lib/complex/serial_nor/devices/AT25FF321A + +# Shared variables +ALLCSRC += $(SNORSRC) +ALLINC += $(SNORINC) diff --git a/os/hal/lib/complex/serial_nor/devices/AT25FF321A/hal_flash_device.c b/os/hal/lib/complex/serial_nor/devices/AT25FF321A/hal_flash_device.c new file mode 100644 index 0000000000..db9d3c77fa --- /dev/null +++ b/os/hal/lib/complex/serial_nor/devices/AT25FF321A/hal_flash_device.c @@ -0,0 +1,636 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_flash_device.c + * @brief AT25FF serial flash driver code. + * + * @addtogroup AT25FF + * @{ + */ + +#include +#include + +#include "at25ff.h" +#include "hal.h" +#include "hal_serial_nor.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define PAGE_SIZE 256U +#define PAGE_MASK (PAGE_SIZE - 1U) + +#if SER_NOR_USE_SUB_SECTORS == TRUE +#define SECTOR_SIZE 0x00001000U +#define CMD_SECTOR_ERASE AT25FF_CMD_SUBSECTOR_ERASE +#else +#define SECTOR_SIZE 0x00010000U +#define CMD_SECTOR_ERASE AT25FF_CMD_SECTOR_ERASE +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief AT25FF descriptor. + */ +flash_descriptor_t snor_descriptor = { + .attributes = FLASH_ATTR_SUSPEND_ERASE_CAPABLE, + .page_size = PAGE_SIZE, + .sectors_count = 0U, /* It is overwritten.*/ + .sectors = NULL, + .sectors_size = SECTOR_SIZE, + .address = 0U, + .size = 0U /* It is overwritten.*/ + +}; + +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) +#if (WSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__) +/** + * @brief Fast read command for memory mapped mode. + */ + + // Note: Don't know What this is. +const wspi_command_t snor_memmap_read = { + // Note: waht's the dummy cycles mean? + .cmd = AT25FF_CMD_FAST_READ, + .addr = 0, + .dummy = AT25FF_READ_DUMMY_CYCLES - 2, + .cfg = WSPI_CFG_ADDR_SIZE_24 | +#if AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_ADDR_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE | +#elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_ADDR_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES | +#else + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_ADDR_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES | +#endif + WSPI_CFG_ALT_MODE_FOUR_LINES | /* Always 4 lines, note.*/ + WSPI_CFG_ALT_SIZE_8 | + WSPI_CFG_SIOO +}; +#endif +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI +/* Initial AT25FF_CMD_READ_ID command.*/ +static const wspi_command_t at25ff_cmd_read_id = { + .cmd = AT25FF_CMD_READ_MFG_ID, + .cfg = 0U | +#if AT25FF_SWITCH_WIDTH == TRUE + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#else +#if AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES, +#elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES, +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES, +#endif +#endif + .addr = 0, + .alt = 0, + .dummy = 0 +}; + +/* Initial AT25FF_CMD_WRITE_STATUS_REGISTERS command.*/ +static const wspi_command_t at25ff_write_cfg_reg = { + .cmd = AT25FF_CMD_WRITE_STATUS_REGISTERS, + .cfg = 0U | +#if AT25FF_SWITCH_WIDTH == TRUE + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#else +#if AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES, +#elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES, +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES, +#endif +#endif + .addr = 0, + .alt = 0, + .dummy = 0 +}; + +/* Initial AT25FF_CMD_WRITE_ENABLE command.*/ +static const wspi_command_t at25ff_cmd_write_enable = { + .cmd = AT25FF_CMD_WRITE_ENABLE, + .cfg = 0U | +#if AT25FF_SWITCH_WIDTH == TRUE + WSPI_CFG_CMD_MODE_ONE_LINE, +#else +#if AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE, +#elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES, +#elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES, +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES, +#endif +#endif + .addr = 0, + .alt = 0, + .dummy = 0 +}; + +/* Bus width initialization.*/ +#if AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI1L +static const uint8_t AT25FF_evconf_value[1] = {0xCF}; +#elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI2L +static const uint8_t AT25FF_evconf_value[1] = {0x8F}; +#else +static const uint8_t AT25FF_evconf_value[1] = {0x4F}; +#endif +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief amendment to hal_serial_nor.c bus_cmd_send function to add receive functionalities + without having to send another command + * + * @param busp pointer to the bus driver + * @param cmd instruction code + * @param read to receive right after send or not + * @param tx_size number of bytes to send + * @param tx_ptr data buffer + * @param rx_size number of bytes to receive + * @param rx_ptr data buffer + */ +static void bus_cmd_send_receive(BUSDriver *busp, uint32_t cmd, bool read, + size_t tx_size, const uint8_t *tx_ptr, + size_t rx_size, const uint8_t *rx_ptr) +{ + /* Only supporting SPI mode*/ + uint8_t buf[1]; + spiSelect(busp); + buf[0] = cmd; + spiSend(busp, 1, buf); + spiSend(busp, tx_size, tx_ptr); + if (read) + { + spiReceive(busp, rx_size, rx_ptr); + } + spiUnselect(busp); +} + +static bool at25ff_find_id(const uint8_t *set, size_t size, uint8_t element) { + size_t i; + + for (i = 0; i < size; i++) { + if (set[i] == element) { + return true; + } + } + return false; +} + +static flash_error_t at25ff_poll_status(SNORDriver *devp) { + uint8_t sts[8]; + uint8_t tx[2] = {0x1, 0x0}; + do { +#if AT25FF_NICE_WAITING == TRUE + osalThreadSleepMilliseconds(1); +#endif + /* Read status command.*/ + bus_cmd_send_receive( + devp->config->busp, + AT25FF_CMD_READ_STATUS_REGISTERS, + true, + 2, tx, //tx + 8, sts ); // rx + } while ( + (((sts[0] << AT25FF_REG_RDY_BSY_POS) & AT25FF_REG_RDY_BSY) != 0U) | + (((sts[1] << AT25FF_REG_SUSP_POS) & AT25FF_REG_SUSP) != 0U) | + (((sts[4] << AT25FF_REG_ES_POS) & AT25FF_REG_ES) != 0U) | + (((sts[4] << AT25FF_REG_PS_POS) & AT25FF_REG_PS) != 0U) ); + + return FLASH_NO_ERROR; +} + +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) +static void at25ff_reset_memory(SNORDriver *devp) { + + /* 1x AT25FF_CMD_RESET_ENABLE command.*/ + static const wspi_command_t cmd_reset_enable_1 = { + .cmd = AT25FF_CMD_RESET_ENABLE, + .cfg = WSPI_CFG_CMD_MODE_ONE_LINE, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* 1x AT25FF_CMD_RESET_MEMORY command.*/ + static const wspi_command_t cmd_reset_memory_1 = { + .cmd = AT25FF_CMD_RESET_MEMORY, + .cfg = WSPI_CFG_CMD_MODE_ONE_LINE, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* If the device is in one bit mode then the following commands are + rejected because shorter than 8 bits. If the device is in multiple + bits mode then the commands are accepted and the device is reset to + one bit mode.*/ +#if AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI4L + /* 4x AT25FF_CMD_RESET_ENABLE command.*/ + static const wspi_command_t cmd_reset_enable_4 = { + .cmd = AT25FF_CMD_RESET_ENABLE, + .cfg = WSPI_CFG_CMD_MODE_FOUR_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* 4x AT25FF_CMD_RESET_MEMORY command.*/ + static const wspi_command_t cmd_reset_memory_4 = { + .cmd = AT25FF_CMD_RESET_MEMORY, + .cfg = WSPI_CFG_CMD_MODE_FOUR_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + wspiCommand(devp->config->busp, &cmd_reset_enable_4); + wspiCommand(devp->config->busp, &cmd_reset_memory_4); +#else + /* 2x AT25FF_CMD_RESET_ENABLE command.*/ + static const wspi_command_t cmd_reset_enable_2 = { + .cmd = AT25FF_CMD_RESET_ENABLE, + .cfg = WSPI_CFG_CMD_MODE_TWO_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* 2x AT25FF_CMD_RESET_MEMORY command.*/ + static const wspi_command_t cmd_reset_memory_2 = { + .cmd = AT25FF_CMD_RESET_MEMORY, + .cfg = WSPI_CFG_CMD_MODE_TWO_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + wspiCommand(devp->config->busp, &cmd_reset_enable_2); + wspiCommand(devp->config->busp, &cmd_reset_memory_2); +#endif + + /* Now the device should be in one bit mode for sure and we perform a + device reset.*/ + wspiCommand(devp->config->busp, &cmd_reset_enable_1); + wspiCommand(devp->config->busp, &cmd_reset_memory_1); +} +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ + +static const uint8_t at25ff_manufacturer_ids[] = AT25FF_SUPPORTED_MANUFACTURE_IDS; + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void snor_device_init(SNORDriver *devp) { + /** Letting voltages stabilize */ + osalThreadSleepMilliseconds(10); + + bus_cmd(devp->config->busp, AT25FF_CMD_RESET_ENABLE); + bus_cmd(devp->config->busp, AT25FF_CMD_RESET_MEMORY); + +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_SPI + /* Reading device ID.*/ + osalThreadSleepMilliseconds(1000); + bus_cmd_receive(devp->config->busp, AT25FF_CMD_READ_MFG_ID, + 3U, &devp->nocache->buf[0]); + bus_cmd_receive(devp->config->busp, AT25FF_CMD_READ_JEDEC_ID, + 3U, &devp->nocache->buf[0]); +#else /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ + /* Attempting a reset of the XIP mode, it could be in an unexpected state + because a CPU reset does not reset the memory too.*/ + snor_reset_xip(devp); + + /* Attempting a reset of the device, it could be in an unexpected state + because a CPU reset does not reset the memory too.*/ + // at25ff_reset_memory(devp); + + /* Reading device ID and unique ID.*/ + wspiReceive(devp->config->busp, &at25ff_cmd_read_id, + 3U, &devp->nocache->buf[0]); +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ + + /* Checking if the device is white listed.*/ + osalDbgAssert(at25ff_find_id(at25ff_manufacturer_ids, + sizeof at25ff_manufacturer_ids, + devp->nocache->buf[0]), + "invalid manufacturer id"); + +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && (AT25FF_SWITCH_WIDTH == TRUE) + /* Setting up final bus width.*/ + wspiCommand(devp->config->busp, &at25ff_cmd_write_enable); + wspiSend(devp->config->busp, &at25ff_cmd_write_evconf, 1, at25ff_evconf_value); + + { + /* Reading ID again for confirmation.*/ + bus_cmd_receive(devp->config->busp, AT25FF_CMD_MULTIPLE_IO_READ_ID, + 3U, &devp->nocache->buf[16]); + + /* Checking if the device is white listed.*/ + osalDbgAssert(memcmp(&devp->nocache->buf[0], + &devp->nocache->buf[16], + 3U) == 0, + "id confirmation failed"); + } +#endif + + /* Setting up the device size.*/ + uint8_t density_code_bitmask = 0b00000111; + uint8_t density_code = devp->nocache->buf[1] & density_code_bitmask; + size_t density_code_mapping = 0x0; + + switch (density_code) + { + case SIZE_32MBIT: + // retrieved from AT25FF datasheet section Memory Architecture + density_code_mapping = SIZE_4MB; + break; + case SIZE_16MBIT: + density_code_mapping = SIZE_2MB; + break; + case SIZE_8MBIT: + density_code_mapping = SIZE_1MB; + break; + case SIZE_4MBIT: + density_code_mapping = SIZE_500KB; + break; + default: + osalDbgAssert(density_code_mapping, "Not supported"); + } + + snor_descriptor.size = (size_t)density_code_mapping; + snor_descriptor.sectors_count = (size_t)(density_code_mapping / + SECTOR_SIZE); + + +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI + // { + // static const uint8_t flash_conf[1] = { + // (AT25FF_READ_DUMMY_CYCLES << 4U) | 0x0FU + // }; + + // /* Setting up the dummy cycles to be used for fast read operations.*/ + // bus_cmd(devp->config->busp, AT25FF_CMD_WRITE_ENABLE); + // bus_cmd_send(devp->config->busp, AT25FF_CMD_WRITE_STATUS_REGISTERS, + // 1, flash_conf); + // } +#endif +} + +flash_error_t snor_device_read(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp) { + +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI + /* Fast read command in WSPI mode.*/ + bus_cmd_addr_dummy_receive(devp->config->busp, AT25FF_CMD_FAST_READ, + offset, AT25FF_READ_DUMMY_CYCLES, n, rp); +#else + /* Normal read command in SPI mode.*/ + bus_cmd_addr_receive(devp->config->busp, AT25FF_CMD_READ, + offset, n, rp); +#endif + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_program(SNORDriver *devp, flash_offset_t offset, + size_t n, const uint8_t *pp) { + + /* Data is programmed page by page.*/ + while (n > 0U) { + flash_error_t err; + + /* Data size that can be written in a single program page operation.*/ + size_t chunk = (size_t)(((offset | PAGE_MASK) + 1U) - offset); + if (chunk > n) { + chunk = n; + } + + /* Enabling write operation.*/ + bus_cmd(devp->config->busp, AT25FF_CMD_WRITE_ENABLE); + + /* Page program command.*/ + bus_cmd_addr_send(devp->config->busp, AT25FF_CMD_PAGE_PROGRAM, offset, + chunk, pp); + + /* Wait for status and check errors.*/ + err = at25ff_poll_status(devp); + if (err != FLASH_NO_ERROR) { + + return err; + } + + /* Next page.*/ + offset += chunk; + pp += chunk; + n -= chunk; + } + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_start_erase_all(SNORDriver *devp) { + + /* Enabling write operation.*/ + bus_cmd(devp->config->busp, AT25FF_CMD_WRITE_ENABLE); + + /* Bulk erase command.*/ + bus_cmd(devp->config->busp, AT25FF_CMD_CHIP_ERASE_1); + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_start_erase_sector(SNORDriver *devp, + flash_sector_t sector) { + flash_offset_t offset = (flash_offset_t)(sector * SECTOR_SIZE); + + /* Enabling write operation.*/ + bus_cmd(devp->config->busp, AT25FF_CMD_WRITE_ENABLE); + + /* Sector erase command.*/ + bus_cmd_addr(devp->config->busp, AT25FF_CMD_SECTOR_ERASE, offset); + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_verify_erase(SNORDriver *devp, + flash_sector_t sector) { + uint8_t cmpbuf[AT25FF_COMPARE_BUFFER_SIZE]; + flash_offset_t offset; + size_t n; + + /* Read command.*/ + offset = (flash_offset_t)(sector * SECTOR_SIZE); + n = SECTOR_SIZE; + while (n > 0U) { + uint8_t *p; + +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI + bus_cmd_addr_dummy_receive(devp->config->busp, AT25FF_CMD_FAST_READ, + offset, AT25FF_READ_DUMMY_CYCLES, + sizeof cmpbuf, cmpbuf); +#else + /* Normal read command in SPI mode.*/ + bus_cmd_addr_receive(devp->config->busp, AT25FF_CMD_READ, + offset, sizeof cmpbuf, cmpbuf); +#endif + + /* Checking for erased state of current buffer.*/ + for (p = cmpbuf; p < &cmpbuf[AT25FF_COMPARE_BUFFER_SIZE]; p++) { + if (*p != 0xFFU) { + return FLASH_ERROR_VERIFY; + } + } + + offset += sizeof cmpbuf; + n -= sizeof cmpbuf; + } + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_query_erase(SNORDriver *devp, uint32_t *msec) { + uint8_t sts[8]; + uint8_t tx[2] = {0x1, 0x0}; + bus_cmd_send_receive( + devp->config->busp, + AT25FF_CMD_READ_STATUS_REGISTERS, + true, + 2, tx, //tx + 8, sts ); // rx + + /* If the P/E bit is zero (busy) or the flash in a suspended state then + report that the operation is still in progress.*/ + if( + (((sts[0] << AT25FF_REG_RDY_BSY_POS) & AT25FF_REG_RDY_BSY) != 0U) | + (((sts[1] << AT25FF_REG_SUSP_POS) & AT25FF_REG_SUSP) != 0U) | + (((sts[4] << AT25FF_REG_ES_POS) & AT25FF_REG_ES) != 0U) | + (((sts[4] << AT25FF_REG_PS_POS) & AT25FF_REG_PS) != 0U) + ) + { + /* Recommended time before polling again, this is a simplified + implementation.*/ + if (msec != NULL) { + *msec = 1U; + } + + return FLASH_BUSY_ERASING; + } + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_read_sfdp(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp) { + + (void)devp; + (void)rp; + (void)offset; + (void)n; + + return FLASH_NO_ERROR; +} + +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) +void snor_activate_xip(SNORDriver *devp) { + static const uint8_t flash_status_xip[1] = { + (AT25FF_READ_DUMMY_CYCLES << 4U) | 0x07U + }; + + /* Activating XIP mode in the device.*/ + bus_cmd(devp->config->busp, AT25FF_CMD_WRITE_ENABLE); + bus_cmd_send(devp->config->busp, AT25FF_CMD_WRITE_STATUS_REGISTERS, + 1, flash_status_xip); +} + +void snor_reset_xip(SNORDriver *devp) { + static const uint8_t flash_conf[1] = { + (AT25FF_READ_DUMMY_CYCLES << 4U) | 0x0FU + }; + wspi_command_t cmd; + uint8_t buf[1]; + + /* Resetting XIP mode by reading one byte without XIP confirmation bit.*/ + cmd.cmd = 0U; + cmd.alt = 0xFFU; + cmd.addr = 0U; + cmd.dummy = AT25FF_READ_DUMMY_CYCLES - 2U; + cmd.cfg = WSPI_CFG_CMD_MODE_NONE | + WSPI_CFG_ADDR_SIZE_24 | +#if AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI1L + WSPI_CFG_ADDR_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE | +#elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI2L + WSPI_CFG_ADDR_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES | +#elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI4L + WSPI_CFG_ADDR_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES | +#else + WSPI_CFG_ADDR_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES | +#endif + WSPI_CFG_ALT_MODE_FOUR_LINES | /* Always 4 lines, note.*/ + WSPI_CFG_ALT_SIZE_8; + wspiReceive(devp->config->busp, &cmd, 1, buf); + + /* Enabling write operation.*/ + bus_cmd(devp->config->busp, AT25FF_CMD_WRITE_ENABLE); + +} +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ + +/** @} */ diff --git a/os/hal/lib/complex/serial_nor/devices/AT25FF321A/hal_flash_device.h b/os/hal/lib/complex/serial_nor/devices/AT25FF321A/hal_flash_device.h new file mode 100644 index 0000000000..415ebd28c6 --- /dev/null +++ b/os/hal/lib/complex/serial_nor/devices/AT25FF321A/hal_flash_device.h @@ -0,0 +1,262 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_flash_device.h + * @brief Renesas AT25FF321A serial flash driver header. + * + * @addtogroup AT25FF321A + * @{ + */ + + #ifndef HAL_FLASH_DEVICE_H + #define HAL_FLASH_DEVICE_H + /*===========================================================================*/ + /* Driver constants. */ + /*===========================================================================*/ + #include "at25ff.h" + + /*===========================================================================*/ + /* Driver pre-compile time settings. */ + /*===========================================================================*/ + + /** + * @brief Switch WSPI bus width on initialization. + * @details A bus width initialization is performed by writing the + * Enhanced Volatile Configuration Register. If the flash + * device is configured using the Non Volatile Configuration + * Register then this option is not required. + * @note This option is only valid in WSPI bus mode. + */ + #if !defined(AT25FF_SWITCH_WIDTH) || defined(__DOXYGEN__) + #define AT25FF_SWITCH_WIDTH TRUE + #endif + + /** + * @brief Device bus mode to be used. + * @note if @p AT25FF_SWITCH_WIDTH is @p FALSE then this is the bus mode + * that the device is expected to be using. + * @note if @p AT25FF_SWITCH_WIDTH is @p TRUE then this is the bus mode + * that the device will be switched in. + * @note This option is only valid in WSPI bus mode. + */ + #if !defined(AT25FF_BUS_MODE) || defined(__DOXYGEN__) + #define AT25FF_BUS_MODE AT25FF_BUS_MODE_WSPI4L + #endif + + /** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the flash waiting + * routines releasing some extra CPU time for threads with lower + * priority, this may slow down the driver a bit however. + */ + #if !defined(AT25FF_NICE_WAITING) || defined(__DOXYGEN__) + #define AT25FF_NICE_WAITING TRUE + #endif + + /** + * @brief Uses 4kB sub-sectors rather than 64kB sectors. + */ + #if !defined(AT25FF_USE_SUB_SECTORS) || defined(__DOXYGEN__) + #define AT25FF_USE_SUB_SECTORS TRUE + #endif + + / ** + * @brief Size of the compare buffer. + * @details This buffer is allocated in the stack frame of the function + * @p flashVerifyErase() and its size must be a power of two. + * Larger buffers lead to better verify performance but increase + * stack usage for that function. + */ + #if !defined(AT25FF_COMPARE_BUFFER_SIZE) || defined(__DOXYGEN__) + #define AT25FF_COMPARE_BUFFER_SIZE 32 + #endif + + /** + * @brief Number of dummy cycles for fast read (1..15). + * @details This is the number of dummy cycles to be used for fast read + * operations. + */ + #if !defined(AT25FF_READ_DUMMY_CYCLES) || defined(__DOXYGEN__) + #define AT25FF_READ_DUMMY_CYCLES 8 + #endif + + /*===========================================================================*/ + /* Derived constants and error checks. */ + /*===========================================================================*/ +// NOTE: all of the stuff below inside Derived constants and error checks is actually for the N25Q series flash devices. +// As far as I know they are not applicable to the at25ff but I've only looked at them briefly. + #if (AT25FF_COMPARE_BUFFER_SIZE & (AT25FF_COMPARE_BUFFER_SIZE - 1)) != 0 + #error "invalid AT25FF_COMPARE_BUFFER_SIZE value" + #endif + + #if (AT25FF_READ_DUMMY_CYCLES < 1) || (AT25FF_READ_DUMMY_CYCLES > 15) + #error "invalid AT25FF_READ_DUMMY_CYCLES value (1..15)" + #endif + + #if (AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI4L) || defined(__DOXYGEN__) + /** + * @brief WSPI settings for command only. + */ + #define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + /** + * @brief WSPI settings for command and address. + */ + #define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_FOUR_LINES | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + /** + * @brief WSPI settings for command and data. + */ + #define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_FOUR_LINES | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + /** + * @brief WSPI settings for command, address and data. + */ + #define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_FOUR_LINES | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_FOUR_LINES | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI2L + #define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_TWO_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_TWO_LINES | \ + WSPI_CFG_ADDR_MODE_TWO_LINES | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_TWO_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_TWO_LINES | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_ONE_LINE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_ONE_LINE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #elif AT25FF_BUS_MODE == AT25FF_BUS_MODE_WSPI1L + #define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_ONE_LINE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_ONE_LINE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_ONE_LINE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_ONE_LINE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #else + #error "invalid AT25FF_BUS_MODE setting" + #endif + + /*===========================================================================*/ + /* Driver data structures and types. */ + /*===========================================================================*/ + + /*===========================================================================*/ + /* Driver macros. */ + /*===========================================================================*/ + + /*===========================================================================*/ + /* External declarations. */ + /*===========================================================================*/ + + #if !defined(__DOXYGEN__) + extern flash_descriptor_t snor_descriptor; + #endif + + #if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && (WSPI_SUPPORTS_MEMMAP == TRUE) + extern const wspi_command_t snor_memmap_read; + #endif + + #ifdef __cplusplus + extern "C" { + #endif + void snor_device_init(SNORDriver *devp); + flash_error_t snor_device_read(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp); + flash_error_t snor_device_program(SNORDriver *devp, flash_offset_t offset, + size_t n, const uint8_t *pp); + flash_error_t snor_device_start_erase_all(SNORDriver *devp); + flash_error_t snor_device_start_erase_sector(SNORDriver *devp, + flash_sector_t sector); + flash_error_t snor_device_verify_erase(SNORDriver *devp, + flash_sector_t sector); + flash_error_t snor_device_query_erase(SNORDriver *devp, uint32_t *msec); + flash_error_t snor_device_read_sfdp(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp); + #if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && \ + (SNOR_DEVICE_SUPPORTS_XIP == TRUE) + void snor_activate_xip(SNORDriver *devp); + void snor_reset_xip(SNORDriver *devp); + #endif + #ifdef __cplusplus + } + #endif + + #endif /* HAL_FLASH_DEVICE_H */ + + /** @} */ + + \ No newline at end of file diff --git a/os/hal/lib/complex/serial_nor/devices/SST26VF/hal_flash_device.c b/os/hal/lib/complex/serial_nor/devices/SST26VF/hal_flash_device.c new file mode 100644 index 0000000000..4341be990e --- /dev/null +++ b/os/hal/lib/complex/serial_nor/devices/SST26VF/hal_flash_device.c @@ -0,0 +1,589 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_flash_device.c + * @brief SST26VF serial flash driver code. + * + * @addtogroup SST26VF + * @{ + */ + +#include +#include + +#include "sst26vf.h" +#include "hal.h" +#include "hal_serial_nor.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define PAGE_SIZE 256U +#define PAGE_MASK (PAGE_SIZE - 1U) + +#if SST26VF_USE_SUB_SECTORS == TRUE +#define SECTOR_SIZE 0x00001000U +#define CMD_SECTOR_ERASE SST26VF_CMD_SUBSECTOR_ERASE +#else +#define SECTOR_SIZE 0x00010000U +#define CMD_SECTOR_ERASE SST26VF_CMD_SECTOR_ERASE +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief SST26VF descriptor. + */ +flash_descriptor_t snor_descriptor = { + .attributes = FLASH_ATTR_SUSPEND_ERASE_CAPABLE, + .page_size = PAGE_SIZE, + .sectors_count = 0U, /* It is overwritten.*/ + .sectors = NULL, + .sectors_size = SECTOR_SIZE, + .address = 0U, + .size = 0U /* It is overwritten.*/ + +}; + +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) +#if (WSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__) +/** + * @brief Fast read command for memory mapped mode. + */ + + // Note: Don't know What this is. +const wspi_command_t snor_memmap_read = { + // Note: waht's the dummy cycles mean? + .cmd = SST26VF_CMD_FAST_READ, + .addr = 0, + .dummy = SST26VF_READ_DUMMY_CYCLES - 2, + .cfg = WSPI_CFG_ADDR_SIZE_24 | +#if SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_ADDR_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE | +#elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_ADDR_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES | +#else + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_ADDR_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES | +#endif + WSPI_CFG_ALT_MODE_FOUR_LINES | /* Always 4 lines, note.*/ + WSPI_CFG_ALT_SIZE_8 | + WSPI_CFG_SIOO +}; +#endif +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI +/* Initial SST26VF_CMD_READ_ID command.*/ +static const wspi_command_t sst26vf_cmd_read_id = { + .cmd = SST26VF_CMD_READ_MFG_ID, + .cfg = 0U | +#if SST26VF_SWITCH_WIDTH == TRUE + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#else +#if SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES, +#elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES, +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES, +#endif +#endif + .addr = 0, + .alt = 0, + .dummy = 0 +}; + +/* Initial SST26VF_CMD_WRITE_STATUS_REGISTERS command.*/ +static const wspi_command_t sst26vf_write_cfg_reg = { + .cmd = SST26VF_CMD_WRITE_STATUS_REGISTERS, + .cfg = 0U | +#if SST26VF_SWITCH_WIDTH == TRUE + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#else +#if SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES, +#elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES, +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES, +#endif +#endif + .addr = 0, + .alt = 0, + .dummy = 0 +}; + +/* Initial SST26VF_CMD_WRITE_ENABLE command.*/ +static const wspi_command_t sst26vf_cmd_write_enable = { + .cmd = SST26VF_CMD_WRITE_ENABLE, + .cfg = 0U | +#if SST26VF_SWITCH_WIDTH == TRUE + WSPI_CFG_CMD_MODE_ONE_LINE, +#else +#if SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE, +#elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES, +#elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES, +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES, +#endif +#endif + .addr = 0, + .alt = 0, + .dummy = 0 +}; + +/* Bus width initialization.*/ +#if SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI1L +static const uint8_t sst26vf_evconf_value[1] = {0xCF}; +#elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI2L +static const uint8_t sst26vf_evconf_value[1] = {0x8F}; +#else +static const uint8_t sst26vf_evconf_value[1] = {0x4F}; +#endif +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief amendment to hal_serial_nor.c bus_cmd_send function to add receive functionalities + without having to send another command + * + * @param busp pointer to the bus driver + * @param cmd instruction code + * @param read to receive right after send or not + * @param tx_size number of bytes to send + * @param tx_ptr data buffer + * @param rx_size number of bytes to receive + * @param rx_ptr data buffer + */ +static void bus_cmd_send_receive(BUSDriver *busp, uint32_t cmd, bool read, + size_t tx_size, const uint8_t *tx_ptr, + size_t rx_size, const uint8_t *rx_ptr) +{ + /* Only supporting SPI mode*/ + uint8_t buf[1]; + spiSelect(busp); + buf[0] = cmd; + spiSend(busp, 1, buf); + spiSend(busp, tx_size, tx_ptr); + if (read) + { + spiReceive(busp, rx_size, rx_ptr); + } + spiUnselect(busp); +} + +static bool sst26vf_find_id(const uint8_t *set, size_t size, uint8_t element) { + size_t i; + + for (i = 0; i < size; i++) { + if (set[i] == element) { + return true; + } + } + return false; +} + +static flash_error_t sst26vf_poll_status(SNORDriver *devp) { + uint8_t sts[1]; + do { +#if SST26VF_NICE_WAITING == TRUE + osalThreadSleepMilliseconds(1); +#endif + bus_cmd_receive(devp->config->busp, SST26VF_CMD_READ_STATUS_REGISTER, + 1U, sts); + } while ( + (((sts[0] << SST26VF_REG_BUSY_POS) & SST26VF_REG_BUSY) != 0U) | + (((sts[0] << SST26VF_REG_BUSY_2_POS) & SST26VF_REG_BUSY_2) != 0U) | + (((sts[0] << SST26VF_REG_WSE_POS) & SST26VF_REG_WSE) != 0U) | + (((sts[0] << SST26VF_REG_WSP_POS) & SST26VF_REG_WSP) != 0U) + ); + return FLASH_NO_ERROR; + +} + +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) +static void sst26vf_reset_memory(SNORDriver *devp) { + + /* 1x SST26VF_CMD_RESET_ENABLE command.*/ + static const wspi_command_t cmd_reset_enable_1 = { + .cmd = SST26VF_CMD_RESET_ENABLE, + .cfg = WSPI_CFG_CMD_MODE_ONE_LINE, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* 1x SST26VF_CMD_RESET_MEMORY command.*/ + static const wspi_command_t cmd_reset_memory_1 = { + .cmd = SST26VF_CMD_RESET_MEMORY, + .cfg = WSPI_CFG_CMD_MODE_ONE_LINE, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* If the device is in one bit mode then the following commands are + rejected because shorter than 8 bits. If the device is in multiple + bits mode then the commands are accepted and the device is reset to + one bit mode.*/ +#if SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI4L + /* 4x SST26VF_CMD_RESET_ENABLE command.*/ + static const wspi_command_t cmd_reset_enable_4 = { + .cmd = SST26VF_CMD_RESET_ENABLE, + .cfg = WSPI_CFG_CMD_MODE_FOUR_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* 4x SST26VF_CMD_RESET_MEMORY command.*/ + static const wspi_command_t cmd_reset_memory_4 = { + .cmd = SST26VF_CMD_RESET_MEMORY, + .cfg = WSPI_CFG_CMD_MODE_FOUR_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + wspiCommand(devp->config->busp, &cmd_reset_enable_4); + wspiCommand(devp->config->busp, &cmd_reset_memory_4); +#else + /* 2x SST26VF_CMD_RESET_ENABLE command.*/ + static const wspi_command_t cmd_reset_enable_2 = { + .cmd = SST26VF_CMD_RESET_ENABLE, + .cfg = WSPI_CFG_CMD_MODE_TWO_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* 2x SST26VF_CMD_RESET_MEMORY command.*/ + static const wspi_command_t cmd_reset_memory_2 = { + .cmd = SST26VF_CMD_RESET_MEMORY, + .cfg = WSPI_CFG_CMD_MODE_TWO_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + wspiCommand(devp->config->busp, &cmd_reset_enable_2); + wspiCommand(devp->config->busp, &cmd_reset_memory_2); +#endif + + /* Now the device should be in one bit mode for sure and we perform a + device reset.*/ + wspiCommand(devp->config->busp, &cmd_reset_enable_1); + wspiCommand(devp->config->busp, &cmd_reset_memory_1); +} +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ + +static const uint8_t sst26vf_manufacturer_ids[] = SST26VF_SUPPORTED_MANUFACTURE_IDS; + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void snor_device_init(SNORDriver *devp) { + /** Letting voltages stabilize */ + osalThreadSleepMilliseconds(10); + + bus_cmd(devp->config->busp, SST26VF_CMD_RESET_ENABLE); + bus_cmd(devp->config->busp, SST26VF_CMD_RESET_MEMORY); + +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_SPI + /* Reading device ID.*/ + osalThreadSleepMilliseconds(1000); + bus_cmd_receive(devp->config->busp, SST26VF_CMD_READ_JEDEC_ID, + 3U, &devp->nocache->buf[0]); +#else /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ + /* Attempting a reset of the XIP mode, it could be in an unexpected state + because a CPU reset does not reset the memory too.*/ + snor_reset_xip(devp); + + /* Attempting a reset of the device, it could be in an unexpected state + because a CPU reset does not reset the memory too.*/ + // sst26vf_reset_memory(devp); + + /* Reading device ID and unique ID.*/ + wspiReceive(devp->config->busp, &sst26vf_cmd_read_id, + 3U, &devp->nocache->buf[0]); +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ + + /* Checking if the device is white listed.*/ + osalDbgAssert(sst26vf_find_id(sst26vf_manufacturer_ids, + sizeof sst26vf_manufacturer_ids, + devp->nocache->buf[0]), + "invalid manufacturer id"); + +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && (SST26VF_SWITCH_WIDTH == TRUE) + /* Setting up final bus width.*/ + wspiCommand(devp->config->busp, &sst26vf_cmd_write_enable); + wspiSend(devp->config->busp, &sst26vf_cmd_write_evconf, 1, sst26vf_evconf_value); + + { + /* Reading ID again for confirmation.*/ + bus_cmd_receive(devp->config->busp, SST26VF_CMD_MULTIPLE_IO_READ_ID, + 3U, &devp->nocache->buf[16]); + + /* Checking if the device is white listed.*/ + osalDbgAssert(memcmp(&devp->nocache->buf[0], + &devp->nocache->buf[16], + 3U) == 0, + "id confirmation failed"); + } +#endif + + snor_descriptor.size = (size_t)SIZE_64MB; + snor_descriptor.sectors_count = (size_t)(SIZE_64MB / SECTOR_SIZE); + + bus_cmd(devp->config->busp, SST26VF_CMD_GLOBAL_BLOCK_PROTECTION_UNLOCK); +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI + osalDbgAssert(false, "WSPI mode is not supported yet for this device"); +#endif +} + +flash_error_t snor_device_read(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp) { + +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI + /* Fast read command in WSPI mode.*/ + bus_cmd_addr_dummy_receive(devp->config->busp, SST26VF_CMD_FAST_READ, + offset, SST26VF_READ_DUMMY_CYCLES, n, rp); +#else + /* Normal read command in SPI mode.*/ + bus_cmd_addr_receive(devp->config->busp, SST26VF_CMD_READ, + offset, n, rp); +#endif + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_program(SNORDriver *devp, flash_offset_t offset, + size_t n, const uint8_t *pp) { + bus_cmd(devp->config->busp, SST26VF_CMD_GLOBAL_BLOCK_PROTECTION_UNLOCK); + /* Data is programmed page by page.*/ + while (n > 0U) { + flash_error_t err; + + /* Data size that can be written in a single program page operation.*/ + size_t chunk = (size_t)(((offset | PAGE_MASK) + 1U) - offset); + if (chunk > n) { + chunk = n; + } + + /* Enabling write operation.*/ + bus_cmd(devp->config->busp, SST26VF_CMD_WRITE_ENABLE); + + /* Page program command.*/ + bus_cmd_addr_send(devp->config->busp, SST26VF_CMD_PAGE_PROGRAM, offset, + chunk, pp); + + /* Wait for status and check errors.*/ + err = sst26vf_poll_status(devp); + if (err != FLASH_NO_ERROR) { + + return err; + } + + /* Next page.*/ + offset += chunk; + pp += chunk; + n -= chunk; + } + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_start_erase_all(SNORDriver *devp) { + bus_cmd(devp->config->busp, SST26VF_CMD_GLOBAL_BLOCK_PROTECTION_UNLOCK); + /* Enabling write operation.*/ + bus_cmd(devp->config->busp, SST26VF_CMD_WRITE_ENABLE); + + /* Bulk erase command.*/ + bus_cmd(devp->config->busp, SST26VF_CMD_CHIP_ERASE_1); + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_start_erase_sector(SNORDriver *devp, + flash_sector_t sector) { + bus_cmd(devp->config->busp, SST26VF_CMD_GLOBAL_BLOCK_PROTECTION_UNLOCK); + flash_offset_t offset = (flash_offset_t)(sector * SECTOR_SIZE); + + /* Enabling write operation.*/ + bus_cmd(devp->config->busp, SST26VF_CMD_WRITE_ENABLE); + + /* Sector erase command.*/ + bus_cmd_addr(devp->config->busp, SST26VF_CMD_SECTOR_ERASE, offset); + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_verify_erase(SNORDriver *devp, + flash_sector_t sector) { + uint8_t cmpbuf[SST26VF_COMPARE_BUFFER_SIZE]; + flash_offset_t offset; + size_t n; + + /* Read command.*/ + offset = (flash_offset_t)(sector * SECTOR_SIZE); + n = SECTOR_SIZE; + while (n > 0U) { + uint8_t *p; + +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI + osalDbgAssert(false, "WSPI mode is not supported yet for this device"); +#else + /* Normal read command in SPI mode.*/ + bus_cmd_addr_receive(devp->config->busp, SST26VF_CMD_READ, + offset, sizeof cmpbuf, cmpbuf); +#endif + + /* Checking for erased state of current buffer.*/ + for (p = cmpbuf; p < &cmpbuf[SST26VF_COMPARE_BUFFER_SIZE]; p++) { + if (*p != 0xFFU) { + return FLASH_ERROR_VERIFY; + } + } + + offset += sizeof cmpbuf; + n -= sizeof cmpbuf; + } + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_query_erase(SNORDriver *devp, uint32_t *msec) { + uint8_t sts[1]; + + bus_cmd_receive(devp->config->busp, SST26VF_CMD_READ_STATUS_REGISTER, + 1U, sts); + + /* If the P/E bit is zero (busy) or the flash in a suspended state then + report that the operation is still in progress.*/ + if( + (((sts[0] << SST26VF_REG_BUSY_POS) & SST26VF_REG_BUSY) != 0U) | + (((sts[0] << SST26VF_REG_BUSY_2_POS) & SST26VF_REG_BUSY_2) != 0U) | + (((sts[0] << SST26VF_REG_WSE_POS) & SST26VF_REG_WSE) != 0U) | + (((sts[0] << SST26VF_REG_WSP_POS) & SST26VF_REG_WSP) != 0U) + ) + { + /* Recommended time before polling again, this is a simplified + implementation.*/ + if (msec != NULL) { + *msec = 1U; + } + + return FLASH_BUSY_ERASING; + } + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_read_sfdp(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp) { + + (void)devp; + (void)rp; + (void)offset; + (void)n; + // not supported currently + return FLASH_NO_ERROR; +} + +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) +void snor_activate_xip(SNORDriver *devp) { + static const uint8_t flash_status_xip[1] = { + (SST26VF_READ_DUMMY_CYCLES << 4U) | 0x07U + }; + + /* Activating XIP mode in the device.*/ + bus_cmd(devp->config->busp, SST26VF_CMD_WRITE_ENABLE); + bus_cmd_send(devp->config->busp, SST26VF_CMD_WRITE_STATUS_REGISTERS, + 1, flash_status_xip); +} + +void snor_reset_xip(SNORDriver *devp) { + static const uint8_t flash_conf[1] = { + (SST26VF_READ_DUMMY_CYCLES << 4U) | 0x0FU + }; + wspi_command_t cmd; + uint8_t buf[1]; + + /* Resetting XIP mode by reading one byte without XIP confirmation bit.*/ + cmd.cmd = 0U; + cmd.alt = 0xFFU; + cmd.addr = 0U; + cmd.dummy = SST26VF_READ_DUMMY_CYCLES - 2U; + cmd.cfg = WSPI_CFG_CMD_MODE_NONE | + WSPI_CFG_ADDR_SIZE_24 | +#if SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI1L + WSPI_CFG_ADDR_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE | +#elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI2L + WSPI_CFG_ADDR_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES | +#elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI4L + WSPI_CFG_ADDR_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES | +#else + WSPI_CFG_ADDR_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES | +#endif + WSPI_CFG_ALT_MODE_FOUR_LINES | /* Always 4 lines, note.*/ + WSPI_CFG_ALT_SIZE_8; + wspiReceive(devp->config->busp, &cmd, 1, buf); + + /* Enabling write operation.*/ + bus_cmd(devp->config->busp, SST26VF_CMD_WRITE_ENABLE); +} +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ + +/** @} */ diff --git a/os/hal/lib/complex/serial_nor/devices/SST26VF/hal_flash_device.h b/os/hal/lib/complex/serial_nor/devices/SST26VF/hal_flash_device.h new file mode 100644 index 0000000000..2353f82daa --- /dev/null +++ b/os/hal/lib/complex/serial_nor/devices/SST26VF/hal_flash_device.h @@ -0,0 +1,264 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_flash_device.h + * @brief Renesas SST26VF064 serial flash driver header. + * + * @addtogroup SST26VF064 + * @{ + */ + + #ifndef HAL_FLASH_DEVICE_H + #define HAL_FLASH_DEVICE_H + /*===========================================================================*/ + /* Driver constants. */ + /*===========================================================================*/ + #include "sst26vf.h" + + /*===========================================================================*/ + /* Driver pre-compile time settings. */ + /*===========================================================================*/ + + /** + * @brief Switch WSPI bus width on initialization. + * @details A bus width initialization is performed by writing the + * Enhanced Volatile Configuration Register. If the flash + * device is configured using the Non Volatile Configuration + * Register then this option is not required. + * @note This option is only valid in WSPI bus mode. + */ + #if !defined(SST26VF_SWITCH_WIDTH) || defined(__DOXYGEN__) + #define SST26VF_SWITCH_WIDTH TRUE + #endif + + /** + * @brief Device bus mode to be used. + * @note if @p SST26VF_SWITCH_WIDTH is @p FALSE then this is the bus mode + * that the device is expected to be using. + * @note if @p SST26VF_SWITCH_WIDTH is @p TRUE then this is the bus mode + * that the device will be switched in. + * @note This option is only valid in WSPI bus mode. + */ + #if !defined(SST26VF_BUS_MODE) || defined(__DOXYGEN__) + #define SST26VF_BUS_MODE SST26VF_BUS_MODE_WSPI4L + #endif + + /** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the flash waiting + * routines releasing some extra CPU time for threads with lower + * priority, this may slow down the driver a bit however. + */ + #if !defined(SST26VF_NICE_WAITING) || defined(__DOXYGEN__) + #define SST26VF_NICE_WAITING TRUE + #endif + + /** + * @brief Uses 4kB sub-sectors rather than 64kB sectors. + */ + #if !defined(SST26VF_USE_SUB_SECTORS) || defined(__DOXYGEN__) + #define SST26VF_USE_SUB_SECTORS TRUE + #endif + + /** + * @brief Size of the compare buffer. + * @details This buffer is allocated in the stack frame of the function + * @p flashVerifyErase() and its size must be a power of two. + * Larger buffers lead to better verify performance but increase + * stack usage for that function. + */ + #if !defined(SST26VF_COMPARE_BUFFER_SIZE) || defined(__DOXYGEN__) + #define SST26VF_COMPARE_BUFFER_SIZE 32 + #endif + + /** + * @brief Number of dummy cycles for fast read (1..15). + * @details This is the number of dummy cycles to be used for fast read + * operations. + */ + #if !defined(SST26VF_READ_DUMMY_CYCLES) || defined(__DOXYGEN__) + #define SST26VF_READ_DUMMY_CYCLES 8 + #endif + + /*===========================================================================*/ + /* Derived constants and error checks. */ + /*===========================================================================*/ +// NOTE: all of the stuff below inside Derived constants and error checks is actually for the N25Q series flash devices. +// As far as I know they are not applicable to the at25ff but I've only looked at them briefly. + #if (SST26VF_COMPARE_BUFFER_SIZE & (SST26VF_COMPARE_BUFFER_SIZE - 1)) != 0 + #error "invalid SST26VF_COMPARE_BUFFER_SIZE value" + #endif + + #if (SST26VF_READ_DUMMY_CYCLES < 1) || (SST26VF_READ_DUMMY_CYCLES > 15) + #error "invalid SST26VF_READ_DUMMY_CYCLES value (1..15)" + #endif + + #if (SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI4L) || defined(__DOXYGEN__) + /** + * @brief WSPI settings for command only. + */ + #define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + /** + * @brief WSPI settings for command and address. + */ + #define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_FOUR_LINES | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + /** + * @brief WSPI settings for command and data. + */ + #define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_FOUR_LINES | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + /** + * @brief WSPI settings for command, address and data. + */ + #define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_FOUR_LINES | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_FOUR_LINES | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI2L + #define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_TWO_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_TWO_LINES | \ + WSPI_CFG_ADDR_MODE_TWO_LINES | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_TWO_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_TWO_LINES | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_ONE_LINE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_ONE_LINE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #elif SST26VF_BUS_MODE == SST26VF_BUS_MODE_WSPI1L + #define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_ONE_LINE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_ONE_LINE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_ONE_LINE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_ONE_LINE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + + #else + #error "invalid SST26VF_BUS_MODE setting" + #endif + + /*===========================================================================*/ + /* Driver data structures and types. */ + /*===========================================================================*/ + + /*===========================================================================*/ + /* Driver macros. */ + /*===========================================================================*/ + + /*===========================================================================*/ + /* External declarations. */ + /*===========================================================================*/ + + #if !defined(__DOXYGEN__) + extern flash_descriptor_t snor_descriptor; + #endif + + #if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && (WSPI_SUPPORTS_MEMMAP == TRUE) + extern const wspi_command_t snor_memmap_read; + #endif + + #ifdef __cplusplus + extern "C" { + #endif + void snor_device_init(SNORDriver *devp); + flash_error_t snor_device_read(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp); + flash_error_t snor_device_program(SNORDriver *devp, flash_offset_t offset, + size_t n, const uint8_t *pp); + flash_error_t snor_device_start_erase_all(SNORDriver *devp); + flash_error_t snor_device_start_erase_sector(SNORDriver *devp, + flash_sector_t sector); + flash_error_t snor_device_verify_erase(SNORDriver *devp, + flash_sector_t sector); + flash_error_t snor_device_query_erase(SNORDriver *devp, uint32_t *msec); + flash_error_t snor_device_read_sfdp(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp); + void snor_device_set_status_register(SNORDriver *devp, uint8_t *sts); + void snor_device_get_status_register(SNORDriver *devp, uint8_t *sts); + #if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && \ + (SNOR_DEVICE_SUPPORTS_XIP == TRUE) + void snor_activate_xip(SNORDriver *devp); + void snor_reset_xip(SNORDriver *devp); + #endif + #ifdef __cplusplus + } + #endif + + #endif /* HAL_FLASH_DEVICE_H */ + + /** @} */ + + \ No newline at end of file diff --git a/os/hal/lib/complex/serial_nor/devices/SST26VF/sst26vf.h b/os/hal/lib/complex/serial_nor/devices/SST26VF/sst26vf.h new file mode 100644 index 0000000000..4b1c0c45e4 --- /dev/null +++ b/os/hal/lib/complex/serial_nor/devices/SST26VF/sst26vf.h @@ -0,0 +1,112 @@ +#ifndef SST26VF_H +#define SST26VF_H + + +/** + * @name Device capabilities + * @{ + */ +#define SNOR_DEVICE_SUPPORTS_XIP TRUE +/** @} */ + +/** + * @name Device identification + * @{ + */ +#define SST26VF_SUPPORTED_MANUFACTURE_IDS {0xBF, 0x26, 0x43} + +#define SIZE_64MB 0x3FFFFFFU + + +/** + * @name Command codes + * @{ + */ +#define SST26VF_CMD_RESET_ENABLE 0x66 +#define SST26VF_CMD_RESET_MEMORY 0x99 + +#define SST26VF_CMD_CHIP_ERASE_1 0xC7 + +#define SST26VF_CMD_4KB_BLOCK_ERASE 0x20 +#define SST26VF_CMD_64KB_BLOCK_ERASE 0xD8 +#define SST26VF_CMD_PROGRAM_ERASE_RESUME 0x30 +#define SST26VF_CMD_PROGRAM_ERASE_SUSPEND 0xB0 +#define SST26VF_CMD_SECTOR_ERASE SST26VF_CMD_64KB_BLOCK_ERASE +#define SST26VF_CMD_SUBSECTOR_ERASE SST26VF_CMD_4KB_BLOCK_ERASE + +#define SST26VF_CMD_WRITE_ENABLE 0x06 +#define SST26VF_CMD_WRITE_DISABLE 0x04 +#define SST26VF_CMD_READ 0x03 +#define SST26VF_CMD_FAST_READ 0x0B +#define SST26VF_CMD_READ_DUAL 0x3B +#define SST26VF_CMD_READ_QUAD 0x6B +#define SST26VF_CMD_READ_DISCOVERY_PARAMETER 0x5A +#define SST26VF_CMD_MULTIPLE_IO_READ_ID 0xAF +#define SST26VF_CMD_READ_JEDEC_ID 0x9F + +#define SST26VF_CMD_READ_CFG_REGISTER 0x35 +#define SST26VF_CMD_READ_STATUS_REGISTER 0x05 +#define SST26VF_CMD_WRITE_STATUS_REGISTER 0x01 +#define SST26VF_CMD_PAGE_PROGRAM 0x02 +#define SST26VF_CMD_PAGE_PROGRAM_QUAD 0x32 + +#define SST26VF_CMD_WRITE_SUSPEND 0xB0 +#define SST26VF_CMD_WRITE_RESUME 0x30 +#define SST26VF_CMD_READ_BLOCK_PROTECTION_REGISTER 0x72 +#define SST26VF_CMD_WRITE_BLOCK_PROTECTION_REGISTER 0x42 +#define SST26VF_CMD_LOCKDOWN_BLOCK_PROTECTION 0x8D +#define SST26VF_CMD_NONVOLATILE_WRITE_LOCKDOWN 0xE8 +#define SST26VF_CMD_GLOBAL_BLOCK_PROTECTION_UNLOCK 0x98 +#define SST26VF_CMD_READ_SECURITY_ID 0x88 +#define SST26VF_CMD_PROGRAM_SECURITY_ID 0xA5 +#define SST26VF_CMD_LOCKOUT_SECURITY_ID 0x85 + +// Status REG +#define SST26VF_REG_BUSY_POS 7U +#define SST26VF_REG_RSVD_POS 6U +#define SST26VF_REG_SEC_POS 5U +#define SST26VF_REG_WPLD_POS 4U +#define SST26VF_REG_WSP_POS 3U +#define SST26VF_REG_WSE_POS 2U +#define SST26VF_REG_WEL_POS 1U +#define SST26VF_REG_BUSY_2_POS 0U + +#define SST26VF_REG_BUSY (1U << SST26VF_REG_BUSY_POS) +#define SST26VF_REG_RSVD (1U << SST26VF_REG_RSVD_POS) +#define SST26VF_REG_SEC (1U << SST26VF_REG_SEC_POS) +#define SST26VF_REG_WPLD (1U << SST26VF_REG_WPLD_POS) +#define SST26VF_REG_WSP (1U << SST26VF_REG_WSP_POS) +#define SST26VF_REG_WSE (1U << SST26VF_REG_WSE_POS) +#define SST26VF_REG_WEL (1U << SST26VF_REG_WEL_POS) +#define SST26VF_REG_BUSY_2 (1U << SST26VF_REG_BUSY_2_POS) + +// Config REG +#define SST26VF_REG_WPEN_POS 7U +#define SST26VF_REG_RSVD_POS 6U +#define SST26VF_REG_RSVD_1_POS 5U +#define SST26VF_REG_RSVD_2_POS 4U +#define SST26VF_REG_BPNV_POS 3U +#define SST26VF_REG_RSVD_3_POS 2U +#define SST26VF_REG_IOC_POS 1U +#define SST26VF_REG_RSVD_4_POS 0U + +#define SST26VF_REG_WPEN (1U << SST26VF_REG_WPEN_POS) +#define SST26VF_REG_RSVD (1U << SST26VF_REG_RSVD_POS) +#define SST26VF_REG_RSVD_1 (1U << SST26VF_REG_RSVD_1_POS) +#define SST26VF_REG_RSVD_2 (1U << SST26VF_REG_RSVD_2_POS) +#define SST26VF_REG_RSVD_3 (1U << SST26VF_REG_RSVD_3_POS) +#define SST26VF_REG_BPNV (1U << SST26VF_REG_BPNV_POS) +#define SST26VF_REG_IOC (1U << SST26VF_REG_IOC_POS) +#define SST26VF_REG_RSVD_4 (1U << SST26VF_REG_RSVD_4_POS) + +// Adding new command definitions for block protection and security ID operations +#define SST26VF_CMD_READ_BLOCK_PROTECTION_REGISTER 0x72 +#define SST26VF_CMD_WRITE_BLOCK_PROTECTION_REGISTER 0x42 +#define SST26VF_CMD_LOCKDOWN_BLOCK_PROTECTION 0x8D +#define SST26VF_CMD_NONVOLATILE_WRITE_LOCKDOWN 0xE8 +#define SST26VF_CMD_GLOBAL_BLOCK_PROTECTION_UNLOCK 0x98 +#define SST26VF_CMD_READ_SECURITY_ID 0x88 +#define SST26VF_CMD_PROGRAM_SECURITY_ID 0xA5 +#define SST26VF_CMD_LOCKOUT_SECURITY_ID 0x85 + +#endif // SST26VF_H \ No newline at end of file diff --git a/os/hal/lib/complex/serial_nor/devices/SST26VF/sst26vf.mk b/os/hal/lib/complex/serial_nor/devices/SST26VF/sst26vf.mk new file mode 100644 index 0000000000..93d748219b --- /dev/null +++ b/os/hal/lib/complex/serial_nor/devices/SST26VF/sst26vf.mk @@ -0,0 +1,11 @@ +# List of all sst26vf device files. +SNORSRC := $(CHIBIOS)/os/hal/lib/complex/serial_nor/hal_serial_nor.c \ + $(CHIBIOS_CONTRIB)/os/hal/lib/complex/serial_nor/devices/SST26VF/hal_flash_device.c + +# Required include directories +SNORINC := $(CHIBIOS)/os/hal/lib/complex/serial_nor \ + $(CHIBIOS_CONTRIB)/os/hal/lib/complex/serial_nor/devices/SST26VF + +# Shared variables +ALLCSRC += $(SNORSRC) +ALLINC += $(SNORINC) \ No newline at end of file diff --git a/os/hal/ports/SAM/LLD/ADCv1/hal_adc_lld.c b/os/hal/ports/SAM/LLD/ADCv1/hal_adc_lld.c index 43b2b89346..14145d8ea0 100644 --- a/os/hal/ports/SAM/LLD/ADCv1/hal_adc_lld.c +++ b/os/hal/ports/SAM/LLD/ADCv1/hal_adc_lld.c @@ -61,11 +61,9 @@ ADCDriver ADCD1; * * @param[in] adcp pointer to the @p ADCDriver object */ -static void adc_lld_stop_adc(ADCDriver *adcp) -{ +static void adc_lld_stop_adc(ADCDriver* adcp) { - if (adcp->adc->ADC_CTRLA & ADC_CTRLA_ENABLE_Msk) - { + if (adcp->adc->ADC_CTRLA & ADC_CTRLA_ENABLE_Msk) { adcp->adc->ADC_CTRLA &= ~ADC_CTRLA_ENABLE_Msk; while (adcp->adc->ADC_CTRLA & ADC_CTRLA_ENABLE_Msk) ; @@ -76,30 +74,28 @@ static void adc_lld_stop_adc(ADCDriver *adcp) /* Driver interrupt handlers. */ /*===========================================================================*/ -static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) -{ - if (adcp->grpp != NULL) - { +static void adc_lld_serve_interrupt(ADCDriver* adcp, uint32_t isr) { + if (adcp->grpp != NULL) { adcerror_t emask = 0U; - if ((isr & ADC_INTFLAG_RESRDY_Msk) && (adcp->state == ADC_ACTIVE)) - { + if ((isr & ADC_INTFLAG_RESRDY_Msk) && (adcp->state == ADC_ACTIVE)) { volatile uint16_t value = adcp->adc->ADC_RESULT; - if (adcp->curr_size == adcp->depth * adcp->grpp->num_channels) - { + if (adcp->curr_size == adcp->depth * adcp->grpp->num_channels) { _adc_isr_full_code(adcp); } - else - { - if (adcp->curr_pin == adcp->grpp->num_channels) - { + else { + if (adcp->curr_pin == adcp->grpp->num_channels) { adcp->curr_pin = 0; } adcp->samples[adcp->curr_size] = value; adcp->curr_size += 1; - ADCD1.adc->ADC_INTENSET = ADC_INTENSET_OVERRUN_Msk | ADC_INTENSET_RESRDY_Msk; + ADCD1.adc->ADC_INTENSET = + ADC_INTENSET_OVERRUN_Msk | ADC_INTENSET_RESRDY_Msk; uint8_t curr_pin = adcp->grpp->seq[adcp->curr_pin]; - adcp->adc->ADC_INPUTCTRL = (adcp->grpp->inputctrl & ~(ADC_INPUTCTRL_MUXPOS_Msk | ADC_INPUTCTRL_INPUTSCAN_Msk)) | ADC_INPUTCTRL_MUXPOS(curr_pin); + adcp->adc->ADC_INPUTCTRL = + (adcp->grpp->inputctrl & + ~(ADC_INPUTCTRL_MUXPOS_Msk | ADC_INPUTCTRL_INPUTSCAN_Msk)) | + ADC_INPUTCTRL_MUXPOS(curr_pin); while ((adcp->adc->ADC_STATUS & ADC_STATUS_SYNCBUSY_Msk) != 0U) ; adcp->curr_pin += 1; @@ -110,14 +106,12 @@ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) } /* Note, an overflow may occur after the conversion ended before the driver is able to stop the ADC, this is why the state is checked too.*/ - if ((isr & ADC_INTFLAG_OVERRUN_Msk) && (adcp->state == ADC_ACTIVE)) - { + if ((isr & ADC_INTFLAG_OVERRUN_Msk) && (adcp->state == ADC_ACTIVE)) { /* ADC overflow condition, this could happen only if the DMA is unable to read data fast enough.*/ emask |= ADC_ERR_OVERFLOW; } - if (emask != 0U) - { + if (emask != 0U) { _adc_isr_error_code(adcp, emask); } } @@ -132,8 +126,7 @@ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) * * @notapi */ -void adc_lld_init(void) -{ +void adc_lld_init(void) { #if SAM_ADC_USE_ADC1 == TRUE /* Driver initialization.*/ @@ -150,26 +143,30 @@ void adc_lld_init(void) * * @notapi */ -void adc_lld_start(ADCDriver *adcp) -{ +void adc_lld_start(ADCDriver* adcp) { - if (adcp->state == ADC_STOP) - { + if (adcp->state == ADC_STOP) { /* Enables the peripheral.*/ #if SAM_ADC_USE_ADC1 == TRUE - if (&ADCD1 == adcp) - { + if (&ADCD1 == adcp) { PM_REGS->PM_APBCMASK |= PM_APBCMASK_ADC_Msk | PM_APBCMASK_EVSYS_Msk; sam_gclk_mux(SAM_ADC_GCLK_SRC_ID, GCLK_CLKCTRL_ID_ADC_Val, 1); // Reset ADC adcp->adc->ADC_CTRLA = ADC_CTRLA_SWRST_Msk; while ((adcp->adc->ADC_STATUS & ADC_STATUS_SYNCBUSY_Msk) != 0U) ; - uint32_t adc_linearity0 = (((*(uint32_t *)OTP4_ADDR) & ADC_LINEARITY0_Msk) >> ADC_LINEARITY0_POS); - uint32_t adc_linearity1 = (((*(uint32_t *)(OTP4_ADDR + 4U)) & ADC_LINEARITY1_Msk) >> ADC_LINEARITY1_POS); - adcp->adc->ADC_CALIB = (uint16_t)((ADC_CALIB_LINEARITY_CAL(adc_linearity0 | - (adc_linearity1 << 5U))) | - ADC_CALIB_BIAS_CAL((((*(uint32_t *)(OTP4_ADDR + 4U)) & ADC_BIASCAL_Msk) >> ADC_BIASCAL_POS))); + uint32_t adc_linearity0 = + (((*(uint32_t*)OTP4_ADDR) & ADC_LINEARITY0_Msk) >> + ADC_LINEARITY0_POS); + uint32_t adc_linearity1 = + (((*(uint32_t*)(OTP4_ADDR + 4U)) & ADC_LINEARITY1_Msk) >> + ADC_LINEARITY1_POS); + adcp->adc->ADC_CALIB = + (uint16_t)((ADC_CALIB_LINEARITY_CAL(adc_linearity0 | + (adc_linearity1 << 5U))) | + ADC_CALIB_BIAS_CAL( + (((*(uint32_t*)(OTP4_ADDR + 4U)) & ADC_BIASCAL_Msk) >> + ADC_BIASCAL_POS))); while ((adcp->adc->ADC_STATUS & ADC_STATUS_SYNCBUSY_Msk) != 0U) ; adcp->adc->ADC_INTFLAG = (uint8_t)ADC_INTFLAG_Msk; @@ -190,17 +187,14 @@ void adc_lld_start(ADCDriver *adcp) * * @notapi */ -void adc_lld_stop(ADCDriver *adcp) -{ +void adc_lld_stop(ADCDriver* adcp) { - if (adcp->state == ADC_READY) - { + if (adcp->state == ADC_READY) { /* Resets the peripheral.*/ adcp->adc->ADC_CTRLA = ADC_CTRLA_SWRST_Msk; /* Disables the peripheral.*/ #if SAM_ADC_USE_ADC1 == TRUE - if (&ADCD1 == adcp) - { + if (&ADCD1 == adcp) { sam_gclk_mux(SAM_ADC_GCLK_SRC_ID, GCLK_CLKCTRL_ID_ADC_Val, 0); } #endif @@ -214,12 +208,14 @@ void adc_lld_stop(ADCDriver *adcp) * * @notapi */ -void adc_lld_start_conversion(ADCDriver *adcp) -{ +void adc_lld_start_conversion(ADCDriver* adcp) { adcp->curr_pin = 0; adcp->curr_size = 0; adcp->adc->ADC_AVGCTRL = adcp->grpp->avgctrl; - adcp->adc->ADC_INPUTCTRL = (adcp->grpp->inputctrl & ~(ADC_INPUTCTRL_MUXPOS_Msk | ADC_INPUTCTRL_INPUTSCAN_Msk)) | ADC_INPUTCTRL_MUXPOS(adcp->grpp->seq[adcp->curr_pin]); + adcp->adc->ADC_INPUTCTRL = + (adcp->grpp->inputctrl & + ~(ADC_INPUTCTRL_MUXPOS_Msk | ADC_INPUTCTRL_INPUTSCAN_Msk)) | + ADC_INPUTCTRL_MUXPOS(adcp->grpp->seq[adcp->curr_pin]); while ((adcp->adc->ADC_STATUS & ADC_STATUS_SYNCBUSY_Msk) != 0U) ; adcp->curr_pin += 1; @@ -227,7 +223,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) adcp->adc->ADC_CTRLB = adcp->grpp->ctrlb; while ((adcp->adc->ADC_STATUS & ADC_STATUS_SYNCBUSY_Msk) != 0U) ; - adcp->adc->ADC_INTENSET = (uint8_t)ADC_INTENSET_OVERRUN_Msk | ADC_INTENSET_RESRDY_Msk; + adcp->adc->ADC_INTENSET = + (uint8_t)ADC_INTENSET_OVERRUN_Msk | ADC_INTENSET_RESRDY_Msk; adcp->adc->ADC_SWTRIG = (uint8_t)ADC_SWTRIG_START_Msk; while ((adcp->adc->ADC_STATUS & ADC_STATUS_SYNCBUSY_Msk) != 0U) ; @@ -240,14 +237,12 @@ void adc_lld_start_conversion(ADCDriver *adcp) * * @notapi */ -void adc_lld_stop_conversion(ADCDriver *adcp) -{ +void adc_lld_stop_conversion(ADCDriver* adcp) { // dmacChnlDisable(adcp->dmacId); adcp->adc->ADC_SWTRIG = ADC_SWTRIG_FLUSH_Msk; } -OSAL_IRQ_HANDLER(ADC_HANDLER) -{ +OSAL_IRQ_HANDLER(ADC_HANDLER) { OSAL_IRQ_PROLOGUE(); uint8_t intflag = ADCD1.adc->ADC_INTFLAG; ADCD1.adc->ADC_INTFLAG = ADC_INTFLAG_Msk; diff --git a/os/hal/ports/SAM/LLD/ADCv1/hal_adc_lld.h b/os/hal/ports/SAM/LLD/ADCv1/hal_adc_lld.h index 82308a3db1..85e603d926 100644 --- a/os/hal/ports/SAM/LLD/ADCv1/hal_adc_lld.h +++ b/os/hal/ports/SAM/LLD/ADCv1/hal_adc_lld.h @@ -35,9 +35,9 @@ * @name Possible ADC errors mask bits. * @{ */ -#define ADC_ERR_DMAFAILURE 1U /**< DMA operations failure. */ -#define ADC_ERR_OVERFLOW 2U /**< ADC overflow condition. */ -#define ADC_ERR_AWD 4U /**< Watchdog triggered. */ +#define ADC_ERR_DMAFAILURE 1U /**< DMA operations failure. */ +#define ADC_ERR_OVERFLOW 2U /**< ADC overflow condition. */ +#define ADC_ERR_AWD 4U /**< Watchdog triggered. */ /** @} */ /*===========================================================================*/ @@ -54,7 +54,7 @@ * @note The default is @p FALSE. */ #if !defined(SAM_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define SAM_ADC_USE_ADC1 FALSE +#define SAM_ADC_USE_ADC1 FALSE #endif /** @} */ @@ -88,31 +88,31 @@ typedef uint32_t adcerror_t; /** * @brief Low level fields of the ADC driver structure. */ -#define adc_lld_driver_fields \ - /* Dummy field, it is not needed.*/ \ - adc_registers_t* adc; \ - uint8_t dmacId; \ - uint16_t curr_size; \ - uint8_t curr_pin; +#define adc_lld_driver_fields \ + /* Dummy field, it is not needed.*/ \ + adc_registers_t* adc; \ + uint8_t dmacId; \ + uint16_t curr_size; \ + uint8_t curr_pin; /** * @brief Low level fields of the ADC configuration structure. */ -#define adc_lld_config_fields \ - /* Dummy configuration, it is not needed.*/ \ - uint32_t dummy +#define adc_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy /** * @brief Low level fields of the ADC configuration structure. */ -#define adc_lld_configuration_group_fields \ - /* Dummy configuration, it is not needed.*/ \ - uint8_t refctrl; \ - uint8_t avgctrl; \ - uint8_t sampctrl; \ - uint16_t ctrlb; \ - uint32_t inputctrl; \ - uint8_t *seq; +#define adc_lld_configuration_group_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint8_t refctrl; \ + uint8_t avgctrl; \ + uint8_t sampctrl; \ + uint16_t ctrlb; \ + uint32_t inputctrl; \ + uint8_t* seq; /*===========================================================================*/ /* External declarations. */ @@ -125,11 +125,11 @@ extern ADCDriver ADCD1; #ifdef __cplusplus extern "C" { #endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); +void adc_lld_init(void); +void adc_lld_start(ADCDriver* adcp); +void adc_lld_stop(ADCDriver* adcp); +void adc_lld_start_conversion(ADCDriver* adcp); +void adc_lld_stop_conversion(ADCDriver* adcp); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/SAM/LLD/DMACv1/sam_dmac.c b/os/hal/ports/SAM/LLD/DMACv1/sam_dmac.c index e8c8216302..87e10249ba 100644 --- a/os/hal/ports/SAM/LLD/DMACv1/sam_dmac.c +++ b/os/hal/ports/SAM/LLD/DMACv1/sam_dmac.c @@ -2,17 +2,16 @@ #if defined(SAM_DMAC_REQUIRED) || defined(__DOXYGEN__) -static struct -{ +static struct { /** * @brief Mask of the allocated streams. */ uint32_t allocated_mask; + /** * @brief DMA IRQ redirectors. */ - struct - { + struct { /** * @brief DMA callback function. */ @@ -20,12 +19,14 @@ static struct /** * @brief DMA callback parameter. */ - void *param; + void* param; } channel[SAM_DMAC_CHAN_NUM]; } dmac; -static dmac_descriptor_registers_t descriptor_section[SAM_DMAC_CHAN_NUM] __ALIGNED(16); -static dmac_descriptor_registers_t writeback_section[SAM_DMAC_CHAN_NUM] __ALIGNED(16); +static dmac_descriptor_registers_t + descriptor_section[SAM_DMAC_CHAN_NUM] __ALIGNED(16); +static dmac_descriptor_registers_t + writeback_section[SAM_DMAC_CHAN_NUM] __ALIGNED(16); const sam_dmac_chnl_t _sam_dmac_chnl[SAM_DMAC_CHAN_NUM] = { {&descriptor_section[0], &writeback_section[0]}, @@ -40,14 +41,35 @@ const sam_dmac_chnl_t _sam_dmac_chnl[SAM_DMAC_CHAN_NUM] = { {&descriptor_section[9], &writeback_section[9]}, {&descriptor_section[10], &writeback_section[10]}, {&descriptor_section[11], &writeback_section[11]}, +#if (SAM_DMAC_CHAN_NUM > 12) + {&descriptor_section[12], &writeback_section[12]}, + {&descriptor_section[13], &writeback_section[13]}, + {&descriptor_section[14], &writeback_section[14]}, + {&descriptor_section[15], &writeback_section[15]}, + {&descriptor_section[16], &writeback_section[16]}, + {&descriptor_section[17], &writeback_section[17]}, + {&descriptor_section[18], &writeback_section[18]}, + {&descriptor_section[19], &writeback_section[19]}, + {&descriptor_section[20], &writeback_section[20]}, + {&descriptor_section[21], &writeback_section[21]}, + {&descriptor_section[22], &writeback_section[22]}, + {&descriptor_section[23], &writeback_section[23]}, + {&descriptor_section[24], &writeback_section[24]}, + {&descriptor_section[25], &writeback_section[25]}, + {&descriptor_section[26], &writeback_section[26]}, + {&descriptor_section[27], &writeback_section[27]}, + {&descriptor_section[28], &writeback_section[28]}, + {&descriptor_section[29], &writeback_section[29]}, + {&descriptor_section[30], &writeback_section[30]}, + {&descriptor_section[31], &writeback_section[31]}, +#endif }; /** * @brief Initialize DMAC Peripheral * */ -void dmacInit(void) -{ +void dmacInit(void) { PM_REGS->PM_APBBMASK |= PM_APBBMASK_DMAC_Msk; PM_REGS->PM_AHBMASK |= PM_AHBMASK_DMAC_Msk; @@ -55,18 +77,21 @@ void dmacInit(void) DMAC_REGS->DMAC_CTRL = DMAC_CTRL_SWRST_Msk; DMAC_REGS->DMAC_BASEADDR = (uint32_t)&descriptor_section[0]; DMAC_REGS->DMAC_WRBADDR = (uint32_t)&writeback_section[0]; - DMAC_REGS->DMAC_PRICTRL0 = DMAC_PRICTRL0_LVLPRI0(1UL) | DMAC_PRICTRL0_RRLVLEN0_Msk | - DMAC_PRICTRL0_LVLPRI1(1UL) | DMAC_PRICTRL0_RRLVLEN1_Msk | - DMAC_PRICTRL0_LVLPRI2(1UL) | DMAC_PRICTRL0_RRLVLEN2_Msk | - DMAC_PRICTRL0_LVLPRI3(1UL) | DMAC_PRICTRL0_RRLVLEN3_Msk; + DMAC_REGS->DMAC_PRICTRL0 = + DMAC_PRICTRL0_LVLPRI0(1UL) | DMAC_PRICTRL0_RRLVLEN0_Msk | + DMAC_PRICTRL0_LVLPRI1(1UL) | DMAC_PRICTRL0_RRLVLEN1_Msk | + DMAC_PRICTRL0_LVLPRI2(1UL) | DMAC_PRICTRL0_RRLVLEN2_Msk | + DMAC_PRICTRL0_LVLPRI3(1UL) | DMAC_PRICTRL0_RRLVLEN3_Msk; unsigned i; dmac.allocated_mask = 0; - for (i = 0; i < SAM_DMAC_CHAN_NUM; i++) - { + for (i = 0; i < SAM_DMAC_CHAN_NUM; i++) { dmac.channel[i].func = NULL; dmac.channel[i].param = NULL; } - DMAC_REGS->DMAC_CTRL = (uint16_t)(DMAC_CTRL_DMAENABLE_Msk | DMAC_CTRL_LVLEN0_Msk | DMAC_CTRL_LVLEN1_Msk | DMAC_CTRL_LVLEN2_Msk | DMAC_CTRL_LVLEN3_Msk); + DMAC_REGS->DMAC_CTRL = + (uint16_t)(DMAC_CTRL_DMAENABLE_Msk | DMAC_CTRL_LVLEN0_Msk | + DMAC_CTRL_LVLEN1_Msk | DMAC_CTRL_LVLEN2_Msk | + DMAC_CTRL_LVLEN3_Msk); nvicEnableVector(DMAC_IRQn, SAM_DMAC_IRQ_PRIORITY); } @@ -80,32 +105,24 @@ void dmacInit(void) * @return int8_t the channel ID * if unable to then return -1 */ -int8_t dmacChnlAllocI(uint8_t id, - uint8_t priority, - sam_dmaisr_t func, - void *param) -{ +int8_t dmacChnlAllocI(uint8_t id, uint8_t priority, sam_dmaisr_t func, + void* param) { uint32_t i, startid, endid; osalDbgCheckClassI(); - if (id < SAM_DMAC_NUM_MAX) - { + if (id < SAM_DMAC_NUM_MAX) { startid = id; endid = id; - } - else - { + } else { startid = 0; endid = SAM_DMAC_NUM_MAX - 1; } - for (i = startid; i <= endid; i++) - { + for (i = startid; i <= endid; i++) { uint32_t mask = (1U << i); - if ((dmac.allocated_mask & mask) == 0U) - { - const sam_dmac_chnl_t *dmastp = &_sam_dmac_chnl[i]; + if ((dmac.allocated_mask & mask) == 0U) { + const sam_dmac_chnl_t* dmastp = &_sam_dmac_chnl[i]; dmastp->desc->DMAC_BTCTRL |= DMAC_BTCTRL_VALID_Msk; /* Installs the DMA handler. */ dmac.channel[i].func = func; @@ -120,11 +137,8 @@ int8_t dmacChnlAllocI(uint8_t id, return -1; } -int8_t dmacChnlAlloc(uint8_t id, - uint8_t priority, - sam_dmaisr_t func, - void *param) -{ +int8_t dmacChnlAlloc(uint8_t id, uint8_t priority, sam_dmaisr_t func, + void* param) { int8_t dmac_id = -1; osalSysLock(); dmac_id = dmacChnlAllocI(id, priority, func, param); @@ -132,8 +146,7 @@ int8_t dmacChnlAlloc(uint8_t id, return dmac_id; } -void dmacChnlFreeI(uint8_t id) -{ +void dmacChnlFreeI(uint8_t id) { osalDbgCheckClassI(); dmacChnlDisableIRQn(id); dmacChnlDisable(id); @@ -142,14 +155,16 @@ void dmacChnlFreeI(uint8_t id) dmac.allocated_mask &= ~(1 << (uint32_t)id); } -void dmacChnlFree(uint8_t id) -{ +void dmacChnlFree(uint8_t id) { osalSysLock(); dmacChnlFreeI(id); osalSysUnlock(); } - +#ifdef SAMD21_CONF OSAL_IRQ_HANDLER(DMAC_HANDLER) +#elif SAME54_CONF +OSAL_IRQ_HANDLER(DMAC_4_31_HANDLER) +#endif { OSAL_IRQ_PROLOGUE(); uint8_t channel = 0U; @@ -158,8 +173,7 @@ OSAL_IRQ_HANDLER(DMAC_HANDLER) DMAC_REGS->DMAC_CHID = channel; chanIntFlagStatus = (uint8_t)DMAC_REGS->DMAC_CHINTFLAG; dmacChnlDisableIRQn(channel); - if (dmac.channel[channel].func != NULL) - { + if (dmac.channel[channel].func != NULL) { dmac.channel[channel].func(dmac.channel[channel].param, chanIntFlagStatus); } OSAL_IRQ_EPILOGUE(); diff --git a/os/hal/ports/SAM/LLD/DMACv1/sam_dmac.h b/os/hal/ports/SAM/LLD/DMACv1/sam_dmac.h index a9af9b5b85..de0d661c23 100644 --- a/os/hal/ports/SAM/LLD/DMACv1/sam_dmac.h +++ b/os/hal/ports/SAM/LLD/DMACv1/sam_dmac.h @@ -6,8 +6,8 @@ /* Driver constants. */ /*===========================================================================*/ #define SAM_DMAC_NUM_MAX SAM_DMAC_CHAN_NUM -typedef enum -{ + +typedef enum { DISABLE = 0, SERCOM0_RX, SERCOM0_TX, @@ -60,8 +60,7 @@ typedef enum TCC3_MC3, } dmac_trigsrc_t; -typedef enum -{ +typedef enum { BLOCK = 0, BEAT = 2, TRANSACTION, @@ -86,14 +85,24 @@ typedef enum * @param[in] flags pre-shifted content of the ISR register, the bits * are aligned to bit zero */ -typedef void (*sam_dmaisr_t)(void *p, uint8_t flags); +typedef void (*sam_dmaisr_t)(void* p, uint8_t flags); -typedef struct -{ - dmac_descriptor_registers_t *desc; - dmac_descriptor_registers_t *wb; +typedef struct { + dmac_descriptor_registers_t* desc; + dmac_descriptor_registers_t* wb; } sam_dmac_chnl_t; +typedef struct { + uint8_t DMAC_CHCTRLA; + uint8_t reserved0[3]; + uint32_t DMAC_CHCTRLB; + uint32_t reserved1[2]; + uint8_t DMAC_CHINTENCLR; + uint8_t DMAC_CHINTENSET; + uint8_t DMAC_CHINTFLAG; + uint8_t DMAC_CHSTATUS; +} sam_dmac_chnl_reg_t; + /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ @@ -106,20 +115,15 @@ extern const sam_dmac_chnl_t _sam_dmac_chnl[SAM_DMAC_CHAN_NUM]; #endif #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif - void dmacInit(void); - int8_t dmacChnlAllocI(uint8_t id, - uint8_t priority, - sam_dmaisr_t func, - void *param); - int8_t dmacChnlAlloc(uint8_t id, - uint8_t priority, - sam_dmaisr_t func, - void *param); - void dmacChnlFree(uint8_t id); - void dmacChnlFreeI(uint8_t id); +void dmacInit(void); +int8_t dmacChnlAllocI(uint8_t id, uint8_t priority, sam_dmaisr_t func, + void* param); +int8_t dmacChnlAlloc(uint8_t id, uint8_t priority, sam_dmaisr_t func, + void* param); +void dmacChnlFree(uint8_t id); +void dmacChnlFreeI(uint8_t id); #ifdef __cplusplus } #endif @@ -127,13 +131,13 @@ extern "C" /*===========================================================================*/ /* Driver inline functions. */ /*===========================================================================*/ -/** + + /** * @brief Resetting DMAC channel * * @param id DMAC Channel */ -static inline void dmacChnlReset(uint8_t id) -{ +static inline void dmacChnlReset(uint8_t id) { DMAC_REGS->DMAC_CHID = id; /* Disable the DMA channel */ DMAC_REGS->DMAC_CHCTRLA = (uint8_t)(DMAC_CHCTRLA_SWRST_Msk); @@ -148,8 +152,7 @@ static inline void dmacChnlReset(uint8_t id) * @param id DMAC Channel * @return uint16_t bytes have been transferred */ -static inline uint16_t dmacChnlGetTransferred(uint8_t id) -{ +static inline uint16_t dmacChnlGetTransferred(uint8_t id) { uint16_t transferredCount = _sam_dmac_chnl[id].desc->DMAC_BTCNT; transferredCount -= _sam_dmac_chnl[id].wb->DMAC_BTCNT; return (transferredCount); @@ -162,8 +165,7 @@ static inline uint16_t dmacChnlGetTransferred(uint8_t id) * @param id DMAC Channel * @param prio channel priority */ -static inline void dmacChnlSetPrio(uint8_t id, uint8_t prio) -{ +static inline void dmacChnlSetPrio(uint8_t id, uint8_t prio) { DMAC_REGS->DMAC_CHID = id; osalDbgAssert(prio < 3, "DMAC Priority out of range"); uint8_t chctrlb = DMAC_REGS->DMAC_CHCTRLB; @@ -177,8 +179,7 @@ static inline void dmacChnlSetPrio(uint8_t id, uint8_t prio) * * @param id DMAC Channel */ -static inline void dmacChnlEnable(uint8_t id) -{ +static inline void dmacChnlEnable(uint8_t id) { DMAC_REGS->DMAC_CHID = id; DMAC_REGS->DMAC_CHCTRLA |= (uint8_t)(DMAC_CHCTRLA_ENABLE_Msk); } @@ -188,8 +189,7 @@ static inline void dmacChnlEnable(uint8_t id) * * @param id DMAC Channel */ -static inline void dmacChnlDisable(uint8_t id) -{ +static inline void dmacChnlDisable(uint8_t id) { DMAC_REGS->DMAC_CHID = id; DMAC_REGS->DMAC_CHCTRLA &= (uint8_t)(~DMAC_CHCTRLA_ENABLE_Msk); } @@ -200,16 +200,16 @@ static inline void dmacChnlDisable(uint8_t id) * @param id DMAC Channel * @param btctrl */ -static inline void dmacChnlSetBtCtrl(uint8_t id, uint16_t btctrl) -{ - dmac_descriptor_registers_t *dmacDescReg = _sam_dmac_chnl[id].desc; +static inline void dmacChnlSetBtCtrl(uint8_t id, uint16_t btctrl) { + dmac_descriptor_registers_t* dmacDescReg = _sam_dmac_chnl[id].desc; dmacDescReg->DMAC_BTCTRL = btctrl; } -static inline uint8_t dmacChnlGetBeatSize(uint8_t id) -{ - dmac_descriptor_registers_t *dmacDescReg = _sam_dmac_chnl[id].desc; - uint8_t beat_size = (uint8_t)((dmacDescReg->DMAC_BTCTRL & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos); +static inline uint8_t dmacChnlGetBeatSize(uint8_t id) { + dmac_descriptor_registers_t* dmacDescReg = _sam_dmac_chnl[id].desc; + uint8_t beat_size = + (uint8_t)((dmacDescReg->DMAC_BTCTRL & DMAC_BTCTRL_BEATSIZE_Msk) >> + DMAC_BTCTRL_BEATSIZE_Pos); return 1u << beat_size; } @@ -219,8 +219,7 @@ static inline uint8_t dmacChnlGetBeatSize(uint8_t id) * @param id DMAC Channel * @param src source to trigger */ -static inline void dmacChnlSetTrigSrc(uint8_t id, dmac_trigsrc_t src) -{ +static inline void dmacChnlSetTrigSrc(uint8_t id, dmac_trigsrc_t src) { DMAC_REGS->DMAC_CHID = id; uint32_t chctrlb = DMAC_REGS->DMAC_CHCTRLB; chctrlb &= ~DMAC_CHCTRLB_TRIGSRC_Msk; @@ -233,8 +232,7 @@ static inline void dmacChnlSetTrigSrc(uint8_t id, dmac_trigsrc_t src) * * @param id DMAC Channel */ -static inline void dmacChnlEnableEventOut(uint8_t id) -{ +static inline void dmacChnlEnableEventOut(uint8_t id) { osalDbgAssert(id < 3, "Cannot map to EVSYS"); DMAC_REGS->DMAC_CHID = id; DMAC_REGS->DMAC_CHCTRLB |= DMAC_CHCTRLB_EVOE_Msk; @@ -245,10 +243,10 @@ static inline void dmacChnlEnableEventOut(uint8_t id) * * @param id DMAC Channel */ -static inline void dmacChnlEnableIRQn(uint8_t id) -{ +static inline void dmacChnlEnableIRQn(uint8_t id) { DMAC_REGS->DMAC_CHID = id; - DMAC_REGS->DMAC_CHINTENSET = (uint8_t)(DMAC_CHINTENSET_TCMPL_Msk | DMAC_CHINTENSET_TERR_Msk); + DMAC_REGS->DMAC_CHINTENSET = + (uint8_t)(DMAC_CHINTENSET_TCMPL_Msk | DMAC_CHINTENSET_TERR_Msk); } /** @@ -256,10 +254,10 @@ static inline void dmacChnlEnableIRQn(uint8_t id) * * @param id DMAC Channel */ -static inline void dmacChnlDisableIRQn(uint8_t id) -{ +static inline void dmacChnlDisableIRQn(uint8_t id) { DMAC_REGS->DMAC_CHID = id; - DMAC_REGS->DMAC_CHINTENCLR = (uint8_t)(DMAC_CHINTENCLR_TCMPL_Msk | DMAC_CHINTENCLR_TERR_Msk); + DMAC_REGS->DMAC_CHINTENCLR = + (uint8_t)(DMAC_CHINTENCLR_TCMPL_Msk | DMAC_CHINTENCLR_TERR_Msk); } /** @@ -268,8 +266,7 @@ static inline void dmacChnlDisableIRQn(uint8_t id) * @param id DMAC Channel */ -static inline void dmacChnlSetTrigAct(uint8_t id, dmac_trigact_t act) -{ +static inline void dmacChnlSetTrigAct(uint8_t id, dmac_trigact_t act) { DMAC_REGS->DMAC_CHID = id; uint32_t chctrlb = DMAC_REGS->DMAC_CHCTRLB; chctrlb &= ~DMAC_CHCTRLB_TRIGACT_Msk; @@ -285,24 +282,20 @@ static inline void dmacChnlSetTrigAct(uint8_t id, dmac_trigact_t act) * @param srcAddr Source Address * @param size number of transfer need to be made per beat */ -static inline void dmacChnlSetDir(uint8_t id, uint32_t dstAddr, uint32_t srcAddr, uint16_t size) -{ - dmac_descriptor_registers_t *dmacDescReg = _sam_dmac_chnl[id].desc; +static inline void dmacChnlSetDir(uint8_t id, uint32_t dstAddr, + uint32_t srcAddr, uint16_t size) { + dmac_descriptor_registers_t* dmacDescReg = _sam_dmac_chnl[id].desc; dmacDescReg->DMAC_BTCNT = size; - if ((dmacDescReg->DMAC_BTCTRL & DMAC_BTCTRL_DSTINC_Msk) == DMAC_BTCTRL_DSTINC_Msk) - { + if ((dmacDescReg->DMAC_BTCTRL & DMAC_BTCTRL_DSTINC_Msk) == + DMAC_BTCTRL_DSTINC_Msk) { dmacDescReg->DMAC_DSTADDR = dstAddr + size * dmacChnlGetBeatSize(id); - } - else - { + } else { dmacDescReg->DMAC_DSTADDR = dstAddr; } - if ((dmacDescReg->DMAC_BTCTRL & DMAC_BTCTRL_SRCINC_Msk) == DMAC_BTCTRL_SRCINC_Msk) - { + if ((dmacDescReg->DMAC_BTCTRL & DMAC_BTCTRL_SRCINC_Msk) == + DMAC_BTCTRL_SRCINC_Msk) { dmacDescReg->DMAC_SRCADDR = srcAddr + size * dmacChnlGetBeatSize(id); - } - else - { + } else { dmacDescReg->DMAC_SRCADDR = srcAddr; } } @@ -325,9 +318,8 @@ static inline void dmacChnlSetDir(uint8_t id, uint32_t dstAddr, uint32_t srcAddr * @param id * @return uint32_t */ -static inline uint32_t dmacChnlGetDstAddr(uint8_t id) -{ - dmac_descriptor_registers_t *dmacDescReg = _sam_dmac_chnl[id].desc; +static inline uint32_t dmacChnlGetDstAddr(uint8_t id) { + dmac_descriptor_registers_t* dmacDescReg = _sam_dmac_chnl[id].desc; return dmacDescReg->DMAC_DSTADDR; } diff --git a/os/hal/ports/SAM/LLD/DMACv2/driver.mk b/os/hal/ports/SAM/LLD/DMACv2/driver.mk new file mode 100644 index 0000000000..5616fc571c --- /dev/null +++ b/os/hal/ports/SAM/LLD/DMACv2/driver.mk @@ -0,0 +1,2 @@ +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SAM/LLD/DMACv2/sam_dmac.c +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SAM/LLD/DMACv2 diff --git a/os/hal/ports/SAM/LLD/DMACv2/sam_dmac.c b/os/hal/ports/SAM/LLD/DMACv2/sam_dmac.c new file mode 100644 index 0000000000..e9c37a3784 --- /dev/null +++ b/os/hal/ports/SAM/LLD/DMACv2/sam_dmac.c @@ -0,0 +1,219 @@ +#include "hal.h" + +#if defined(SAM_DMAC_REQUIRED) || defined(__DOXYGEN__) + +static struct { + /** + * @brief Mask of the allocated streams. + */ + uint32_t allocated_mask; + + /** + * @brief DMA IRQ redirectors. + */ + struct { + /** + * @brief DMA callback function. + */ + sam_dmaisr_t func; + /** + * @brief DMA callback parameter. + */ + void* param; + } channel[SAM_DMAC_CHAN_NUM]; +} dmac; + +static dmac_descriptor_registers_t + descriptor_section[SAM_DMAC_CHAN_NUM] __ALIGNED(16); +static dmac_descriptor_registers_t + writeback_section[SAM_DMAC_CHAN_NUM] __ALIGNED(16); + +const sam_dmac_chnl_t _sam_dmac_chnl[SAM_DMAC_CHAN_NUM] = { + {&descriptor_section[0], &writeback_section[0]}, + {&descriptor_section[1], &writeback_section[1]}, + {&descriptor_section[2], &writeback_section[2]}, + {&descriptor_section[3], &writeback_section[3]}, + {&descriptor_section[4], &writeback_section[4]}, + {&descriptor_section[5], &writeback_section[5]}, + {&descriptor_section[6], &writeback_section[6]}, + {&descriptor_section[7], &writeback_section[7]}, + {&descriptor_section[8], &writeback_section[8]}, + {&descriptor_section[9], &writeback_section[9]}, + {&descriptor_section[10], &writeback_section[10]}, + {&descriptor_section[11], &writeback_section[11]}, + {&descriptor_section[12], &writeback_section[12]}, + {&descriptor_section[13], &writeback_section[13]}, + {&descriptor_section[14], &writeback_section[14]}, + {&descriptor_section[15], &writeback_section[15]}, + {&descriptor_section[16], &writeback_section[16]}, + {&descriptor_section[17], &writeback_section[17]}, + {&descriptor_section[18], &writeback_section[18]}, + {&descriptor_section[19], &writeback_section[19]}, + {&descriptor_section[20], &writeback_section[20]}, + {&descriptor_section[21], &writeback_section[21]}, + {&descriptor_section[22], &writeback_section[22]}, + {&descriptor_section[23], &writeback_section[23]}, + {&descriptor_section[24], &writeback_section[24]}, + {&descriptor_section[25], &writeback_section[25]}, + {&descriptor_section[26], &writeback_section[26]}, + {&descriptor_section[27], &writeback_section[27]}, + {&descriptor_section[28], &writeback_section[28]}, + {&descriptor_section[29], &writeback_section[29]}, + {&descriptor_section[30], &writeback_section[30]}, + {&descriptor_section[31], &writeback_section[31]}, +}; + +/** + * @brief Initialize DMAC Peripheral + * + */ +void dmacInit(void) { + MCLK_REGS->MCLK_AHBMASK |= MCLK_AHBMASK_DMAC_Msk; + + /* Reset DMAC before usage */ + DMAC_REGS->DMAC_CTRL = DMAC_CTRL_SWRST_Msk; + DMAC_REGS->DMAC_BASEADDR = (uint32_t)&descriptor_section[0]; + DMAC_REGS->DMAC_WRBADDR = (uint32_t)&writeback_section[0]; + DMAC_REGS->DMAC_PRICTRL0 = + DMAC_PRICTRL0_LVLPRI0(1UL) | DMAC_PRICTRL0_RRLVLEN0_Msk | + DMAC_PRICTRL0_LVLPRI1(1UL) | DMAC_PRICTRL0_RRLVLEN1_Msk | + DMAC_PRICTRL0_LVLPRI2(1UL) | DMAC_PRICTRL0_RRLVLEN2_Msk | + DMAC_PRICTRL0_LVLPRI3(1UL) | DMAC_PRICTRL0_RRLVLEN3_Msk; + unsigned i; + dmac.allocated_mask = 0; + for (i = 0; i < SAM_DMAC_CHAN_NUM; i++) { + dmac.channel[i].func = NULL; + dmac.channel[i].param = NULL; + } + DMAC_REGS->DMAC_CTRL = + (uint16_t)(DMAC_CTRL_DMAENABLE_Msk | DMAC_CTRL_LVLEN0_Msk | + DMAC_CTRL_LVLEN1_Msk | DMAC_CTRL_LVLEN2_Msk | + DMAC_CTRL_LVLEN3_Msk); + nvicEnableVector(DMAC_0_IRQn, SAM_DMAC_IRQ_PRIORITY); + nvicEnableVector(DMAC_1_IRQn, SAM_DMAC_IRQ_PRIORITY); + nvicEnableVector(DMAC_2_IRQn, SAM_DMAC_IRQ_PRIORITY); + nvicEnableVector(DMAC_3_IRQn, SAM_DMAC_IRQ_PRIORITY); + nvicEnableVector(DMAC_OTHER_IRQn, SAM_DMAC_IRQ_PRIORITY); +} + +/** + * @brief Obtain DMAC Channel from the pool + * + * @param id DMAC Channel + * @param priority Priority for that channel + * @param func callback function + * @param param parameters to input for that callback + * @return int8_t the channel ID + * if unable to then return -1 + */ +int8_t dmacChnlAllocI(uint8_t id, uint8_t priority, sam_dmaisr_t func, + void* param) { + uint32_t i, startid, endid; + + osalDbgCheckClassI(); + + if (id < SAM_DMAC_NUM_MAX) { + startid = id; + endid = id; + } else { + startid = 0; + endid = SAM_DMAC_NUM_MAX - 1; + } + + for (i = startid; i <= endid; i++) { + uint32_t mask = (1U << i); + if ((dmac.allocated_mask & mask) == 0U) { + const sam_dmac_chnl_t* dmastp = &_sam_dmac_chnl[i]; + dmastp->desc->DMAC_BTCTRL |= DMAC_BTCTRL_VALID_Msk; + /* Installs the DMA handler. */ + dmac.channel[i].func = func; + dmac.channel[i].param = param; + dmac.allocated_mask |= mask; + /* Resetting the channel */ + dmacChnlReset(i); + dmacChnlSetPrio(i, priority); + return (int8_t)i; + } + } + return -1; +} + +int8_t dmacChnlAlloc(uint8_t id, uint8_t priority, sam_dmaisr_t func, + void* param) { + int8_t dmac_id = -1; + osalSysLock(); + dmac_id = dmacChnlAllocI(id, priority, func, param); + osalSysUnlock(); + return dmac_id; +} + +void dmacChnlFreeI(uint8_t id) { + osalDbgCheckClassI(); + dmacChnlDisableIRQn(id); + dmacChnlDisable(id); + dmac.channel[id].func = NULL; + dmac.channel[id].param = NULL; + dmac.allocated_mask &= ~(1 << (uint32_t)id); +} + +void dmacChnlFree(uint8_t id) { + osalSysLock(); + dmacChnlFreeI(id); + osalSysUnlock(); +} + +static void dmacInterrupt(uint8_t id) +{ + uint8_t chanIntFlagStatus = 0U; + + chanIntFlagStatus = (uint8_t)DMAC_REGS->CHANNEL[id].DMAC_CHINTFLAG; + dmacChnlDisableIRQn(id); + if (dmac.channel[id].func != NULL) { + dmac.channel[id].func(dmac.channel[id].param, chanIntFlagStatus); + } +} + +OSAL_IRQ_HANDLER(SAM_DMAC_0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + dmacInterrupt(0); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_DMAC_1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + dmacInterrupt(1); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_DMAC_2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + dmacInterrupt(2); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_DMAC_3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + dmacInterrupt(3); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_DMAC_4_31_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + uint32_t chIntMsk = 0U; + uint32_t chIntPos = 0U; + for (uint8_t i = 4; i <= 31; ++i) + { + chIntPos = (uint32_t)i; + chIntMsk = (1 << chIntPos); + uint32_t intVal = DMAC_REGS->DMAC_INTSTATUS; + if ((intVal & chIntMsk) != 0) + { + dmacInterrupt(i); + } + } + OSAL_IRQ_EPILOGUE(); +} + +#endif \ No newline at end of file diff --git a/os/hal/ports/SAM/LLD/DMACv2/sam_dmac.h b/os/hal/ports/SAM/LLD/DMACv2/sam_dmac.h new file mode 100644 index 0000000000..623f93ad0c --- /dev/null +++ b/os/hal/ports/SAM/LLD/DMACv2/sam_dmac.h @@ -0,0 +1,357 @@ +#ifndef SAM_DMAC_H_ +#define SAM_DMAC_H_ + + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ +#include "sam.h" +#define SAM_DMAC_NUM_MAX SAM_DMAC_CHAN_NUM + +typedef enum { + DISABLE = 0x00, + RESERVED1 = 0x01, + RESERVED2 = 0x02, + RESERVED3 = 0x03, + SERCOM0_RX = 0x04, + SERCOM0_TX = 0x05, + SERCOM1_RX = 0x06, + SERCOM1_TX = 0x07, + SERCOM2_RX = 0x08, + SERCOM2_TX = 0x09, + SERCOM3_RX = 0x0A, + SERCOM3_TX = 0x0B, + SERCOM4_RX = 0x0C, + SERCOM4_TX = 0x0D, + SERCOM5_RX = 0x0E, + SERCOM5_TX = 0x0F, + SERCOM6_RX = 0x10, + SERCOM6_TX = 0x11, + SERCOM7_RX = 0x12, + SERCOM7_TX = 0x13, + CAN0_DBG = 0x14, + CAN1_DBG = 0x15, + TCC0_OVF = 0x16, + TCC0_MC0 = 0x17, + TCC0_MC1 = 0x18, + TCC0_MC2 = 0x19, + TCC0_MC3 = 0x1A, + TCC0_MC4 = 0x1B, + TCC0_MC5 = 0x1C, + TCC1_OVF = 0x1D, + TCC1_MC0 = 0x1E, + TCC1_MC1 = 0x1F, + TCC1_MC2 = 0x20, + TCC1_MC3 = 0x21, + TCC2_OVF = 0x22, + TCC2_MC0 = 0x23, + TCC2_MC1 = 0x24, + TCC2_MC2 = 0x25, + TCC3_OVF = 0x26, + TCC3_MC0 = 0x27, + TCC3_MC1 = 0x28, + TCC4_OVF = 0x29, + TCC4_MC1 = 0x2A, + TCC4_MC2 = 0x2B, + TC0_OVF = 0x2C, + TC0_MC0 = 0x2D, + TC0_MC1 = 0x2E, + TC1_OVF = 0x2F, + TC1_MC0 = 0x30, + TC1_MC1 = 0x31, + TC2_OVF = 0x32, + TC2_MC0 = 0x33, + TC2_MC1 = 0x34, + TC3_OVF = 0x35, + TC3_MC0 = 0x36, + TC3_MC1 = 0x37, + TC4_OVF = 0x38, + TC4_MC0 = 0x39, + TC4_MC1 = 0x3A, + TC5_OVF = 0x3B, + TC5_MC0 = 0x3C, + TC5_MC1 = 0x3D, + TC6_OVF = 0x3E, + TC6_MC0 = 0x3F, + TC6_MC1 = 0x40, + TC7_OVF = 0x41, + TC7_MC0 = 0x42, + TC7_MC1 = 0x43, + ADC0_RESRDY = 0x44, + ADC0_SEQ = 0x45, + ADC1_RESRDY = 0x46, + ADC1_SEQ = 0x47, + DAC0_EMPTY = 0x48, + DAC0_RESRDY = 0x49, + DAC1_EMPTY = 0x4A, + DAC1_RESRDY = 0x4B, + I2S_RX0 = 0x4C, + I2S_RX1 = 0x4D, + I2S_TX0 = 0x4E, + I2S_TX1 = 0x4F, + PCC_RX = 0x50, + AES_WR = 0x51, + AES_RD = 0x52, + QSPI_RX = 0x53, + QSPI_TX = 0x54, +} dmac_trigsrc_t; + + + +typedef enum { + BLOCK = 0x0, + RSVD = 0x1, + BURST = 0x2, + TRANSACTION = 0x3, +} dmac_trigact_t; + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a DMA callback. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register, the bits + * are aligned to bit zero + */ +typedef void (*sam_dmaisr_t)(void* p, uint8_t flags); + +typedef struct { + dmac_descriptor_registers_t* desc; + dmac_descriptor_registers_t* wb; +} sam_dmac_chnl_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ +#if !defined(__DOXYGEN__) +extern const sam_dmac_chnl_t _sam_dmac_chnl[SAM_DMAC_CHAN_NUM]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif +void dmacInit(void); +int8_t dmacChnlAllocI(uint8_t id, uint8_t priority, sam_dmaisr_t func, + void* param); +int8_t dmacChnlAlloc(uint8_t id, uint8_t priority, sam_dmaisr_t func, + void* param); +void dmacChnlFree(uint8_t id); +void dmacChnlFreeI(uint8_t id); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + + /** + * @brief Resetting DMAC channel + * + * @param id DMAC Channel + */ +static inline void dmacChnlReset(uint8_t id) { + /* Disable the DMA channel */ + DMAC_REGS->CHANNEL[id].DMAC_CHCTRLA = (DMAC_CHCTRLA_SWRST_Msk); + while ((DMAC_REGS->CHANNEL[id].DMAC_CHCTRLA & DMAC_CHCTRLA_ENABLE_Msk) != 0U) + ; +} + +/** + * @brief Check DMAC how many bytes has been transferred + * + * @param id DMAC Channel + * @return uint16_t bytes have been transferred + */ +static inline uint16_t dmacChnlGetTransferred(uint8_t id) { + uint16_t transferredCount = _sam_dmac_chnl[id].desc->DMAC_BTCNT; + transferredCount -= _sam_dmac_chnl[id].wb->DMAC_BTCNT; + return (transferredCount); +} + +/** + * @brief Set Priority of DMAC + * Can only run when the channel is not enabled + * + * @param id DMAC Channel + * @param prio channel priority + */ +static inline void dmacChnlSetPrio(uint8_t id, uint8_t prio) { + osalDbgAssert(prio < 3, "DMAC Priority out of range"); + DMAC_REGS->CHANNEL[id].DMAC_CHPRILVL &= ~DMAC_CHPRILVL_PRILVL_Msk; + DMAC_REGS->CHANNEL[id].DMAC_CHPRILVL |= DMAC_CHPRILVL_PRILVL(prio); +} + +/** + * @brief Enable DMAC Channel + * + * @param id DMAC Channel + */ +static inline void dmacChnlEnable(uint8_t id) { + DMAC_REGS->CHANNEL[id].DMAC_CHCTRLA |= (DMAC_CHCTRLA_ENABLE_Msk); +} + +/** + * @brief Disable DMAC Channel + * + * @param id DMAC Channel + */ +static inline void dmacChnlDisable(uint8_t id) { + DMAC_REGS->CHANNEL[id].DMAC_CHCTRLA &= (~DMAC_CHCTRLA_ENABLE_Msk); +} + +/** + * @brief Setting BTCTRL for the DMAC Channel + * + * @param id DMAC Channel + * @param btctrl + */ +static inline void dmacChnlSetBtCtrl(uint8_t id, uint16_t btctrl) { + dmac_descriptor_registers_t* dmacDescReg = _sam_dmac_chnl[id].desc; + dmacDescReg->DMAC_BTCTRL = btctrl; +} + +static inline uint8_t dmacChnlGetBeatSize(uint8_t id) { + dmac_descriptor_registers_t* dmacDescReg = _sam_dmac_chnl[id].desc; + uint8_t beat_size = + (uint8_t)((dmacDescReg->DMAC_BTCTRL & DMAC_BTCTRL_BEATSIZE_Msk) >> + DMAC_BTCTRL_BEATSIZE_Pos); + return 1u << beat_size; +} + + +/** + * @brief Set trigger SRC + * + * @param id DMAC Channel + * @param src source to trigger + */ +static inline void dmacChnlSetTrigSrc(uint8_t id, dmac_trigsrc_t src) { + DMAC_REGS->CHANNEL[id].DMAC_CHCTRLA &= ~DMAC_CHCTRLA_TRIGSRC_Msk; + DMAC_REGS->CHANNEL[id].DMAC_CHCTRLA |= DMAC_CHCTRLA_TRIGSRC(src); +} + +/** + * @brief Enabling Event Output to EVSYS (This only works on DMAC 0-3) + * + * @param id DMAC Channel + */ +static inline void dmacChnlEnableEventOut(uint8_t id) { + osalDbgAssert(id < 3, "Cannot map to EVSYS"); + DMAC_REGS->CHANNEL[id].DMAC_CHEVCTRL |= DMAC_CHEVCTRL_EVOE_Msk; +} + +/** + * @brief Enable IRQ for that channel + * + * @param id DMAC Channel + */ +static inline void dmacChnlEnableIRQn(uint8_t id) { + DMAC_REGS->CHANNEL[id].DMAC_CHINTENSET = (DMAC_CHINTENSET_TCMPL_Msk | DMAC_CHINTENSET_TERR_Msk); +} + +/** + * @brief Disable IRQ for that channel + * + * @param id DMAC Channel + */ +static inline void dmacChnlDisableIRQn(uint8_t id) { + DMAC_REGS->CHANNEL[id].DMAC_CHINTENCLR = (DMAC_CHINTENCLR_TCMPL_Msk | DMAC_CHINTENCLR_TERR_Msk); +} + +/** + * @brief Setting trigact for that channel + * + * @param id DMAC Channel + */ +static inline void dmacChnlSetTrigAct(uint8_t id, dmac_trigact_t act) { + DMAC_REGS->CHANNEL[id].DMAC_CHCTRLA &= ~DMAC_CHCTRLA_TRIGACT_Msk; + DMAC_REGS->CHANNEL[id].DMAC_CHCTRLA |= DMAC_CHCTRLA_TRIGACT(act); +} + +/** + * @brief Suspend a DMAC channel + * + * @param id DMAC Channel + */ +static inline void dmacChnlSuspend(uint8_t id) +{ + DMAC_REGS->CHANNEL[id].DMAC_CHCTRLB &= (~DMAC_CHCTRLB_CMD_Msk); + DMAC_REGS->CHANNEL[id].DMAC_CHCTRLB |= (DMAC_CHCTRLB_CMD_SUSPEND); +} + +/** + * @brief Resume a DMAC channel + * + * @param id DMAC Channel + */ +static inline void dmacChnlResume(uint8_t id) +{ + DMAC_REGS->CHANNEL[id].DMAC_CHCTRLB &= (~DMAC_CHCTRLB_CMD_Msk); + DMAC_REGS->CHANNEL[id].DMAC_CHCTRLB |= (DMAC_CHCTRLB_CMD_RESUME); +} + +/** + * @brief Setup Destination as well as Source + * + * @param id DMAC Channel + * @param dstAddr Destination Address + * @param srcAddr Source Address + * @param size number of transfer need to be made per beat + */ +static inline void dmacChnlSetDir(uint8_t id, uint32_t dstAddr, + uint32_t srcAddr, uint16_t size) { + dmac_descriptor_registers_t* dmacDescReg = _sam_dmac_chnl[id].desc; + dmacDescReg->DMAC_BTCNT = size; + if ((dmacDescReg->DMAC_BTCTRL & DMAC_BTCTRL_DSTINC_Msk) == + DMAC_BTCTRL_DSTINC_Msk) { + dmacDescReg->DMAC_DSTADDR = dstAddr + size * dmacChnlGetBeatSize(id); + } else { + dmacDescReg->DMAC_DSTADDR = dstAddr; + } + if ((dmacDescReg->DMAC_BTCTRL & DMAC_BTCTRL_SRCINC_Msk) == + DMAC_BTCTRL_SRCINC_Msk) { + dmacDescReg->DMAC_SRCADDR = srcAddr + size * dmacChnlGetBeatSize(id); + } else { + dmacDescReg->DMAC_SRCADDR = srcAddr; + } +} + +// TODO: fix this function +// static inline void dmacChnlSetCircular(uint8_t id, uint8_t isCircular) +// { +// dmac_descriptor_registers_t *dmacDescReg = _sam_dmac_chnl[id].desc; +// if(isCircular) { +// dmacDescReg->DMAC_DESCADDR = ((uint32_t)dmacDescReg); +// } +// else { +// dmacDescReg->DMAC_DESCADDR = 0U; +// } +// } + +/** + * @brief Get Destination address + * + * @param id + * @return uint32_t + */ +static inline uint32_t dmacChnlGetDstAddr(uint8_t id) { + dmac_descriptor_registers_t* dmacDescReg = _sam_dmac_chnl[id].desc; + return dmacDescReg->DMAC_DSTADDR; +} +#endif \ No newline at end of file diff --git a/os/hal/ports/SAM/LLD/PORTv1/hal_pal_lld.c b/os/hal/ports/SAM/LLD/PORTv1/hal_pal_lld.c index 82e0884a74..fd18a63033 100644 --- a/os/hal/ports/SAM/LLD/PORTv1/hal_pal_lld.c +++ b/os/hal/ports/SAM/LLD/PORTv1/hal_pal_lld.c @@ -29,7 +29,9 @@ /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ - +#ifdef SAME54_MCUCONF +#include "sam_gclk_add.h" +#endif /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -38,61 +40,90 @@ /* Driver local variables and types. */ /*===========================================================================*/ #if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) -#define EIC_CONFIG_SENSE_NONE_Val _U_(0x0) /**< (EIC_CONFIG) No detection */ -#define EIC_CONFIG_SENSE_RISE_Val _U_(0x1) /**< (EIC_CONFIG) Rising edge detection */ -#define EIC_CONFIG_SENSE_FALL_Val _U_(0x2) /**< (EIC_CONFIG) Falling edge detection */ -#define EIC_CONFIG_SENSE_BOTH_Val _U_(0x3) /**< (EIC_CONFIG) Both edges detection */ +#define EIC_CONFIG_SENSE_NONE_Val 0x0 /**< (EIC_CONFIG) No detection */ +#define EIC_CONFIG_SENSE_RISE_Val \ + 0x1 /**< (EIC_CONFIG) Rising edge detection */ +#define EIC_CONFIG_SENSE_FALL_Val \ + 0x2 /**< (EIC_CONFIG) Falling edge detection */ +#define EIC_CONFIG_SENSE_BOTH_Val 0x3 /**< (EIC_CONFIG) Both edges detection */ palevent_t _pal_events[16]; static const uint32_t extint_sense_msk[] = { - EIC_CONFIG_SENSE0_Msk, - EIC_CONFIG_SENSE1_Msk, - EIC_CONFIG_SENSE2_Msk, - EIC_CONFIG_SENSE3_Msk, - EIC_CONFIG_SENSE4_Msk, - EIC_CONFIG_SENSE5_Msk, - EIC_CONFIG_SENSE6_Msk, - EIC_CONFIG_SENSE7_Msk, + EIC_CONFIG_SENSE0_Msk, EIC_CONFIG_SENSE1_Msk, EIC_CONFIG_SENSE2_Msk, + EIC_CONFIG_SENSE3_Msk, EIC_CONFIG_SENSE4_Msk, EIC_CONFIG_SENSE5_Msk, + EIC_CONFIG_SENSE6_Msk, EIC_CONFIG_SENSE7_Msk, }; static const uint32_t extint_filten_msk[] = { - EIC_CONFIG_FILTEN0_Msk, - EIC_CONFIG_FILTEN1_Msk, - EIC_CONFIG_FILTEN2_Msk, - EIC_CONFIG_FILTEN3_Msk, - EIC_CONFIG_FILTEN4_Msk, - EIC_CONFIG_FILTEN5_Msk, - EIC_CONFIG_FILTEN6_Msk, - EIC_CONFIG_FILTEN7_Msk, + EIC_CONFIG_FILTEN0_Msk, EIC_CONFIG_FILTEN1_Msk, EIC_CONFIG_FILTEN2_Msk, + EIC_CONFIG_FILTEN3_Msk, EIC_CONFIG_FILTEN4_Msk, EIC_CONFIG_FILTEN5_Msk, + EIC_CONFIG_FILTEN6_Msk, EIC_CONFIG_FILTEN7_Msk, }; static const uint32_t extint_sense_pos[] = { - EIC_CONFIG_SENSE0_Pos, - EIC_CONFIG_SENSE1_Pos, - EIC_CONFIG_SENSE2_Pos, - EIC_CONFIG_SENSE3_Pos, - EIC_CONFIG_SENSE4_Pos, - EIC_CONFIG_SENSE5_Pos, - EIC_CONFIG_SENSE6_Pos, - EIC_CONFIG_SENSE7_Pos, + EIC_CONFIG_SENSE0_Pos, EIC_CONFIG_SENSE1_Pos, EIC_CONFIG_SENSE2_Pos, + EIC_CONFIG_SENSE3_Pos, EIC_CONFIG_SENSE4_Pos, EIC_CONFIG_SENSE5_Pos, + EIC_CONFIG_SENSE6_Pos, EIC_CONFIG_SENSE7_Pos, }; static const uint32_t extint_filten_pos[] = { - EIC_CONFIG_FILTEN0_Pos, - EIC_CONFIG_FILTEN1_Pos, - EIC_CONFIG_FILTEN2_Pos, - EIC_CONFIG_FILTEN3_Pos, - EIC_CONFIG_FILTEN4_Pos, - EIC_CONFIG_FILTEN5_Pos, - EIC_CONFIG_FILTEN6_Pos, - EIC_CONFIG_FILTEN7_Pos, + EIC_CONFIG_FILTEN0_Pos, EIC_CONFIG_FILTEN1_Pos, EIC_CONFIG_FILTEN2_Pos, + EIC_CONFIG_FILTEN3_Pos, EIC_CONFIG_FILTEN4_Pos, EIC_CONFIG_FILTEN5_Pos, + EIC_CONFIG_FILTEN6_Pos, EIC_CONFIG_FILTEN7_Pos, +}; + +#ifdef SAME54_MCUCONF +static const uint8_t eic_irq_prio[16] = { + SAM_EIC_EXTI0_IRQ_PRIORITY, SAM_EIC_EXTI1_IRQ_PRIORITY, + SAM_EIC_EXTI2_IRQ_PRIORITY, SAM_EIC_EXTI3_IRQ_PRIORITY, + SAM_EIC_EXTI4_IRQ_PRIORITY, SAM_EIC_EXTI5_IRQ_PRIORITY, + SAM_EIC_EXTI6_IRQ_PRIORITY, SAM_EIC_EXTI7_IRQ_PRIORITY, + SAM_EIC_EXTI8_IRQ_PRIORITY, SAM_EIC_EXTI9_IRQ_PRIORITY, + SAM_EIC_EXTI10_IRQ_PRIORITY, SAM_EIC_EXTI11_IRQ_PRIORITY, + SAM_EIC_EXTI12_IRQ_PRIORITY, SAM_EIC_EXTI13_IRQ_PRIORITY, + SAM_EIC_EXTI14_IRQ_PRIORITY, SAM_EIC_EXTI15_IRQ_PRIORITY, }; +#endif + #endif /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) +#ifdef SAME54_MCUCONF + +static inline void pal_lld_serve_interrupt(const uint32_t line) { + unsigned long intflag = 1UL << line; + if ((EIC_REGS->EIC_INTFLAG & intflag) == intflag) { + _pal_isr_code(line); + EIC_REGS->EIC_INTFLAG = (1UL << line); // Clear flag + } +} + +static inline void pal_lld_eic_enable_set(const bool en) { + /* Enable EIC */ + if (en) + EIC_REGS->EIC_CTRLA |= EIC_CTRLA_ENABLE_Msk; + else + EIC_REGS->EIC_CTRLA &= ~EIC_CTRLA_ENABLE_Msk; + while ((EIC_REGS->EIC_SYNCBUSY & EIC_SYNCBUSY_ENABLE_Msk) == + EIC_SYNCBUSY_ENABLE_Msk) {} +} + +#elif defined(SAMD21_MCUCONF) +static inline void pal_lld_eic_enable_set(const bool en) { + /* Enable EIC */ + if (en) + EIC_REGS->EIC_CTRL |= EIC_CTRL_ENABLE_Msk; + else + EIC_REGS->EIC_CTRL &= ~EIC_CTRL_ENABLE_Msk; + while ((EIC_REGS->EIC_STATUS & EIC_STATUS_SYNCBUSY_Msk) == + EIC_STATUS_SYNCBUSY_Msk) {} +} +#endif +#endif /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -108,20 +139,37 @@ static const uint32_t extint_filten_pos[] = { */ void _pal_lld_init(void) { #if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) - PM_REGS->PM_APBAMASK |= PM_APBAMASK_EIC_Msk; // Enable Sync Clock for EIC + +#if defined(SAMD21_MCUCONF) + PM_REGS->PM_APBAMASK |= PM_APBAMASK_EIC_Msk; // Enable Sync Clock for EIC /* Map EIC to Generator 0 */ - sam_gclk_mux(0, GCLK_CLKCTRL_ID_EIC_Val, 1); + sam_gclk_mux(0, GCLK_PCHCTRL_ID_EIC_Val, 1); /* Reset the EIC */ EIC_REGS->EIC_CTRL |= EIC_CTRL_SWRST_Msk; - while((EIC_REGS->EIC_STATUS & EIC_STATUS_SYNCBUSY_Msk) == EIC_STATUS_SYNCBUSY_Msk); - /* Enable the EIC */ - EIC_REGS->EIC_CTRL |= EIC_CTRL_ENABLE_Msk; - while((EIC_REGS->EIC_STATUS & EIC_STATUS_SYNCBUSY_Msk) == EIC_STATUS_SYNCBUSY_Msk); - unsigned i; + while ((EIC_REGS->EIC_STATUS & EIC_STATUS_SYNCBUSY_Msk) == + EIC_STATUS_SYNCBUSY_Msk) + unsigned i; for (i = 0; i < 16; i++) { - _pal_init_event(i); + _pal_init_event(i); } nvicEnableVector(EIC_IRQn, SAM_EIC_IRQ_PRIORITY); + +#elif defined(SAME54_MCUCONF) + MCLK_REGS->MCLK_APBAMASK |= MCLK_APBAMASK_EIC_Msk; + /* Map EIC to Generator 0 */ + sam_gclk_mux(0, GCLK_PCHCTRL_ID_EIC_Val, TRUE); + /* Reset all registers in the EIC module to their initial state and + EIC will be disabled. */ + EIC_REGS->EIC_CTRLA |= (uint8_t)EIC_CTRLA_SWRST_Msk; + + while ((EIC_REGS->EIC_SYNCBUSY & EIC_SYNCBUSY_SWRST_Msk) == + EIC_SYNCBUSY_SWRST_Msk) {} + + for (unsigned i = 0; i < 16; i++) { + _pal_init_event(i); + } +#endif + #endif } @@ -136,41 +184,36 @@ void _pal_lld_init(void) { * * @notapi */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) -{ +void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) { /* Part of PINCFG */ - uint32_t pmuxen = (mode & PAL_SAM_PMUXEN_MASK) >> 0; - uint32_t inen = (mode & PAL_SAM_INEN_MASK) >> 1; - uint32_t pullen = (mode & PAL_SAM_PULLEN_MASK) >> 2; - uint32_t drvstr = (mode & PAL_SAM_DRVSTR_MASK) >> 3; + uint32_t pmuxen = (mode & PAL_SAM_PMUXEN_MASK) >> 0; + uint32_t inen = (mode & PAL_SAM_INEN_MASK) >> 1; + uint32_t pullen = (mode & PAL_SAM_PULLEN_MASK) >> 2; + uint32_t drvstr = (mode & PAL_SAM_DRVSTR_MASK) >> 3; /* DIR and OUT */ - uint32_t dir = (mode & PAL_SAM_DIR_MASK) >> 4; - uint32_t out = (mode & PAL_SAM_OUT_MASK) >> 5; + uint32_t dir = (mode & PAL_SAM_DIR_MASK) >> 4; + uint32_t out = (mode & PAL_SAM_OUT_MASK) >> 5; /* PMUX */ - uint32_t altr = (mode & PAL_SAM_ALTERNATE_MASK) >> 6; - uint32_t bit = 0; + uint32_t altr = (mode & PAL_SAM_ALTERNATE_MASK) >> 6; + uint32_t bit = 0; uint32_t m1; - while(1) { - if((mask & 1) != 0) { - m1 = 1 << bit; - if((out >> bit) == 1) { + while (1) { + if ((mask & 1) != 0) { + m1 = 1 << bit; + if ((out >> bit) == 1) { port->PORT_OUTSET = m1; - } - else { + } else { port->PORT_OUTCLR = m1; } - if((dir >> bit) == 1) { + if ((dir >> bit) == 1) { port->PORT_DIRSET = m1; - } - else { + } else { port->PORT_DIRCLR = m1; } - if(pmuxen == PAL_SAM_PMUXEN_PMUX) { + if (pmuxen == PAL_SAM_PMUXEN_PMUX) { uint8_t pinmux_val = (uint8_t)(port->PORT_PMUX[(bit >> 1)]); /* Odd pin */ - if(0U != (bit & 0x01U)) { + if (0U != (bit & 0x01U)) { pinmux_val = (pinmux_val & ~0xF0U) | (altr << 4); } /* Even pin */ @@ -179,9 +222,10 @@ void _pal_lld_setgroupmode(ioportid_t port, } port->PORT_PMUX[(bit >> 1)] = (uint8_t)pinmux_val; } - uint8_t pincfg_val = (PORT_PINCFG_DRVSTR(drvstr) | PORT_PINCFG_PULLEN(pullen) | - PORT_PINCFG_INEN(inen) | PORT_PINCFG_PMUXEN(pmuxen)); - port->PORT_PINCFG[bit] = pincfg_val; + uint8_t pincfg_val = + (PORT_PINCFG_DRVSTR(drvstr) | PORT_PINCFG_PULLEN(pullen) | + PORT_PINCFG_INEN(inen) | PORT_PINCFG_PMUXEN(pmuxen)); + port->PORT_PINCFG[bit] = pincfg_val; } mask >>= 1; if (mask == 0) { @@ -190,7 +234,7 @@ void _pal_lld_setgroupmode(ioportid_t port, dir <<= 1; out <<= 1; bit++; - } + } } /** @@ -207,8 +251,8 @@ void _pal_lld_setgroupmode(ioportid_t port, * * @notapi */ -void _pal_lld_writegroup(ioportid_t port, ioportmask_t mask, uint32_t offset, uint32_t bits) -{ +void _pal_lld_writegroup(ioportid_t port, ioportmask_t mask, uint32_t offset, + uint32_t bits) { uint32_t out = ((uint32_t)(bits) & (uint32_t)(mask)) << (offset); (port)->PORT_OUTSET = out; (port)->PORT_OUTCLR = ~out; @@ -225,17 +269,20 @@ void _pal_lld_writegroup(ioportid_t port, ioportmask_t mask, uint32_t offset, ui * * @notapi */ -void _pal_lld_enablepadevent(ioportid_t port, - iopadid_t pad, - ioeventmode_t mode) -{ +void _pal_lld_enablepadevent(ioportid_t port, iopadid_t pad, + ioeventmode_t mode) { + pal_lld_eic_enable_set(FALSE); int8_t extint = _get_extint(port, pad); osalDbgAssert(extint >= 0, "Invalid EIC Pin"); - uint32_t inteset = (1ul << extint); + if (extint < 0) { + return; + } + uint32_t intenset = (1ul << extint); // if interrupt has been set, asserted as we cannot use 2 pins at the same time - osalDbgAssert((EIC_REGS->EIC_INTENSET & inteset) == inteset, "EIC Pin has been used"); + osalDbgAssert((EIC_REGS->EIC_INTENSET & intenset) != intenset, + "EIC Pin has been used"); uint8_t bank = 0; - if(extint > 7) { + if (extint > 7) { bank = 1; } uint32_t oldcfg = EIC_REGS->EIC_CONFIG[bank]; @@ -243,19 +290,25 @@ void _pal_lld_enablepadevent(ioportid_t port, // Enable Filtering by default uint32_t cfg = (1 << extint_filten_pos[cfg_channel]); // Configuring Sense - if((mode & PAL_EVENT_MODE_BOTH_EDGES) == PAL_EVENT_MODE_BOTH_EDGES) { + if ((mode & PAL_EVENT_MODE_BOTH_EDGES) == PAL_EVENT_MODE_BOTH_EDGES) { cfg |= EIC_CONFIG_SENSE_BOTH_Val << extint_sense_pos[cfg_channel]; - } - else if ((mode & PAL_EVENT_MODE_RISING_EDGE) == PAL_EVENT_MODE_RISING_EDGE) { + } else if ((mode & PAL_EVENT_MODE_RISING_EDGE) == + PAL_EVENT_MODE_RISING_EDGE) { cfg |= EIC_CONFIG_SENSE_RISE_Val << extint_sense_pos[cfg_channel]; - } - else if ((mode & PAL_EVENT_MODE_FALLING_EDGE) == PAL_EVENT_MODE_FALLING_EDGE) { + } else if ((mode & PAL_EVENT_MODE_FALLING_EDGE) == + PAL_EVENT_MODE_FALLING_EDGE) { cfg |= EIC_CONFIG_SENSE_FALL_Val << extint_sense_pos[cfg_channel]; } - oldcfg &= ~(extint_sense_msk[cfg_channel] | extint_filten_msk[cfg_channel]); // clear out the bit + oldcfg &= ~(extint_sense_msk[cfg_channel] | + extint_filten_msk[cfg_channel]); // clear out the bit oldcfg |= cfg; +#ifdef SAME54_MCUCONF + nvicEnableVector(EIC_EXTINT_0_IRQn + extint, eic_irq_prio[extint]); +#endif EIC_REGS->EIC_CONFIG[bank] = oldcfg; - EIC_REGS->EIC_INTENSET |= inteset; + EIC_REGS->EIC_INTENSET = intenset; + /* Enable EIC */ + pal_lld_eic_enable_set(TRUE); } /** @@ -267,12 +320,14 @@ void _pal_lld_enablepadevent(ioportid_t port, * * @notapi */ -void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) -{ +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { int8_t extint = _get_extint(port, pad); osalDbgAssert(extint >= 0, "Invalid EIC Pin"); uint32_t intenclr = (1ul << extint); - EIC_REGS->EIC_INTENCLR |= intenclr; + EIC_REGS->EIC_INTENCLR = intenclr; +#ifdef SAME54_MCUCONF + nvicDisableVector(EIC_EXTINT_0_IRQn + extint); +#endif } /** @@ -284,13 +339,10 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) * @notapi */ -palevent_t* _pal_lld_get_pad_event(ioportid_t port, - iopadid_t pad) -{ +palevent_t* _pal_lld_get_pad_event(ioportid_t port, iopadid_t pad) { return &_pal_events[_get_extint(port, pad)]; } - /** * @brief Returns a PAL event structure associated to a line. * @@ -299,35 +351,132 @@ palevent_t* _pal_lld_get_pad_event(ioportid_t port, * @notapi */ -palevent_t* _pal_lld_get_line_event(ioline_t line) -{ +palevent_t* _pal_lld_get_line_event(ioline_t line) { return &_pal_events[_get_extint(PAL_PORT(line), PAL_PAD(line))]; } -bool _pal_lld_ispadeventenabled(ioportid_t port, iopadid_t pad) -{ +bool _pal_lld_ispadeventenabled(ioportid_t port, iopadid_t pad) { int8_t extint = _get_extint(port, pad); uint32_t intenset = 1 << extint; - if((EIC_REGS->EIC_INTENSET & intenset) == intenset) { + if ((EIC_REGS->EIC_INTENSET & intenset) == intenset) { return true; } return false; } - -OSAL_IRQ_HANDLER(EIC_HANDLER) -{ +#ifdef SAMD21_MCUCONF +OSAL_IRQ_HANDLER(EIC_HANDLER) { OSAL_IRQ_PROLOGUE(); unsigned i; - for(i = 0; i < 16; i++) { + for (i = 0; i < 16; i++) { unsigned long intflag = 1UL << i; - if((EIC_REGS->EIC_INTFLAG & intflag) == intflag) { + if ((EIC_REGS->EIC_INTFLAG & intflag) == intflag) { _pal_isr_code(i); - EIC_REGS->EIC_INTFLAG = (1UL << i); // Clear flag + EIC_REGS->EIC_INTFLAG = (1UL << i); // Clear flag } } OSAL_IRQ_EPILOGUE(); } +#elif defined(SAME54_MCUCONF) + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_0_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(0); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_1_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(1); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_2_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(2); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_3_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(3); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_4_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(4); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_5_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(5); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_6_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(6); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_7_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(7); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_8_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(8); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_9_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(9); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_10_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(10); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_11_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(11); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_12_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(12); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_13_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(13); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_14_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(14); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_EIC_EXTINT_15_HANDLER) { + OSAL_IRQ_PROLOGUE(); + pal_lld_serve_interrupt(15); + OSAL_IRQ_EPILOGUE(); +} + +#endif + #endif #endif /* HAL_USE_PAL == TRUE */ diff --git a/os/hal/ports/SAM/LLD/PORTv1/hal_pal_lld.h b/os/hal/ports/SAM/LLD/PORTv1/hal_pal_lld.h index 140023c151..48d0a644ea 100644 --- a/os/hal/ports/SAM/LLD/PORTv1/hal_pal_lld.h +++ b/os/hal/ports/SAM/LLD/PORTv1/hal_pal_lld.h @@ -55,32 +55,32 @@ // #define PAL_SAM_ALTERNATE_MASK (15U << 7U) // #define PAL_SAM_ALTERNATE(n) ((n) << 7U) -#define PAL_SAM_PMUXEN_MASK (1U << 0U) -#define PAL_SAM_PMUXEN_PMUX (1U << 0U) -#define PAL_SAM_PMUXEN_IO (0U << 0U) +#define PAL_SAM_PMUXEN_MASK (1U << 0U) +#define PAL_SAM_PMUXEN_PMUX (1U << 0U) +#define PAL_SAM_PMUXEN_IO (0U << 0U) -#define PAL_SAM_INEN_MASK (1U << 1U) -#define PAL_SAM_INEN_ENABLE (1U << 1U) -#define PAL_SAM_INEN_DISABLE (0U << 1U) +#define PAL_SAM_INEN_MASK (1U << 1U) +#define PAL_SAM_INEN_ENABLE (1U << 1U) +#define PAL_SAM_INEN_DISABLE (0U << 1U) -#define PAL_SAM_PULLEN_MASK (1U << 2U) -#define PAL_SAM_PULLEN_ENABLE (1U << 2U) -#define PAL_SAM_PULLEN_DISABLE (0U << 2U) +#define PAL_SAM_PULLEN_MASK (1U << 2U) +#define PAL_SAM_PULLEN_ENABLE (1U << 2U) +#define PAL_SAM_PULLEN_DISABLE (0U << 2U) -#define PAL_SAM_DRVSTR_MASK (1U << 3U) -#define PAL_SAM_DRVSTR_NORMAL (0U << 3U) -#define PAL_SAM_DRVSTR_STRONGER (1U << 3U) +#define PAL_SAM_DRVSTR_MASK (1U << 3U) +#define PAL_SAM_DRVSTR_NORMAL (0U << 3U) +#define PAL_SAM_DRVSTR_STRONGER (1U << 3U) -#define PAL_SAM_DIR_MASK (1U << 4U) -#define PAL_SAM_DIR_OUT (1U << 4U) -#define PAL_SAM_DIR_IN (0U << 4U) +#define PAL_SAM_DIR_MASK (1U << 4U) +#define PAL_SAM_DIR_OUT (1U << 4U) +#define PAL_SAM_DIR_IN (0U << 4U) -#define PAL_SAM_OUT_MASK (1U << 5U) -#define PAL_SAM_OUT_ENABLE (1U << 5U) -#define PAL_SAM_OUT_DISABLE (0U << 5U) +#define PAL_SAM_OUT_MASK (1U << 5U) +#define PAL_SAM_OUT_ENABLE (1U << 5U) +#define PAL_SAM_OUT_DISABLE (0U << 5U) -#define PAL_SAM_ALTERNATE_MASK (7U << 6U) -#define PAL_SAM_ALTERNATE(n) ((n) << 6U) +#define PAL_SAM_ALTERNATE_MASK (7U << 6U) +#define PAL_SAM_ALTERNATE(n) ((n) << 6U) #define PAL_NEW_INIT #undef PAL_MODE_RESET @@ -93,52 +93,68 @@ #undef PAL_MODE_OUTPUT_OPENDRAIN // PORT RESET MODE -#define PAL_SAM_RESET (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_DISABLE | \ - PAL_SAM_PULLEN_DISABLE | PAL_SAM_DIR_IN) - +#define PAL_SAM_RESET \ + (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_DISABLE | PAL_SAM_PULLEN_DISABLE | \ + PAL_SAM_DIR_IN) /* PORT INPUT MODE: FLOAT, PULLUP, PULLDOWN pg 368 */ -#define PAL_MODE_INPUT (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_ENABLE | \ - PAL_SAM_PULLEN_DISABLE | PAL_SAM_DIR_IN) - -#define PAL_MODE_INPUT_PULLUP (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_ENABLE | \ - PAL_SAM_PULLEN_ENABLE | PAL_SAM_DIR_IN | \ - PAL_SAM_OUT_ENABLE) +#define PAL_MODE_INPUT \ + (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_ENABLE | PAL_SAM_PULLEN_DISABLE | \ + PAL_SAM_DIR_IN) -#define PAL_MODE_INPUT_PULLDOWN (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_ENABLE | \ - PAL_SAM_PULLEN_ENABLE | PAL_SAM_DIR_IN | \ - PAL_SAM_OUT_DISABLE) +#define PAL_MODE_INPUT_PULLUP \ + (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_ENABLE | PAL_SAM_PULLEN_ENABLE | \ + PAL_SAM_DIR_IN | PAL_SAM_OUT_ENABLE) +#define PAL_MODE_INPUT_PULLDOWN \ + (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_ENABLE | PAL_SAM_PULLEN_ENABLE | \ + PAL_SAM_DIR_IN | PAL_SAM_OUT_DISABLE) /* PORT OUTPUT MODE pg 369 */ -#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_DISABLE | \ - PAL_SAM_PULLEN_ENABLE | PAL_SAM_DIR_OUT) +#define PAL_MODE_OUTPUT_OPENDRAIN \ + (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_DISABLE | PAL_SAM_PULLEN_ENABLE | \ + PAL_SAM_DIR_OUT) -#define PAL_MODE_OUTPUT_INBUFF (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_ENABLE | \ - PAL_SAM_PULLEN_DISABLE | PAL_SAM_DIR_OUT | \ - PAL_SAM_OUT_ENABLE) +#define PAL_MODE_OUTPUT_INBUFF \ + (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_ENABLE | PAL_SAM_PULLEN_DISABLE | \ + PAL_SAM_DIR_OUT | PAL_SAM_OUT_ENABLE) -#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_DISABLE | \ - PAL_SAM_PULLEN_DISABLE | PAL_SAM_DIR_OUT) +#define PAL_MODE_OUTPUT_PUSHPULL \ + (PAL_SAM_PMUXEN_IO | PAL_SAM_INEN_DISABLE | PAL_SAM_PULLEN_DISABLE | \ + PAL_SAM_DIR_OUT) + +/* +* Refer to SAM Datasheet under I/O Multiplexing and Considerations to determine what mode to put your GPIO in. +*/ +#define PAL_SAM_FUNC_A 0 +#define PAL_SAM_FUNC_B 1 +#define PAL_SAM_FUNC_C 2 +#define PAL_SAM_FUNC_D 3 +#define PAL_SAM_FUNC_E 4 +#define PAL_SAM_FUNC_F 5 +#define PAL_SAM_FUNC_G 6 +#define PAL_SAM_FUNC_H 7 + +#ifdef SAME54_MCUCONF +#define PAL_SAM_FUNC_I 8 +#define PAL_SAM_FUNC_J 9 +#define PAL_SAM_FUNC_K 10 +#define PAL_SAM_FUNC_L 11 +#define PAL_SAM_FUNC_M 12 +#define PAL_SAM_FUNC_N 13 +#endif // PORT ALTERNATE MODE +#define PAL_MODE_ALTERNATE(n) (PAL_SAM_PMUXEN_PMUX | PAL_SAM_ALTERNATE(n)) + +// PORT ANALOG MODE -#define PAL_MODE_ALTERNATE(n) (PAL_SAM_PMUXEN_PMUX | PAL_SAM_ALTERNATE(n)) +#define PAL_MODE_ANALOG (PAL_SAM_RESET | PAL_MODE_ALTERNATE(1)) -// PORT ANALOG MODE -#define PAL_MODE_ANALOG (PAL_SAM_RESET | PAL_MODE_ALTERNATE(1)) -#define PAL_SAM_FUNC_A 0 -#define PAL_SAM_FUNC_B 1 -#define PAL_SAM_FUNC_C 2 -#define PAL_SAM_FUNC_D 3 -#define PAL_SAM_FUNC_E 4 -#define PAL_SAM_FUNC_F 5 -#define PAL_SAM_FUNC_G 6 -#define PAL_SAM_FUNC_H 7 /*===========================================================================*/ /* I/O Ports Types and constants. */ /*===========================================================================*/ @@ -150,13 +166,13 @@ /** * @brief Width, in bits, of an I/O port. */ -#define PAL_IOPORTS_WIDTH 32U +#define PAL_IOPORTS_WIDTH 32U /** * @brief Whole port mask. * @details This macro specifies all the valid bits into a port. */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFU) +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFU) /** @} */ /** @@ -168,25 +184,23 @@ * @details A port/pad pair are encoded into an @p ioline_t type. The encoding * of this type is platform-dependent. */ -#define PAL_LINE(port, pad) \ - ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) +#define PAL_LINE(port, pad) ((ioline_t)((uintptr_t)(port)) | ((uint32_t)(pad))) /** * @brief Decodes a port identifier from a line identifier. */ -#define PAL_PORT(line) \ - ((ioportid_t)(((uint32_t)(line)) & 0xFFFFFF80U)) +#define PAL_PORT(line) ((ioportid_t)(((uint32_t)(line)) & 0xFFFFFF80U)) /** * @brief Decodes a pad identifier from a line identifier. */ -#define PAL_PAD(line) \ - ((uint32_t)((uint32_t)(line) & 0x0000001FU)) +#define PAL_PAD(line) ((uint32_t)((uint32_t)(line)&0x0000001FU)) /** * @brief Value identifying an invalid line. */ -#define PAL_NOLINE 0U +#define PAL_NOLINE 0U + /** @} */ /** @@ -244,18 +258,34 @@ typedef uint8_t iopadid_t; * @details Low level drivers can define multiple ports, it is suggested to * use this naming convention. */ - + #if defined(SAM_HAS_GPIOA) || defined(__DOXYGEN__) -#define GPIOA &PORT_REGS->GROUP[0] -#define IOPORT1 &PORT_REGS->GROUP[0] +#define GPIOA &PORT_REGS->GROUP[0] +#define IOPORT1 &PORT_REGS->GROUP[0] #endif /** * @brief GPIO port B identifier. */ -#if defined(SAM_HAS_GPIOA) || defined(__DOXYGEN__) -#define GPIOB &PORT_REGS->GROUP[1] -#define IOPORT2 &PORT_REGS->GROUP[1] +#if defined(SAM_HAS_GPIOB) || defined(__DOXYGEN__) +#define GPIOB &PORT_REGS->GROUP[1] +#define IOPORT2 &PORT_REGS->GROUP[1] +#endif + +/** + * @brief GPIO port B identifier. + */ +#if defined(SAM_HAS_GPIOC) || defined(__DOXYGEN__) +#define GPIOC &PORT_REGS->GROUP[2] +#define IOPORT3 &PORT_REGS->GROUP[2] +#endif + +/** + * @brief GPIO port D identifier. + */ +#if defined(SAM_HAS_GPIOD) || defined(__DOXYGEN__) +#define GPIOD &PORT_REGS->GROUP[3] +#define IOPORT4 &PORT_REGS->GROUP[3] #endif /*===========================================================================*/ @@ -340,23 +370,9 @@ typedef uint8_t iopadid_t; * @notapi */ #define pal_lld_toggleport(port, bits) ((port)->PORT_OUTTGL = bits) -/** - * @brief Reads a group of bits. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @return The group logical states. - * - * @notapi - */ -#define pal_lld_readgroup(port, mask, offset) ((port)->PORT_IN >> offset) #define pal_lld_writegroup(port, mask, offset, bits) \ - _pal_lld_writegroup(port, mask, offset, bits) + _pal_lld_writegroup(port, mask, offset, bits) /** * @brief Pads group mode setup. @@ -371,7 +387,7 @@ typedef uint8_t iopadid_t; * * @notapi */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ _pal_lld_setgroupmode(port, mask << offset, mode) /** * @brief Sets a pad logical state to @p PAL_HIGH. @@ -397,7 +413,7 @@ typedef uint8_t iopadid_t; * * @notapi */ -#define pal_lld_clearpad(port, pad) ((port)->PORT_OUTCLR = (1 << pad)) +#define pal_lld_clearpad(port, pad) ((port)->PORT_OUTCLR = (1 << pad)) /** * @brief Toggles a pad logical state. @@ -410,7 +426,7 @@ typedef uint8_t iopadid_t; * * @notapi */ -#define pal_lld_togglepad(port, pad) ((port)->PORT_OUTTGL = (1 << pad)) +#define pal_lld_togglepad(port, pad) ((port)->PORT_OUTTGL = (1 << pad)) /** * @brief Pad event enable. @@ -422,7 +438,7 @@ typedef uint8_t iopadid_t; * * @notapi */ -#define pal_lld_enablepadevent(port, pad, mode) \ +#define pal_lld_enablepadevent(port, pad, mode) \ _pal_lld_enablepadevent(port, pad, mode) /** @@ -434,9 +450,7 @@ typedef uint8_t iopadid_t; * * @notapi */ -#define pal_lld_disablepadevent(port, pad) \ - _pal_lld_disablepadevent(port, pad) - +#define pal_lld_disablepadevent(port, pad) _pal_lld_disablepadevent(port, pad) /** * @brief Returns a PAL event structure associated to a pad. @@ -446,8 +460,7 @@ typedef uint8_t iopadid_t; * * @notapi */ -#define pal_lld_get_pad_event(port, pad) \ - _pal_lld_get_pad_event(port, pad) +#define pal_lld_get_pad_event(port, pad) _pal_lld_get_pad_event(port, pad) /** * @brief Returns a PAL event structure associated to a line. @@ -456,8 +469,7 @@ typedef uint8_t iopadid_t; * * @notapi */ -#define pal_lld_get_line_event(line) \ - _pal_lld_get_line_event(line) +#define pal_lld_get_line_event(line) _pal_lld_get_line_event(line) /** * @brief Pad event enable check. @@ -470,7 +482,7 @@ typedef uint8_t iopadid_t; * * @notapi */ -#define pal_lld_ispadeventenabled(port, pad) \ +#define pal_lld_ispadeventenabled(port, pad) \ _pal_lld_ispadeventenabled(port, pad) #if !defined(__DOXYGEN__) @@ -482,23 +494,18 @@ extern palevent_t _pal_events[16]; #ifdef __cplusplus extern "C" { #endif - void _pal_lld_init(void); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); - void _pal_lld_writegroup(ioportid_t port, - ioportmask_t mask, - uint32_t offset, - uint32_t bits); - void _pal_lld_enablepadevent(ioportid_t port, - iopadid_t pad, - ioeventmode_t mode); - void _pal_lld_disablepadevent(ioportid_t port, - iopadid_t pad); - bool _pal_lld_ispadeventenabled(ioportid_t port, iopadid_t pad); - palevent_t* _pal_lld_get_line_event(ioline_t line); - palevent_t* _pal_lld_get_pad_event(ioportid_t port, - iopadid_t pad); +void _pal_lld_init(void); +void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode); +void _pal_lld_writegroup(ioportid_t port, ioportmask_t mask, uint32_t offset, + uint32_t bits); +#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) +void _pal_lld_enablepadevent(ioportid_t port, iopadid_t pad, + ioeventmode_t mode); +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad); +bool _pal_lld_ispadeventenabled(ioportid_t port, iopadid_t pad); +palevent_t* _pal_lld_get_line_event(ioline_t line); +palevent_t* _pal_lld_get_pad_event(ioportid_t port, iopadid_t pad); +#endif #ifdef __cplusplus } #endif diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/driver.mk b/os/hal/ports/SAM/LLD/SERCOMv1/driver.mk index e7f55357b3..c4449f6803 100644 --- a/os/hal/ports/SAM/LLD/SERCOMv1/driver.mk +++ b/os/hal/ports/SAM/LLD/SERCOMv1/driver.mk @@ -3,7 +3,7 @@ ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld.c endif ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld.c +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom.c endif ifneq ($(findstring HAL_USE_SIO TRUE,$(HALCONF)),) PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld.c diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld.c b/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld.c index d7a31638f4..8ac5410d0e 100644 --- a/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld.c +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld.c @@ -32,126 +32,64 @@ #define i2c_lld_get_rxbytes(i2cp) (i2cp)->rxbytes #define i2c_lld_get_txbytes(i2cp) (i2cp)->txbytes -#define SERCOM_I2C_CTRLA_FORBIDDEN (SERCOM_I2CM_CTRLA_MODE_Msk | \ - SERCOM_I2CM_CTRLA_ENABLE_Msk | \ - SERCOM_I2CM_CTRLA_SWRST_Msk | \ - SERCOM_I2CM_CTRLA_SPEED_Msk) -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief I2C1 driver identifier. - */ -#if (SAM_I2C_USE_SERCOM0 == TRUE) || defined(__DOXYGEN__) -I2CDriver I2CD1; -#endif - -/** - * @brief I2C2 driver identifier. - */ -#if (SAM_I2C_USE_SERCOM1 == TRUE) || defined(__DOXYGEN__) -I2CDriver I2CD2; -#endif - -/** - * @brief I2C3 driver identifier. - */ -#if (SAM_I2C_USE_SERCOM2 == TRUE) || defined(__DOXYGEN__) -I2CDriver I2CD3; -#endif - -/** - * @brief I2C4 driver identifier. - */ -#if (SAM_I2C_USE_SERCOM3 == TRUE) || defined(__DOXYGEN__) -I2CDriver I2CD4; -#endif - -/** - * @brief I2C5 driver identifier. - */ -#if (SAM_I2C_USE_SERCOM4 == TRUE) || defined(__DOXYGEN__) -I2CDriver I2CD5; -#endif - -/** - * @brief I2C6 driver identifier. - */ -#if (SAM_I2C_USE_SERCOM5 == TRUE) || defined(__DOXYGEN__) -I2CDriver I2CD6; -#endif +#define SERCOM_I2C_CTRLA_FORBIDDEN \ + (SERCOM_I2CM_CTRLA_MODE_Msk | SERCOM_I2CM_CTRLA_ENABLE_Msk | \ + SERCOM_I2CM_CTRLA_SWRST_Msk | SERCOM_I2CM_CTRLA_SPEED_Msk) /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ + /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ -static inline void sam_i2c_busy_wait(I2CDriver *i2cp) -{ +static inline void sam_i2c_busy_wait(I2CDriver* i2cp) { while ((i2cp->i2c->SERCOM_SYNCBUSY) != 0U) ; } -static bool sam_i2c_cal_baud(uint32_t srcClkFreq, uint32_t i2cClkSpeed, uint32_t *baudVal) -{ - osalDbgAssert(i2cClkSpeed <= 400000, "This Clock is currently not supported"); +static bool sam_i2c_cal_baud(uint32_t srcClkFreq, uint32_t i2cClkSpeed, + uint32_t* baudVal) { + // osalDbgAssert(i2cClkSpeed <= 400000, "This Clock is currently not supported"); uint32_t baudValue = 0U; float fSrcClkFreq = (float)srcClkFreq; float fI2cClkSpeed = (float)i2cClkSpeed; float fBaudValue = 0.0f; /* Reference clock frequency must be atleast two times the baud rate */ - if (srcClkFreq < (2U * i2cClkSpeed)) - { + if (srcClkFreq < (2U * i2cClkSpeed)) { return false; } - if (i2cClkSpeed <= 1000000U) - { + if (i2cClkSpeed <= 1000000U) { /* Standard, FM and FM+ baud calculation */ - fBaudValue = (fSrcClkFreq / fI2cClkSpeed) - ((fSrcClkFreq * (100.0f / 1000000000.0f)) + 10.0f); + fBaudValue = (fSrcClkFreq / fI2cClkSpeed) - + ((fSrcClkFreq * (100.0f / 1000000000.0f)) + 10.0f); baudValue = (uint32_t)fBaudValue; - } - else - { + } else { return false; } - if (i2cClkSpeed <= 400000U) - { + if (i2cClkSpeed <= 400000U) { /* For I2C clock speed upto 400 kHz, the value of BAUD<7:0> determines both SCL_L and SCL_H with SCL_L = SCL_H */ - if (baudValue > (0xFFU * 2U)) - { + if (baudValue > (0xFFU * 2U)) { /* Set baud rate to the minimum possible value */ baudValue = 0xFFU; - } - else if (baudValue <= 1U) - { + } else if (baudValue <= 1U) { /* Baud value cannot be 0. Set baud rate to maximum possible value */ baudValue = 1U; - } - else - { + } else { baudValue /= 2U; } - } - else - { + } else { /* To maintain the ratio of SCL_L:SCL_H to 2:1, the max value of BAUD_LOW<15:8>:BAUD<7:0> can be 0xFF:0x7F. Hence BAUD_LOW + BAUD can not exceed 255+127 = 382 */ - if (baudValue >= 382U) - { + if (baudValue >= 382U) { /* Set baud rate to the minimum possible value while maintaining SCL_L:SCL_H to 2:1 */ baudValue = (0xFFUL << 8U) | (0x7FU); - } - else if (baudValue <= 3U) - { + } else if (baudValue <= 3U) { /* Baud value cannot be 0. Set baud rate to maximum possible value while maintaining SCL_L:SCL_H to 2:1 */ baudValue = (2UL << 8U) | 1U; - } - else - { + } else { /* For Fm+ mode, I2C SCL_L:SCL_H to 2:1 */ baudValue = ((((baudValue * 2U) / 3U) << 8U) | (baudValue / 3U)); } @@ -160,8 +98,7 @@ static bool sam_i2c_cal_baud(uint32_t srcClkFreq, uint32_t i2cClkSpeed, uint32_t return true; } -static void i2c_lld_abort_operation(I2CDriver *i2cp) -{ +static void i2c_lld_abort_operation(I2CDriver* i2cp) { /* Disable the I2C module */ i2cp->i2c->SERCOM_CTRLA &= ~SERCOM_I2CM_CTRLA_ENABLE_Msk; sam_i2c_busy_wait(i2cp); @@ -173,65 +110,56 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) sam_i2c_busy_wait(i2cp); } -static void i2c_lld_set_address(I2CDriver *i2cp, i2caddr_t addr, bool dir) -{ +static void i2c_lld_set_address(I2CDriver* i2cp, i2caddr_t addr, bool dir) { i2cp->addr = addr; uint32_t temp = ((uint32_t)(i2cp->addr << 1U) | (dir ? 1U : 0U)); i2cp->i2c->SERCOM_ADDR = temp; /* Wait for synchronization */ sam_i2c_busy_wait(i2cp); } + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ -static void i2c_lld_serve_interrupt(I2CDriver *i2cp) -{ - sercom_i2cm_registers_t *dp = i2cp->i2c; +static void i2c_lld_serve_interrupt(I2CDriver* i2cp) { + sercom_i2cm_registers_t* dp = i2cp->i2c; uint8_t isr = dp->SERCOM_STATUS; bool isFinished = false; - if (i2cp->i2c->SERCOM_INTENSET != 0U) - { + if (i2cp->i2c->SERCOM_INTENSET != 0U) { /* Checks if the arbitration lost in multi-master scenario */ - if ((isr & SERCOM_I2CM_STATUS_ARBLOST_Msk) == SERCOM_I2CM_STATUS_ARBLOST_Msk) - { + if ((isr & SERCOM_I2CM_STATUS_ARBLOST_Msk) == + SERCOM_I2CM_STATUS_ARBLOST_Msk) { /* Set Error status */ i2cp->errors |= I2C_ARBITRATION_LOST; } /* Check for Bus Error during transmission */ - else if ((isr & SERCOM_I2CM_STATUS_BUSERR_Msk) == SERCOM_I2CM_STATUS_BUSERR_Msk) - { + else if ((isr & SERCOM_I2CM_STATUS_BUSERR_Msk) == + SERCOM_I2CM_STATUS_BUSERR_Msk) { /* Set Error status */ i2cp->errors |= I2C_BUS_ERROR; } /* Checks slave acknowledge for address or data */ - else if ((isr & SERCOM_I2CM_STATUS_RXNACK_Msk) == SERCOM_I2CM_STATUS_RXNACK_Msk) - { + else if ((isr & SERCOM_I2CM_STATUS_RXNACK_Msk) == + SERCOM_I2CM_STATUS_RXNACK_Msk) { i2cp->errors |= I2C_ACK_FAILURE; } - if (i2cp->errors) - { + if (i2cp->errors) { dp->SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); sam_i2c_busy_wait(i2cp); dp->SERCOM_INTENCLR = SERCOM_I2CM_INTENCLR_Msk; _i2c_wakeup_error_isr(i2cp); - } - else - { - if (i2cp->state == I2C_ACTIVE_TX && (dp->SERCOM_INTFLAG & SERCOM_I2CM_INTFLAG_MB_Msk)) - { - if (i2cp->txbytes == 0 && i2cp->rxbytes != 0) - { + } else { + if (i2cp->state == I2C_ACTIVE_TX && + (dp->SERCOM_INTFLAG & SERCOM_I2CM_INTFLAG_MB_Msk)) { + if (i2cp->txbytes == 0 && i2cp->rxbytes != 0) { i2c_lld_set_address(i2cp, i2cp->addr, true); i2cp->state = I2C_ACTIVE_RX; - } - else if (i2cp->txbytes == 0) - { + } else if (i2cp->txbytes == 0) { dp->SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); sam_i2c_busy_wait(i2cp); isFinished = true; - } - else { + } else { dp->SERCOM_INTFLAG |= SERCOM_I2CM_INTFLAG_MB_Msk; uint8_t data = (uint8_t)*i2cp->txptr; i2cp->txptr++; @@ -240,12 +168,11 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) sam_i2c_busy_wait(i2cp); } - } - else if (i2cp->state == I2C_ACTIVE_RX && (dp->SERCOM_INTFLAG & SERCOM_I2CM_INTFLAG_SB_Msk)) - { - if (i2cp->rxbytes == 1) - { - dp->SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_ACKACT_Msk | SERCOM_I2CM_CTRLB_CMD(3UL); + } else if (i2cp->state == I2C_ACTIVE_RX && + (dp->SERCOM_INTFLAG & SERCOM_I2CM_INTFLAG_SB_Msk)) { + if (i2cp->rxbytes == 1) { + dp->SERCOM_CTRLB |= + SERCOM_I2CM_CTRLB_ACKACT_Msk | SERCOM_I2CM_CTRLB_CMD(3UL); sam_i2c_busy_wait(i2cp); isFinished = true; } @@ -255,11 +182,11 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) dp->SERCOM_INTFLAG |= SERCOM_I2CM_INTFLAG_SB_Msk; sam_i2c_busy_wait(i2cp); } - if (isFinished) - { + if (isFinished) { dp->SERCOM_INTFLAG = (uint8_t)SERCOM_I2CM_INTFLAG_Msk; dp->SERCOM_INTENCLR = SERCOM_I2CM_INTENCLR_Msk; - while ((dp->SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) != SERCOM_I2CM_STATUS_BUSSTATE(0x01U)) + while ((dp->SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) != + SERCOM_I2CM_STATUS_BUSSTATE(0x01U)) ; _i2c_wakeup_isr(i2cp); } @@ -267,217 +194,12 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) } } -#if SAM_I2C_USE_SERCOM0 == TRUE -OSAL_IRQ_HANDLER(SERCOM0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - i2c_lld_serve_interrupt(&I2CD1); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if SAM_I2C_USE_SERCOM1 == TRUE -OSAL_IRQ_HANDLER(SERCOM1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - i2c_lld_serve_interrupt(&I2CD2); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if SAM_I2C_USE_SERCOM2 == TRUE -OSAL_IRQ_HANDLER(SERCOM2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - i2c_lld_serve_interrupt(&I2CD3); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if SAM_I2C_USE_SERCOM3 == TRUE -OSAL_IRQ_HANDLER(SERCOM3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - i2c_lld_serve_interrupt(&I2CD4); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if SAM_I2C_USE_SERCOM4 == TRUE -OSAL_IRQ_HANDLER(SERCOM4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - i2c_lld_serve_interrupt(&I2CD5); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if SAM_I2C_USE_SERCOM5 == TRUE -OSAL_IRQ_HANDLER(SERCOM5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - i2c_lld_serve_interrupt(&I2CD6); - OSAL_IRQ_EPILOGUE(); -} +#if defined(SAMD21_MCUCONF) +#include "hal_i2c_lld_samd2x.inc" +#elif defined(SAME54_MCUCONF) +#include "hal_i2c_lld_same5x.inc" #endif -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2C driver initialization. - * - * @notapi - */ -void i2c_lld_init(void) -{ - -#if SAM_I2C_USE_SERCOM0 == TRUE - i2cObjectInit(&I2CD1); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM0_Msk; - I2CD1.i2c = &SERCOM0_REGS->I2CM; - I2CD1.clock = SAM_SERCOM0_GCLK_SRC_FREQ; -#endif -#if SAM_I2C_USE_SERCOM1 == TRUE - i2cObjectInit(&I2CD2); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM1_Msk; - I2CD2.i2c = &SERCOM1_REGS->I2CM; - I2CD2.clock = SAM_SERCOM1_GCLK_SRC_FREQ; -#endif -#if SAM_I2C_USE_SERCOM2 == TRUE - i2cObjectInit(&I2CD3); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM2_Msk; - I2CD3.i2c = &SERCOM2_REGS->I2CM; - I2CD3.clock = SAM_SERCOM2_GCLK_SRC_FREQ; -#endif -#if SAM_I2C_USE_SERCOM3 == TRUE - i2cObjectInit(&I2CD4); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM3_Msk; - I2CD4.i2c = &SERCOM3_REGS->I2CM; - I2CD4.clock = SAM_SERCOM3_GCLK_SRC_FREQ; -#endif -#if SAM_I2C_USE_SERCOM4 == TRUE - i2cObjectInit(&I2CD5); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM4_Msk; - I2CD5.i2c = &SERCOM4_REGS->I2CM; - I2CD5.clock = SAM_SERCOM4_GCLK_SRC_FREQ; -#endif -#if SAM_I2C_USE_SERCOM5 == TRUE - i2cObjectInit(&I2CD6); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM5_Msk; - I2CD6.i2c = &SERCOM5_REGS->I2CM; - I2CD6.clock = SAM_SERCOM5_GCLK_SRC_FREQ; -#endif -} - -/** - * @brief Configures and activates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_start(I2CDriver *i2cp) -{ - - if (i2cp->state == I2C_STOP) - { - sercom_i2cm_registers_t *dp = i2cp->i2c; - /* Enables the peripheral.*/ -#if SAM_I2C_USE_SERCOM0 == TRUE - if (&I2CD1 == i2cp) - { - sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, 1); - nvicEnableVector(SERCOM0_IRQn, SAM_SERCOM0_IRQ_PRIORITY); - } -#endif - -#if SAM_I2C_USE_SERCOM1 == TRUE - if (&I2CD2 == i2cp) - { - sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, 1); - nvicEnableVector(SERCOM1_IRQn, SAM_SERCOM1_IRQ_PRIORITY); - } -#endif - -#if SAM_I2C_USE_SERCOM2 == TRUE - if (&I2CD3 == i2cp) - { - sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, 1); - nvicEnableVector(SERCOM2_IRQn, SAM_SERCOM1_IRQ_PRIORITY); - } -#endif - -#if SAM_I2C_USE_SERCOM3 == TRUE - if (&I2CD4 == i2cp) - { - sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, 1); - nvicEnableVector(SERCOM3_IRQn, SAM_SERCOM3_IRQ_PRIORITY); - } -#endif - -#if SAM_I2C_USE_SERCOM4 == TRUE - if (&I2CD5 == i2cp) - { - sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, 1); - nvicEnableVector(SERCOM4_IRQn, SAM_SERCOM4_IRQ_PRIORITY); - } -#endif - -#if SAM_I2C_USE_SERCOM5 == TRUE - if (&I2CD6 == i2cp) - { - sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, 1); - nvicEnableVector(SERCOM5_IRQn, SAM_SERCOM5_IRQ_PRIORITY); - } -#endif - // Resetting sercom module - i2cp->i2c->SERCOM_CTRLA = SERCOM_I2CM_CTRLA_SWRST_Msk; - - /* Wait for synchronization */ - sam_i2c_busy_wait(i2cp); - - /* Enable smart mode */ - dp->SERCOM_CTRLB = SERCOM_I2CM_CTRLB_SMEN_Msk; - uint32_t baud_val = 0; - osalDbgAssert(sam_i2c_cal_baud(i2cp->clock, i2cp->config->i2cSpeed, &baud_val), "unable to calculate baud"); - dp->SERCOM_BAUD = baud_val; - dp->SERCOM_CTRLA = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER | (i2cp->config->ctrla & ~SERCOM_I2C_CTRLA_FORBIDDEN) | SERCOM_I2CM_CTRLA_ENABLE_Msk; - sam_i2c_busy_wait(i2cp); - i2cp->i2c->SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); - sam_i2c_busy_wait(i2cp); - } -} - -/** - * @brief Deactivates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_stop(I2CDriver *i2cp) -{ - if (i2cp->state != I2C_STOP) - { - i2c_lld_abort_operation(i2cp); - /* Disables the peripheral.*/ -#if SAM_I2C_USE_SERCOM1 == TRUE - if (&I2CD2 == i2cp) - { - nvicDisableVector(SERCOM1_IRQn); - } -#endif - } -} - /** * @brief Receives data via the I2C bus as master. * @@ -499,12 +221,11 @@ void i2c_lld_stop(I2CDriver *i2cp) * * @notapi */ -msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - sysinterval_t timeout) -{ +msg_t i2c_lld_master_receive_timeout(I2CDriver* i2cp, i2caddr_t addr, + uint8_t* rxbuf, size_t rxbytes, + sysinterval_t timeout) { msg_t msg; - sercom_i2cm_registers_t *dp = i2cp->i2c; + sercom_i2cm_registers_t* dp = i2cp->i2c; systime_t start, end; osalSysUnlock(); i2cp->rxptr = rxbuf; @@ -513,19 +234,18 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, end = osalTimeAddX(start, OSAL_MS2I(SAM_I2C_BUSY_TIMEOUT)); /* Waits until BUSY flag is reset or, alternatively, for a timeout condition.*/ - while (true) - { + while (true) { osalSysLock(); /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if (((dp->SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) == SERCOM_I2CM_STATUS_BUSSTATE(0x01U))) + if (((dp->SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) == + SERCOM_I2CM_STATUS_BUSSTATE(0x01U))) break; /* If the system time went outside the allowed window then a timeout condition is returned.*/ - if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) - { + if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) { return MSG_TIMEOUT; } osalSysUnlock(); @@ -536,8 +256,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, sam_i2c_busy_wait(i2cp); i2c_lld_set_address(i2cp, addr, true); msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); - if (msg == MSG_TIMEOUT) - { + if (msg == MSG_TIMEOUT) { dp->SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); sam_i2c_busy_wait(i2cp); } @@ -567,13 +286,12 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, * * @notapi */ -msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - sysinterval_t timeout) -{ +msg_t i2c_lld_master_transmit_timeout(I2CDriver* i2cp, i2caddr_t addr, + const uint8_t* txbuf, size_t txbytes, + uint8_t* rxbuf, size_t rxbytes, + sysinterval_t timeout) { msg_t msg; - sercom_i2cm_registers_t *dp = i2cp->i2c; + sercom_i2cm_registers_t* dp = i2cp->i2c; systime_t start, end; osalSysUnlock(); i2cp->txbytes = txbytes; @@ -584,19 +302,18 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, end = osalTimeAddX(start, OSAL_MS2I(SAM_I2C_BUSY_TIMEOUT)); /* Waits until BUSY flag is reset or, alternatively, for a timeout condition.*/ - while (true) - { + while (true) { osalSysLock(); /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if (((dp->SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) == SERCOM_I2CM_STATUS_BUSSTATE(0x01U))) + if (((dp->SERCOM_STATUS & SERCOM_I2CM_STATUS_BUSSTATE_Msk) == + SERCOM_I2CM_STATUS_BUSSTATE(0x01U))) break; /* If the system time went outside the allowed window then a timeout condition is returned.*/ - if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) - { + if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) { return MSG_TIMEOUT; } osalSysUnlock(); @@ -607,8 +324,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, sam_i2c_busy_wait(i2cp); i2c_lld_set_address(i2cp, addr, false); msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); - if (msg == MSG_TIMEOUT) - { + if (msg == MSG_TIMEOUT) { dp->SERCOM_CTRLB |= SERCOM_I2CM_CTRLB_CMD(3UL); sam_i2c_busy_wait(i2cp); } diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld.h b/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld.h index 78b8879bc7..ab8a79c6f2 100644 --- a/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld.h +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld.h @@ -142,10 +142,28 @@ #endif #endif +#if SAM_I2C_USE_SERCOM6 == TRUE +#if SAM_SIO_USE_SERCOM6 == TRUE || SAM_SPI_USE_SERCOM6 == TRUE +#error "SERCOM6: Can only configured as one function only" +#endif +#endif + +#if SAM_I2C_USE_SERCOM7 == TRUE +#if SAM_SIO_USE_SERCOM7 == TRUE || SAM_SPI_USE_SERCOM7 == TRUE +#error "SERCOM7: Can only configured as one function only" +#endif +#endif /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ +#define SERCOM_I2C_CTRLA_DEFAULT \ + (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER | SERCOM_I2CM_CTRLA_SDAHOLD_75NS | \ + SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE | \ + SERCOM_I2CM_CTRLA_SCLSM(0UL) | SERCOM_I2CM_CTRLA_ENABLE_Msk) + +#define SERCOM_I2C_CTRLB_DEFAULT \ + (SERCOM_I2CM_CTRLB_CMD(3UL)) /** * @brief Type representing an I2C address. */ @@ -161,8 +179,7 @@ typedef uint32_t i2cflags_t; * @note Implementations may extend this structure to contain more, * architecture dependent, fields. */ -struct hal_i2c_config -{ +struct hal_i2c_config { /* End of the mandatory fields.*/ uint32_t i2cSpeed; uint32_t ctrla; @@ -181,8 +198,7 @@ typedef struct hal_i2c_driver I2CDriver; /** * @brief Structure representing an I2C driver. */ -struct hal_i2c_driver -{ +struct hal_i2c_driver { /** * @brief Driver state. */ @@ -190,7 +206,7 @@ struct hal_i2c_driver /** * @brief Current configuration data. */ - const I2CConfig *config; + const I2CConfig* config; /** * @brief Error flags. */ @@ -210,7 +226,7 @@ struct hal_i2c_driver /** * @brief Pointer to the next TX buffer location. */ - const uint8_t *txptr; + const uint8_t* txptr; /** * @brief Number of bytes in TX phase. */ @@ -218,12 +234,12 @@ struct hal_i2c_driver /** * @brief Pointer to the next RX buffer location. */ - uint8_t *rxptr; + uint8_t* rxptr; /** * @brief Number of bytes in RX phase. */ size_t rxbytes; - sercom_i2cm_registers_t *i2c; + sercom_i2cm_registers_t* i2c; i2caddr_t addr; /* End of the mandatory fields.*/ }; @@ -269,20 +285,32 @@ extern I2CDriver I2CD5; extern I2CDriver I2CD6; #endif +#ifdef SAME54_MCUCONF + +#if (SAM_I2C_USE_SERCOM6 == TRUE) && !defined(__DOXYGEN__) +extern I2CDriver I2CD7; +#endif + +#if (SAM_I2C_USE_SERCOM7 == TRUE) && !defined(__DOXYGEN__) +extern I2CDriver I2CD8; +#endif + +#endif + + #ifdef __cplusplus -extern "C" -{ -#endif - void i2c_lld_init(void); - void i2c_lld_start(I2CDriver *i2cp); - void i2c_lld_stop(I2CDriver *i2cp); - msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - sysinterval_t timeout); - msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - sysinterval_t timeout); +extern "C" { +#endif +void i2c_lld_init(void); +void i2c_lld_start(I2CDriver* i2cp); +void i2c_lld_stop(I2CDriver* i2cp); +msg_t i2c_lld_master_transmit_timeout(I2CDriver* i2cp, i2caddr_t addr, + const uint8_t* txbuf, size_t txbytes, + uint8_t* rxbuf, size_t rxbytes, + sysinterval_t timeout); +msg_t i2c_lld_master_receive_timeout(I2CDriver* i2cp, i2caddr_t addr, + uint8_t* rxbuf, size_t rxbytes, + sysinterval_t timeout); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld_samd2x.inc b/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld_samd2x.inc new file mode 100644 index 0000000000..26a2879442 --- /dev/null +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld_samd2x.inc @@ -0,0 +1,287 @@ +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief I2C1 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM0 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/** + * @brief I2C2 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM1 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD2; +#endif + +/** + * @brief I2C3 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM2 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD3; +#endif + +/** + * @brief I2C4 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM3 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD4; +#endif + +/** + * @brief I2C5 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM4 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD5; +#endif + +/** + * @brief I2C6 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM5 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD6; +#endif + +#if SAM_I2C_USE_SERCOM0 == TRUE +OSAL_IRQ_HANDLER(SERCOM0_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD1); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM1 == TRUE +OSAL_IRQ_HANDLER(SERCOM1_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD2); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM2 == TRUE +OSAL_IRQ_HANDLER(SERCOM2_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD3); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM3 == TRUE +OSAL_IRQ_HANDLER(SERCOM3_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD4); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM4 == TRUE +OSAL_IRQ_HANDLER(SERCOM4_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD5); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM5 == TRUE +OSAL_IRQ_HANDLER(SERCOM5_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD6); + OSAL_IRQ_EPILOGUE(); +} +#endif + + + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + +#if SAM_I2C_USE_SERCOM0 == TRUE + i2cObjectInit(&I2CD1); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM0_Msk; + I2CD1.i2c = &SERCOM0_REGS->I2CM; + I2CD1.clock = SAM_SERCOM0_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM1 == TRUE + i2cObjectInit(&I2CD2); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM1_Msk; + I2CD2.i2c = &SERCOM1_REGS->I2CM; + I2CD2.clock = SAM_SERCOM1_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM2 == TRUE + i2cObjectInit(&I2CD3); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM2_Msk; + I2CD3.i2c = &SERCOM2_REGS->I2CM; + I2CD3.clock = SAM_SERCOM2_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM3 == TRUE + i2cObjectInit(&I2CD4); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM3_Msk; + I2CD4.i2c = &SERCOM3_REGS->I2CM; + I2CD4.clock = SAM_SERCOM3_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM4 == TRUE + i2cObjectInit(&I2CD5); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM4_Msk; + I2CD5.i2c = &SERCOM4_REGS->I2CM; + I2CD5.clock = SAM_SERCOM4_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM5 == TRUE + i2cObjectInit(&I2CD6); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM5_Msk; + I2CD6.i2c = &SERCOM5_REGS->I2CM; + I2CD6.clock = SAM_SERCOM5_GCLK_FREQ; +#endif +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver* i2cp) { + + if (i2cp->state == I2C_STOP) { + sercom_i2cm_registers_t* dp = i2cp->i2c; + /* Enables the peripheral.*/ +#if SAM_I2C_USE_SERCOM0 == TRUE + if (&I2CD1 == i2cp) { + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, + 1); + nvicEnableVector(SERCOM0_IRQn, SAM_SERCOM0_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM1 == TRUE + if (&I2CD2 == i2cp) { + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, + 1); + nvicEnableVector(SERCOM1_IRQn, SAM_SERCOM1_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM2 == TRUE + if (&I2CD3 == i2cp) { + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, + 1); + nvicEnableVector(SERCOM2_IRQn, SAM_SERCOM1_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM3 == TRUE + if (&I2CD4 == i2cp) { + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, + 1); + nvicEnableVector(SERCOM3_IRQn, SAM_SERCOM3_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM4 == TRUE + if (&I2CD5 == i2cp) { + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, + 1); + nvicEnableVector(SERCOM4_IRQn, SAM_SERCOM4_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM5 == TRUE + if (&I2CD6 == i2cp) { + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, + 1); + nvicEnableVector(SERCOM5_IRQn, SAM_SERCOM5_IRQ_PRIORITY); + } +#endif + // Resetting sercom module + i2cp->i2c->SERCOM_CTRLA = SERCOM_I2CM_CTRLA_SWRST_Msk; + + /* Wait for synchronization */ + sam_i2c_busy_wait(i2cp); + + /* Enable smart mode */ + dp->SERCOM_CTRLB = SERCOM_I2CM_CTRLB_SMEN_Msk; + uint32_t baud_val = 0; + osalDbgAssert( + sam_i2c_cal_baud(i2cp->clock, i2cp->config->i2cSpeed, &baud_val), + "unable to calculate baud"); + dp->SERCOM_BAUD = baud_val; + dp->SERCOM_CTRLA = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER | + (i2cp->config->ctrla & ~SERCOM_I2C_CTRLA_FORBIDDEN) | + SERCOM_I2CM_CTRLA_ENABLE_Msk; + sam_i2c_busy_wait(i2cp); + i2cp->i2c->SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); + sam_i2c_busy_wait(i2cp); + } +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver* i2cp) { + if (i2cp->state != I2C_STOP) { + i2c_lld_abort_operation(i2cp); + /* Disables the peripheral.*/ +#if SAM_I2C_USE_SERCOM0 == TRUE + if (&I2CD1 == i2cp) { + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, 0); + nvicDisableVector(SERCOM0_IRQn); + } +#endif +#if SAM_I2C_USE_SERCOM1 == TRUE + if (&I2CD2 == i2cp) { + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, 0); + nvicDisableVector(SERCOM1_IRQn); + } +#endif +#if SAM_I2C_USE_SERCOM2 == TRUE + if (&I2CD3 == i2cp) { + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, 0); + nvicDisableVector(SERCOM2_IRQn); + } +#endif +#if SAM_I2C_USE_SERCOM3 == TRUE + if (&I2CD4 == i2cp) { + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, 0); + nvicDisableVector(SERCOM3_IRQn); + } +#endif +#if SAM_I2C_USE_SERCOM4 == TRUE + if (&I2CD5 == i2cp) { + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, 0); + nvicDisableVector(SERCOM4_IRQn); + } +#endif +#if SAM_I2C_USE_SERCOM5 == TRUE + if (&I2CD6 == i2cp) { + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, 0); + nvicDisableVector(SERCOM5_IRQn); + } +#endif + } +} \ No newline at end of file diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld_same5x.inc b/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld_same5x.inc new file mode 100644 index 0000000000..d19338eae2 --- /dev/null +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_i2c_lld_same5x.inc @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief I2C1 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM0 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/** + * @brief I2C2 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM1 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD2; +#endif + +/** + * @brief I2C3 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM2 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD3; +#endif + +/** + * @brief I2C4 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM3 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD4; +#endif + +/** + * @brief I2C5 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM4 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD5; +#endif + +/** + * @brief I2C6 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM5 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD6; +#endif + +/** + * @brief I2C6 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM6 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD7; +#endif + +/** + * @brief I2C6 driver identifier. + */ +#if (SAM_I2C_USE_SERCOM7 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD8; +#endif + + +#if SAM_I2C_USE_SERCOM0 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_0_0_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD1); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_0_1_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD1); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_0_2_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD1); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_0_3_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD1); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM1 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_1_0_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD2); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_1_1_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD2); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_1_2_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD2); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_1_3_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD2); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM2 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_2_0_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD3); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_2_1_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD3); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_2_2_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD3); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_2_3_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD3); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM3 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_3_0_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD4); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_3_1_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD4); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_3_2_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD4); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_3_3_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD4); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM4 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_4_0_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD5); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_4_1_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD5); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_4_2_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD5); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_4_3_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD5); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM5 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_5_0_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD6); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_5_1_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD6); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_5_2_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD6); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_5_3_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD6); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM6 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_6_0_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD7); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_6_1_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD7); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_6_2_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD7); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_6_3_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD7); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_I2C_USE_SERCOM7 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_7_0_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD8); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_7_1_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD8); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_7_2_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD8); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_7_3_HANDLER) { + OSAL_IRQ_PROLOGUE(); + i2c_lld_serve_interrupt(&I2CD8); + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * @todo + * @notapi + */ +void i2c_lld_init(void) { + +#if SAM_I2C_USE_SERCOM0 == TRUE + i2cObjectInit(&I2CD1); + MCLK_REGS->MCLK_APBAMASK |= MCLK_APBAMASK_SERCOM0_Msk; + I2CD1.i2c = &SERCOM0_REGS->I2CM; + I2CD1.clock = SAM_SERCOM0_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM1 == TRUE + i2cObjectInit(&I2CD2); + MCLK_REGS->MCLK_APBAMASK |= MCLK_APBAMASK_SERCOM1_Msk; + I2CD2.i2c = &SERCOM1_REGS->I2CM; + I2CD2.clock = SAM_SERCOM1_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM2 == TRUE + i2cObjectInit(&I2CD3); + MCLK_REGS->MCLK_APBBMASK |= MCLK_APBBMASK_SERCOM2_Msk; + I2CD3.i2c = &SERCOM2_REGS->I2CM; + I2CD3.clock = SAM_SERCOM2_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM3 == TRUE + i2cObjectInit(&I2CD4); + MCLK_REGS->MCLK_APBBMASK |= MCLK_APBBMASK_SERCOM3_Msk; + I2CD4.i2c = &SERCOM3_REGS->I2CM; + I2CD4.clock = SAM_SERCOM3_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM4 == TRUE + i2cObjectInit(&I2CD5); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM4_Msk; + I2CD5.i2c = &SERCOM4_REGS->I2CM; + I2CD5.clock = SAM_SERCOM4_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM5 == TRUE + i2cObjectInit(&I2CD6); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM5_Msk; + I2CD6.i2c = &SERCOM5_REGS->I2CM; + I2CD6.clock = SAM_SERCOM5_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM6 == TRUE + i2cObjectInit(&I2CD7); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM6_Msk; + I2CD7.i2c = &SERCOM6_REGS->I2CM; + I2CD7.clock = SAM_SERCOM6_GCLK_FREQ; +#endif +#if SAM_I2C_USE_SERCOM7 == TRUE + i2cObjectInit(&I2CD8); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM7_Msk; + I2CD8.i2c = &SERCOM7_REGS->I2CM; + I2CD8.clock = SAM_SERCOM7_GCLK_FREQ; +#endif +} + +/** + * @brief Configures and activates the I2C peripheral. + * @todo + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver* i2cp) { + + if (i2cp->state == I2C_STOP) { + sercom_i2cm_registers_t* dp = i2cp->i2c; + /* Enables the peripheral.*/ +#if SAM_I2C_USE_SERCOM0 == TRUE + if (&I2CD1 == i2cp) { + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM0_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM0_CORE_Val, + 1); + nvicEnableVector(SERCOM0_0_IRQn, SAM_SERCOM0_IRQ_PRIORITY); + nvicEnableVector(SERCOM0_1_IRQn, SAM_SERCOM0_IRQ_PRIORITY); + nvicEnableVector(SERCOM0_2_IRQn, SAM_SERCOM0_IRQ_PRIORITY); + nvicEnableVector(SERCOM0_OTHER_IRQn, SAM_SERCOM0_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM1 == TRUE + if (&I2CD2 == i2cp) { + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM1_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM1_CORE_Val, + 1); + nvicEnableVector(SERCOM1_0_IRQn, SAM_SERCOM1_IRQ_PRIORITY); + nvicEnableVector(SERCOM1_1_IRQn, SAM_SERCOM1_IRQ_PRIORITY); + nvicEnableVector(SERCOM1_2_IRQn, SAM_SERCOM1_IRQ_PRIORITY); + nvicEnableVector(SERCOM1_OTHER_IRQn, SAM_SERCOM1_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM2 == TRUE + if (&I2CD3 == i2cp) { + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM2_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM2_CORE_Val, + 1); + nvicEnableVector(SERCOM2_0_IRQn, SAM_SERCOM2_IRQ_PRIORITY); + nvicEnableVector(SERCOM2_1_IRQn, SAM_SERCOM2_IRQ_PRIORITY); + nvicEnableVector(SERCOM2_2_IRQn, SAM_SERCOM2_IRQ_PRIORITY); + nvicEnableVector(SERCOM2_OTHER_IRQn, SAM_SERCOM2_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM3 == TRUE + if (&I2CD4 == i2cp) { + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM3_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM3_CORE_Val, + 1); + nvicEnableVector(SERCOM3_0_IRQn, SAM_SERCOM3_IRQ_PRIORITY); + nvicEnableVector(SERCOM3_1_IRQn, SAM_SERCOM3_IRQ_PRIORITY); + nvicEnableVector(SERCOM3_2_IRQn, SAM_SERCOM3_IRQ_PRIORITY); + nvicEnableVector(SERCOM3_OTHER_IRQn, SAM_SERCOM3_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM4 == TRUE + if (&I2CD5 == i2cp) { + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM4_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM4_CORE_Val, + 1); + nvicEnableVector(SERCOM4_0_IRQn, SAM_SERCOM4_IRQ_PRIORITY); + nvicEnableVector(SERCOM4_1_IRQn, SAM_SERCOM4_IRQ_PRIORITY); + nvicEnableVector(SERCOM4_2_IRQn, SAM_SERCOM4_IRQ_PRIORITY); + nvicEnableVector(SERCOM4_OTHER_IRQn, SAM_SERCOM4_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM5 == TRUE + if (&I2CD6 == i2cp) { + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM5_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM5_CORE_Val, + 1); + nvicEnableVector(SERCOM5_0_IRQn, SAM_SERCOM5_IRQ_PRIORITY); + nvicEnableVector(SERCOM5_1_IRQn, SAM_SERCOM5_IRQ_PRIORITY); + nvicEnableVector(SERCOM5_2_IRQn, SAM_SERCOM5_IRQ_PRIORITY); + nvicEnableVector(SERCOM5_OTHER_IRQn, SAM_SERCOM5_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM6 == TRUE + if (&I2CD7 == i2cp) { + sam_gclk_mux(SAM_SERCOM6_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM6_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM6_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM6_CORE_Val, + 1); + nvicEnableVector(SERCOM6_0_IRQn, SAM_SERCOM6_IRQ_PRIORITY); + nvicEnableVector(SERCOM6_1_IRQn, SAM_SERCOM6_IRQ_PRIORITY); + nvicEnableVector(SERCOM6_2_IRQn, SAM_SERCOM6_IRQ_PRIORITY); + nvicEnableVector(SERCOM6_OTHER_IRQn, SAM_SERCOM6_IRQ_PRIORITY); + } +#endif + +#if SAM_I2C_USE_SERCOM7 == TRUE + if (&I2CD8 == i2cp) { + sam_gclk_mux(SAM_SERCOM7_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM7_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM7_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM7_CORE_Val, + 1); + nvicEnableVector(SERCOM7_0_IRQn, SAM_SERCOM7_IRQ_PRIORITY); + nvicEnableVector(SERCOM7_1_IRQn, SAM_SERCOM7_IRQ_PRIORITY); + nvicEnableVector(SERCOM7_2_IRQn, SAM_SERCOM7_IRQ_PRIORITY); + nvicEnableVector(SERCOM7_OTHER_IRQn, SAM_SERCOM7_IRQ_PRIORITY); + } +#endif + + // Resetting sercom module + i2cp->i2c->SERCOM_CTRLA = SERCOM_I2CM_CTRLA_SWRST_Msk; + + /* Wait for synchronization */ + sam_i2c_busy_wait(i2cp); + + /* Enable smart mode */ + dp->SERCOM_CTRLB = SERCOM_I2CM_CTRLB_SMEN_Msk; + uint32_t baud_val = 0; + sam_i2c_cal_baud(i2cp->clock, i2cp->config->i2cSpeed, &baud_val); + // osalDbgAssert( + // sam_i2c_cal_baud(i2cp->clock, i2cp->config->i2cSpeed, &baud_val), + // "unable to calculate baud"); + dp->SERCOM_BAUD = baud_val; + dp->SERCOM_CTRLA = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER | + (i2cp->config->ctrla & ~SERCOM_I2C_CTRLA_FORBIDDEN) | + SERCOM_I2CM_CTRLA_ENABLE_Msk; + sam_i2c_busy_wait(i2cp); + i2cp->i2c->SERCOM_STATUS = (uint16_t)SERCOM_I2CM_STATUS_BUSSTATE(0x01UL); + sam_i2c_busy_wait(i2cp); + } +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver* i2cp) { + if (i2cp->state != I2C_STOP) { + i2c_lld_abort_operation(i2cp); + /* Disables the peripheral.*/ + +#if SAM_I2C_USE_SERCOM0 == TRUE + if (&I2CD1 == i2cp) { + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM0_CORE_Val, 0); + nvicDisableVector(SERCOM0_0_IRQn); + nvicDisableVector(SERCOM0_1_IRQn); + nvicDisableVector(SERCOM0_2_IRQn); + nvicDisableVector(SERCOM0_OTHER_IRQn); + } +#endif + +#if SAM_I2C_USE_SERCOM1 == TRUE + if (&I2CD2 == i2cp) { + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM1_CORE_Val, 0); + nvicDisableVector(SERCOM1_0_IRQn); + nvicDisableVector(SERCOM1_1_IRQn); + nvicDisableVector(SERCOM1_2_IRQn); + nvicDisableVector(SERCOM1_OTHER_IRQn); + } +#endif + +#if SAM_I2C_USE_SERCOM2 == TRUE + if (&I2CD3 == i2cp) { + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM2_CORE_Val, 0); + nvicDisableVector(SERCOM2_0_IRQn); + nvicDisableVector(SERCOM2_1_IRQn); + nvicDisableVector(SERCOM2_2_IRQn); + nvicDisableVector(SERCOM2_OTHER_IRQn); + } +#endif + +#if SAM_I2C_USE_SERCOM3 == TRUE + if (&I2CD4 == i2cp) { + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM3_CORE_Val, 0); + nvicDisableVector(SERCOM3_0_IRQn); + nvicDisableVector(SERCOM3_1_IRQn); + nvicDisableVector(SERCOM3_2_IRQn); + nvicDisableVector(SERCOM3_OTHER_IRQn); + } +#endif + +#if SAM_I2C_USE_SERCOM4 == TRUE + if (&I2CD5 == i2cp) { + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM4_CORE_Val, 0); + nvicDisableVector(SERCOM4_0_IRQn); + nvicDisableVector(SERCOM4_1_IRQn); + nvicDisableVector(SERCOM4_2_IRQn); + nvicDisableVector(SERCOM4_OTHER_IRQn); + } +#endif + +#if SAM_I2C_USE_SERCOM5 == TRUE + if (&I2CD6 == i2cp) { + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM5_CORE_Val, 0); + nvicDisableVector(SERCOM5_0_IRQn); + nvicDisableVector(SERCOM5_1_IRQn); + nvicDisableVector(SERCOM5_2_IRQn); + nvicDisableVector(SERCOM5_OTHER_IRQn); + } +#endif + +#if SAM_I2C_USE_SERCOM6 == TRUE + if (&I2CD7 == i2cp) { + sam_gclk_mux(SAM_SERCOM6_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM6_CORE_Val, 0); + nvicDisableVector(SERCOM6_0_IRQn); + nvicDisableVector(SERCOM6_1_IRQn); + nvicDisableVector(SERCOM6_2_IRQn); + nvicDisableVector(SERCOM6_OTHER_IRQn); + } +#endif + +#if SAM_I2C_USE_SERCOM7 == TRUE + if (&I2CD8 == i2cp) { + sam_gclk_mux(SAM_SERCOM7_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM7_CORE_Val, 0); + nvicDisableVector(SERCOM7_0_IRQn); + nvicDisableVector(SERCOM7_1_IRQn); + nvicDisableVector(SERCOM7_2_IRQn); + nvicDisableVector(SERCOM7_OTHER_IRQn); + } +#endif + + } +} \ No newline at end of file diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld.c b/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld.c index 52485485a2..ff5ef9c835 100644 --- a/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld.c +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld.c @@ -26,62 +26,21 @@ #if (HAL_USE_SIO == TRUE) || defined(__DOXYGEN__) #include "sercom_clk.h" + /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ -#define SERCOM_UART_CTRLA_FORBIDDEN (SERCOM_USART_INT_CTRLA_ENABLE_Msk | \ - SERCOM_USART_INT_CTRLA_SWRST_Msk | \ - SERCOM_USART_INT_CTRLA_TXPO_Msk | \ - SERCOM_USART_INT_CTRLA_RXPO_Msk) +#define SERCOM_UART_CTRLA_FORBIDDEN \ + (SERCOM_USART_INT_CTRLA_ENABLE_Msk | SERCOM_USART_INT_CTRLA_SWRST_Msk | \ + SERCOM_USART_INT_CTRLA_TXPO_Msk | SERCOM_USART_INT_CTRLA_RXPO_Msk) #define SERCOM_UART_CTRLB_FORBIDDEN (SERCOM_USART_INT_CTRLB_ENC_Msk) + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ -/** - * @brief SIO1 driver identifier. - */ -#if (SAM_SIO_USE_SERCOM0 == TRUE) || defined(__DOXYGEN__) -SIODriver SIOD1; -#endif - -/** - * @brief SIO2 driver identifier. - */ -#if (SAM_SIO_USE_SERCOM1 == TRUE) || defined(__DOXYGEN__) -SIODriver SIOD2; -#endif - -/** - * @brief SIO3 driver identifier. - */ -#if (SAM_SIO_USE_SERCOM2 == TRUE) || defined(__DOXYGEN__) -SIODriver SIOD3; -#endif - -/** - * @brief SIO4 driver identifier. - */ -#if (SAM_SIO_USE_SERCOM3 == TRUE) || defined(__DOXYGEN__) -SIODriver SIOD4; -#endif - -/** - * @brief SIO5 driver identifier. - */ -#if (SAM_SIO_USE_SERCOM4 == TRUE) || defined(__DOXYGEN__) -SIODriver SIOD5; -#endif - -/** - * @brief SIO6 driver identifier. - */ -#if (SAM_SIO_USE_SERCOM5 == TRUE) || defined(__DOXYGEN__) -SIODriver SIOD6; -#endif - /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -90,60 +49,68 @@ SIODriver SIOD6; /* Driver local functions. */ /*===========================================================================*/ -static inline uint16_t usart_baud_calc(SIODriver *siop) -{ - return (uint16_t)((uint64_t)65536 * (siop->clock - 16 * siop->config->baud) / siop->clock); +static inline uint16_t usart_baud_calc(SIODriver* siop) { + return (uint16_t)(65536U - + (uint32_t)(((uint64_t)65536U * 16U * siop->config->baud) / + siop->clock)); + // return (uint16_t)(65536ul * (siop->clock - 16 * siop->config->baud) / siop->clock); } -static inline void usart_reset(SIODriver *siop) -{ +static inline void usart_reset(SIODriver* siop) { siop->usart->SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_SWRST_Msk; - while ((siop->usart->SERCOM_SYNCBUSY & SERCOM_USART_INT_SYNCBUSY_SWRST_Msk) != 0U) + while ((siop->usart->SERCOM_SYNCBUSY & SERCOM_USART_INT_SYNCBUSY_SWRST_Msk) != + 0U) ; } -static inline void usart_init(SIODriver *siop) -{ - siop->usart->SERCOM_BAUD = SERCOM_USART_INT_BAUD_BAUD(usart_baud_calc(siop)); - siop->usart->SERCOM_CTRLA = (siop->config->ctrla & ~(SERCOM_UART_CTRLA_FORBIDDEN)) | - SERCOM_USART_INT_CTRLA_TXPO(siop->config->txpo) | - SERCOM_USART_INT_CTRLA_RXPO(siop->config->rxpo) | - SERCOM_USART_INT_CTRLA_ENABLE_Msk; - while ((siop->usart->SERCOM_SYNCBUSY & SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk) != 0U) +static inline void usart_init(SIODriver* siop) { + siop->usart->SERCOM_BAUD = + (uint16_t)(SERCOM_USART_INT_BAUD_BAUD(usart_baud_calc(siop))); + siop->usart->SERCOM_CTRLA = + (siop->config->ctrla & ~(SERCOM_UART_CTRLA_FORBIDDEN)) | + SERCOM_USART_INT_CTRLA_TXPO(siop->config->txpo) | + SERCOM_USART_INT_CTRLA_RXPO(siop->config->rxpo) | + SERCOM_USART_INT_CTRLA_ENABLE_Msk; + while ((siop->usart->SERCOM_SYNCBUSY & + SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk) != 0U) ; - siop->usart->SERCOM_CTRLB = (siop->config->ctrlb & ~(SERCOM_UART_CTRLB_FORBIDDEN)) | SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk; - while ((siop->usart->SERCOM_SYNCBUSY & SERCOM_USART_INT_SYNCBUSY_CTRLB_Msk) != 0U) + siop->usart->SERCOM_CTRLB = + (siop->config->ctrlb & ~(SERCOM_UART_CTRLB_FORBIDDEN)) | + SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk; + while ((siop->usart->SERCOM_SYNCBUSY & SERCOM_USART_INT_SYNCBUSY_CTRLB_Msk) != + 0U) ; } -static inline void usart_enable_rx_errors_irq(SIODriver *siop) -{ - uint8_t intenset = __sio_reloc_field(siop->enabled, SIO_EV_OVERRUN_ERR, SIO_EV_OVERRUN_ERR_POS, SERCOM_USART_INT_INTENSET_ERROR_Pos) | - __sio_reloc_field(siop->enabled, SIO_EV_RXBREAK, SIO_EV_RXBREAK_POS, SERCOM_USART_INT_INTENSET_RXBRK_Pos) | - __sio_reloc_field(siop->enabled, SIO_EV_PARITY_ERR, SIO_EV_PARITY_ERR_POS, SERCOM_USART_INT_INTENSET_ERROR_Pos) | - __sio_reloc_field(siop->enabled, SIO_EV_FRAMING_ERR, SIO_EV_FRAMING_ERR_POS, SERCOM_USART_INT_INTENSET_ERROR_Pos); +static inline void usart_enable_rx_errors_irq(SIODriver* siop) { + uint8_t intenset = + __sio_reloc_field(siop->enabled, SIO_EV_OVERRUN_ERR, + SIO_EV_OVERRUN_ERR_POS, + SERCOM_USART_INT_INTENSET_ERROR_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_RXBREAK, SIO_EV_RXBREAK_POS, + SERCOM_USART_INT_INTENSET_RXBRK_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_PARITY_ERR, SIO_EV_PARITY_ERR_POS, + SERCOM_USART_INT_INTENSET_ERROR_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_FRAMING_ERR, + SIO_EV_FRAMING_ERR_POS, + SERCOM_USART_INT_INTENSET_ERROR_Pos); + siop->usart->SERCOM_INTENSET = intenset; } -static inline void usart_enable_rx_irq(SIODriver *siop) -{ - if ((siop->enabled & SIO_EV_RXNOTEMPY) != 0U) - { +static inline void usart_enable_rx_irq(SIODriver* siop) { + if ((siop->enabled & SIO_EV_RXNOTEMPY) != 0U) { siop->usart->SERCOM_INTENSET |= SERCOM_USART_INT_INTENSET_RXC_Msk; } } -static inline void usart_enable_tx_irq(SIODriver *siop) -{ - if ((siop->enabled & SIO_EV_TXNOTFULL) != 0U) - { +static inline void usart_enable_tx_irq(SIODriver* siop) { + if ((siop->enabled & SIO_EV_TXNOTFULL) != 0U) { siop->usart->SERCOM_INTENSET |= SERCOM_USART_INT_INTENSET_DRE_Msk; } } -static inline void usart_enable_tx_end_irq(SIODriver *siop) -{ - if ((siop->enabled & SIO_EV_TXDONE) != 0U) - { +static inline void usart_enable_tx_end_irq(SIODriver* siop) { + if ((siop->enabled & SIO_EV_TXDONE) != 0U) { siop->usart->SERCOM_INTENSET |= SERCOM_USART_INT_INTENSET_TXC_Msk; } } @@ -152,292 +119,43 @@ static inline void usart_enable_tx_end_irq(SIODriver *siop) /* Driver interrupt handlers. */ /*===========================================================================*/ -#if SAM_SIO_USE_SERCOM0 == TRUE -OSAL_IRQ_HANDLER(SERCOM0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - sio_lld_serve_interrupt(&SIOD1); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if SAM_SIO_USE_SERCOM1 == TRUE -OSAL_IRQ_HANDLER(SERCOM1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - sio_lld_serve_interrupt(&SIOD2); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if SAM_SIO_USE_SERCOM2 == TRUE -OSAL_IRQ_HANDLER(SERCOM2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - sio_lld_serve_interrupt(&SIOD3); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if SAM_SIO_USE_SERCOM3 == TRUE -OSAL_IRQ_HANDLER(SERCOM3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - sio_lld_serve_interrupt(&SIOD4); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if SAM_SIO_USE_SERCOM4 == TRUE -OSAL_IRQ_HANDLER(SERCOM4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - sio_lld_serve_interrupt(&SIOD5); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if SAM_SIO_USE_SERCOM5 == TRUE -OSAL_IRQ_HANDLER(SERCOM5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - sio_lld_serve_interrupt(&SIOD6); - OSAL_IRQ_EPILOGUE(); -} +#if defined(SAMD21_MCUCONF) +#include "hal_sio_lld_samd2x.inc" +#elif defined(SAME54_MCUCONF) +#include "hal_sio_lld_same5x.inc" #endif /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ -/** - * @brief Low level SIO driver initialization. - * - * @notapi - */ -void sio_lld_init(void) -{ - -#if SAM_SIO_USE_SERCOM0 == TRUE - /* Driver initialization.*/ - sioObjectInit(&SIOD1); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM0_Msk; - SIOD1.usart = &SERCOM0_REGS->USART_INT; - SIOD1.clock = SAM_SERCOM0_GCLK_SRC_FREQ; -#endif -#if SAM_SIO_USE_SERCOM1 == TRUE - /* Driver initialization.*/ - sioObjectInit(&SIOD2); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM1_Msk; - SIOD2.usart = &SERCOM1_REGS->USART_INT; - SIOD2.clock = SAM_SERCOM1_GCLK_SRC_FREQ; -#endif -#if SAM_SIO_USE_SERCOM2 == TRUE - /* Driver initialization.*/ - sioObjectInit(&SIOD3); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM2_Msk; - SIOD3.usart = &SERCOM2_REGS->USART_INT; - SIOD3.clock = SAM_SERCOM2_GCLK_SRC_FREQ; -#endif -#if SAM_SIO_USE_SERCOM3 == TRUE - /* Driver initialization.*/ - sioObjectInit(&SIOD4); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM3_Msk; - SIOD4.usart = &SERCOM3_REGS->USART_INT; - SIOD4.clock = SAM_SERCOM3_GCLK_SRC_FREQ; -#endif -#if SAM_SIO_USE_SERCOM4 == TRUE - /* Driver initialization.*/ - sioObjectInit(&SIOD5); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM4_Msk; - SIOD5.usart = &SERCOM4_REGS->USART_INT; - SIOD5.clock = SAM_SERCOM4_GCLK_SRC_FREQ; -#endif -#if SAM_SIO_USE_SERCOM5 == TRUE - /* Driver initialization.*/ - sioObjectInit(&SIOD6); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM5_Msk; - SIOD6.usart = &SERCOM5_REGS->USART_INT; - SIOD6.clock = SAM_SERCOM5_GCLK_SRC_FREQ; -#endif -} - -/** - * @brief Configures and activates the SIO peripheral. - * - * @param[in] siop pointer to the @p SIODriver object - * @return The operation status. - * - * @notapi - */ -msg_t sio_lld_start(SIODriver *siop) -{ - - if (siop->config == NULL) - { - osalDbgAssert(siop->config, "SERCOM requires configuration"); - } - if (siop->state == SIO_STOP) - { - /* Enables the peripheral.*/ -#if SAM_SIO_USE_SERCOM0 == TRUE - if (&SIOD1 == siop) - { - sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, 1); - usart_reset(&SIOD1); - nvicEnableVector(SERCOM0_IRQn, SAM_SERCOM0_IRQ_PRIORITY); - } -#endif - -#if SAM_SIO_USE_SERCOM1 == TRUE - if (&SIOD2 == siop) - { - sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, 1); - usart_reset(&SIOD2); - nvicEnableVector(SERCOM1_IRQn, SAM_SERCOM1_IRQ_PRIORITY); - } -#endif - -#if SAM_SIO_USE_SERCOM2 == TRUE - if (&SIOD3 == siop) - { - sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, 1); - usart_reset(&SIOD3); - nvicEnableVector(SERCOM2_IRQn, SAM_SERCOM2_IRQ_PRIORITY); - } -#endif - -#if SAM_SIO_USE_SERCOM3 == TRUE - if (&SIOD4 == siop) - { - sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, 1); - usart_reset(&SIOD4); - nvicEnableVector(SERCOM3_IRQn, SAM_SERCOM3_IRQ_PRIORITY); - } -#endif - -#if SAM_SIO_USE_SERCOM4 == TRUE - if (&SIOD5 == siop) - { - sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, 1); - usart_reset(&SIOD5); - nvicEnableVector(SERCOM4_IRQn, SAM_SERCOM4_IRQ_PRIORITY); - } -#endif - -#if SAM_SIO_USE_SERCOM5 == TRUE - if (&SIOD6 == siop) - { - sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, 1); - usart_reset(&SIOD6); - nvicEnableVector(SERCOM5_IRQn, SAM_SERCOM5_IRQ_PRIORITY); - } -#endif - } - /* Configures the peripheral.*/ - usart_init(siop); - return HAL_RET_SUCCESS; -} - -/** - * @brief Deactivates the SIO peripheral. - * - * @param[in] siop pointer to the @p SIODriver object - * - * @notapi - */ -void sio_lld_stop(SIODriver *siop) -{ - - if (siop->state == SIO_READY) - { - /* Resets the peripheral.*/ - siop->usart->SERCOM_INTENCLR = SERCOM_USART_INT_INTENCLR_Msk; - // disable sercom - siop->usart->SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; - while ((siop->usart->SERCOM_SYNCBUSY & SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk) != 0U) - ; - /* Disables the peripheral.*/ -#if SAM_SIO_USE_SERCOM0 == TRUE - if (&SIOD1 == siop) - { - usart_reset(&SIOD1); - sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, 0); - nvicDisableVector(SERCOM0_IRQn); - } -#endif - -#if SAM_SIO_USE_SERCOM1 == TRUE - if (&SIOD2 == siop) - { - usart_reset(&SIOD2); - sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, 0); - nvicDisableVector(SERCOM1_IRQn); - } -#endif - -#if SAM_SIO_USE_SERCOM2 == TRUE - if (&SIOD3 == siop) - { - usart_reset(&SIOD3); - sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, 0); - nvicDisableVector(SERCOM2_IRQn); - } -#endif - -#if SAM_SIO_USE_SERCOM3 == TRUE - if (&SIOD4 == siop) - { - usart_reset(&SIOD4); - sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, 0); - nvicDisableVector(SERCOM3_IRQn); - } -#endif - -#if SAM_SIO_USE_SERCOM4 == TRUE - if (&SIOD5 == siop) - { - usart_reset(&SIOD5); - sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, 0); - nvicDisableVector(SERCOM4_IRQn); - } -#endif - -#if SAM_SIO_USE_SERCOM5 == TRUE - if (&SIOD6 == siop) - { - usart_reset(&SIOD6); - sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, 0); - nvicDisableVector(SERCOM5_IRQn); - } -#endif - } -} - /** * @brief Enable flags change notification. * * @param[in] siop pointer to the @p SIODriver object */ -void sio_lld_update_enable_flags(SIODriver *siop) -{ +void sio_lld_update_enable_flags(SIODriver* siop) { uint8_t intenset; // osalDbgAssert((siop->enabled & SIO_EV_RXIDLE) == 0U, "unsupported event"); - intenset = __sio_reloc_field(siop->enabled, SIO_EV_RXNOTEMPY, SIO_EV_RXNOTEMPY_POS, SERCOM_USART_INT_INTENSET_RXC_Pos) | - __sio_reloc_field(siop->enabled, SIO_EV_TXNOTFULL, SIO_EV_TXNOTFULL_POS, SERCOM_USART_INT_INTENSET_DRE_Pos) | - __sio_reloc_field(siop->enabled, SIO_EV_OVERRUN_ERR, SIO_EV_OVERRUN_ERR_POS, SERCOM_USART_INT_INTENSET_ERROR_Pos) | - __sio_reloc_field(siop->enabled, SIO_EV_RXBREAK, SIO_EV_RXBREAK_POS, SERCOM_USART_INT_INTENSET_RXBRK_Pos) | - __sio_reloc_field(siop->enabled, SIO_EV_PARITY_ERR, SIO_EV_PARITY_ERR_POS, SERCOM_USART_INT_INTENSET_ERROR_Pos) | - __sio_reloc_field(siop->enabled, SIO_EV_FRAMING_ERR, SIO_EV_FRAMING_ERR_POS, SERCOM_USART_INT_INTENSET_ERROR_Pos) | - __sio_reloc_field(siop->enabled, SIO_EV_TXDONE, SIO_EV_TXDONE_POS, SERCOM_USART_INT_INTENSET_TXC_Pos); + intenset = + __sio_reloc_field(siop->enabled, SIO_EV_RXNOTEMPY, SIO_EV_RXNOTEMPY_POS, + SERCOM_USART_INT_INTENSET_RXC_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_TXNOTFULL, SIO_EV_TXNOTFULL_POS, + SERCOM_USART_INT_INTENSET_DRE_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_OVERRUN_ERR, + SIO_EV_OVERRUN_ERR_POS, + SERCOM_USART_INT_INTENSET_ERROR_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_RXBREAK, SIO_EV_RXBREAK_POS, + SERCOM_USART_INT_INTENSET_RXBRK_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_PARITY_ERR, SIO_EV_PARITY_ERR_POS, + SERCOM_USART_INT_INTENSET_ERROR_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_FRAMING_ERR, + SIO_EV_FRAMING_ERR_POS, + SERCOM_USART_INT_INTENSET_ERROR_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_TXDONE, SIO_EV_TXDONE_POS, + SERCOM_USART_INT_INTENSET_TXC_Pos); /* Setting up the operation.*/ siop->usart->SERCOM_INTENSET = intenset; @@ -451,19 +169,28 @@ void sio_lld_update_enable_flags(SIODriver *siop) * * @notapi */ -sioevents_t sio_lld_get_and_clear_errors(SIODriver *siop) -{ +sioevents_t sio_lld_get_and_clear_errors(SIODriver* siop) { sioevents_t errors = 0U; uint8_t status = 0; uint8_t irq_status = 0; status = (uint8_t)(siop->usart->SERCOM_STATUS); irq_status = (uint8_t)(siop->usart->SERCOM_INTFLAG); - siop->usart->SERCOM_STATUS |= SERCOM_USART_INT_STATUS_BUFOVF_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | SERCOM_USART_INT_STATUS_PERR_Msk; + siop->usart->SERCOM_STATUS |= SERCOM_USART_INT_STATUS_BUFOVF_Msk | + SERCOM_USART_INT_STATUS_FERR_Msk | + SERCOM_USART_INT_STATUS_PERR_Msk; siop->usart->SERCOM_INTFLAG |= SERCOM_USART_INT_INTFLAG_RXBRK_Msk; - errors = __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_RXBRK_Msk, SERCOM_USART_INT_INTFLAG_RXBRK_Pos, SIO_EV_RXBREAK_POS) | - __sio_reloc_field(status, SERCOM_USART_INT_STATUS_BUFOVF_Msk, SERCOM_USART_INT_STATUS_BUFOVF_Pos, SIO_EV_OVERRUN_ERR_POS) | - __sio_reloc_field(status, SERCOM_USART_INT_STATUS_FERR_Msk, SERCOM_USART_INT_STATUS_FERR_Pos, SIO_EV_FRAMING_ERR_POS) | - __sio_reloc_field(status, SERCOM_USART_INT_STATUS_PERR_Msk, SERCOM_USART_INT_STATUS_PERR_Pos, SIO_EV_PARITY_ERR_POS); + errors = __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_RXBRK_Msk, + SERCOM_USART_INT_INTFLAG_RXBRK_Pos, + SIO_EV_RXBREAK_POS) | + __sio_reloc_field(status, SERCOM_USART_INT_STATUS_BUFOVF_Msk, + SERCOM_USART_INT_STATUS_BUFOVF_Pos, + SIO_EV_OVERRUN_ERR_POS) | + __sio_reloc_field(status, SERCOM_USART_INT_STATUS_FERR_Msk, + SERCOM_USART_INT_STATUS_FERR_Pos, + SIO_EV_FRAMING_ERR_POS) | + __sio_reloc_field(status, SERCOM_USART_INT_STATUS_PERR_Msk, + SERCOM_USART_INT_STATUS_PERR_Pos, + SIO_EV_PARITY_ERR_POS); return errors; } @@ -476,8 +203,7 @@ sioevents_t sio_lld_get_and_clear_errors(SIODriver *siop) * * @notapi */ -sioevents_t sio_lld_get_and_clear_events(SIODriver *siop) -{ +sioevents_t sio_lld_get_and_clear_events(SIODriver* siop) { sioevents_t events = 0U; uint8_t status = 0; uint8_t irq_status = 0; @@ -486,13 +212,27 @@ sioevents_t sio_lld_get_and_clear_events(SIODriver *siop) // clear both status and intflag siop->usart->SERCOM_STATUS = SERCOM_USART_INT_STATUS_Msk; siop->usart->SERCOM_INTFLAG = SERCOM_USART_INT_INTFLAG_Msk; - events |= __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_RXC_Msk, SERCOM_USART_INT_INTFLAG_RXC_Pos, SIO_EV_RXNOTEMPY_POS) | - __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_DRE_Msk, SERCOM_USART_INT_INTFLAG_DRE_Pos, SIO_EV_TXNOTFULL_POS) | - __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_TXC_Msk, SERCOM_USART_INT_INTFLAG_TXC_Pos, SIO_EV_TXDONE_POS) | - __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_RXBRK_Msk, SERCOM_USART_INT_INTFLAG_RXBRK_Pos, SIO_EV_RXBREAK_POS) | - __sio_reloc_field(status, SERCOM_USART_INT_STATUS_BUFOVF_Msk, SERCOM_USART_INT_STATUS_BUFOVF_Pos, SIO_EV_OVERRUN_ERR_POS) | - __sio_reloc_field(status, SERCOM_USART_INT_STATUS_FERR_Msk, SERCOM_USART_INT_STATUS_FERR_Pos, SIO_EV_FRAMING_ERR_POS) | - __sio_reloc_field(status, SERCOM_USART_INT_STATUS_PERR_Msk, SERCOM_USART_INT_STATUS_PERR_Pos, SIO_EV_PARITY_ERR_POS); + events |= + __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_RXC_Msk, + SERCOM_USART_INT_INTFLAG_RXC_Pos, + SIO_EV_RXNOTEMPY_POS) | + __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_DRE_Msk, + SERCOM_USART_INT_INTFLAG_DRE_Pos, + SIO_EV_TXNOTFULL_POS) | + __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_TXC_Msk, + SERCOM_USART_INT_INTFLAG_TXC_Pos, SIO_EV_TXDONE_POS) | + __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_RXBRK_Msk, + SERCOM_USART_INT_INTFLAG_RXBRK_Pos, + SIO_EV_RXBREAK_POS) | + __sio_reloc_field(status, SERCOM_USART_INT_STATUS_BUFOVF_Msk, + SERCOM_USART_INT_STATUS_BUFOVF_Pos, + SIO_EV_OVERRUN_ERR_POS) | + __sio_reloc_field(status, SERCOM_USART_INT_STATUS_FERR_Msk, + SERCOM_USART_INT_STATUS_FERR_Pos, + SIO_EV_FRAMING_ERR_POS) | + __sio_reloc_field(status, SERCOM_USART_INT_STATUS_PERR_Msk, + SERCOM_USART_INT_STATUS_PERR_Pos, + SIO_EV_PARITY_ERR_POS); return events; } @@ -506,20 +246,34 @@ sioevents_t sio_lld_get_and_clear_events(SIODriver *siop) * @notapi */ -sioevents_t sio_lld_get_events(SIODriver *siop) -{ +sioevents_t sio_lld_get_events(SIODriver* siop) { sioevents_t events = 0U; uint8_t status = 0; uint8_t irq_status = 0; status = (uint8_t)(siop->usart->SERCOM_STATUS); irq_status = (uint8_t)(siop->usart->SERCOM_INTFLAG); - events |= __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_RXC_Msk, SERCOM_USART_INT_INTFLAG_RXC_Pos, SIO_EV_RXNOTEMPY_POS) | - __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_DRE_Msk, SERCOM_USART_INT_INTFLAG_DRE_Pos, SIO_EV_TXNOTFULL_POS) | - __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_TXC_Msk, SERCOM_USART_INT_INTFLAG_TXC_Pos, SIO_EV_TXDONE_POS) | - __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_RXBRK_Msk, SERCOM_USART_INT_INTFLAG_RXBRK_Pos, SIO_EV_RXBREAK_POS) | - __sio_reloc_field(status, SERCOM_USART_INT_STATUS_BUFOVF_Msk, SERCOM_USART_INT_STATUS_BUFOVF_Pos, SIO_EV_OVERRUN_ERR_POS) | - __sio_reloc_field(status, SERCOM_USART_INT_STATUS_FERR_Msk, SERCOM_USART_INT_STATUS_FERR_Pos, SIO_EV_FRAMING_ERR_POS) | - __sio_reloc_field(status, SERCOM_USART_INT_STATUS_PERR_Msk, SERCOM_USART_INT_STATUS_PERR_Pos, SIO_EV_PARITY_ERR_POS); + events |= + __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_RXC_Msk, + SERCOM_USART_INT_INTFLAG_RXC_Pos, + SIO_EV_RXNOTEMPY_POS) | + __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_DRE_Msk, + SERCOM_USART_INT_INTFLAG_DRE_Pos, + SIO_EV_TXNOTFULL_POS) | + __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_TXC_Msk, + SERCOM_USART_INT_INTFLAG_TXC_Pos, SIO_EV_TXDONE_POS) | + __sio_reloc_field(irq_status, SERCOM_USART_INT_INTFLAG_RXBRK_Msk, + SERCOM_USART_INT_INTFLAG_RXBRK_Pos, + SIO_EV_RXBREAK_POS) | + __sio_reloc_field(status, SERCOM_USART_INT_STATUS_BUFOVF_Msk, + SERCOM_USART_INT_STATUS_BUFOVF_Pos, + SIO_EV_OVERRUN_ERR_POS) | + __sio_reloc_field(status, SERCOM_USART_INT_STATUS_FERR_Msk, + SERCOM_USART_INT_STATUS_FERR_Pos, + SIO_EV_FRAMING_ERR_POS) | + __sio_reloc_field(status, SERCOM_USART_INT_STATUS_PERR_Msk, + SERCOM_USART_INT_STATUS_PERR_Pos, + SIO_EV_PARITY_ERR_POS); + return events; } /** @@ -533,25 +287,21 @@ sioevents_t sio_lld_get_events(SIODriver *siop) * @return The number of frames copied from the buffer. * @retval 0 if the TX FIFO is full. */ -size_t sio_lld_read(SIODriver *siop, uint8_t *buffer, size_t n) -{ +size_t sio_lld_read(SIODriver* siop, uint8_t* buffer, size_t n) { size_t rd; rd = 0U; - while (true) - { + while (true) { /* If the RX FIFO has been emptied then the interrupt is enabled again.*/ - if (sio_lld_is_rx_empty(siop)) - { + if (sio_lld_is_rx_empty(siop)) { usart_enable_rx_irq(siop); break; } /* Buffer filled condition.*/ - if (rd > n) - { + if (rd > n) { break; } @@ -573,25 +323,21 @@ size_t sio_lld_read(SIODriver *siop, uint8_t *buffer, size_t n) * @return The number of frames copied from the buffer. * @retval 0 if the TX FIFO is full. */ -size_t sio_lld_write(SIODriver *siop, const uint8_t *buffer, size_t n) -{ +size_t sio_lld_write(SIODriver* siop, const uint8_t* buffer, size_t n) { size_t wr; wr = 0U; - while (true) - { + while (true) { /* If the TX FIFO has been filled then the interrupt is enabled again.*/ - if (sio_lld_is_tx_full(siop)) - { + if (sio_lld_is_tx_full(siop)) { usart_enable_tx_irq(siop); break; } /* Buffer emptied condition.*/ - if (wr >= n) - { + if (wr >= n) { break; } uint8_t data = *buffer++; @@ -614,15 +360,13 @@ size_t sio_lld_write(SIODriver *siop, const uint8_t *buffer, size_t n) * * @notapi */ -msg_t sio_lld_get(SIODriver *siop) -{ +msg_t sio_lld_get(SIODriver* siop) { msg_t msg; msg = (uint8_t)(siop->usart->SERCOM_DATA); /* If the RX FIFO has been emptied then the interrupt is enabled again.*/ - if (sio_lld_is_rx_empty(siop)) - { + if (sio_lld_is_rx_empty(siop)) { usart_enable_rx_irq(siop); } @@ -638,14 +382,12 @@ msg_t sio_lld_get(SIODriver *siop) * * @notapi */ -void sio_lld_put(SIODriver *siop, uint_fast16_t data) -{ +void sio_lld_put(SIODriver* siop, uint_fast16_t data) { siop->usart->SERCOM_DATA = (uint8_t)data; /* If the TX FIFO has been filled then the interrupt is enabled again.*/ - if (sio_lld_is_tx_full(siop)) - { + if (sio_lld_is_tx_full(siop)) { usart_enable_tx_irq(siop); } @@ -667,8 +409,7 @@ void sio_lld_put(SIODriver *siop, uint_fast16_t data) * * @notapi */ -msg_t sio_lld_control(SIODriver *siop, unsigned int operation, void *arg) -{ +msg_t sio_lld_control(SIODriver* siop, unsigned int operation, void* arg) { (void)siop; (void)operation; @@ -684,30 +425,26 @@ msg_t sio_lld_control(SIODriver *siop, unsigned int operation, void *arg) * * @notapi */ -void sio_lld_serve_interrupt(SIODriver *siop) -{ +void sio_lld_serve_interrupt(SIODriver* siop) { osalDbgAssert(siop->state == SIO_READY, "invalid state"); uint8_t intflag = siop->usart->SERCOM_INTFLAG; - uint8_t intenset = siop->usart->SERCOM_INTENSET; uint8_t intenclr = 0; uint8_t evtmask = intflag & (SERCOM_USART_INT_INTFLAG_ERROR_Msk | SERCOM_USART_INT_INTFLAG_RXBRK_Msk); siop->usart->SERCOM_INTFLAG = SERCOM_USART_INT_INTFLAG_Msk; - if (evtmask != 0) - { + if (evtmask != 0) { __sio_wakeup_errors(siop); - intenclr |= (SERCOM_USART_INT_INTENCLR_ERROR_Msk | SERCOM_USART_INT_INTENCLR_RXBRK_Msk); + intenclr |= (SERCOM_USART_INT_INTENCLR_ERROR_Msk | + SERCOM_USART_INT_INTENCLR_RXBRK_Msk); } - if (intflag & SERCOM_USART_INT_INTFLAG_RXC_Msk) - { + if (intflag & SERCOM_USART_INT_INTFLAG_RXC_Msk) { __sio_wakeup_rx(siop); /* Called once then the interrupt source is disabled.*/ intenclr |= SERCOM_USART_INT_INTENCLR_RXC_Msk; } /* TX FIFO is non-full.*/ - if (intflag & SERCOM_USART_INT_INTFLAG_DRE_Msk) - { + if (intflag & SERCOM_USART_INT_INTFLAG_DRE_Msk) { /* Waiting thread woken, if any.*/ __sio_wakeup_tx(siop); @@ -717,8 +454,7 @@ void sio_lld_serve_interrupt(SIODriver *siop) } /* Physical transmission end.*/ - if (intflag & SERCOM_USART_INT_INTFLAG_TXC_Msk) - { + if (intflag & SERCOM_USART_INT_INTFLAG_TXC_Msk) { /* Waiting thread woken, if any.*/ __sio_wakeup_txend(siop); diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld.h b/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld.h index 7c3ebda090..d4f5b63550 100644 --- a/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld.h +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld.h @@ -145,7 +145,7 @@ * @brief Low level fields of the SIO driver structure. */ #define sio_lld_driver_fields \ - sercom_usart_int_registers_t *usart; \ + sercom_usart_int_registers_t* usart; \ uint32_t clock; /** @@ -158,11 +158,11 @@ uint8_t txpo; \ uint8_t rxpo; -#define SERCOM_CTRLA_DEFAULT (SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | \ - SERCOM_USART_INT_CTRLA_DORD_Msk | \ - SERCOM_USART_INT_CTRLA_IBON_Msk) +#define SERCOM_SIO_CTRLA_DEFAULT \ + (SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | \ + SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk) -#define SERCOM_CTRLB_DEFAULT (0) +#define SERCOM_SIO_CTRLB_DEFAULT (0) /** * @brief Determines the state of the RX FIFO. @@ -174,8 +174,9 @@ * * @notapi */ -#define sio_lld_is_rx_empty(siop) !((siop->usart->SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == \ - SERCOM_USART_INT_INTFLAG_RXC_Msk) +#define sio_lld_is_rx_empty(siop) \ + !((siop->usart->SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXC_Msk) == \ + SERCOM_USART_INT_INTFLAG_RXC_Msk) /** * @brief Determines the activity state of the receiver. @@ -201,10 +202,11 @@ * * @notapi */ -#define sio_lld_has_rx_errors(siop) ((siop->usart->SERCOM_STATUS & (SERCOM_USART_INT_STATUS_BUFOVF_Msk | \ - SERCOM_USART_INT_STATUS_FERR_Msk | \ - SERCOM_USART_INT_STATUS_PERR_Msk) != 0) | \ - (siop->usart->SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXBRK_Msk) != 0) +#define sio_lld_has_rx_errors(siop) \ + (((siop->usart->SERCOM_STATUS & \ + (SERCOM_USART_INT_STATUS_BUFOVF_Msk | SERCOM_USART_INT_STATUS_FERR_Msk | \ + SERCOM_USART_INT_STATUS_PERR_Msk)) != 0) | \ + ((siop->usart->SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_RXBRK_Msk) != 0)) /** * @brief Determines the state of the TX FIFO. @@ -216,8 +218,9 @@ * * @notapi */ -#define sio_lld_is_tx_full(siop) !((siop->usart->SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == \ - SERCOM_USART_INT_INTFLAG_DRE_Msk) +#define sio_lld_is_tx_full(siop) \ + !((siop->usart->SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk) == \ + SERCOM_USART_INT_INTFLAG_DRE_Msk) /** * @brief Determines the transmission state. @@ -229,8 +232,9 @@ * * @notapi */ -#define sio_lld_is_tx_ongoing(siop) !((siop->usart->SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_TXC_Msk) == \ - SERCOM_USART_INT_INTFLAG_TXC_Msk) +#define sio_lld_is_tx_ongoing(siop) \ + !((siop->usart->SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_TXC_Msk) == \ + SERCOM_USART_INT_INTFLAG_TXC_Msk) /*===========================================================================*/ /* External declarations. */ @@ -260,23 +264,34 @@ extern SIODriver SIOD5; extern SIODriver SIOD6; #endif +#ifdef SAME54_MCUCONF + +#if (SAM_SIO_USE_SERCOM6 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD7; +#endif + +#if (SAM_SIO_USE_SERCOM7 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD8; +#endif + +#endif + #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif - void sio_lld_init(void); - msg_t sio_lld_start(SIODriver *siop); - void sio_lld_stop(SIODriver *siop); - void sio_lld_update_enable_flags(SIODriver *siop); - sioevents_t sio_lld_get_and_clear_errors(SIODriver *siop); - sioevents_t sio_lld_get_and_clear_events(SIODriver *siop); - sioevents_t sio_lld_get_events(SIODriver *siop); - size_t sio_lld_read(SIODriver *siop, uint8_t *buffer, size_t n); - size_t sio_lld_write(SIODriver *siop, const uint8_t *buffer, size_t n); - msg_t sio_lld_get(SIODriver *siop); - void sio_lld_put(SIODriver *siop, uint_fast16_t data); - msg_t sio_lld_control(SIODriver *siop, unsigned int operation, void *arg); - void sio_lld_serve_interrupt(SIODriver *siop); +void sio_lld_init(void); +msg_t sio_lld_start(SIODriver* siop); +void sio_lld_stop(SIODriver* siop); +void sio_lld_update_enable_flags(SIODriver* siop); +sioevents_t sio_lld_get_and_clear_errors(SIODriver* siop); +sioevents_t sio_lld_get_and_clear_events(SIODriver* siop); +sioevents_t sio_lld_get_events(SIODriver* siop); +size_t sio_lld_read(SIODriver* siop, uint8_t* buffer, size_t n); +size_t sio_lld_write(SIODriver* siop, const uint8_t* buffer, size_t n); +msg_t sio_lld_get(SIODriver* siop); +void sio_lld_put(SIODriver* siop, uint_fast16_t data); +msg_t sio_lld_control(SIODriver* siop, unsigned int operation, void* arg); +void sio_lld_serve_interrupt(SIODriver* siop); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld_samd2x.inc b/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld_samd2x.inc new file mode 100644 index 0000000000..f9f6c9696f --- /dev/null +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld_samd2x.inc @@ -0,0 +1,329 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief SIO1 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM0 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD1; +#endif + +/** + * @brief SIO2 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM1 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD2; +#endif + +/** + * @brief SIO3 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM2 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD3; +#endif + +/** + * @brief SIO4 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM3 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD4; +#endif + +/** + * @brief SIO5 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM4 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD5; +#endif + +/** + * @brief SIO6 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM5 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD6; +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SAM_SIO_USE_SERCOM0 == TRUE +OSAL_IRQ_HANDLER(SERCOM0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD1); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM1 == TRUE +OSAL_IRQ_HANDLER(SERCOM1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD2); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM2 == TRUE +OSAL_IRQ_HANDLER(SERCOM2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD3); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM3 == TRUE +OSAL_IRQ_HANDLER(SERCOM3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD4); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM4 == TRUE +OSAL_IRQ_HANDLER(SERCOM4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD5); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM5 == TRUE +OSAL_IRQ_HANDLER(SERCOM5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD6); + OSAL_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief Low level SIO driver initialization. + * + * @notapi + */ +void sio_lld_init(void) +{ + +#if SAM_SIO_USE_SERCOM0 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD1); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM0_Msk; + SIOD1.usart = &SERCOM0_REGS->USART_INT; + SIOD1.clock = SAM_SERCOM0_GCLK_FREQ; +#endif +#if SAM_SIO_USE_SERCOM1 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD2); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM1_Msk; + SIOD2.usart = &SERCOM1_REGS->USART_INT; + SIOD2.clock = SAM_SERCOM1_GCLK_FREQ; +#endif +#if SAM_SIO_USE_SERCOM2 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD3); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM2_Msk; + SIOD3.usart = &SERCOM2_REGS->USART_INT; + SIOD3.clock = SAM_SERCOM2_GCLK_FREQ; +#endif +#if SAM_SIO_USE_SERCOM3 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD4); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM3_Msk; + SIOD4.usart = &SERCOM3_REGS->USART_INT; + SIOD4.clock = SAM_SERCOM3_GCLK_FREQ; +#endif +#if SAM_SIO_USE_SERCOM4 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD5); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM4_Msk; + SIOD5.usart = &SERCOM4_REGS->USART_INT; + SIOD5.clock = SAM_SERCOM4_GCLK_FREQ; +#endif +#if SAM_SIO_USE_SERCOM5 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD6); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM5_Msk; + SIOD6.usart = &SERCOM5_REGS->USART_INT; + SIOD6.clock = SAM_SERCOM5_GCLK_FREQ; +#endif +} + +/** + * @brief Configures and activates the SIO peripheral. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The operation status. + * + * @notapi + */ +msg_t sio_lld_start(SIODriver *siop) +{ + + if (siop->config == NULL) + { + osalDbgAssert(siop->config, "SERCOM requires configuration"); + } + if (siop->state == SIO_STOP) + { + /* Enables the peripheral.*/ +#if SAM_SIO_USE_SERCOM0 == TRUE + if (&SIOD1 == siop) + { + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, 1); + usart_reset(&SIOD1); + nvicEnableVector(SERCOM0_IRQn, SAM_SERCOM0_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM1 == TRUE + if (&SIOD2 == siop) + { + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, 1); + usart_reset(&SIOD2); + nvicEnableVector(SERCOM1_IRQn, SAM_SERCOM1_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM2 == TRUE + if (&SIOD3 == siop) + { + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, 1); + usart_reset(&SIOD3); + nvicEnableVector(SERCOM2_IRQn, SAM_SERCOM2_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM3 == TRUE + if (&SIOD4 == siop) + { + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, 1); + usart_reset(&SIOD4); + nvicEnableVector(SERCOM3_IRQn, SAM_SERCOM3_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM4 == TRUE + if (&SIOD5 == siop) + { + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, 1); + usart_reset(&SIOD5); + nvicEnableVector(SERCOM4_IRQn, SAM_SERCOM4_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM5 == TRUE + if (&SIOD6 == siop) + { + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, 1); + usart_reset(&SIOD6); + nvicEnableVector(SERCOM5_IRQn, SAM_SERCOM5_IRQ_PRIORITY); + } +#endif + } + /* Configures the peripheral.*/ + usart_init(siop); + return HAL_RET_SUCCESS; +} + +/** + * @brief Deactivates the SIO peripheral. + * + * @param[in] siop pointer to the @p SIODriver object + * + * @notapi + */ +void sio_lld_stop(SIODriver *siop) +{ + + if (siop->state == SIO_READY) + { + /* Resets the peripheral.*/ + siop->usart->SERCOM_INTENCLR = SERCOM_USART_INT_INTENCLR_Msk; + // disable sercom + siop->usart->SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + while ((siop->usart->SERCOM_SYNCBUSY & SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk) != 0U) + ; + /* Disables the peripheral.*/ +#if SAM_SIO_USE_SERCOM0 == TRUE + if (&SIOD1 == siop) + { + usart_reset(&SIOD1); + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, 0); + nvicDisableVector(SERCOM0_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM1 == TRUE + if (&SIOD2 == siop) + { + usart_reset(&SIOD2); + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, 0); + nvicDisableVector(SERCOM1_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM2 == TRUE + if (&SIOD3 == siop) + { + usart_reset(&SIOD3); + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, 0); + nvicDisableVector(SERCOM2_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM3 == TRUE + if (&SIOD4 == siop) + { + usart_reset(&SIOD4); + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, 0); + nvicDisableVector(SERCOM3_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM4 == TRUE + if (&SIOD5 == siop) + { + usart_reset(&SIOD5); + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, 0); + nvicDisableVector(SERCOM4_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM5 == TRUE + if (&SIOD6 == siop) + { + usart_reset(&SIOD6); + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, 0); + nvicDisableVector(SERCOM5_IRQn); + } +#endif + } +} \ No newline at end of file diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld_same5x.inc b/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld_same5x.inc new file mode 100644 index 0000000000..0ed70930fd --- /dev/null +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_sio_lld_same5x.inc @@ -0,0 +1,628 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief SIO1 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM0 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD1; +#endif + +/** + * @brief SIO2 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM1 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD2; +#endif + +/** + * @brief SIO3 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM2 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD3; +#endif + +/** + * @brief SIO4 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM3 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD4; +#endif + +/** + * @brief SIO5 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM4 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD5; +#endif + +/** + * @brief SIO6 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM5 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD6; +#endif + +/** + * @brief SIO7 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM6 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD6; +#endif + +/** + * @brief SIO8 driver identifier. + */ +#if (SAM_SIO_USE_SERCOM7 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD8; +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SAM_SIO_USE_SERCOM0 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_0_0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD1); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_0_1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD1); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_0_2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD1); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_0_3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD1); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM1 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_1_0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD2); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_1_1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD2); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_1_2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD2); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_1_3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD2); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM2 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_2_0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD3); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_2_1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD3); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_2_2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD3); + OSAL_IRQ_EPILOGUE(); +} +OSAL_IRQ_HANDLER(SAM_SERCOM_2_3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD3); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM3 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_3_0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD4); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_3_1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD4); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_3_2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD4); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_3_3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD4); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM4 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_4_0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD5); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_4_1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD5); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_4_2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD5); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_4_3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD5); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM5 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_5_0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD6); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_5_1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD6); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_5_2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD6); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_5_3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD6); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM6 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_6_0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD7); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_6_1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD7); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_6_2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD7); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_6_3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD7); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SAM_SIO_USE_SERCOM7 == TRUE +OSAL_IRQ_HANDLER(SAM_SERCOM_7_0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD8); + OSAL_IRQ_EPILOGUE(); +} + +OSAL_IRQ_HANDLER(SAM_SERCOM_7_1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD8); + OSAL_IRQ_EPILOGUE(); +} + + +OSAL_IRQ_HANDLER(SAM_SERCOM_7_2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD8); + OSAL_IRQ_EPILOGUE(); +} + + +OSAL_IRQ_HANDLER(SAM_SERCOM_7_3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + sio_lld_serve_interrupt(&SIOD8); + OSAL_IRQ_EPILOGUE(); +} + +#endif + +/** + * @brief Low level SIO driver initialization. + * + * @notapi + */ +void sio_lld_init(void) +{ + +#if SAM_SIO_USE_SERCOM0 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD1); + MCLK_REGS->MCLK_APBAMASK |= MCLK_APBAMASK_SERCOM0_Msk; + SIOD1.usart = &SERCOM0_REGS->USART_INT; + SIOD1.clock = SAM_SERCOM0_GCLK_FREQ; +#endif +#if SAM_SIO_USE_SERCOM1 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD2); + MCLK_REGS->MCLK_APBAMASK |= MCLK_APBAMASK_SERCOM1_Msk; + SIOD2.usart = &SERCOM1_REGS->USART_INT; + SIOD2.clock = SAM_SERCOM1_GCLK_FREQ; +#endif +#if SAM_SIO_USE_SERCOM2 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD3); + MCLK_REGS->MCLK_APBBMASK |= MCLK_APBBMASK_SERCOM2_Msk; + SIOD3.usart = &SERCOM2_REGS->USART_INT; + SIOD3.clock = SAM_SERCOM2_GCLK_FREQ; +#endif +#if SAM_SIO_USE_SERCOM3 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD4); + MCLK_REGS->MCLK_APBBMASK |= MCLK_APBBMASK_SERCOM3_Msk; + SIOD4.usart = &SERCOM3_REGS->USART_INT; + SIOD4.clock = SAM_SERCOM3_GCLK_FREQ; +#endif +#if SAM_SIO_USE_SERCOM4 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD5); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM4_Msk; + SIOD5.usart = &SERCOM4_REGS->USART_INT; + SIOD5.clock = SAM_SERCOM4_GCLK_FREQ; +#endif +#if SAM_SIO_USE_SERCOM5 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD6); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM5_Msk; + SIOD6.usart = &SERCOM5_REGS->USART_INT; + SIOD6.clock = SAM_SERCOM5_GCLK_FREQ; +#endif + +#if SAM_SIO_USE_SERCOM6 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD7); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM6_Msk; + SIOD7.usart = &SERCOM6_REGS->USART_INT; + SIOD7.clock = SAM_SERCOM6_GCLK_FREQ; +#endif + +#if SAM_SIO_USE_SERCOM7 == TRUE + /* Driver initialization.*/ + sioObjectInit(&SIOD8); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM7_Msk; + SIOD8.usart = &SERCOM7_REGS->USART_INT; + SIOD8.clock = SAM_SERCOM7_GCLK_FREQ; +#endif +} + +/** + * @brief Configures and activates the SIO peripheral. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The operation status. + * + * @notapi + */ +msg_t sio_lld_start(SIODriver *siop) +{ + + if (siop->config == NULL) + { + osalDbgAssert(siop->config, "SERCOM requires configuration"); + } + if (siop->state == SIO_STOP) + { + /* Enables the peripheral.*/ +#if SAM_SIO_USE_SERCOM0 == TRUE + if (&SIOD1 == siop) + { + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM0_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM0_CORE_Val, 1); + usart_reset(&SIOD1); + nvicEnableVector(SERCOM0_0_IRQn, SAM_SERCOM0_IRQ_PRIORITY); + nvicEnableVector(SERCOM0_1_IRQn, SAM_SERCOM0_IRQ_PRIORITY); + nvicEnableVector(SERCOM0_2_IRQn, SAM_SERCOM0_IRQ_PRIORITY); + nvicEnableVector(SERCOM0_OTHER_IRQn, SAM_SERCOM0_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM1 == TRUE + if (&SIOD2 == siop) + { + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM1_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM1_CORE_Val, 1); + usart_reset(&SIOD2); + nvicEnableVector(SERCOM1_0_IRQn, SAM_SERCOM1_IRQ_PRIORITY); + nvicEnableVector(SERCOM1_1_IRQn, SAM_SERCOM1_IRQ_PRIORITY); + nvicEnableVector(SERCOM1_2_IRQn, SAM_SERCOM1_IRQ_PRIORITY); + nvicEnableVector(SERCOM1_OTHER_IRQn, SAM_SERCOM1_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM2 == TRUE + if (&SIOD3 == siop) + { + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM2_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM2_CORE_Val, 1); + usart_reset(&SIOD3); + nvicEnableVector(SERCOM2_0_IRQn, SAM_SERCOM2_IRQ_PRIORITY); + nvicEnableVector(SERCOM2_1_IRQn, SAM_SERCOM2_IRQ_PRIORITY); + nvicEnableVector(SERCOM2_2_IRQn, SAM_SERCOM2_IRQ_PRIORITY); + nvicEnableVector(SERCOM2_OTHER_IRQn, SAM_SERCOM2_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM3 == TRUE + if (&SIOD4 == siop) + { + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM3_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM3_CORE_Val, 1); + usart_reset(&SIOD4); + nvicEnableVector(SERCOM3_0_IRQn, SAM_SERCOM3_IRQ_PRIORITY); + nvicEnableVector(SERCOM3_1_IRQn, SAM_SERCOM3_IRQ_PRIORITY); + nvicEnableVector(SERCOM3_2_IRQn, SAM_SERCOM3_IRQ_PRIORITY); + nvicEnableVector(SERCOM3_OTHER_IRQn, SAM_SERCOM3_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM4 == TRUE + if (&SIOD5 == siop) + { + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM4_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM4_CORE_Val, 1); + usart_reset(&SIOD5); + nvicEnableVector(SERCOM4_0_IRQn, SAM_SERCOM4_IRQ_PRIORITY); + nvicEnableVector(SERCOM4_1_IRQn, SAM_SERCOM4_IRQ_PRIORITY); + nvicEnableVector(SERCOM4_2_IRQn, SAM_SERCOM4_IRQ_PRIORITY); + nvicEnableVector(SERCOM4_OTHER_IRQn, SAM_SERCOM4_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM5 == TRUE + if (&SIOD6 == siop) + { + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM5_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM5_CORE_Val, 1); + usart_reset(&SIOD6); + nvicEnableVector(SERCOM5_0_IRQn, SAM_SERCOM5_IRQ_PRIORITY); + nvicEnableVector(SERCOM5_1_IRQn, SAM_SERCOM5_IRQ_PRIORITY); + nvicEnableVector(SERCOM5_2_IRQn, SAM_SERCOM5_IRQ_PRIORITY); + nvicEnableVector(SERCOM5_OTHER_IRQn, SAM_SERCOM5_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM6 == TRUE + if (&SIOD7 == siop) + { + sam_gclk_mux(SAM_SERCOM6_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM6_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM6_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM6_CORE_Val, 1); + usart_reset(&SIOD7); + nvicEnableVector(SERCOM6_0_IRQn, SAM_SERCOM6_IRQ_PRIORITY); + nvicEnableVector(SERCOM6_1_IRQn, SAM_SERCOM6_IRQ_PRIORITY); + nvicEnableVector(SERCOM6_2_IRQn, SAM_SERCOM6_IRQ_PRIORITY); + nvicEnableVector(SERCOM6_OTHER_IRQn, SAM_SERCOM6_IRQ_PRIORITY); + } +#endif + +#if SAM_SIO_USE_SERCOM7 == TRUE + if (&SIOD8 == siop) + { + sam_gclk_mux(SAM_SERCOM7_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM7_CORE_Val, 0); + sam_gclk_mux(SAM_SERCOM7_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM7_CORE_Val, 1); + usart_reset(&SIOD8); + nvicEnableVector(SERCOM7_0_IRQn, SAM_SERCOM7_IRQ_PRIORITY); + nvicEnableVector(SERCOM7_1_IRQn, SAM_SERCOM7_IRQ_PRIORITY); + nvicEnableVector(SERCOM7_2_IRQn, SAM_SERCOM7_IRQ_PRIORITY); + nvicEnableVector(SERCOM7_OTHER_IRQn, SAM_SERCOM7_IRQ_PRIORITY); + } +#endif + } + /* Configures the peripheral.*/ + usart_init(siop); + return HAL_RET_SUCCESS; +} + +/** + * @brief Deactivates the SIO peripheral. + * + * @param[in] siop pointer to the @p SIODriver object + * + * @notapi + */ +void sio_lld_stop(SIODriver *siop) +{ + + if (siop->state == SIO_READY) + { + /* Resets the peripheral.*/ + siop->usart->SERCOM_INTENCLR = SERCOM_USART_INT_INTENCLR_Msk; + // disable sercom + siop->usart->SERCOM_CTRLA &= ~SERCOM_USART_INT_CTRLA_ENABLE_Msk; + while ((siop->usart->SERCOM_SYNCBUSY & SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk) != 0U) + ; + /* Disables the peripheral.*/ +#if SAM_SIO_USE_SERCOM0 == TRUE + if (&SIOD1 == siop) + { + usart_reset(&SIOD1); + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM0_CORE_Val, 0); + nvicDisableVector(SERCOM0_0_IRQn); + nvicDisableVector(SERCOM0_1_IRQn); + nvicDisableVector(SERCOM0_2_IRQn); + nvicDisableVector(SERCOM0_OTHER_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM1 == TRUE + if (&SIOD2 == siop) + { + usart_reset(&SIOD2); + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM1_CORE_Val, 0); + nvicDisableVector(SERCOM1_0_IRQn); + nvicDisableVector(SERCOM1_1_IRQn); + nvicDisableVector(SERCOM1_2_IRQn); + nvicDisableVector(SERCOM1_OTHER_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM2 == TRUE + if (&SIOD3 == siop) + { + usart_reset(&SIOD3); + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM2_CORE_Val, 0); + nvicDisableVector(SERCOM2_0_IRQn); + nvicDisableVector(SERCOM2_1_IRQn); + nvicDisableVector(SERCOM2_2_IRQn); + nvicDisableVector(SERCOM2_OTHER_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM3 == TRUE + if (&SIOD4 == siop) + { + usart_reset(&SIOD4); + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM3_CORE_Val, 0); + nvicDisableVector(SERCOM3_0_IRQn); + nvicDisableVector(SERCOM3_1_IRQn); + nvicDisableVector(SERCOM3_2_IRQn); + nvicDisableVector(SERCOM3_OTHER_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM4 == TRUE + if (&SIOD5 == siop) + { + usart_reset(&SIOD5); + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM4_CORE_Val, 0); + nvicDisableVector(SERCOM4_0_IRQn); + nvicDisableVector(SERCOM4_1_IRQn); + nvicDisableVector(SERCOM4_2_IRQn); + nvicDisableVector(SERCOM4_OTHER_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM5 == TRUE + if (&SIOD6 == siop) + { + usart_reset(&SIOD6); + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM5_CORE_Val, 0); + nvicDisableVector(SERCOM5_0_IRQn); + nvicDisableVector(SERCOM5_1_IRQn); + nvicDisableVector(SERCOM5_2_IRQn); + nvicDisableVector(SERCOM5_OTHER_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM6 == TRUE + if (&SIOD7 == siop) + { + usart_reset(&SIOD6); + sam_gclk_mux(SAM_SERCOM6_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM6_CORE_Val, 0); + nvicDisableVector(SERCOM6_0_IRQn); + nvicDisableVector(SERCOM6_1_IRQn); + nvicDisableVector(SERCOM6_2_IRQn); + nvicDisableVector(SERCOM6_OTHER_IRQn); + } +#endif + +#if SAM_SIO_USE_SERCOM7 == TRUE + if (&SIOD8 == siop) + { + usart_reset(&SIOD8); + sam_gclk_mux(SAM_SERCOM7_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM7_CORE_Val, 0); + nvicDisableVector(SERCOM7_0_IRQn); + nvicDisableVector(SERCOM7_1_IRQn); + nvicDisableVector(SERCOM7_2_IRQn); + nvicDisableVector(SERCOM7_OTHER_IRQn); + } +#endif + } +} \ No newline at end of file diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld.c b/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld.c deleted file mode 100644 index 69aae92aa4..0000000000 --- a/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld.c +++ /dev/null @@ -1,694 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_spi_v2_lld.c - * @brief PLATFORM SPI (v2) subsystem low level driver source. - * - * @addtogroup SPI_V2 - * @{ - */ - -#include "hal.h" -#include "sercom_clk.h" -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief SPI1 driver identifier. - */ -#if (SAM_SPI_USE_SERCOM0 == TRUE) || defined(__DOXYGEN__) -SPIDriver SPID1; -#endif - -/** - * @brief SPI2 driver identifier. - */ -#if (SAM_SPI_USE_SERCOM1 == TRUE) || defined(__DOXYGEN__) -SPIDriver SPID2; -#endif - -/** - * @brief SPI3 driver identifier. - */ -#if (SAM_SPI_USE_SERCOM2 == TRUE) || defined(__DOXYGEN__) -SPIDriver SPID3; -#endif - -/** - * @brief SPI4 driver identifier. - */ -#if (SAM_SPI_USE_SERCOM3 == TRUE) || defined(__DOXYGEN__) -SPIDriver SPID4; -#endif - -/** - * @brief SPI5 driver identifier. - */ -#if (SAM_SPI_USE_SERCOM4 == TRUE) || defined(__DOXYGEN__) -SPIDriver SPID5; -#endif - -/** - * @brief SPI6 driver identifier. - */ -#if (SAM_SPI_USE_SERCOM5 == TRUE) || defined(__DOXYGEN__) -SPIDriver SPID6; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ -static const uint16_t dummytx = 0xFFFFU; -static uint16_t dummyrx; -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ -static void spi_lld_disable(SPIDriver *spip) -{ - dmacChnlDisable(spip->dmaTxId); - spip->spi->SERCOM_CTRLA &= ~SERCOM_SPIM_CTRLA_ENABLE_Msk; - dmacChnlDisable(spip->dmaRxId); -} -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint8_t flag) -{ - if (flag & DMAC_CHINTFLAG_TERR_Msk) - { - /* Stopping DMAs.*/ - dmacChnlDisable(spip->dmaTxId); - dmacChnlDisable(spip->dmaRxId); - - /* Reporting the failure.*/ - __spi_isr_error_code(spip, HAL_RET_HW_FAILURE); - } - if (flag & DMAC_CHINTFLAG_TCMPL_Msk) - { - /* Stopping DMAs.*/ - dmacChnlDisable(spip->dmaTxId); - dmacChnlDisable(spip->dmaRxId); - - /* Operation finished interrupt.*/ - __spi_isr_complete_code(spip); - } -} - -static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint8_t flag) -{ - if (flag & DMAC_CHINTFLAG_TERR_Msk) - { - /* Stopping DMAs.*/ - dmacChnlDisable(spip->dmaTxId); - dmacChnlDisable(spip->dmaRxId); - - /* Reporting the failure.*/ - __spi_isr_error_code(spip, HAL_RET_HW_FAILURE); - } -} - -/** - * @brief DMA streams allocation. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] rxstream stream to be allocated for RX - * @param[in] txstream stream to be allocated for TX - * @param[in] priority streams IRQ priority - * @return The operation status. - */ -static msg_t spi_lld_get_dma(SPIDriver *spip, uint8_t rxstream, - uint8_t txstream, uint8_t priority) -{ - int8_t dmacId = dmacChnlAllocI(rxstream, priority, - (sam_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - if (dmacId < 0) - { - return HAL_RET_NO_RESOURCE; - } - spip->dmaRxId = (uint8_t)dmacId; - - dmacId = dmacChnlAllocI(txstream, priority, - (sam_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - if (dmacId < 0) - { - dmacChnlFreeI(spip->dmaRxId); - return HAL_RET_NO_RESOURCE; - } - spip->dmaTxId = (uint8_t)dmacId; - - return HAL_RET_SUCCESS; -} -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - * - * @notapi - */ -void spi_lld_init(void) -{ -#if SAM_SPI_USE_SERCOM0 == TRUE - /* Driver initialization.*/ - spiObjectInit(&SPID1); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM0_Msk; - SPID1.spi = &SERCOM0_REGS->SPIM; - SPID1.clock = SAM_SERCOM0_GCLK_SRC_FREQ; -#endif -#if SAM_SPI_USE_SERCOM1 == TRUE - /* Driver initialization.*/ - spiObjectInit(&SPID2); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM1_Msk; - SPID2.spi = &SERCOM1_REGS->SPIM; - SPID2.clock = SAM_SERCOM1_GCLK_SRC_FREQ; -#endif -#if SAM_SPI_USE_SERCOM2 == TRUE - /* Driver initialization.*/ - spiObjectInit(&SPID3); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM2_Msk; - SPID3.spi = &SERCOM2_REGS->SPIM; - SPID3.clock = SAM_SERCOM2_GCLK_SRC_FREQ; -#endif -#if SAM_SPI_USE_SERCOM3 == TRUE - /* Driver initialization.*/ - spiObjectInit(&SPID4); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM3_Msk; - SPID4.spi = &SERCOM3_REGS->SPIM; - SPID4.clock = SAM_SERCOM3_GCLK_SRC_FREQ; -#endif -#if SAM_SPI_USE_SERCOM4 == TRUE - /* Driver initialization.*/ - spiObjectInit(&SPID5); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM4_Msk; - SPID5.spi = &SERCOM4_REGS->SPIM; - SPID5.clock = SAM_SERCOM4_GCLK_SRC_FREQ; -#endif -#if SAM_SPI_USE_SERCOM5 == TRUE - /* Driver initialization.*/ - spiObjectInit(&SPID6); - PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM5_Msk; - SPID6.spi = &SERCOM5_REGS->SPIM; - SPID6.clock = SAM_SERCOM5_GCLK_SRC_FREQ; -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * @return The operation status. - * - * @notapi - */ -msg_t spi_lld_start(SPIDriver *spip) -{ - - if (spip->state == SPI_STOP) - { - - /* Enables the peripheral.*/ - if (false) - { - } - -#if SAM_SPI_USE_SERCOM0 == TRUE - else if (&SPID1 == spip) - { - sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, 1); - msg_t msg = spi_lld_get_dma(spip, - SAM_SPI0_DMARX_CHANNEL, - SAM_SPI0_DMATX_CHANNEL, - SAM_SPI0_DMA_PRIO); - if (msg != HAL_RET_SUCCESS) - { - return msg; - } - dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM0_TX); - dmacChnlSetTrigAct(spip->dmaTxId, BEAT); - dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM0_RX); - dmacChnlSetTrigAct(spip->dmaRxId, BEAT); - } -#endif - -#if SAM_SPI_USE_SERCOM1 == TRUE - else if (&SPID2 == spip) - { - sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, 1); - msg_t msg = spi_lld_get_dma(spip, - SAM_SPI1_DMARX_CHANNEL, - SAM_SPI1_DMATX_CHANNEL, - SAM_SPI1_DMA_PRIO); - if (msg != HAL_RET_SUCCESS) - { - return msg; - } - dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM1_TX); - dmacChnlSetTrigAct(spip->dmaTxId, BEAT); - dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM1_RX); - dmacChnlSetTrigAct(spip->dmaRxId, BEAT); - } -#endif - -#if SAM_SPI_USE_SERCOM2 == TRUE - else if (&SPID3 == spip) - { - sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, 1); - msg_t msg = spi_lld_get_dma(spip, - SAM_SPI2_DMARX_CHANNEL, - SAM_SPI2_DMATX_CHANNEL, - SAM_SPI2_DMA_PRIO); - if (msg != HAL_RET_SUCCESS) - { - return msg; - } - dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM2_TX); - dmacChnlSetTrigAct(spip->dmaTxId, BEAT); - dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM2_RX); - dmacChnlSetTrigAct(spip->dmaRxId, BEAT); - } -#endif - -#if SAM_SPI_USE_SERCOM3 == TRUE - else if (&SPID4 == spip) - { - sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, 1); - msg_t msg = spi_lld_get_dma(spip, - SAM_SPI3_DMARX_CHANNEL, - SAM_SPI3_DMATX_CHANNEL, - SAM_SPI3_DMA_PRIO); - if (msg != HAL_RET_SUCCESS) - { - return msg; - } - dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM3_TX); - dmacChnlSetTrigAct(spip->dmaTxId, BEAT); - dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM3_RX); - dmacChnlSetTrigAct(spip->dmaRxId, BEAT); - } -#endif - -#if SAM_SPI_USE_SERCOM4 == TRUE - else if (&SPID5 == spip) - { - sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, 1); - msg_t msg = spi_lld_get_dma(spip, - SAM_SPI4_DMARX_CHANNEL, - SAM_SPI4_DMATX_CHANNEL, - SAM_SPI4_DMA_PRIO); - if (msg != HAL_RET_SUCCESS) - { - return msg; - } - dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM4_TX); - dmacChnlSetTrigAct(spip->dmaTxId, BEAT); - dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM4_RX); - dmacChnlSetTrigAct(spip->dmaRxId, BEAT); - } -#endif - -#if SAM_SPI_USE_SERCOM5 == TRUE - else if (&SPID6 == spip) - { - sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, 0); - sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, 1); - msg_t msg = spi_lld_get_dma(spip, - SAM_SPI5_DMARX_CHANNEL, - SAM_SPI5_DMATX_CHANNEL, - SAM_SPI5_DMA_PRIO); - if (msg != HAL_RET_SUCCESS) - { - return msg; - } - dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM5_TX); - dmacChnlSetTrigAct(spip->dmaTxId, BEAT); - dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM5_RX); - dmacChnlSetTrigAct(spip->dmaRxId, BEAT); - } -#endif - - else - { - osalDbgAssert(false, "invalid SPI instance"); - } - } - else - { - spi_lld_disable(spip); - } - spip->spi->SERCOM_CTRLA = SERCOM_SPIM_CTRLA_SWRST_Msk; - while (spip->spi->SERCOM_SYNCBUSY != 0) - ; - uint32_t baud_val = spip->clock / (2U * spip->config->freq) - 1; - if (baud_val > 255) - { - baud_val = 255; - } - spip->spi->SERCOM_BAUD = baud_val; - spip->spi->SERCOM_CTRLB = (spip->config->ctrlb & ~(SERCOM_SPIM_CTRLB_MSSEN_Msk | SERCOM_SPIM_CTRLB_AMODE_Msk)) | SERCOM_SPIM_CTRLB_RXEN_Msk; - while (spip->spi->SERCOM_SYNCBUSY != 0) - ; - spip->spi->SERCOM_CTRLA = (spip->config->ctrla & ~(SERCOM_SPIM_CTRLA_SWRST_Msk | SERCOM_SPIM_CTRLA_MODE_Msk)) | - (spip->config->slave ? SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE : SERCOM_SPIM_CTRLA_MODE_SPI_MASTER) | - SERCOM_SPIM_CTRLA_ENABLE_Msk; - while (spip->spi->SERCOM_SYNCBUSY != 0) - ; - return HAL_RET_SUCCESS; -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_stop(SPIDriver *spip) -{ - - if (spip->state == SPI_READY) - { - uint8_t id = 0; - uint8_t id_val = 0; - /* Disables the peripheral.*/ - if (false) - { - } -#if SAM_SPI_USE_SERCOM0 == TRUE - else if (&SPID1 == spip) - { - id = SAM_SERCOM0_GCLK_SRC_ID; - id_val = GCLK_CLKCTRL_ID_SERCOM0_CORE_Val; - } -#endif -#if SAM_SPI_USE_SERCOM1 == TRUE - else if (&SPID2 == spip) - { - id = SAM_SERCOM1_GCLK_SRC_ID; - id_val = GCLK_CLKCTRL_ID_SERCOM1_CORE_Val; - } -#endif -#if SAM_SPI_USE_SERCOM2 == TRUE - else if (&SPID3 == spip) - { - id = SAM_SERCOM2_GCLK_SRC_ID; - id_val = GCLK_CLKCTRL_ID_SERCOM2_CORE_Val; - } -#endif -#if SAM_SPI_USE_SERCOM3 == TRUE - else if (&SPID4 == spip) - { - id = SAM_SERCOM3_GCLK_SRC_ID; - id_val = GCLK_CLKCTRL_ID_SERCOM3_CORE_Val; - } -#endif -#if SAM_SPI_USE_SERCOM4 == TRUE - else if (&SPID5 == spip) - { - id = SAM_SERCOM4_GCLK_SRC_ID; - id_val = GCLK_CLKCTRL_ID_SERCOM4_CORE_Val; - } -#endif -#if SAM_SPI_USE_SERCOM5 == TRUE - else if (&SPID6 == spip) - { - id = SAM_SERCOM5_GCLK_SRC_ID; - id_val = GCLK_CLKCTRL_ID_SERCOM5_CORE_Val; - } -#endif - else - { - osalDbgAssert(false, "invalid SPI instance"); - } - spi_lld_disable(spip); - dmacChnlFreeI(spip->dmaRxId); - dmacChnlFreeI(spip->dmaTxId); - sam_gclk_mux(id, id_val, 0); - } -} - -#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_select(SPIDriver *spip) -{ - - (void)spip; -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_unselect(SPIDriver *spip) -{ - - (void)spip; -} -#endif - -/** - * @brief Ignores data on the SPI bus. - * @details This synchronous function performs the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @pre In order to use this function the option @p SPI_USE_SYNCHRONIZATION - * must be enabled. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * @return The operation status. - * - * @notapi - */ -msg_t spi_lld_ignore(SPIDriver *spip, size_t n) -{ - if ((spip->config->ctrlb & SERCOM_SPIM_CTRLB_CHSIZE_Msk) == SERCOM_SPIM_CTRLB_CHSIZE_9_BIT) - { - dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_VALID_Msk); - dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_VALID_Msk); - } - else - { - dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_VALID_Msk); - dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_VALID_Msk); - } - dmacChnlSetDir(spip->dmaTxId, (uint32_t)&spip->spi->SERCOM_DATA, (uint32_t)&spip->txsource, n); - dmacChnlSetDir(spip->dmaRxId, (uint32_t)&spip->rxsink, (uint32_t)&spip->spi->SERCOM_DATA, n); - dmacChnlEnableIRQn(spip->dmaTxId); - dmacChnlEnableIRQn(spip->dmaRxId); - dmacChnlEnable(spip->dmaRxId); - dmacChnlEnable(spip->dmaTxId); - return HAL_RET_SUCCESS; -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * @return The operation status. - * - * @notapi - */ -msg_t spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) -{ - if (spip->config->ctrlb & SERCOM_SPIM_CTRLB_CHSIZE_Msk == SERCOM_SPIM_CTRLB_CHSIZE_9_BIT) - { - dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_SRCINC_Msk | DMAC_BTCTRL_VALID_Msk); - dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_DSTINC_Msk | DMAC_BTCTRL_VALID_Msk); - } - else - { - dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_SRCINC_Msk | DMAC_BTCTRL_VALID_Msk); - dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_DSTINC_Msk | DMAC_BTCTRL_VALID_Msk); - } - dmacChnlSetDir(spip->dmaTxId, (uint32_t)&spip->spi->SERCOM_DATA, (uint32_t)txbuf, n); - dmacChnlSetDir(spip->dmaRxId, (uint32_t)rxbuf, (uint32_t)&spip->spi->SERCOM_DATA, n); - dmacChnlEnableIRQn(spip->dmaTxId); - dmacChnlEnableIRQn(spip->dmaRxId); - dmacChnlEnable(spip->dmaRxId); - dmacChnlEnable(spip->dmaTxId); - return HAL_RET_SUCCESS; -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * @return The operation status. - * - * @notapi - */ -msg_t spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) -{ - if (spip->config->ctrlb & SERCOM_SPIM_CTRLB_CHSIZE_Msk == SERCOM_SPIM_CTRLB_CHSIZE_9_BIT) - { - dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_SRCINC_Msk | DMAC_BTCTRL_VALID_Msk); - dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_VALID_Msk); - } - else - { - dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_SRCINC_Msk | DMAC_BTCTRL_VALID_Msk); - dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_VALID_Msk); - } - dmacChnlSetDir(spip->dmaTxId, (uint32_t)&spip->spi->SERCOM_DATA, (uint32_t)txbuf, n); - dmacChnlSetDir(spip->dmaRxId, (uint32_t)&spip->rxsink, (uint32_t)&spip->spi->SERCOM_DATA, n); - dmacChnlEnableIRQn(spip->dmaTxId); - dmacChnlEnableIRQn(spip->dmaRxId); - dmacChnlEnable(spip->dmaRxId); - dmacChnlEnable(spip->dmaTxId); - return HAL_RET_SUCCESS; -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * @return The operation status. - * - * @notapi - */ -msg_t spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) -{ - if (spip->config->ctrlb & SERCOM_SPIM_CTRLB_CHSIZE_Msk == SERCOM_SPIM_CTRLB_CHSIZE_9_BIT) - { - dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_VALID_Msk); - dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_DSTINC_Msk | DMAC_BTCTRL_VALID_Msk); - } - else - { - dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_VALID_Msk); - dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_DSTINC_Msk | DMAC_BTCTRL_VALID_Msk); - } - dmacChnlSetDir(spip->dmaTxId, (uint32_t)&spip->spi->SERCOM_DATA, (uint32_t)&spip->txsource, n); - dmacChnlSetDir(spip->dmaRxId, (uint32_t)rxbuf, (uint32_t)&spip->spi->SERCOM_DATA, n); - dmacChnlEnableIRQn(spip->dmaTxId); - dmacChnlEnableIRQn(spip->dmaRxId); - dmacChnlEnable(spip->dmaRxId); - dmacChnlEnable(spip->dmaTxId); - return HAL_RET_SUCCESS; -} - -/** - * @brief Aborts the ongoing SPI operation, if any. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[out] sizep pointer to the counter of frames not yet transferred - * or @p NULL - * @return The operation status. - * - * @notapi - */ -msg_t spi_lld_stop_transfer(SPIDriver *spip, size_t *sizep) -{ - - dmacChnlDisable(spip->dmaTxId); - while (!(spip->spi->SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk)) - ; - /* Size of unprocessed data.*/ - if (sizep != NULL) - { - *sizep = dmacChnlGetTransferred(spip->dmaRxId); - } - dmacChnlDisable(spip->dmaRxId); - return HAL_RET_SUCCESS; -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) -{ - if (spip->config->ctrlb & SERCOM_SPIM_CTRLB_CHSIZE_Msk == SERCOM_SPIM_CTRLB_CHSIZE_9_BIT) - { - volatile uint16_t *dr16p = (volatile uint16_t *)&spip->spi->SERCOM_DATA; - *dr16p = (uint16_t)frame; - while ((spip->spi->SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == 0U) - { - /* Waiting frame transfer.*/ - } - frame = (uint16_t)*dr16p; - } - else - { - volatile uint8_t *dr8p = (volatile uint8_t *)&spip->spi->SERCOM_DATA; - *dr8p = (uint8_t)frame; - while ((spip->spi->SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == 0U) - { - /* Waiting frame transfer.*/ - } - frame = (uint16_t)*dr8p; - } - return frame; -} - -#endif /* HAL_USE_SPI */ - -/** @} */ diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom.c b/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom.c new file mode 100644 index 0000000000..703c9e73e3 --- /dev/null +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom.c @@ -0,0 +1,383 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_spi_v2_lld.c + * @brief PLATFORM SPI (v2) subsystem low level driver source. + * + * @addtogroup SPI_V2 + * @{ + */ + +#include "hal.h" +#include "sercom_clk.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ +#define SERCOM_SPIM_CTRLA_FORBIDDEN (SERCOM_SPIM_CTRLA_SWRST_Msk | \ + SERCOM_SPIM_CTRLA_MODE_Msk | \ + SERCOM_SPIM_CTRLA_DIPO_Msk | \ + SERCOM_SPIM_CTRLA_DOPO_Msk) +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ +static void sercom_spi_lld_disable(SPIDriver* spip) { + dmacChnlDisable(spip->dmaTxId); + spip->spi->SERCOM_CTRLA &= ~SERCOM_SPIM_CTRLA_ENABLE_Msk; + dmacChnlDisable(spip->dmaRxId); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +static void sercom_spi_lld_serve_rx_interrupt(SPIDriver* spip, uint8_t flag) { + if (flag & DMAC_CHINTFLAG_TERR_Msk) { + /* Stopping DMAs.*/ + dmacChnlDisable(spip->dmaTxId); + dmacChnlDisable(spip->dmaRxId); + + /* Reporting the failure.*/ + __spi_isr_error_code(spip, HAL_RET_HW_FAILURE); + } + if (flag & DMAC_CHINTFLAG_TCMPL_Msk) { + /* Stopping DMAs.*/ + dmacChnlDisable(spip->dmaTxId); + dmacChnlDisable(spip->dmaRxId); + + /* Operation finished interrupt.*/ + __spi_isr_complete_code(spip); + } +} + +static void sercom_spi_lld_serve_tx_interrupt(SPIDriver* spip, uint8_t flag) { + if (flag & DMAC_CHINTFLAG_TERR_Msk) { + /* Stopping DMAs.*/ + dmacChnlDisable(spip->dmaTxId); + dmacChnlDisable(spip->dmaRxId); + + /* Reporting the failure.*/ + __spi_isr_error_code(spip, HAL_RET_HW_FAILURE); + } +} + +/** + * @brief DMA streams allocation. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] rxstream stream to be allocated for RX + * @param[in] txstream stream to be allocated for TX + * @param[in] priority streams IRQ priority + * @return The operation status. + */ +static msg_t sercom_spi_lld_get_dma(SPIDriver* spip, uint8_t rxstream, + uint8_t txstream, uint8_t priority) { + int8_t dmacId = + dmacChnlAllocI(rxstream, priority, + (sam_dmaisr_t)sercom_spi_lld_serve_rx_interrupt, (void*)spip); + if (dmacId < 0) { + return HAL_RET_NO_RESOURCE; + } + spip->dmaRxId = (uint8_t)dmacId; + + dmacId = + dmacChnlAllocI(txstream, priority, + (sam_dmaisr_t)sercom_spi_lld_serve_tx_interrupt, (void*)spip); + if (dmacId < 0) { + dmacChnlFreeI(spip->dmaRxId); + return HAL_RET_NO_RESOURCE; + } + spip->dmaTxId = (uint8_t)dmacId; + + return HAL_RET_SUCCESS; +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +#if defined(SAMD21_MCUCONF) +#include "hal_spi_v2_lld_sercom_samd2x.inc" +#elif defined(SAME54_MCUCONF) +#include "hal_spi_v2_lld_sercom_same5x.inc" +#endif + + + +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void sercom_spi_lld_select(SPIDriver* spip) { + + (void)spip; +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void sercom_spi_lld_unselect(SPIDriver* spip) { + + (void)spip; +} +#endif + +/** + * @brief Ignores data on the SPI bus. + * @details This synchronous function performs the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @pre In order to use this function the option @p SPI_USE_SYNCHRONIZATION + * must be enabled. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * @return The operation status. + * + * @notapi + */ +msg_t sercom_spi_lld_ignore(SPIDriver* spip, size_t n) { + if ((spip->config->sercom_cfg.ctrlb & SERCOM_SPIM_CTRLB_CHSIZE_Msk) == + SERCOM_SPIM_CTRLB_CHSIZE_9_BIT) { + dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BLOCKACT_INT | + DMAC_BTCTRL_BEATSIZE_HWORD | + DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BLOCKACT_INT | + DMAC_BTCTRL_BEATSIZE_HWORD | + DMAC_BTCTRL_VALID_Msk); + } else { + dmacChnlSetBtCtrl(spip->dmaTxId, + DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, + DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_VALID_Msk); + } + dmacChnlSetDir(spip->dmaTxId, (uint32_t)&spip->spi->SERCOM_DATA, + (uint32_t)&spip->txsource, n); + dmacChnlSetDir(spip->dmaRxId, (uint32_t)&spip->rxsink, + (uint32_t)&spip->spi->SERCOM_DATA, n); + dmacChnlEnableIRQn(spip->dmaTxId); + dmacChnlEnableIRQn(spip->dmaRxId); + dmacChnlEnable(spip->dmaRxId); + dmacChnlEnable(spip->dmaTxId); + return HAL_RET_SUCCESS; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * @return The operation status. + * + * @notapi + */ +msg_t sercom_spi_lld_exchange(SPIDriver* spip, size_t n, const void* txbuf, + void* rxbuf) { + if ((spip->config->sercom_cfg.ctrlb & + SERCOM_SPIM_CTRLB_CHSIZE_Msk) == SERCOM_SPIM_CTRLB_CHSIZE_9_BIT) { + dmacChnlSetBtCtrl(spip->dmaTxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | + DMAC_BTCTRL_SRCINC_Msk | DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | + DMAC_BTCTRL_DSTINC_Msk | DMAC_BTCTRL_VALID_Msk); + } else { + dmacChnlSetBtCtrl(spip->dmaTxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_SRCINC_Msk | DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_DSTINC_Msk | DMAC_BTCTRL_VALID_Msk); + } + dmacChnlSetDir(spip->dmaTxId, (uint32_t)&spip->spi->SERCOM_DATA, + (uint32_t)txbuf, n); + dmacChnlSetDir(spip->dmaRxId, (uint32_t)rxbuf, + (uint32_t)&spip->spi->SERCOM_DATA, n); + dmacChnlEnableIRQn(spip->dmaTxId); + dmacChnlEnableIRQn(spip->dmaRxId); + dmacChnlEnable(spip->dmaRxId); + dmacChnlEnable(spip->dmaTxId); + return HAL_RET_SUCCESS; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * @return The operation status. + * + * @notapi + */ +msg_t sercom_spi_lld_send(SPIDriver* spip, size_t n, const void* txbuf) { + if ((spip->config->sercom_cfg.ctrlb & + SERCOM_SPIM_CTRLB_CHSIZE_Msk) == SERCOM_SPIM_CTRLB_CHSIZE_9_BIT) { + dmacChnlSetBtCtrl(spip->dmaTxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | + DMAC_BTCTRL_SRCINC_Msk | DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BLOCKACT_INT | + DMAC_BTCTRL_BEATSIZE_HWORD | + DMAC_BTCTRL_VALID_Msk); + } else { + dmacChnlSetBtCtrl(spip->dmaTxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_SRCINC_Msk | DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BLOCKACT_INT | + DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_VALID_Msk); + } + dmacChnlSetDir(spip->dmaTxId, (uint32_t)&spip->spi->SERCOM_DATA, + (uint32_t)txbuf, n); + dmacChnlSetDir(spip->dmaRxId, (uint32_t)&spip->rxsink, + (uint32_t)&spip->spi->SERCOM_DATA, n); + dmacChnlEnableIRQn(spip->dmaTxId); + dmacChnlEnableIRQn(spip->dmaRxId); + dmacChnlEnable(spip->dmaRxId); + dmacChnlEnable(spip->dmaTxId); + return HAL_RET_SUCCESS; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * @return The operation status. + * + * @notapi + */ +msg_t sercom_spi_lld_receive(SPIDriver* spip, size_t n, void* rxbuf) { + if ((spip->config->sercom_cfg.ctrlb & + SERCOM_SPIM_CTRLB_CHSIZE_Msk) == SERCOM_SPIM_CTRLB_CHSIZE_9_BIT) { + dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BLOCKACT_INT | + DMAC_BTCTRL_BEATSIZE_HWORD | + DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_HWORD | + DMAC_BTCTRL_DSTINC_Msk | DMAC_BTCTRL_VALID_Msk); + } else { + dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BLOCKACT_INT | + DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_DSTINC_Msk | DMAC_BTCTRL_VALID_Msk); + } + dmacChnlSetDir(spip->dmaTxId, (uint32_t)&spip->spi->SERCOM_DATA, + (uint32_t)&spip->txsource, n); + dmacChnlSetDir(spip->dmaRxId, (uint32_t)rxbuf, + (uint32_t)&spip->spi->SERCOM_DATA, n); + dmacChnlEnableIRQn(spip->dmaTxId); + dmacChnlEnableIRQn(spip->dmaRxId); + dmacChnlEnable(spip->dmaRxId); + dmacChnlEnable(spip->dmaTxId); + return HAL_RET_SUCCESS; +} + +/** + * @brief Aborts the ongoing SPI operation, if any. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[out] sizep pointer to the counter of frames not yet transferred + * or @p NULL + * @return The operation status. + * + * @notapi + */ +msg_t sercom_spi_lld_stop_transfer(SPIDriver* spip, size_t* sizep) { + + dmacChnlDisable(spip->dmaTxId); + sercom_spim_registers_t *spid = spip->spi; + while (!(spid->SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_TXC_Msk)) + ; + /* Size of unprocessed data.*/ + if (sizep != NULL) { + *sizep = dmacChnlGetTransferred(spip->dmaRxId); + } + dmacChnlDisable(spip->dmaRxId); + return HAL_RET_SUCCESS; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t sercom_spi_lld_polled_exchange(SPIDriver* spip, uint16_t frame) { + if ((spip->config->sercom_cfg.ctrlb & + SERCOM_SPIM_CTRLB_CHSIZE_Msk) == SERCOM_SPIM_CTRLB_CHSIZE_9_BIT) { + volatile uint16_t* dr16p = (volatile uint16_t*)&spip->spi->SERCOM_DATA; + *dr16p = (uint16_t)frame; + while ((spip->spi->SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == 0U) { + /* Waiting frame transfer.*/ + } + frame = (uint16_t)*dr16p; + } else { + volatile uint8_t* dr8p = (volatile uint8_t*)&spip->spi->SERCOM_DATA; + *dr8p = (uint8_t)frame; + while ((spip->spi->SERCOM_INTFLAG & SERCOM_SPIM_INTFLAG_RXC_Msk) == 0U) { + /* Waiting frame transfer.*/ + } + frame = (uint16_t)*dr8p; + } + return frame; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld.h b/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom.h similarity index 77% rename from os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld.h rename to os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom.h index ddf95ea6fb..a0722b8107 100644 --- a/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld.h +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom.h @@ -22,10 +22,10 @@ * @{ */ -#ifndef HAL_SPI_V2_LLD_H -#define HAL_SPI_V2_LLD_H +#ifndef HAL_SPI_V2_LLD_SERCOM_H +#define HAL_SPI_V2_LLD_SERCOM_H -#if HAL_USE_SPI || defined(__DOXYGEN__) +#if HAL_USE_SPI == TRUE || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -112,6 +112,30 @@ #if !defined(SAM_SPI5_DMA_PRIO) #define SAM_SPI5_DMA_PRIO 1 #endif + +#if !defined(SAM_SPI6_DMATX_CHANNEL) +#define SAM_SPI6_DMATX_CHANNEL SAM_DMAC_NUM_MAX +#endif + +#if !defined(SAM_SPI6_DMARX_CHANNEL) +#define SAM_SPI6_DMARX_CHANNEL SAM_DMAC_NUM_MAX +#endif + +#if !defined(SAM_SPI6_DMA_PRIO) +#define SAM_SPI6_DMA_PRIO 1 +#endif + +#if !defined(SAM_SPI7_DMATX_CHANNEL) +#define SAM_SPI7_DMATX_CHANNEL SAM_DMAC_NUM_MAX +#endif + +#if !defined(SAM_SPI7_DMARX_CHANNEL) +#define SAM_SPI7_DMARX_CHANNEL SAM_DMAC_NUM_MAX +#endif + +#if !defined(SAM_SPI7_DMA_PRIO) +#define SAM_SPI7_DMA_PRIO 1 +#endif /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -180,7 +204,7 @@ * */ #if !defined(SAM_DMAC_REQUIRED) -#define SAM_DMAC_REQUIRED +#define SAM_DMAC_REQUIRED TRUE #endif /** @} */ @@ -225,6 +249,17 @@ #endif #endif +#if SAM_SPI_USE_SERCOM6 == TRUE +#if SAM_SIO_USE_SERCOM6 == TRUE || SAM_I2C_USE_SERCOM6 == TRUE +#error "SERCOM6: Can only configured as one function only" +#endif +#endif + +#if SAM_SPI_USE_SERCOM7 == TRUE +#if SAM_SIO_USE_SERCOM7 == TRUE || SAM_I2C_USE_SERCOM7 == TRUE +#error "SERCOM7: Can only configured as one function only" +#endif +#endif /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -233,25 +268,6 @@ /* Driver macros. */ /*===========================================================================*/ -/** - * @brief Low level fields of the SPI driver structure. - */ -#define spi_lld_driver_fields \ - sercom_spim_registers_t *spi; \ - uint32_t clock; \ - uint8_t dmaTxId; \ - uint8_t dmaRxId; \ - uint32_t rxsink; \ - uint32_t txsource; - -/** - * @brief Low level fields of the SPI configuration structure. - */ -#define spi_lld_config_fields \ - uint32_t ctrla; \ - uint32_t ctrlb; \ - uint32_t freq; - /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ @@ -298,24 +314,48 @@ extern SPIDriver SPID5; extern SPIDriver SPID6; #endif +/** + * @brief SPI7 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM6 == TRUE) || defined(__DOXYGEN__) +extern SPIDriver SPID7; +#endif + +/** + * @brief SPI8 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM7 == TRUE) || defined(__DOXYGEN__) +extern SPIDriver SPID8; +#endif + +typedef struct { + /* CTRLA register, */ + uint32_t ctrla; + /* CTRLB register, MSSEN is disabled and AMODE is Masked*/ + uint32_t ctrlb; + uint32_t freq; + /* DIPO and DOPO from CTRLA refer to the SPI CTRLA Table */ + uint8_t dipo; + uint8_t dopo; +} sercom_spi_config_t; + #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif - void spi_lld_init(void); - msg_t spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); +void sercom_spi_lld_init(void); +msg_t sercom_spi_lld_start(SPIDriver* spip); +void sercom_spi_lld_stop(SPIDriver* spip); #if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); -#endif - msg_t spi_lld_ignore(SPIDriver *spip, size_t n); - msg_t spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - msg_t spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - msg_t spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); - msg_t spi_lld_stop_transfer(SPIDriver *spip, size_t *sizep); - uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +void sercom_spi_lld_select(SPIDriver* spip); +void sercom_spi_lld_unselect(SPIDriver* spip); +#endif +msg_t sercom_spi_lld_ignore(SPIDriver* spip, size_t n); +msg_t sercom_spi_lld_exchange(SPIDriver* spip, size_t n, const void* txbuf, + void* rxbuf); +msg_t sercom_spi_lld_send(SPIDriver* spip, size_t n, const void* txbuf); +msg_t sercom_spi_lld_receive(SPIDriver* spip, size_t n, void* rxbuf); +msg_t sercom_spi_lld_stop_transfer(SPIDriver* spip, size_t* sizep); +uint16_t sercom_spi_lld_polled_exchange(SPIDriver* spip, uint16_t frame); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom_samd2x.inc b/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom_samd2x.inc new file mode 100644 index 0000000000..abea71f4d4 --- /dev/null +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom_samd2x.inc @@ -0,0 +1,316 @@ + +/** + * @brief SPI1 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM0 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** + * @brief SPI2 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM1 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/** + * @brief SPI3 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM2 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID3; +#endif + +/** + * @brief SPI4 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM3 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID4; +#endif + +/** + * @brief SPI5 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM4 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID5; +#endif + +/** + * @brief SPI6 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM5 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID6; +#endif + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { +#if SAM_SPI_USE_SERCOM0 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID1); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM0_Msk; + SPID1.spi = &SERCOM0_REGS->SPIM; + SPID1.clock = SAM_SERCOM0_GCLK_FREQ; + SPID1.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM1 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID2); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM1_Msk; + SPID2.spi = &SERCOM1_REGS->SPIM; + SPID2.clock = SAM_SERCOM1_GCLK_FREQ; + SPID2.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM2 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID3); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM2_Msk; + SPID3.spi = &SERCOM2_REGS->SPIM; + SPID3.clock = SAM_SERCOM2_GCLK_FREQ; + SPID3.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM3 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID4); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM3_Msk; + SPID4.spi = &SERCOM3_REGS->SPIM; + SPID4.clock = SAM_SERCOM3_GCLK_FREQ; + SPID4.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM4 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID5); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM4_Msk; + SPID5.spi = &SERCOM4_REGS->SPIM; + SPID5.clock = SAM_SERCOM4_GCLK_FREQ; + SPID5.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM5 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID6); + PM_REGS->PM_APBCMASK |= PM_APBCMASK_SERCOM5_Msk; + SPID6.spi = &SERCOM5_REGS->SPIM; + SPID6.clock = SAM_SERCOM5_GCLK_FREQ; + SPID6.is_qspi = false; +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * @return The operation status. + * + * @notapi + */ +msg_t sercom_spi_lld_start(SPIDriver* spip) { + + if (spip->state == SPI_STOP) { + + /* Enables the peripheral.*/ + if (false) { + } + +#if SAM_SPI_USE_SERCOM0 == TRUE + else if (&SPID1 == spip) { + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM0_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI0_DMARX_CHANNEL, + SAM_SPI0_DMATX_CHANNEL, SAM_SPI0_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM0_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BEAT); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM0_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BEAT); + } +#endif + +#if SAM_SPI_USE_SERCOM1 == TRUE + else if (&SPID2 == spip) { + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM1_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI1_DMARX_CHANNEL, + SAM_SPI1_DMATX_CHANNEL, SAM_SPI1_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM1_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BEAT); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM1_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BEAT); + } +#endif + +#if SAM_SPI_USE_SERCOM2 == TRUE + else if (&SPID3 == spip) { + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM2_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI2_DMARX_CHANNEL, + SAM_SPI2_DMATX_CHANNEL, SAM_SPI2_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM2_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BEAT); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM2_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BEAT); + } +#endif + +#if SAM_SPI_USE_SERCOM3 == TRUE + else if (&SPID4 == spip) { + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM3_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI3_DMARX_CHANNEL, + SAM_SPI3_DMATX_CHANNEL, SAM_SPI3_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM3_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BEAT); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM3_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BEAT); + } +#endif + +#if SAM_SPI_USE_SERCOM4 == TRUE + else if (&SPID5 == spip) { + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM4_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI4_DMARX_CHANNEL, + SAM_SPI4_DMATX_CHANNEL, SAM_SPI4_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM4_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BEAT); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM4_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BEAT); + } +#endif + +#if SAM_SPI_USE_SERCOM5 == TRUE + else if (&SPID6 == spip) { + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_CLKCTRL_ID_SERCOM5_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI5_DMARX_CHANNEL, + SAM_SPI5_DMATX_CHANNEL, SAM_SPI5_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM5_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BEAT); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM5_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BEAT); + } +#endif + else { + osalDbgAssert(false, "invalid SPI instance"); + } + } else { + sercom_spi_lld_disable(spip); + } + spip->spi->SERCOM_CTRLA = SERCOM_SPIM_CTRLA_SWRST_Msk; + while (spip->spi->SERCOM_SYNCBUSY != 0) + ; + uint32_t baud_val = spip->clock / (2U * spip->config->sercom_cfg.freq) - 1; + if (baud_val > 255) { + baud_val = 255; + } + spip->spi->SERCOM_BAUD = baud_val; + spip->spi->SERCOM_CTRLB = + (spip->config->sercom_cfg.ctrlb & + ~(SERCOM_SPIM_CTRLB_MSSEN_Msk | SERCOM_SPIM_CTRLB_AMODE_Msk)) | + SERCOM_SPIM_CTRLB_RXEN_Msk; + while (spip->spi->SERCOM_SYNCBUSY != 0) + ; + uint32_t ctrla = (spip->config->sercom_cfg.ctrla & + ~SERCOM_SPIM_CTRLA_FORBIDDEN) | + SERCOM_SPIM_CTRLA_DIPO(spip->config->sercom_cfg.dipo) | + SERCOM_SPIM_CTRLA_DOPO(spip->config->sercom_cfg.dopo) | + (spip->config->slave ? SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE + : SERCOM_SPIM_CTRLA_MODE_SPI_MASTER) | + SERCOM_SPIM_CTRLA_ENABLE_Msk; + spip->spi->SERCOM_CTRLA = ctrla; + + while (spip->spi->SERCOM_SYNCBUSY != 0) + ; + return HAL_RET_SUCCESS; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void sercom_spi_lld_stop(SPIDriver* spip) { + + if (spip->state == SPI_READY) { + uint8_t id = 0; + uint8_t id_val = 0; + /* Disables the peripheral.*/ + if (false) { + } +#if SAM_SPI_USE_SERCOM0 == TRUE + else if (&SPID1 == spip) { + id = SAM_SERCOM0_GCLK_SRC_ID; + id_val = GCLK_CLKCTRL_ID_SERCOM0_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM1 == TRUE + else if (&SPID2 == spip) { + id = SAM_SERCOM1_GCLK_SRC_ID; + id_val = GCLK_CLKCTRL_ID_SERCOM1_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM2 == TRUE + else if (&SPID3 == spip) { + id = SAM_SERCOM2_GCLK_SRC_ID; + id_val = GCLK_CLKCTRL_ID_SERCOM2_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM3 == TRUE + else if (&SPID4 == spip) { + id = SAM_SERCOM3_GCLK_SRC_ID; + id_val = GCLK_CLKCTRL_ID_SERCOM3_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM4 == TRUE + else if (&SPID5 == spip) { + id = SAM_SERCOM4_GCLK_SRC_ID; + id_val = GCLK_CLKCTRL_ID_SERCOM4_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM5 == TRUE + else if (&SPID6 == spip) { + id = SAM_SERCOM5_GCLK_SRC_ID; + id_val = GCLK_CLKCTRL_ID_SERCOM5_CORE_Val; + } +#endif + else { + osalDbgAssert(false, "invalid SPI instance"); + } + sercom_spi_lld_disable(spip); + dmacChnlFreeI(spip->dmaRxId); + dmacChnlFreeI(spip->dmaTxId); + sam_gclk_mux(id, id_val, 0); + } +} diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom_same5x.inc b/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom_same5x.inc new file mode 100644 index 0000000000..3db0a49762 --- /dev/null +++ b/os/hal/ports/SAM/LLD/SERCOMv1/hal_spi_v2_lld_sercom_same5x.inc @@ -0,0 +1,396 @@ + +/** + * @brief SPI1 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM0 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** + * @brief SPI2 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM1 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/** + * @brief SPI3 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM2 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID3; +#endif + +/** + * @brief SPI4 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM3 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID4; +#endif + +/** + * @brief SPI5 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM4 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID5; +#endif + +/** + * @brief SPI6 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM5 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID6; +#endif + +/** + * @brief SPI7 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM6 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID7; +#endif + +/** + * @brief SPI8 driver identifier. + */ +#if (SAM_SPI_USE_SERCOM7 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID8; +#endif + + + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void sercom_spi_lld_init(void) { +#if SAM_SPI_USE_SERCOM0 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID1); + MCLK_REGS->MCLK_APBAMASK |= MCLK_APBAMASK_SERCOM0_Msk; + SPID1.spi = &SERCOM0_REGS->SPIM; + SPID1.clock = SAM_SERCOM0_GCLK_FREQ; + SPID1.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM1 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID2); + MCLK_REGS->MCLK_APBAMASK |= MCLK_APBAMASK_SERCOM1_Msk; + SPID2.spi = &SERCOM1_REGS->SPIM; + SPID2.clock = SAM_SERCOM1_GCLK_FREQ; + SPID2.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM2 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID3); + MCLK_REGS->MCLK_APBBMASK |= MCLK_APBBMASK_SERCOM2_Msk; + SPID3.spi = &SERCOM2_REGS->SPIM; + SPID3.clock = SAM_SERCOM2_GCLK_FREQ; + SPID3.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM3 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID4); + MCLK_REGS->MCLK_APBBMASK |= MCLK_APBBMASK_SERCOM3_Msk; + SPID4.spi = &SERCOM3_REGS->SPIM; + SPID4.clock = SAM_SERCOM3_GCLK_FREQ; + SPID4.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM4 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID5); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM4_Msk; + SPID5.spi = &SERCOM4_REGS->SPIM; + SPID5.clock = SAM_SERCOM4_GCLK_FREQ; + SPID5.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM5 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID6); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM5_Msk; + SPID6.spi = &SERCOM5_REGS->SPIM; + SPID6.clock = SAM_SERCOM5_GCLK_FREQ; + SPID6.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM6 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID7); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM6_Msk; + SPID7.spi = &SERCOM6_REGS->SPIM; + SPID7.clock = SAM_SERCOM6_GCLK_FREQ; + SPID7.is_qspi = false; +#endif +#if SAM_SPI_USE_SERCOM7 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID8); + MCLK_REGS->MCLK_APBDMASK |= MCLK_APBDMASK_SERCOM7_Msk; + SPID8.spi = &SERCOM7_REGS->SPIM; + SPID8.clock = SAM_SERCOM7_GCLK_FREQ; + SPID8.is_qspi = false; +#endif + +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * @return The operation status. + * + * @notapi + */ +msg_t sercom_spi_lld_start(SPIDriver* spip) { + + if (spip->state == SPI_STOP) { + + /* Enables the peripheral.*/ + if (false) { + } + +#if SAM_SPI_USE_SERCOM0 == TRUE + else if (&SPID1 == spip) { + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM0_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM0_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM0_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI0_DMARX_CHANNEL, + SAM_SPI0_DMATX_CHANNEL, SAM_SPI0_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM0_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BURST); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM0_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BURST); + } +#endif + +#if SAM_SPI_USE_SERCOM1 == TRUE + else if (&SPID2 == spip) { + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM1_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM1_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM1_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI1_DMARX_CHANNEL, + SAM_SPI1_DMATX_CHANNEL, SAM_SPI1_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM1_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BURST); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM1_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BURST); + } +#endif + +#if SAM_SPI_USE_SERCOM2 == TRUE + else if (&SPID3 == spip) { + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM2_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM2_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM2_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI2_DMARX_CHANNEL, + SAM_SPI2_DMATX_CHANNEL, SAM_SPI2_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM2_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BURST); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM2_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BURST); + } +#endif + +#if SAM_SPI_USE_SERCOM3 == TRUE + else if (&SPID4 == spip) { + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM3_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM3_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM3_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI3_DMARX_CHANNEL, + SAM_SPI3_DMATX_CHANNEL, SAM_SPI3_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM3_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BURST); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM3_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BURST); + } +#endif + +#if SAM_SPI_USE_SERCOM4 == TRUE + else if (&SPID5 == spip) { + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM4_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM4_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM4_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI4_DMARX_CHANNEL, + SAM_SPI4_DMATX_CHANNEL, SAM_SPI4_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM4_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BURST); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM4_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BURST); + } +#endif + +#if SAM_SPI_USE_SERCOM5 == TRUE + else if (&SPID6 == spip) { + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM5_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM5_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM5_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI5_DMARX_CHANNEL, + SAM_SPI5_DMATX_CHANNEL, SAM_SPI5_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM5_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BURST); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM5_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BURST); + } +#endif +#if SAM_SPI_USE_SERCOM6 == TRUE + else if (&SPID7 == spip) { + sam_gclk_mux(SAM_SERCOM6_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM6_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM6_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM6_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI6_DMARX_CHANNEL, + SAM_SPI6_DMATX_CHANNEL, SAM_SPI6_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM6_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BURST); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM6_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BURST); + } +#endif +#if SAM_SPI_USE_SERCOM7 == TRUE + else if (&SPID8 == spip) { + sam_gclk_mux(SAM_SERCOM7_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM7_CORE_Val, + 0); + sam_gclk_mux(SAM_SERCOM7_GCLK_SRC_ID, GCLK_PCHCTRL_ID_SERCOM7_CORE_Val, + 1); + msg_t msg = sercom_spi_lld_get_dma(spip, SAM_SPI7_DMARX_CHANNEL, + SAM_SPI7_DMATX_CHANNEL, SAM_SPI7_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, SERCOM7_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BURST); + dmacChnlSetTrigSrc(spip->dmaRxId, SERCOM7_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BURST); + } +#endif + + else { + osalDbgAssert(false, "invalid SPI instance"); + } + } else { + sercom_spi_lld_disable(spip); + } + spip->spi->SERCOM_CTRLA = SERCOM_SPIM_CTRLA_SWRST_Msk; + while (spip->spi->SERCOM_SYNCBUSY != 0) + ; + uint32_t baud_val = spip->clock / (2U * spip->config->sercom_cfg.freq) - 1; + if (baud_val > 255) { + baud_val = 255; + } + spip->spi->SERCOM_BAUD = baud_val; + spip->spi->SERCOM_CTRLB = + (spip->config->sercom_cfg.ctrlb & + ~(SERCOM_SPIM_CTRLB_MSSEN_Msk | SERCOM_SPIM_CTRLB_AMODE_Msk)) | + SERCOM_SPIM_CTRLB_RXEN_Msk; + while (spip->spi->SERCOM_SYNCBUSY != 0) + ; + uint32_t ctrla = (spip->config->sercom_cfg.ctrla & + ~SERCOM_SPIM_CTRLA_FORBIDDEN) | + SERCOM_SPIM_CTRLA_DIPO(spip->config->sercom_cfg.dipo) | + SERCOM_SPIM_CTRLA_DOPO(spip->config->sercom_cfg.dopo) | + (spip->config->slave ? SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE + : SERCOM_SPIM_CTRLA_MODE_SPI_MASTER) | + SERCOM_SPIM_CTRLA_ENABLE_Msk; + spip->spi->SERCOM_CTRLA = ctrla; + + while (spip->spi->SERCOM_SYNCBUSY != 0) + ; + return HAL_RET_SUCCESS; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void sercom_spi_lld_stop(SPIDriver* spip) { + + if (spip->state == SPI_READY) { + uint8_t id = 0; + uint8_t id_val = 0; + /* Disables the peripheral.*/ + if (false) { + } +#if SAM_SPI_USE_SERCOM0 == TRUE + else if (&SPID1 == spip) { + id = SAM_SERCOM0_GCLK_SRC_ID; + id_val = GCLK_PCHCTRL_ID_SERCOM0_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM1 == TRUE + else if (&SPID2 == spip) { + id = SAM_SERCOM1_GCLK_SRC_ID; + id_val = GCLK_PCHCTRL_ID_SERCOM1_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM2 == TRUE + else if (&SPID3 == spip) { + id = SAM_SERCOM2_GCLK_SRC_ID; + id_val = GCLK_PCHCTRL_ID_SERCOM2_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM3 == TRUE + else if (&SPID4 == spip) { + id = SAM_SERCOM3_GCLK_SRC_ID; + id_val = GCLK_PCHCTRL_ID_SERCOM3_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM4 == TRUE + else if (&SPID5 == spip) { + id = SAM_SERCOM4_GCLK_SRC_ID; + id_val = GCLK_PCHCTRL_ID_SERCOM4_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM5 == TRUE + else if (&SPID6 == spip) { + id = SAM_SERCOM5_GCLK_SRC_ID; + id_val = GCLK_PCHCTRL_ID_SERCOM5_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM6 == TRUE + else if (&SPID7 == spip) { + id = SAM_SERCOM6_GCLK_SRC_ID; + id_val = GCLK_PCHCTRL_ID_SERCOM6_CORE_Val; + } +#endif +#if SAM_SPI_USE_SERCOM7 == TRUE + else if (&SPID8 == spip) { + id = SAM_SERCOM7_GCLK_SRC_ID; + id_val = GCLK_PCHCTRL_ID_SERCOM7_CORE_Val; + } +#endif + else { + osalDbgAssert(false, "invalid SPI instance"); + } + sercom_spi_lld_disable(spip); + dmacChnlFreeI(spip->dmaRxId); + dmacChnlFreeI(spip->dmaTxId); + sam_gclk_mux(id, id_val, 0); + } +} \ No newline at end of file diff --git a/os/hal/ports/SAM/LLD/SERCOMv1/sercom_clk.h b/os/hal/ports/SAM/LLD/SERCOMv1/sercom_clk.h index e15c89f3fd..29a68bdb38 100644 --- a/os/hal/ports/SAM/LLD/SERCOMv1/sercom_clk.h +++ b/os/hal/ports/SAM/LLD/SERCOMv1/sercom_clk.h @@ -2,190 +2,266 @@ #define SERCOM_CLK_H_ #if defined(SAM_SERCOM0_GCLK_SRC_ID) #if SAM_SERCOM0_GCLK_SRC_ID == 0 -#define SAM_SERCOM0_GCLK_GENDIV SAM_GCLK0_GENDIV -#define SAM_SERCOM0_GCLK_SRC_FREQ SAM_GCLK0_FREQ +#define SAM_SERCOM0_GCLK_FREQ SAM_GCLK0_FREQ #elif SAM_SERCOM0_GCLK_SRC_ID == 1 -#define SAM_SERCOM0_GCLK_GENDIV SAM_GCLK1_GENDIV -#define SAM_SERCOM0_GCLK_SRC_FREQ SAM_GCLK1_FREQ +#define SAM_SERCOM0_GCLK_FREQ SAM_GCLK1_FREQ #elif SAM_SERCOM0_GCLK_SRC_ID == 2 -#define SAM_SERCOM0_GCLK_GENDIV SAM_GCLK2_GENDIV -#define SAM_SERCOM0_GCLK_SRC_FREQ SAM_GCLK2_FREQ +#define SAM_SERCOM0_GCLK_FREQ SAM_GCLK2_FREQ #elif SAM_SERCOM0_GCLK_SRC_ID == 3 -#define SAM_SERCOM0_GCLK_GENDIV SAM_GCLK3_GENDIV -#define SAM_SERCOM0_GCLK_SRC_FREQ SAM_GCLK3_FREQ +#define SAM_SERCOM0_GCLK_FREQ SAM_GCLK3_FREQ #elif SAM_SERCOM0_GCLK_SRC_ID == 4 -#define SAM_SERCOM0_GCLK_GENDIV SAM_GCLK4_GENDIV -#define SAM_SERCOM0_GCLK_SRC_FREQ SAM_GCLK4_FREQ +#define SAM_SERCOM0_GCLK_FREQ SAM_GCLK4_FREQ #elif SAM_SERCOM0_GCLK_SRC_ID == 5 -#define SAM_SERCOM0_GCLK_GENDIV SAM_GCLK5_GENDIV -#define SAM_SERCOM0_GCLK_SRC_FREQ SAM_GCLK5_FREQ +#define SAM_SERCOM0_GCLK_FREQ SAM_GCLK5_FREQ #elif SAM_SERCOM0_GCLK_SRC_ID == 6 -#define SAM_SERCOM0_GCLK_GENDIV SAM_GCLK6_GENDIV -#define SAM_SERCOM0_GCLK_SRC_FREQ SAM_GCLK6_FREQ +#define SAM_SERCOM0_GCLK_FREQ SAM_GCLK6_FREQ #elif SAM_SERCOM0_GCLK_SRC_ID == 7 -#define SAM_SERCOM0_GCLK_GENDIV SAM_GCLK7_GENDIV -#define SAM_SERCOM0_GCLK_SRC_FREQ SAM_GCLK7_FREQ +#define SAM_SERCOM0_GCLK_FREQ SAM_GCLK7_FREQ #elif SAM_SERCOM0_GCLK_SRC_ID == 8 -#define SAM_SERCOM0_GCLK_GENDIV SAM_GCLK8_GENDIV -#define SAM_SERCOM0_GCLK_SRC_FREQ SAM_GCLK8_FREQ -#endif +#define SAM_SERCOM0_GCLK_FREQ SAM_GCLK8_FREQ +#elif SAM_SERCOM0_GCLK_SRC_ID == 9 +#define SAM_SERCOM0_GCLK_FREQ SAM_GCLK9_FREQ #endif +#endif /*SAM_SERCOM0_GCLK_SRC_ID*/ #if defined(SAM_SERCOM1_GCLK_SRC_ID) #if SAM_SERCOM1_GCLK_SRC_ID == 0 -#define SAM_SERCOM1_GCLK_GENDIV SAM_GCLK0_GENDIV -#define SAM_SERCOM1_GCLK_SRC_FREQ SAM_GCLK0_SRC_FREQ +#define SAM_SERCOM1_GCLK_FREQ SAM_GCLK0_FREQ #elif SAM_SERCOM1_GCLK_SRC_ID == 1 -#define SAM_SERCOM1_GCLK_GENDIV SAM_GCLK1_GENDIV -#define SAM_SERCOM1_GCLK_SRC_FREQ SAM_GCLK1_SRC_FREQ +#define SAM_SERCOM1_GCLK_FREQ SAM_GCLK1_FREQ #elif SAM_SERCOM1_GCLK_SRC_ID == 2 -#define SAM_SERCOM1_GCLK_GENDIV SAM_GCLK2_GENDIV -#define SAM_SERCOM1_GCLK_SRC_FREQ SAM_GCLK2_SRC_FREQ +#define SAM_SERCOM1_GCLK_FREQ SAM_GCLK2_FREQ #elif SAM_SERCOM1_GCLK_SRC_ID == 3 -#define SAM_SERCOM1_GCLK_GENDIV SAM_GCLK3_GENDIV -#define SAM_SERCOM1_GCLK_SRC_FREQ SAM_GCLK3_SRC_FREQ +#define SAM_SERCOM1_GCLK_FREQ SAM_GCLK3_FREQ #elif SAM_SERCOM1_GCLK_SRC_ID == 4 -#define SAM_SERCOM1_GCLK_GENDIV SAM_GCLK4_GENDIV -#define SAM_SERCOM1_GCLK_SRC_FREQ SAM_GCLK4_SRC_FREQ +#define SAM_SERCOM1_GCLK_FREQ SAM_GCLK4_FREQ #elif SAM_SERCOM1_GCLK_SRC_ID == 5 -#define SAM_SERCOM1_GCLK_GENDIV SAM_GCLK5_GENDIV -#define SAM_SERCOM1_GCLK_SRC_FREQ SAM_GCLK5_SRC_FREQ +#define SAM_SERCOM1_GCLK_FREQ SAM_GCLK5_FREQ #elif SAM_SERCOM1_GCLK_SRC_ID == 6 -#define SAM_SERCOM1_GCLK_GENDIV SAM_GCLK6_GENDIV -#define SAM_SERCOM1_GCLK_SRC_FREQ SAM_GCLK6_SRC_FREQ +#define SAM_SERCOM1_GCLK_FREQ SAM_GCLK6_FREQ #elif SAM_SERCOM1_GCLK_SRC_ID == 7 -#define SAM_SERCOM1_GCLK_GENDIV SAM_GCLK7_GENDIV -#define SAM_SERCOM1_GCLK_SRC_FREQ SAM_GCLK7_SRC_FREQ +#define SAM_SERCOM1_GCLK_FREQ SAM_GCLK7_FREQ #elif SAM_SERCOM1_GCLK_SRC_ID == 8 -#define SAM_SERCOM1_GCLK_GENDIV SAM_GCLK8_GENDIV -#define SAM_SERCOM1_GCLK_SRC_FREQ SAM_GCLK8_SRC_FREQ -#endif +#define SAM_SERCOM1_GCLK_FREQ SAM_GCLK8_FREQ +#elif SAM_SERCOM1_GCLK_SRC_ID == 9 +#define SAM_SERCOM1_GCLK_FREQ SAM_GCLK9_FREQ #endif +#endif /*SAM_SERCOM1_GCLK_SRC_ID*/ #if defined(SAM_SERCOM2_GCLK_SRC_ID) #if SAM_SERCOM2_GCLK_SRC_ID == 0 -#define SAM_SERCOM2_GCLK_GENDIV SAM_GCLK0_GENDIV -#define SAM_SERCOM2_GCLK_SRC_FREQ SAM_GCLK0_SRC_FREQ +#define SAM_SERCOM2_GCLK_FREQ SAM_GCLK0_FREQ #elif SAM_SERCOM2_GCLK_SRC_ID == 1 #define SAM_SERCOM2_GCLK_GENDIV SAM_GCLK1_GENDIV -#define SAM_SERCOM2_GCLK_SRC_FREQ SAM_GCLK1_SRC_FREQ +#define SAM_SERCOM2_GCLK_FREQ SAM_GCLK1_FREQ #elif SAM_SERCOM2_GCLK_SRC_ID == 2 #define SAM_SERCOM2_GCLK_GENDIV SAM_GCLK2_GENDIV -#define SAM_SERCOM2_GCLK_SRC_FREQ SAM_GCLK2_SRC_FREQ +#define SAM_SERCOM2_GCLK_FREQ SAM_GCLK2_FREQ #elif SAM_SERCOM2_GCLK_SRC_ID == 3 #define SAM_SERCOM2_GCLK_GENDIV SAM_GCLK3_GENDIV -#define SAM_SERCOM2_GCLK_SRC_FREQ SAM_GCLK3_SRC_FREQ +#define SAM_SERCOM2_GCLK_FREQ SAM_GCLK3_FREQ #elif SAM_SERCOM2_GCLK_SRC_ID == 4 #define SAM_SERCOM2_GCLK_GENDIV SAM_GCLK4_GENDIV -#define SAM_SERCOM2_GCLK_SRC_FREQ SAM_GCLK4_SRC_FREQ +#define SAM_SERCOM2_GCLK_FREQ SAM_GCLK4_FREQ #elif SAM_SERCOM2_GCLK_SRC_ID == 5 #define SAM_SERCOM2_GCLK_GENDIV SAM_GCLK5_GENDIV -#define SAM_SERCOM2_GCLK_SRC_FREQ SAM_GCLK5_SRC_FREQ +#define SAM_SERCOM2_GCLK_FREQ SAM_GCLK5_FREQ #elif SAM_SERCOM2_GCLK_SRC_ID == 6 #define SAM_SERCOM2_GCLK_GENDIV SAM_GCLK6_GENDIV -#define SAM_SERCOM2_GCLK_SRC_FREQ SAM_GCLK6_SRC_FREQ +#define SAM_SERCOM2_GCLK_FREQ SAM_GCLK6_FREQ #elif SAM_SERCOM2_GCLK_SRC_ID == 7 #define SAM_SERCOM2_GCLK_GENDIV SAM_GCLK7_GENDIV -#define SAM_SERCOM2_GCLK_SRC_FREQ SAM_GCLK7_SRC_FREQ +#define SAM_SERCOM2_GCLK_FREQ SAM_GCLK7_FREQ #elif SAM_SERCOM2_GCLK_SRC_ID == 8 #define SAM_SERCOM2_GCLK_GENDIV SAM_GCLK8_GENDIV -#define SAM_SERCOM2_GCLK_SRC_FREQ SAM_GCLK8_SRC_FREQ +#define SAM_SERCOM2_GCLK_FREQ SAM_GCLK8_FREQ +#elif SAM_SERCOM2_GCLK_SRC_ID == 9 +#define SAM_SERCOM2_GCLK_GENDIV SAM_GCLK9_GENDIV +#define SAM_SERCOM2_GCLK_FREQ SAM_GCLK9_FREQ #endif -#endif - - +#endif /*SAM_SERCOM2_GCLK_SRC_ID*/ + #if defined(SAM_SERCOM3_GCLK_SRC_ID) #if SAM_SERCOM3_GCLK_SRC_ID == 0 #define SAM_SERCOM3_GCLK_GENDIV SAM_GCLK0_GENDIV -#define SAM_SERCOM3_GCLK_SRC_FREQ SAM_GCLK0_SRC_FREQ +#define SAM_SERCOM3_GCLK_FREQ SAM_GCLK0_FREQ #elif SAM_SERCOM3_GCLK_SRC_ID == 1 #define SAM_SERCOM3_GCLK_GENDIV SAM_GCLK1_GENDIV -#define SAM_SERCOM3_GCLK_SRC_FREQ SAM_GCLK1_SRC_FREQ +#define SAM_SERCOM3_GCLK_FREQ SAM_GCLK1_FREQ #elif SAM_SERCOM3_GCLK_SRC_ID == 2 #define SAM_SERCOM3_GCLK_GENDIV SAM_GCLK2_GENDIV -#define SAM_SERCOM3_GCLK_SRC_FREQ SAM_GCLK2_SRC_FREQ +#define SAM_SERCOM3_GCLK_FREQ SAM_GCLK2_FREQ #elif SAM_SERCOM3_GCLK_SRC_ID == 3 #define SAM_SERCOM3_GCLK_GENDIV SAM_GCLK3_GENDIV -#define SAM_SERCOM3_GCLK_SRC_FREQ SAM_GCLK3_SRC_FREQ +#define SAM_SERCOM3_GCLK_FREQ SAM_GCLK3_FREQ #elif SAM_SERCOM3_GCLK_SRC_ID == 4 #define SAM_SERCOM3_GCLK_GENDIV SAM_GCLK4_GENDIV -#define SAM_SERCOM3_GCLK_SRC_FREQ SAM_GCLK4_SRC_FREQ +#define SAM_SERCOM3_GCLK_FREQ SAM_GCLK4_FREQ #elif SAM_SERCOM3_GCLK_SRC_ID == 5 #define SAM_SERCOM3_GCLK_GENDIV SAM_GCLK5_GENDIV -#define SAM_SERCOM3_GCLK_SRC_FREQ SAM_GCLK5_SRC_FREQ +#define SAM_SERCOM3_GCLK_FREQ SAM_GCLK5_FREQ #elif SAM_SERCOM3_GCLK_SRC_ID == 6 #define SAM_SERCOM3_GCLK_GENDIV SAM_GCLK6_GENDIV -#define SAM_SERCOM3_GCLK_SRC_FREQ SAM_GCLK6_SRC_FREQ +#define SAM_SERCOM3_GCLK_FREQ SAM_GCLK6_FREQ #elif SAM_SERCOM3_GCLK_SRC_ID == 7 #define SAM_SERCOM3_GCLK_GENDIV SAM_GCLK7_GENDIV -#define SAM_SERCOM3_GCLK_SRC_FREQ SAM_GCLK7_SRC_FREQ +#define SAM_SERCOM3_GCLK_FREQ SAM_GCLK7_FREQ #elif SAM_SERCOM3_GCLK_SRC_ID == 8 #define SAM_SERCOM3_GCLK_GENDIV SAM_GCLK8_GENDIV -#define SAM_SERCOM3_GCLK_SRC_FREQ SAM_GCLK8_SRC_FREQ -#endif +#define SAM_SERCOM3_GCLK_FREQ SAM_GCLK8_FREQ +#elif SAM_SERCOM3_GCLK_SRC_ID == 9 +#define SAM_SERCOM3_GCLK_GENDIV SAM_GCLK9_GENDIV +#define SAM_SERCOM3_GCLK_FREQ SAM_GCLK9_FREQ #endif +#endif /*SAM_SERCOM3_GCLK_SRC_ID*/ #if defined(SAM_SERCOM4_GCLK_SRC_ID) #if SAM_SERCOM4_GCLK_SRC_ID == 0 #define SAM_SERCOM4_GCLK_GENDIV SAM_GCLK0_GENDIV -#define SAM_SERCOM4_GCLK_SRC_FREQ SAM_GCLK0_SRC_FREQ +#define SAM_SERCOM4_GCLK_FREQ SAM_GCLK0_FREQ #elif SAM_SERCOM4_GCLK_SRC_ID == 1 #define SAM_SERCOM4_GCLK_GENDIV SAM_GCLK1_GENDIV -#define SAM_SERCOM4_GCLK_SRC_FREQ SAM_GCLK1_SRC_FREQ +#define SAM_SERCOM4_GCLK_FREQ SAM_GCLK1_FREQ #elif SAM_SERCOM4_GCLK_SRC_ID == 2 #define SAM_SERCOM4_GCLK_GENDIV SAM_GCLK2_GENDIV -#define SAM_SERCOM4_GCLK_SRC_FREQ SAM_GCLK2_SRC_FREQ +#define SAM_SERCOM4_GCLK_FREQ SAM_GCLK2_FREQ #elif SAM_SERCOM4_GCLK_SRC_ID == 3 #define SAM_SERCOM4_GCLK_GENDIV SAM_GCLK3_GENDIV -#define SAM_SERCOM4_GCLK_SRC_FREQ SAM_GCLK3_SRC_FREQ +#define SAM_SERCOM4_GCLK_FREQ SAM_GCLK3_FREQ #elif SAM_SERCOM4_GCLK_SRC_ID == 4 #define SAM_SERCOM4_GCLK_GENDIV SAM_GCLK4_GENDIV -#define SAM_SERCOM4_GCLK_SRC_FREQ SAM_GCLK4_SRC_FREQ +#define SAM_SERCOM4_GCLK_FREQ SAM_GCLK4_FREQ #elif SAM_SERCOM4_GCLK_SRC_ID == 5 #define SAM_SERCOM4_GCLK_GENDIV SAM_GCLK5_GENDIV -#define SAM_SERCOM4_GCLK_SRC_FREQ SAM_GCLK5_SRC_FREQ +#define SAM_SERCOM4_GCLK_FREQ SAM_GCLK5_FREQ #elif SAM_SERCOM4_GCLK_SRC_ID == 6 #define SAM_SERCOM4_GCLK_GENDIV SAM_GCLK6_GENDIV -#define SAM_SERCOM4_GCLK_SRC_FREQ SAM_GCLK6_SRC_FREQ +#define SAM_SERCOM4_GCLK_FREQ SAM_GCLK6_FREQ #elif SAM_SERCOM4_GCLK_SRC_ID == 7 #define SAM_SERCOM4_GCLK_GENDIV SAM_GCLK7_GENDIV -#define SAM_SERCOM4_GCLK_SRC_FREQ SAM_GCLK7_SRC_FREQ +#define SAM_SERCOM4_GCLK_FREQ SAM_GCLK7_FREQ #elif SAM_SERCOM4_GCLK_SRC_ID == 8 #define SAM_SERCOM4_GCLK_GENDIV SAM_GCLK8_GENDIV -#define SAM_SERCOM4_GCLK_SRC_FREQ SAM_GCLK8_SRC_FREQ -#endif +#define SAM_SERCOM4_GCLK_FREQ SAM_GCLK8_FREQ +#elif SAM_SERCOM4_GCLK_SRC_ID == 9 +#define SAM_SERCOM4_GCLK_GENDIV SAM_GCLK9_GENDIV +#define SAM_SERCOM4_GCLK_FREQ SAM_GCLK9_FREQ #endif +#endif /*SAM_SERCOM4_GCLK_SRC_ID*/ #if defined(SAM_SERCOM5_GCLK_SRC_ID) #if SAM_SERCOM5_GCLK_SRC_ID == 0 #define SAM_SERCOM5_GCLK_GENDIV SAM_GCLK0_GENDIV -#define SAM_SERCOM5_GCLK_SRC_FREQ SAM_GCLK0_SRC_FREQ +#define SAM_SERCOM5_GCLK_FREQ SAM_GCLK0_FREQ #elif SAM_SERCOM5_GCLK_SRC_ID == 1 #define SAM_SERCOM5_GCLK_GENDIV SAM_GCLK1_GENDIV -#define SAM_SERCOM5_GCLK_SRC_FREQ SAM_GCLK1_SRC_FREQ +#define SAM_SERCOM5_GCLK_FREQ SAM_GCLK1_FREQ #elif SAM_SERCOM5_GCLK_SRC_ID == 2 #define SAM_SERCOM5_GCLK_GENDIV SAM_GCLK2_GENDIV -#define SAM_SERCOM5_GCLK_SRC_FREQ SAM_GCLK2_SRC_FREQ +#define SAM_SERCOM5_GCLK_FREQ SAM_GCLK2_FREQ #elif SAM_SERCOM5_GCLK_SRC_ID == 3 #define SAM_SERCOM5_GCLK_GENDIV SAM_GCLK3_GENDIV -#define SAM_SERCOM5_GCLK_SRC_FREQ SAM_GCLK3_SRC_FREQ +#define SAM_SERCOM5_GCLK_FREQ SAM_GCLK3_FREQ #elif SAM_SERCOM5_GCLK_SRC_ID == 4 #define SAM_SERCOM5_GCLK_GENDIV SAM_GCLK4_GENDIV -#define SAM_SERCOM5_GCLK_SRC_FREQ SAM_GCLK4_SRC_FREQ +#define SAM_SERCOM5_GCLK_FREQ SAM_GCLK4_FREQ #elif SAM_SERCOM5_GCLK_SRC_ID == 5 #define SAM_SERCOM5_GCLK_GENDIV SAM_GCLK5_GENDIV -#define SAM_SERCOM5_GCLK_SRC_FREQ SAM_GCLK5_SRC_FREQ +#define SAM_SERCOM5_GCLK_FREQ SAM_GCLK5_FREQ #elif SAM_SERCOM5_GCLK_SRC_ID == 6 #define SAM_SERCOM5_GCLK_GENDIV SAM_GCLK6_GENDIV -#define SAM_SERCOM5_GCLK_SRC_FREQ SAM_GCLK6_SRC_FREQ +#define SAM_SERCOM5_GCLK_FREQ SAM_GCLK6_FREQ #elif SAM_SERCOM5_GCLK_SRC_ID == 7 #define SAM_SERCOM5_GCLK_GENDIV SAM_GCLK7_GENDIV -#define SAM_SERCOM5_GCLK_SRC_FREQ SAM_GCLK7_SRC_FREQ +#define SAM_SERCOM5_GCLK_FREQ SAM_GCLK7_FREQ #elif SAM_SERCOM5_GCLK_SRC_ID == 8 #define SAM_SERCOM5_GCLK_GENDIV SAM_GCLK8_GENDIV -#define SAM_SERCOM5_GCLK_SRC_FREQ SAM_GCLK8_SRC_FREQ +#define SAM_SERCOM5_GCLK_FREQ SAM_GCLK8_FREQ +#elif SAM_SERCOM5_GCLK_SRC_ID == 9 +#define SAM_SERCOM5_GCLK_GENDIV SAM_GCLK9_GENDIV +#define SAM_SERCOM5_GCLK_FREQ SAM_GCLK9_FREQ #endif +#endif /*SAM_SERCOM5_GCLK_SRC_ID*/ + +#if defined(SAM_SERCOM6_GCLK_SRC_ID) +#if SAM_SERCOM6_GCLK_SRC_ID == 0 +#define SAM_SERCOM6_GCLK_GENDIV SAM_GCLK0_GENDIV +#define SAM_SERCOM6_GCLK_FREQ SAM_GCLK0_FREQ +#elif SAM_SERCOM6_GCLK_SRC_ID == 1 +#define SAM_SERCOM6_GCLK_GENDIV SAM_GCLK1_GENDIV +#define SAM_SERCOM6_GCLK_FREQ SAM_GCLK1_FREQ +#elif SAM_SERCOM6_GCLK_SRC_ID == 2 +#define SAM_SERCOM6_GCLK_GENDIV SAM_GCLK2_GENDIV +#define SAM_SERCOM6_GCLK_FREQ SAM_GCLK2_FREQ +#elif SAM_SERCOM6_GCLK_SRC_ID == 3 +#define SAM_SERCOM6_GCLK_GENDIV SAM_GCLK3_GENDIV +#define SAM_SERCOM6_GCLK_FREQ SAM_GCLK3_FREQ +#elif SAM_SERCOM6_GCLK_SRC_ID == 4 +#define SAM_SERCOM6_GCLK_GENDIV SAM_GCLK4_GENDIV +#define SAM_SERCOM6_GCLK_FREQ SAM_GCLK4_FREQ +#elif SAM_SERCOM6_GCLK_SRC_ID == 5 +#define SAM_SERCOM6_GCLK_GENDIV SAM_GCLK5_GENDIV +#define SAM_SERCOM6_GCLK_FREQ SAM_GCLK5_FREQ +#elif SAM_SERCOM6_GCLK_SRC_ID == 6 +#define SAM_SERCOM6_GCLK_GENDIV SAM_GCLK6_GENDIV +#define SAM_SERCOM6_GCLK_FREQ SAM_GCLK6_FREQ +#elif SAM_SERCOM6_GCLK_SRC_ID == 7 +#define SAM_SERCOM6_GCLK_GENDIV SAM_GCLK7_GENDIV +#define SAM_SERCOM6_GCLK_FREQ SAM_GCLK7_FREQ +#elif SAM_SERCOM6_GCLK_SRC_ID == 8 +#define SAM_SERCOM6_GCLK_GENDIV SAM_GCLK8_GENDIV +#define SAM_SERCOM6_GCLK_FREQ SAM_GCLK8_FREQ +#elif SAM_SERCOM6_GCLK_SRC_ID == 9 +#define SAM_SERCOM6_GCLK_GENDIV SAM_GCLK9_GENDIV +#define SAM_SERCOM6_GCLK_FREQ SAM_GCLK9_FREQ +#endif +#endif/*SAM_SERCOM6_GCLK_SRC_ID*/ + +#if defined(SAM_SERCOM7_GCLK_SRC_ID) +#if SAM_SERCOM7_GCLK_SRC_ID == 0 +#define SAM_SERCOM7_GCLK_GENDIV SAM_GCLK0_GENDIV +#define SAM_SERCOM7_GCLK_FREQ SAM_GCLK0_FREQ +#elif SAM_SERCOM7_GCLK_SRC_ID == 1 +#define SAM_SERCOM7_GCLK_GENDIV SAM_GCLK1_GENDIV +#define SAM_SERCOM7_GCLK_FREQ SAM_GCLK1_FREQ +#elif SAM_SERCOM7_GCLK_SRC_ID == 2 +#define SAM_SERCOM7_GCLK_GENDIV SAM_GCLK2_GENDIV +#define SAM_SERCOM7_GCLK_FREQ SAM_GCLK2_FREQ +#elif SAM_SERCOM7_GCLK_SRC_ID == 3 +#define SAM_SERCOM7_GCLK_GENDIV SAM_GCLK3_GENDIV +#define SAM_SERCOM7_GCLK_FREQ SAM_GCLK3_FREQ +#elif SAM_SERCOM7_GCLK_SRC_ID == 4 +#define SAM_SERCOM7_GCLK_GENDIV SAM_GCLK4_GENDIV +#define SAM_SERCOM7_GCLK_FREQ SAM_GCLK4_FREQ +#elif SAM_SERCOM7_GCLK_SRC_ID == 5 +#define SAM_SERCOM7_GCLK_GENDIV SAM_GCLK5_GENDIV +#define SAM_SERCOM7_GCLK_FREQ SAM_GCLK5_FREQ +#elif SAM_SERCOM7_GCLK_SRC_ID == 6 +#define SAM_SERCOM7_GCLK_GENDIV SAM_GCLK6_GENDIV +#define SAM_SERCOM7_GCLK_FREQ SAM_GCLK6_FREQ +#elif SAM_SERCOM7_GCLK_SRC_ID == 7 +#define SAM_SERCOM7_GCLK_GENDIV SAM_GCLK7_GENDIV +#define SAM_SERCOM7_GCLK_FREQ SAM_GCLK7_FREQ +#elif SAM_SERCOM7_GCLK_SRC_ID == 8 +#define SAM_SERCOM7_GCLK_GENDIV SAM_GCLK8_GENDIV +#define SAM_SERCOM7_GCLK_FREQ SAM_GCLK8_FREQ +#elif SAM_SERCOM7_GCLK_SRC_ID == 9 +#define SAM_SERCOM7_GCLK_GENDIV SAM_GCLK9_GENDIV +#define SAM_SERCOM7_GCLK_FREQ SAM_GCLK9_FREQ #endif +#endif /*SAM_SERCOM7_GCLK_SRC_ID*/ +#ifdef SAME54_MCUCONF + +#define GCLK_PCHCTRL_ID_SERCOM0_CORE_Val 7 +#define GCLK_PCHCTRL_ID_SERCOM1_CORE_Val 8 +#define GCLK_PCHCTRL_ID_SERCOM2_CORE_Val 23 +#define GCLK_PCHCTRL_ID_SERCOM3_CORE_Val 24 +#define GCLK_PCHCTRL_ID_SERCOM4_CORE_Val 34 +#define GCLK_PCHCTRL_ID_SERCOM5_CORE_Val 35 +#define GCLK_PCHCTRL_ID_SERCOM6_CORE_Val 36 +#define GCLK_PCHCTRL_ID_SERCOM7_CORE_Val 37 + +#endif -#endif \ No newline at end of file +#endif /*SERCOM_CLK_H_*/ \ No newline at end of file diff --git a/os/hal/ports/SAM/LLD/SPIv1/driver.mk b/os/hal/ports/SAM/LLD/SPIv1/driver.mk new file mode 100644 index 0000000000..2f4fe919dc --- /dev/null +++ b/os/hal/ports/SAM/LLD/SPIv1/driver.mk @@ -0,0 +1,4 @@ +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld_qspi.c +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld.c + +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/SAM/LLD/SPIv1 \ No newline at end of file diff --git a/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld.c b/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld.c new file mode 100644 index 0000000000..a50731f4c7 --- /dev/null +++ b/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_spi_v2_lld.c + * @brief PLATFORM SPI (v2) subsystem low level driver source. + * + * @addtogroup SPI_V2 + * @{ + */ + +#include "hal.h" +#include "sercom_clk.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + + +void spi_lld_init(void) +{ + sercom_spi_lld_init(); + qspi_spi_lld_init(); +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_start(SPIDriver* spip) { + if(!spip->is_qspi) { + return sercom_spi_lld_start(spip); + } + else { + return qspi_spi_lld_start(spip); + } +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver* spip) { + if (spip->is_qspi) { + return sercom_spi_lld_stop(spip); + } + else { + return qspi_spi_lld_stop(spip); + } +} + +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver* spip) { + if(!spip->is_qspi) { + sercom_spi_lld_select(spip); + } + else { + qspi_spi_lld_select(spip); + } +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver* spip) { + if(!spip->is_qspi) { + sercom_spi_lld_select(spip); + } + else { + qspi_spi_lld_select(spip); + } +} +#endif + +/** + * @brief Ignores data on the SPI bus. + * @details This synchronous function performs the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @pre In order to use this function the option @p SPI_USE_SYNCHRONIZATION + * must be enabled. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_ignore(SPIDriver* spip, size_t n) { + if(!spip->is_qspi) { + return sercom_spi_lld_ignore(spip, n); + } + else { + return qspi_spi_lld_ignore(spip, n); + } +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_exchange(SPIDriver* spip, size_t n, const void* txbuf, + void* rxbuf) +{ + if(!spip->is_qspi) { + return sercom_spi_lld_exchange(spip, n, txbuf, rxbuf); + } + else { + return qspi_spi_lld_exchange(spip, n, txbuf, rxbuf); + } +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_send(SPIDriver* spip, size_t n, const void* txbuf) { + if(!spip->is_qspi) { + return sercom_spi_lld_send(spip, n, txbuf); + } + else { + return qspi_spi_lld_send(spip, n, txbuf); + } +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_receive(SPIDriver* spip, size_t n, void* rxbuf) { + if(!spip->is_qspi) { + return sercom_spi_lld_receive(spip, n, rxbuf); + } + else { + return qspi_spi_lld_receive(spip, n, rxbuf); + } +} + +/** + * @brief Aborts the ongoing SPI operation, if any. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[out] sizep pointer to the counter of frames not yet transferred + * or @p NULL + * @return The operation status. + * + * @notapi + */ +msg_t spi_lld_stop_transfer(SPIDriver* spip, size_t* sizep) { + if(!spip->is_qspi) { + return sercom_spi_lld_stop_transfer(spip, sizep); + } + else { + return qspi_spi_lld_stop_transfer(spip, sizep); + } +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver* spip, uint16_t frame) { + if(!spip->is_qspi) { + return sercom_spi_lld_polled_exchange(spip, frame); + } + else { + return qspi_spi_lld_polled_exchange(spip, frame); + } +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld.h b/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld.h new file mode 100644 index 0000000000..2956d9beff --- /dev/null +++ b/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld.h @@ -0,0 +1,231 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_spi_v2_lld.h + * @brief PLATFORM SPI (v2) subsystem low level driver header. + * + * @addtogroup SPI_V2 + * @{ + */ + +#ifndef HAL_SPI_V2_LLD_H +#define HAL_SPI_V2_LLD_H + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Circular mode support flag. + */ +#define SPI_SUPPORTS_CIRCULAR FALSE + +/** + * @brief Slave mode support flag. + */ +#define SPI_SUPPORTS_SLAVE_MODE TRUE + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SPI1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SAM_SPI_USE_SERCOM0) || defined(__DOXYGEN__) +#define SAM_SPI_USE_SERCOM0 FALSE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for SPI2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SAM_SPI_USE_SERCOM1) || defined(__DOXYGEN__) +#define SAM_SPI_USE_SERCOM1 FALSE +#endif + +/** + * @brief SPI3 driver enable switch. + * @details If set to @p TRUE the support for SPI3 is included. + * @note The default is @p FALSE. + */ +#if !defined(SAM_SPI_USE_SERCOM2) || defined(__DOXYGEN__) +#define SAM_SPI_USE_SERCOM2 FALSE +#endif + +/** + * @brief SPI4 driver enable switch. + * @details If set to @p TRUE the support for SPI4 is included. + * @note The default is @p FALSE. + */ +#if !defined(SAM_SPI_USE_SERCOM3) || defined(__DOXYGEN__) +#define SAM_SPI_USE_SERCOM3 FALSE +#endif + +/** + * @brief SPI5 driver enable switch. + * @details If set to @p TRUE the support for SPI5 is included. + * @note The default is @p FALSE. + */ +#if !defined(SAM_SPI_USE_SERCOM4) || defined(__DOXYGEN__) +#define SAM_SPI_USE_SERCOM4 FALSE +#endif + +/** + * @brief SPI6 driver enable switch. + * @details If set to @p TRUE the support for SPI6 is included. + * @note The default is @p FALSE. + */ +#if !defined(SAM_SPI_USE_SERCOM5) || defined(__DOXYGEN__) +#define SAM_SPI_USE_SERCOM5 FALSE +#endif + +/** + * @brief SPI Driver requires DMAC to be enabled + * + */ +#if !defined(SAM_DMAC_REQUIRED) +#define SAM_DMAC_REQUIRED +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if SAM_SPI_USE_SERCOM0 == TRUE +#if SAM_SIO_USE_SERCOM0 == TRUE || SAM_I2C_USE_SERCOM0 == TRUE +#error "SERCOM0: Can only configured as one function only" +#endif +#endif + +#if SAM_SPI_USE_SERCOM1 == TRUE +#if SAM_SIO_USE_SERCOM1 == TRUE || SAM_I2C_USE_SERCOM1 == TRUE +#error "SERCOM1: Can only configured as one function only" +#endif +#endif + +#if SAM_SPI_USE_SERCOM2 == TRUE +#if SAM_SIO_USE_SERCOM2 == TRUE || SAM_I2C_USE_SERCOM2 == TRUE +#error "SERCOM2: Can only configured as one function only" +#endif +#endif + +#if SAM_SPI_USE_SERCOM3 == TRUE +#if SAM_SIO_USE_SERCOM3 == TRUE || SAM_I2C_USE_SERCOM3 == TRUE +#error "SERCOM3: Can only configured as one function only" +#endif +#endif + +#if SAM_SPI_USE_SERCOM4 == TRUE +#if SAM_SIO_USE_SERCOM4 == TRUE || SAM_I2C_USE_SERCOM4 == TRUE +#error "SERCOM4: Can only configured as one function only" +#endif +#endif + +#if SAM_SPI_USE_SERCOM5 == TRUE +#if SAM_SIO_USE_SERCOM5 == TRUE || SAM_I2C_USE_SERCOM5 == TRUE +#error "SERCOM5: Can only configured as one function only" +#endif +#endif + +#if SAM_SPI_USE_SERCOM6 == TRUE +#if SAM_SIO_USE_SERCOM6 == TRUE || SAM_I2C_USE_SERCOM6 == TRUE +#error "SERCOM6: Can only configured as one function only" +#endif +#endif + +#if SAM_SPI_USE_SERCOM7 == TRUE +#if SAM_SIO_USE_SERCOM7 == TRUE || SAM_I2C_USE_SERCOM7 == TRUE +#error "SERCOM7: Can only configured as one function only" +#endif +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the SPI driver structure. + */ +#define spi_lld_driver_fields \ + union { \ + sercom_spim_registers_t* spi; \ + qspi_registers_t *qspi; \ + }; \ + uint32_t clock; \ + uint8_t dmaTxId; \ + uint8_t dmaRxId; \ + uint32_t rxsink; \ + uint32_t txsource; \ + bool is_qspi; + +/** + * @brief Low level fields of the SPI configuration structure. + */ +#define spi_lld_config_fields \ + union { \ + sercom_spi_config_t sercom_cfg; \ + qspi_spi_config_t qspi_cfg; \ + }; + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ +#include "hal_spi_v2_lld_sercom.h" +#include "hal_spi_v2_lld_qspi.h" +#ifdef __cplusplus +extern "C" { +#endif +void spi_lld_init(void); +msg_t spi_lld_start(SPIDriver* spip); +void spi_lld_stop(SPIDriver* spip); +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) +void spi_lld_select(SPIDriver* spip); +void spi_lld_unselect(SPIDriver* spip); +#endif +msg_t spi_lld_ignore(SPIDriver* spip, size_t n); +msg_t spi_lld_exchange(SPIDriver* spip, size_t n, const void* txbuf, + void* rxbuf); +msg_t spi_lld_send(SPIDriver* spip, size_t n, const void* txbuf); +msg_t spi_lld_receive(SPIDriver* spip, size_t n, void* rxbuf); +msg_t spi_lld_stop_transfer(SPIDriver* spip, size_t* sizep); +uint16_t spi_lld_polled_exchange(SPIDriver* spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* HAL_SPI_V2_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld_qspi.c b/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld_qspi.c new file mode 100644 index 0000000000..69a8197ce7 --- /dev/null +++ b/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld_qspi.c @@ -0,0 +1,305 @@ +#include "hal.h" +#if HAL_USE_SPI || defined(__DOXYGEN__) + + +/** + * @brief SPI9 driver identifier. + */ +#if (SAM_SPI_USE_QSPI1 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID9; +#endif + +// Use SPI Mode +// DATALEN = 8 +#define QSPI_CTRLB_FORBIDDEN (QSPI_CTRLB_MODE_Msk | QSPI_CTRLB_DATALEN_Msk) + +static inline void qspi_spi_lld_enable_irq(SPIDriver* spip) { + qspi_registers_t *qspi = spip->qspi; + qspi->QSPI_INTENSET = QSPI_INTENSET_CSRISE_Msk | QSPI_INTENSET_ERROR_Msk; +} +static inline void qspi_spi_lld_disable_irq(SPIDriver* spip) { + qspi_registers_t *qspi = spip->qspi; + qspi->QSPI_INTENCLR = QSPI_INTENCLR_CSRISE_Msk | QSPI_INTENCLR_ERROR_Msk; +} + +static inline void qspi_spi_lld_err_irq(SPIDriver* spip) { + /* Stopping DMAs.*/ + dmacChnlDisable(spip->dmaTxId); + dmacChnlDisable(spip->dmaRxId); + + /* Reporting the failure.*/ + __spi_isr_error_code(spip, HAL_RET_HW_FAILURE); +} +static void qspi_spi_lld_serve_interrupt(SPIDriver* spip) { + qspi_registers_t *qspi = spip->qspi; + uint32_t intflag = qspi->QSPI_INTFLAG; + // Clear intflag + qspi->QSPI_INTFLAG = intflag; + if (intflag & QSPI_INTFLAG_ERROR_Msk){ + // Handle error + qspi_spi_lld_err_irq(spip); + } + if (intflag & QSPI_INTFLAG_CSRISE_Msk) { + /* Stopping DMAs.*/ + dmacChnlDisable(spip->dmaTxId); + dmacChnlDisable(spip->dmaRxId); + qspi_spi_lld_disable_irq(spip); + /* Operation finished interrupt.*/ + __spi_isr_complete_code(spip); + } +} + +static void qspi_spi_dma_lld_serve_rx_interrupt(SPIDriver* spip, uint8_t flag) { + if (flag & DMAC_CHINTFLAG_TERR_Msk) { + qspi_spi_lld_err_irq(spip); + } + else if(flag & DMAC_CHINTFLAG_TCMPL_Msk) { + qspi_spi_lld_enable_irq(spip); + } +} + +static void qspi_spi_lld_dma_serve_tx_interrupt(SPIDriver* spip, uint8_t flag) { + if (flag & DMAC_CHINTFLAG_TERR_Msk) { + qspi_spi_lld_err_irq(spip); + } +} + +static inline void qspi_spi_lld_disable(SPIDriver* spip) { + dmacChnlDisable(spip->dmaTxId); + spip->qspi->QSPI_CTRLA &= ~QSPI_CTRLA_ENABLE_Msk; + while((spip->qspi->QSPI_STATUS & QSPI_STATUS_ENABLE_Msk) == QSPI_STATUS_ENABLE_Msk); + dmacChnlDisable(spip->dmaRxId); +} + + +/** + * @brief DMA streams allocation. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] rxstream stream to be allocated for RX + * @param[in] txstream stream to be allocated for TX + * @param[in] priority streams IRQ priority + * @return The operation status. + */ +static msg_t qspi_spi_lld_get_dma(SPIDriver* spip, uint8_t rxstream, + uint8_t txstream, uint8_t priority) { + int8_t dmacId = + dmacChnlAllocI(rxstream, priority, + (sam_dmaisr_t)qspi_spi_dma_lld_serve_rx_interrupt, (void*)spip); + if (dmacId < 0) { + return HAL_RET_NO_RESOURCE; + } + spip->dmaRxId = (uint8_t)dmacId; + + dmacId = + dmacChnlAllocI(txstream, priority, + (sam_dmaisr_t)qspi_spi_lld_dma_serve_tx_interrupt, (void*)spip); + if (dmacId < 0) { + dmacChnlFreeI(spip->dmaRxId); + return HAL_RET_NO_RESOURCE; + } + spip->dmaTxId = (uint8_t)dmacId; + + return HAL_RET_SUCCESS; +} + +void qspi_spi_lld_init(void) +{ +#if SAM_SPI_USE_QSPI1 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID9); + SPID9.qspi = QSPI_REGS; + SPID9.clock = SAM_CPU_FREQ; + SPID9.is_qspi = true; +#endif +} + +msg_t qspi_spi_lld_start(SPIDriver* spip) +{ + qspi_registers_t *qspi = spip->qspi; + uint32_t ctrlb = 0; + uint32_t baud_val = 0; + if (spip->state == SPI_STOP) { + if(false) { + + } + #if SAM_SPI_USE_QSPI1 == TRUE + else if(&SPID9 == spip) { + MCLK_REGS->MCLK_AHBMASK |= (MCLK_AHBMASK_QSPI_Msk); + MCLK_REGS->MCLK_APBCMASK |= MCLK_APBCMASK_QSPI_Msk; + msg_t msg = qspi_spi_lld_get_dma(spip, SAM_QSPI1_DMARX_CHANNEL, + SAM_QSPI1_DMATX_CHANNEL, SAM_QSPI1_DMA_PRIO); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + dmacChnlSetTrigSrc(spip->dmaTxId, QSPI_TX); + dmacChnlSetTrigAct(spip->dmaTxId, BURST); + dmacChnlSetTrigSrc(spip->dmaRxId, QSPI_RX); + dmacChnlSetTrigAct(spip->dmaRxId, BURST); + nvicEnableVector(QSPI_IRQn, SAM_QSPI_IRQ_PRIORITY); + } + + } + else { + qspi_spi_lld_disable(spip); + } + #endif + if (spip->config->slave) { + osalDbgAssert(false, "Slave config is not supported on QSPI SPI mode"); + } + qspi->QSPI_CTRLA = QSPI_CTRLA_SWRST_Msk; + + //TODO: Work on this + baud_val = (spip->clock / (spip->config->qspi_cfg.freq)) - 1; + if (baud_val > 255) { + baud_val = 255; + } + qspi->QSPI_BAUD = QSPI_BAUD_BAUD(baud_val) | QSPI_BAUD_CPHA(spip->config->qspi_cfg.cpha) | QSPI_BAUD_CPOL(spip->config->qspi_cfg.cpol); + ctrlb = (spip->config->qspi_cfg.ctrlb & ~(QSPI_CTRLB_FORBIDDEN)); + qspi->QSPI_CTRLB = ctrlb; + qspi->QSPI_CTRLA = QSPI_CTRLA_ENABLE_Msk; + while((qspi->QSPI_STATUS & QSPI_STATUS_ENABLE_Msk) != QSPI_STATUS_ENABLE_Msk); + return HAL_RET_SUCCESS; +} +void qspi_spi_lld_stop(SPIDriver* spip) +{ + qspi_registers_t *qspi = spip->qspi; + if (spip->state == SPI_READY) { + qspi_spi_lld_disable(spip); + dmacChnlFreeI(spip->dmaRxId); + dmacChnlFreeI(spip->dmaTxId); + nvicDisableVector(QSPI_IRQn); + if(false) { + + } + #if SAM_SPI_USE_QSPI1 == TRUE + else if(&SPID9 == spip) { + MCLK_REGS->MCLK_AHBMASK &= ~MCLK_AHBMASK_QSPI_Msk; + MCLK_REGS->MCLK_APBCMASK &= ~MCLK_APBCMASK_QSPI_Msk; + } + } + #endif +} +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) +void qspi_spi_lld_select(SPIDriver* spip) +{ + qspi_registers_t *qspi = spip->qspi; +} +void qspi_spi_lld_unselect(SPIDriver* spip) +{ + qspi_registers_t *qspi = spip->qspi; +} +#endif + +msg_t qspi_spi_lld_ignore(SPIDriver* spip, size_t n) +{ + qspi_registers_t *qspi = spip->qspi; + dmacChnlSetBtCtrl(spip->dmaTxId, + DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, + DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_VALID_Msk); + dmacChnlSetDir(spip->dmaTxId, (uint32_t)&qspi->QSPI_RXDATA, + (uint32_t)&spip->txsource, n); + dmacChnlSetDir(spip->dmaRxId, (uint32_t)&spip->rxsink, + (uint32_t)&qspi->QSPI_RXDATA, n); + dmacChnlEnableIRQn(spip->dmaTxId); + dmacChnlEnableIRQn(spip->dmaRxId); + dmacChnlEnable(spip->dmaRxId); + dmacChnlEnable(spip->dmaTxId); + return HAL_RET_SUCCESS; +} +msg_t qspi_spi_lld_exchange(SPIDriver* spip, size_t n, const void* txbuf, + void* rxbuf) +{ + qspi_registers_t *qspi = spip->qspi; + + dmacChnlSetBtCtrl(spip->dmaTxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_SRCINC_Msk | DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_DSTINC_Msk | DMAC_BTCTRL_VALID_Msk); + dmacChnlSetDir(spip->dmaTxId, (uint32_t)&qspi->QSPI_TXDATA, + (uint32_t)txbuf, n); + dmacChnlSetDir(spip->dmaRxId, (uint32_t)rxbuf, + (uint32_t)&qspi->QSPI_RXDATA, n); + dmacChnlEnableIRQn(spip->dmaTxId); + dmacChnlEnableIRQn(spip->dmaRxId); + dmacChnlEnable(spip->dmaRxId); + dmacChnlEnable(spip->dmaTxId); + return HAL_RET_SUCCESS; +} +msg_t qspi_spi_lld_send(SPIDriver* spip, size_t n, const void* txbuf) +{ + qspi_registers_t *qspi = spip->qspi; + dmacChnlSetBtCtrl(spip->dmaTxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_SRCINC_Msk | DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, DMAC_BTCTRL_BLOCKACT_INT | + DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_VALID_Msk); + dmacChnlSetDir(spip->dmaTxId, (uint32_t)&qspi->QSPI_TXDATA, + (uint32_t)txbuf, n); + dmacChnlSetDir(spip->dmaRxId, (uint32_t)&spip->rxsink, + (uint32_t)&qspi->QSPI_RXDATA, n); + dmacChnlEnableIRQn(spip->dmaTxId); + dmacChnlEnableIRQn(spip->dmaRxId); + dmacChnlEnable(spip->dmaRxId); + dmacChnlEnable(spip->dmaTxId); + return HAL_RET_SUCCESS; +} +msg_t qspi_spi_lld_receive(SPIDriver* spip, size_t n, void* rxbuf) +{ + qspi_registers_t *qspi = spip->qspi; + dmacChnlSetBtCtrl(spip->dmaTxId, DMAC_BTCTRL_BLOCKACT_INT | + DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_VALID_Msk); + dmacChnlSetBtCtrl(spip->dmaRxId, + DMAC_BTCTRL_BLOCKACT_INT | DMAC_BTCTRL_BEATSIZE_BYTE | + DMAC_BTCTRL_DSTINC_Msk | DMAC_BTCTRL_VALID_Msk); + dmacChnlSetDir(spip->dmaTxId, (uint32_t)&qspi->QSPI_TXDATA, + (uint32_t)&spip->txsource, n); + dmacChnlSetDir(spip->dmaRxId, (uint32_t)rxbuf, + (uint32_t)&qspi->QSPI_RXDATA, n); + dmacChnlEnableIRQn(spip->dmaTxId); + dmacChnlEnableIRQn(spip->dmaRxId); + dmacChnlEnable(spip->dmaRxId); + dmacChnlEnable(spip->dmaTxId); + return HAL_RET_SUCCESS; +} +msg_t qspi_spi_lld_stop_transfer(SPIDriver* spip, size_t* sizep) +{ + qspi_registers_t *qspi = spip->qspi; + dmacChnlDisable(spip->dmaTxId); + + while (!(qspi->QSPI_INTFLAG & QSPI_INTFLAG_TXC_Msk)) + /* Size of unprocessed data.*/ + if (sizep != NULL) { + *sizep = dmacChnlGetTransferred(spip->dmaRxId); + } + dmacChnlDisable(spip->dmaRxId); + qspi_spi_lld_disable_irq(spip); + return HAL_RET_SUCCESS; +} +uint16_t qspi_spi_lld_polled_exchange(SPIDriver* spip, uint16_t frame) +{ + qspi_registers_t *qspi = spip->qspi; + qspi->QSPI_TXDATA = frame; + while ((qspi->QSPI_INTFLAG & QSPI_INTFLAG_RXC_Msk) == 0U) { + /* Waiting frame transfer.*/ + } + frame = qspi->QSPI_RXDATA; + return frame; +} + +#if SAM_SPI_USE_QSPI1 == TRUE +OSAL_IRQ_HANDLER(SAM_QSPI_HANDLER) +{ + OSAL_IRQ_EPILOGUE(); + qspi_spi_lld_serve_interrupt(&SPID9); + OSAL_IRQ_PROLOGUE(); +} +#endif +#endif /* HAL_USE_SPI */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld_qspi.h b/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld_qspi.h new file mode 100644 index 0000000000..1a50a88e24 --- /dev/null +++ b/os/hal/ports/SAM/LLD/SPIv1/hal_spi_v2_lld_qspi.h @@ -0,0 +1,147 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_spi_v2_lld.h + * @brief PLATFORM SPI (v2) subsystem low level driver header. + * + * @addtogroup SPI_V2 + * @{ + */ + +#ifndef HAL_SPI_V2_LLD_QSPI_H +#define HAL_SPI_V2_LLD_QSPI_H + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Circular mode support flag. + */ +#define SPI_SUPPORTS_CIRCULAR FALSE + +/** + * @brief Slave mode support flag. + */ +#define SPI_SUPPORTS_SLAVE_MODE TRUE + +#if !defined(SAM_QSPI1_DMATX_CHANNEL) +#define SAM_QSPI1_DMATX_CHANNEL SAM_DMAC_NUM_MAX +#endif + +#if !defined(SAM_QSPI1_DMARX_CHANNEL) +#define SAM_QSPI1_DMARX_CHANNEL SAM_DMAC_NUM_MAX +#endif + +#if !defined(SAM_QSPI1_DMA_PRIO) +#define SAM_QSPI1_DMA_PRIO 1 +#endif +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ + +/** + * @brief QSPI1 SPI Mode driver enable switch. + * @details If set to @p TRUE the support for SPI1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SAM_SPI_USE_QSPI1) || defined(__DOXYGEN__) +#define SAM_SPI_USE_QSPI1 FALSE +#endif + +/** + * @brief SPI Driver requires DMAC to be enabled + * + */ +#if !defined(SAM_DMAC_REQUIRED) +#define SAM_DMAC_REQUIRED +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if SAM_SPI_USE_QSPI1 == TRUE +#if SAM_WSPI_USE_QSPI1 == TRUE +#error "QSPI1: Can only configured as one function only" +#endif +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +typedef struct { + /* CTRLB register */ + uint32_t ctrlb; + /* Desired frequency, it will calculate the baud based on the input clock */ + uint32_t freq; + /* DELAY before SCK, check the calculation on DLYBS on QSPI Driver */ + uint8_t dlybs; + /* CPOL register, check the description in BAUD Register */ + bool cpol; + /* CPHA register */ + bool cpha; +} qspi_spi_config_t; +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ +/** +* @brief SPI9 driver identifier. +*/ +#if (SAM_SPI_USE_QSPI1 == TRUE) || defined(__DOXYGEN__) +extern SPIDriver SPID9; +#endif + +#ifdef __cplusplus +extern "C" { +#endif +void qspi_spi_lld_init(); +msg_t qspi_spi_lld_start(SPIDriver* spip); +void qspi_spi_lld_stop(SPIDriver* spip); +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) +void qspi_spi_lld_select(SPIDriver* spip); +void qspi_spi_lld_unselect(SPIDriver* spip); +#endif +msg_t qspi_spi_lld_ignore(SPIDriver* spip, size_t n); +msg_t qspi_spi_lld_exchange(SPIDriver* spip, size_t n, const void* txbuf, + void* rxbuf); +msg_t qspi_spi_lld_send(SPIDriver* spip, size_t n, const void* txbuf); +msg_t qspi_spi_lld_receive(SPIDriver* spip, size_t n, void* rxbuf); +msg_t qspi_spi_lld_stop_transfer(SPIDriver* spip, size_t* sizep); +uint16_t qspi_spi_lld_polled_exchange(SPIDriver* spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* HAL_SPI_V2_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SAM/LLD/SYSTICKv1/hal_st_lld.c b/os/hal/ports/SAM/LLD/SYSTICKv1/hal_st_lld.c index 9ade8a2134..e0b45be310 100644 --- a/os/hal/ports/SAM/LLD/SYSTICKv1/hal_st_lld.c +++ b/os/hal/ports/SAM/LLD/SYSTICKv1/hal_st_lld.c @@ -29,10 +29,10 @@ /* Driver local definitions. */ /*===========================================================================*/ #if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC -#define ST_HANDLER SysTick_Handler -#define SYSTICK_CK SAM_CPU_FREQ +#define ST_HANDLER SysTick_Handler +#define SYSTICK_CK SAM_CPU_FREQ #elif OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING -#define ST_HANDLER RTC_HANDLER +#define ST_HANDLER RTC_HANDLER #endif /*===========================================================================*/ /* Driver exported variables. */ @@ -72,9 +72,8 @@ static void st_lld_serve_interrupt(void); * * @notapi */ -void st_lld_init(void) -{ - #if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING +void st_lld_init(void) { +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING isAlarmActive = false; PM_REGS->PM_APBAMASK |= PM_APBAMASK_RTC_Msk; /* Connect GENCLK to RTC */ @@ -82,24 +81,26 @@ void st_lld_init(void) /* Reset Peripheral before usage */ RTC_REGS->MODE0.RTC_CTRL = RTC_MODE0_CTRL_SWRST_Msk; - while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == RTC_STATUS_SYNCBUSY_Msk) + while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == + RTC_STATUS_SYNCBUSY_Msk) ; /* Set to 32 */ - RTC_REGS->MODE0.RTC_CTRL = RTC_MODE0_CTRL_PRESCALER(SAM_RTC_DIV) | RTC_MODE0_CTRL_MODE_COUNT32; - while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == RTC_STATUS_SYNCBUSY_Msk) + RTC_REGS->MODE0.RTC_CTRL = + RTC_MODE0_CTRL_PRESCALER(SAM_RTC_DIV) | RTC_MODE0_CTRL_MODE_COUNT32; + while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == + RTC_STATUS_SYNCBUSY_Msk) ; nvicEnableVector(RTC_IRQn, SAM_EIC_IRQ_PRIORITY); - #endif - #if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC +#endif +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC SysTick->LOAD = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1; SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk; /* IRQ enabled.*/ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, SAM_ST_IRQ_PRIORITY); - #endif +#endif } #if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING /** @@ -111,18 +112,20 @@ void st_lld_init(void) * * @notapi */ -void st_lld_start_alarm(systime_t abstime) -{ +void st_lld_start_alarm(systime_t abstime) { RTC_REGS->MODE0.RTC_CTRL &= ~RTC_MODE0_CTRL_ENABLE_Msk; - while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == RTC_STATUS_SYNCBUSY_Msk) + while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == + RTC_STATUS_SYNCBUSY_Msk) ; RTC_REGS->MODE0.RTC_INTFLAG = RTC_MODE0_INTENSET_CMP0_Msk; RTC_REGS->MODE0.RTC_COMP = (uint32_t)abstime; - while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == RTC_STATUS_SYNCBUSY_Msk) + while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == + RTC_STATUS_SYNCBUSY_Msk) ; RTC_REGS->MODE0.RTC_INTENSET = RTC_MODE0_INTENSET_CMP0_Msk; RTC_REGS->MODE0.RTC_CTRL |= RTC_MODE0_CTRL_ENABLE_Msk; - while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == RTC_STATUS_SYNCBUSY_Msk) + while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == + RTC_STATUS_SYNCBUSY_Msk) ; isAlarmActive = true; } @@ -132,12 +135,11 @@ void st_lld_start_alarm(systime_t abstime) * * @notapi */ -void st_lld_stop_alarm(void) -{ - #if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING +void st_lld_stop_alarm(void) { +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING RTC_REGS->MODE0.RTC_INTENCLR = RTC_MODE0_INTENCLR_CMP0_Msk; isAlarmActive = false; - #endif +#endif } /** @@ -149,30 +151,28 @@ void st_lld_stop_alarm(void) * * @notapi */ -bool st_lld_is_alarm_active(void) -{ +bool st_lld_is_alarm_active(void) { return isAlarmActive; } #endif -static void st_lld_serve_interrupt(void) -{ - #if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING +static void st_lld_serve_interrupt(void) { +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING uint8_t isr; /* Get and clear the RTC interrupts. */ isr = RTC_REGS->MODE0.RTC_INTFLAG; RTC_REGS->MODE0.RTC_INTFLAG = isr; RTC_REGS->MODE0.RTC_INTENCLR = isr; - if(isr & RTC_MODE0_INTFLAG_CMP0_Msk) - #endif + if (isr & RTC_MODE0_INTFLAG_CMP0_Msk) +#endif { osalSysLockFromISR(); osalOsTimerHandlerI(); osalSysUnlockFromISR(); } } -OSAL_IRQ_HANDLER(ST_HANDLER) -{ + +OSAL_IRQ_HANDLER(ST_HANDLER) { OSAL_IRQ_PROLOGUE(); st_lld_serve_interrupt(); diff --git a/os/hal/ports/SAM/LLD/SYSTICKv1/hal_st_lld.h b/os/hal/ports/SAM/LLD/SYSTICKv1/hal_st_lld.h index de94a00ccb..4d302e43dc 100644 --- a/os/hal/ports/SAM/LLD/SYSTICKv1/hal_st_lld.h +++ b/os/hal/ports/SAM/LLD/SYSTICKv1/hal_st_lld.h @@ -35,22 +35,24 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ #if HAL_USE_RTC == TRUE && OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING -#error "SYSTICKv1 already uses RTC for freerunning, please change to periodic mode" +#error \ + "SYSTICKv1 already uses RTC for freerunning, please change to periodic mode" #endif #if OSAL_ST_RESOLUTION != 32 -#error "SYSTICKv1 already requires OSAL_ST_RESOLUTION == 32" +#error "SYSTICKv1 requires OSAL_ST_RESOLUTION == 32" #endif /** * @brief SysTick timer IRQ priority. */ #if !defined(SAM_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define SAM_ST_IRQ_PRIORITY 8 +#define SAM_ST_IRQ_PRIORITY 8 #endif /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING #if SAM_RTC_GCLK_SRC_ID == 0 #define SAM_RTC_GCLK_GENDIV SAM_GCLK0_GENDIV #define SAM_RTC_GCLK_SRC_FREQ SAM_GCLK0_SRC_FREQ @@ -81,10 +83,11 @@ #endif #if SAM_RTC_GCLK_GENDIV == 0 #error SAM_RTC_GCLK_GENDIV cannot be 0 -#elif (SAM_RTC_GCLK_GENDIV * OSAL_ST_FREQUENCY * (1UL << SAM_RTC_DIV)) != SAM_RTC_GCLK_SRC_FREQ +#elif (SAM_RTC_GCLK_GENDIV * OSAL_ST_FREQUENCY * (1UL << SAM_RTC_DIV)) != \ + SAM_RTC_GCLK_SRC_FREQ #error SAM_RTC_DIV and SAM_RTC_GCLK_SRC_FREQ does not satisfy for OSAL_ST_FREQUENCY #endif - +#endif /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -98,15 +101,14 @@ /*===========================================================================*/ #ifdef __cplusplus -extern "C" -{ +extern "C" { +#endif +void st_lld_init(void); +#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) +void st_lld_start_alarm(systime_t abstime); +void st_lld_stop_alarm(void); +bool st_lld_is_alarm_active(void); #endif - void st_lld_init(void); - #if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) - void st_lld_start_alarm(systime_t abstime); - void st_lld_stop_alarm(void); - bool st_lld_is_alarm_active(void); - #endif #ifdef __cplusplus } #endif @@ -125,10 +127,10 @@ extern "C" * @notapi */ -static inline systime_t st_lld_get_counter(void) -{ +static inline systime_t st_lld_get_counter(void) { RTC_REGS->MODE0.RTC_READREQ = RTC_READREQ_RREQ_Msk | RTC_READREQ_ADDR(0x10U); - while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == RTC_STATUS_SYNCBUSY_Msk) + while ((RTC_REGS->MODE0.RTC_STATUS & RTC_STATUS_SYNCBUSY_Msk) == + RTC_STATUS_SYNCBUSY_Msk) ; uint32_t counter = (RTC_REGS->MODE0.RTC_COUNT); return counter; @@ -141,12 +143,10 @@ static inline systime_t st_lld_get_counter(void) * * @notapi */ -static inline void st_lld_set_alarm(systime_t abstime) -{ +static inline void st_lld_set_alarm(systime_t abstime) { st_lld_start_alarm(abstime); } -#endif /** * @brief Returns the current alarm time. * @@ -154,11 +154,10 @@ static inline void st_lld_set_alarm(systime_t abstime) * * @notapi */ -static inline systime_t st_lld_get_alarm(void) -{ - return ((RTC_REGS->MODE0.RTC_COMP)); +static inline systime_t st_lld_get_alarm(void) { + return (systime_t)(RTC_REGS->MODE0.RTC_COMP); } - +#endif #endif /* HAL_ST_LLD_H */ /** @} */ diff --git a/os/hal/ports/SAM/SAMD21A/hal_efl_lld.c b/os/hal/ports/SAM/SAMD21A/hal_efl_lld.c index 5fa1c70725..18ca985063 100644 --- a/os/hal/ports/SAM/SAMD21A/hal_efl_lld.c +++ b/os/hal/ports/SAM/SAMD21A/hal_efl_lld.c @@ -27,7 +27,7 @@ /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ -#define SAM_FLASH_SECTOR_SIZE 256 +#define SAM_FLASH_SECTOR_SIZE 256 /*===========================================================================*/ /* Driver exported variables. */ @@ -45,91 +45,85 @@ EFlashDriver EFLD1; /*===========================================================================*/ typedef union { - uint16_t hw[FLASH_PAGE_SIZE / sizeof (uint16_t)]; - uint8_t b[FLASH_PAGE_SIZE / sizeof (uint8_t)]; + uint16_t hw[FLASH_PAGE_SIZE / sizeof(uint16_t)]; + uint8_t b[FLASH_PAGE_SIZE / sizeof(uint8_t)]; } pg_buffer_t; static const flash_descriptor_t efl_lld_descriptor = { - .attributes = FLASH_ATTR_ERASED_IS_ONE | - FLASH_ATTR_MEMORY_MAPPED, - .page_size = FLASH_PAGE_SIZE, - .sectors_count = (FLASH_SIZE - SAM_FLASH_START_OFFSET) / SAM_FLASH_SECTOR_SIZE, - .sectors = NULL, - .sectors_size = SAM_FLASH_SECTOR_SIZE, - .address = (uint8_t *)FLASH_ADDR + SAM_FLASH_START_OFFSET, - .size = FLASH_SIZE -}; + .attributes = FLASH_ATTR_ERASED_IS_ONE | FLASH_ATTR_MEMORY_MAPPED, + .page_size = FLASH_PAGE_SIZE, + .sectors_count = + (FLASH_SIZE - SAM_FLASH_START_OFFSET) / SAM_FLASH_SECTOR_SIZE, + .sectors = NULL, + .sectors_size = SAM_FLASH_SECTOR_SIZE, + .address = (uint8_t*)FLASH_ADDR + SAM_FLASH_START_OFFSET, + .size = FLASH_SIZE}; /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ -static inline void sam_flash_clear_status(EFlashDriver *eflp) -{ +static inline void sam_flash_clear_status(EFlashDriver* eflp) { eflp->flash->NVMCTRL_STATUS = 0x001F; } -static inline void sam_flash_exc_cmd(EFlashDriver *eflp, uint16_t cmd) -{ - eflp->flash->NVMCTRL_CTRLA = (uint16_t)(NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD(cmd)); +static inline void sam_flash_exc_cmd(EFlashDriver* eflp, uint16_t cmd) { + eflp->flash->NVMCTRL_CTRLA = + (uint16_t)(NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD(cmd)); } -static inline void sam_flash_set_addr(EFlashDriver *eflp, uint32_t addr) -{ +static inline void sam_flash_set_addr(EFlashDriver* eflp, uint32_t addr) { eflp->flash->NVMCTRL_ADDR = (addr >> 1) & NVMCTRL_ADDR_ADDR_Msk; } -static inline bool sam_flash_is_busy(EFlashDriver *eflp) -{ - return (eflp->flash->NVMCTRL_INTFLAG & NVMCTRL_INTFLAG_READY_Msk) != NVMCTRL_INTFLAG_READY_Msk; +static inline bool sam_flash_is_busy(EFlashDriver* eflp) { + return (eflp->flash->NVMCTRL_INTFLAG & NVMCTRL_INTFLAG_READY_Msk) != + NVMCTRL_INTFLAG_READY_Msk; } -static inline void sam_flash_wait_busy(EFlashDriver *eflp) -{ - while(sam_flash_is_busy(eflp)); +static inline void sam_flash_wait_busy(EFlashDriver* eflp) { + while (sam_flash_is_busy(eflp)) + ; } -static inline flash_error_t sam_flash_get_error(EFlashDriver *eflp) -{ - uint16_t stat = (eflp->flash->NVMCTRL_STATUS & (NVMCTRL_STATUS_PROGE_Msk | - NVMCTRL_STATUS_NVME_Msk)); +static inline flash_error_t sam_flash_get_error(EFlashDriver* eflp) { + uint16_t stat = (eflp->flash->NVMCTRL_STATUS & + (NVMCTRL_STATUS_PROGE_Msk | NVMCTRL_STATUS_NVME_Msk)); sam_flash_clear_status(eflp); - if((stat & NVMCTRL_STATUS_NVME_Msk) != 0) - { + if ((stat & NVMCTRL_STATUS_NVME_Msk) != 0) { return FLASH_ERROR_HW_FAILURE; } - if((stat & NVMCTRL_STATUS_PROGE_Msk) != 0) - { + if ((stat & NVMCTRL_STATUS_PROGE_Msk) != 0) { return FLASH_ERROR_PROGRAM; } return FLASH_NO_ERROR; } -static inline uint16_t read_unaligned_uint16(const void *data) -{ +static inline uint16_t read_unaligned_uint16(const void* data) { union { uint16_t u16; uint8_t u8[2]; } res; - const uint8_t *d = (const uint8_t *)data; + + const uint8_t* d = (const uint8_t*)data; res.u8[0] = d[0]; res.u8[1] = d[1]; return res.u16; } -static flash_error_t sam_flash_page_write(EFlashDriver *eflp, uint8_t *dest, const uint8_t *src, size_t n) -{ - osalDbgCheck((eflp != NULL) && ((uint32_t)dest % sizeof(uint16_t) == 0) - && (n > 0U) && (n <= FLASH_PAGE_SIZE) && (n % 2 == 0)); +static flash_error_t sam_flash_page_write(EFlashDriver* eflp, uint8_t* dest, + const uint8_t* src, size_t n) { + osalDbgCheck((eflp != NULL) && ((uint32_t)dest % sizeof(uint16_t) == 0) && + (n > 0U) && (n <= FLASH_PAGE_SIZE) && (n % 2 == 0)); flash_error_t err = FLASH_NO_ERROR; n /= 2; - volatile uint16_t *dst_addr = (volatile uint16_t *)dest; - const uint16_t *src_addr = (uint16_t *)src; + volatile uint16_t* dst_addr = (volatile uint16_t*)dest; + const uint16_t* src_addr = (uint16_t*)src; sam_flash_wait_busy(eflp); sam_flash_exc_cmd(eflp, NVMCTRL_CTRLA_CMD_PBC_Val); sam_flash_wait_busy(eflp); uint32_t i; - for (i=0; i<(FLASH_PAGE_SIZE/2) && n; i++) { + for (i = 0; i < (FLASH_PAGE_SIZE / 2) && n; i++) { *dst_addr = read_unaligned_uint16(src_addr); src_addr++; dst_addr++; @@ -138,7 +132,7 @@ static flash_error_t sam_flash_page_write(EFlashDriver *eflp, uint8_t *dest, con sam_flash_exc_cmd(eflp, NVMCTRL_CTRLA_CMD_WP_Val); sam_flash_wait_busy(eflp); err = sam_flash_get_error(eflp); - if(memcmp(dest, src, n) != 0) { + if (memcmp(dest, src, n) != 0) { err = FLASH_ERROR_PROGRAM; } return err; @@ -173,18 +167,15 @@ void efl_lld_init(void) { * * @notapi */ -void efl_lld_start(EFlashDriver *eflp) { +void efl_lld_start(EFlashDriver* eflp) { if (eflp->state == FLASH_STOP) { /* Enables the peripheral.*/ #if SAM_EFL_USE_EFL1 == TRUE - if (&EFLD1 == eflp) { - - } + if (&EFLD1 == eflp) {} #endif } /* Configures the peripheral.*/ - } /** @@ -194,16 +185,14 @@ void efl_lld_start(EFlashDriver *eflp) { * * @notapi */ -void efl_lld_stop(EFlashDriver *eflp) { +void efl_lld_stop(EFlashDriver* eflp) { if (eflp->state == FLASH_READY) { /* Resets the peripheral.*/ /* Disables the peripheral.*/ #if SAM_EFL_USE_EFL1 == TRUE - if (&EFLD1 == eflp) { - - } + if (&EFLD1 == eflp) {} #endif } } @@ -216,7 +205,7 @@ void efl_lld_stop(EFlashDriver *eflp) { * * @notapi */ -const flash_descriptor_t *efl_lld_get_descriptor(void *instance) { +const flash_descriptor_t* efl_lld_get_descriptor(void* instance) { (void)instance; @@ -238,9 +227,9 @@ const flash_descriptor_t *efl_lld_get_descriptor(void *instance) { * * @notapi */ -flash_error_t efl_lld_read(void *instance, flash_offset_t offset, - size_t n, uint8_t *rp) { - EFlashDriver *devp = (EFlashDriver *)instance; +flash_error_t efl_lld_read(void* instance, flash_offset_t offset, size_t n, + uint8_t* rp) { + EFlashDriver* devp = (EFlashDriver*)instance; flash_error_t err = FLASH_NO_ERROR; osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U)); @@ -258,7 +247,7 @@ flash_error_t efl_lld_read(void *instance, flash_offset_t offset, /* IMPLEMENT */ sam_flash_clear_status(devp); - memcpy((void *)rp, (const void *)efl_lld_descriptor.address + offset, n); + memcpy((void*)rp, (const void*)efl_lld_descriptor.address + offset, n); /* Ready state again.*/ devp->state = FLASH_READY; return err; @@ -281,9 +270,9 @@ flash_error_t efl_lld_read(void *instance, flash_offset_t offset, * * @notapi */ -flash_error_t efl_lld_program(void *instance, flash_offset_t offset, - size_t n, const uint8_t *pp) { - EFlashDriver *devp = (EFlashDriver *)instance; +flash_error_t efl_lld_program(void* instance, flash_offset_t offset, size_t n, + const uint8_t* pp) { + EFlashDriver* devp = (EFlashDriver*)instance; flash_error_t err = FLASH_NO_ERROR; osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U)); @@ -303,15 +292,15 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset, /* IMPLEMENT */ sam_flash_wait_busy(devp); sam_flash_clear_status(devp); - uint8_t *address; + uint8_t* address; /* Programming address aligned to flash lines.*/ - address = (uint8_t *)(efl_lld_descriptor.address + (offset)); + address = (uint8_t*)(efl_lld_descriptor.address + (offset)); size_t pg_offset = ((uint32_t)address) % FLASH_PAGE_SIZE; /* If pg_offset occurred, write fully in that page first */ - if(pg_offset > 0 && n > FLASH_PAGE_SIZE) { + if (pg_offset > 0 && n > FLASH_PAGE_SIZE) { size_t bytes_writing = FLASH_PAGE_SIZE - pg_offset; err = sam_flash_page_write(devp, address, pp, bytes_writing); - if(err != FLASH_NO_ERROR) { + if (err != FLASH_NO_ERROR) { goto error; } address += bytes_writing; @@ -320,9 +309,9 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset, } size_t num_pages = n / FLASH_PAGE_SIZE; - while(num_pages > 0U) { + while (num_pages > 0U) { err = sam_flash_page_write(devp, address, pp, FLASH_PAGE_SIZE); - if(err != FLASH_NO_ERROR) { + if (err != FLASH_NO_ERROR) { goto error; } address += FLASH_PAGE_SIZE; @@ -330,7 +319,7 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset, num_pages--; n -= FLASH_PAGE_SIZE; } - if(n > 0) { + if (n > 0) { err = sam_flash_page_write(devp, address, pp, n); } error: @@ -354,8 +343,8 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset, * * @notapi */ -flash_error_t efl_lld_start_erase_all(void *instance) { - (void) instance; +flash_error_t efl_lld_start_erase_all(void* instance) { + (void)instance; return FLASH_ERROR_UNIMPLEMENTED; } @@ -371,9 +360,9 @@ flash_error_t efl_lld_start_erase_all(void *instance) { * * @notapi */ -flash_error_t efl_lld_start_erase_sector(void *instance, +flash_error_t efl_lld_start_erase_sector(void* instance, flash_sector_t sector) { - EFlashDriver *devp = (EFlashDriver *)instance; + EFlashDriver* devp = (EFlashDriver*)instance; osalDbgCheck(instance != NULL); osalDbgCheck(sector < efl_lld_descriptor.sectors_count); @@ -391,8 +380,9 @@ flash_error_t efl_lld_start_erase_sector(void *instance, /* IMPLEMENT */ sam_flash_wait_busy(devp); sam_flash_clear_status(devp); - uint32_t address = (uint32_t)(efl_lld_descriptor.address + - flashGetSectorOffset(getBaseFlash(devp), sector)); + uint32_t address = + (uint32_t)(efl_lld_descriptor.address + + flashGetSectorOffset(getBaseFlash(devp), sector)); osalDbgCheck(address % SAM_FLASH_SECTOR_SIZE == 0); sam_flash_set_addr(devp, address); sam_flash_exc_cmd(devp, NVMCTRL_CTRLA_CMD_ER_Val); @@ -414,8 +404,8 @@ flash_error_t efl_lld_start_erase_sector(void *instance, * * @api */ -flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) { - EFlashDriver *devp = (EFlashDriver *)instance; +flash_error_t efl_lld_query_erase(void* instance, uint32_t* msec) { + EFlashDriver* devp = (EFlashDriver*)instance; flash_error_t err = FLASH_NO_ERROR; (void)msec; @@ -424,20 +414,18 @@ flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) { if (devp->state == FLASH_ERASE) { /* IMPLEMENT */ - if(sam_flash_is_busy(devp) == 0) { + if (sam_flash_is_busy(devp) == 0) { devp->state = FLASH_READY; err = sam_flash_get_error(devp); - } - else { - if(msec != NULL) { + } else { + if (msec != NULL) { *msec = (uint32_t)SAM_FLASH_WAIT_TIME_MS; } err = FLASH_BUSY_ERASING; } - } - else { + } else { err = FLASH_NO_ERROR; } return err; @@ -456,10 +444,10 @@ flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) { * * @notapi */ -flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) { - EFlashDriver *devp = (EFlashDriver *)instance; +flash_error_t efl_lld_verify_erase(void* instance, flash_sector_t sector) { + EFlashDriver* devp = (EFlashDriver*)instance; flash_error_t err = FLASH_NO_ERROR; - uint32_t *address; + uint32_t* address; unsigned i; osalDbgCheck(instance != NULL); @@ -474,13 +462,12 @@ flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) { /* IMPLEMENT */ /* Address of the sector.*/ - address = (uint32_t *)(efl_lld_descriptor.address + - flashGetSectorOffset(getBaseFlash(devp), sector)); + address = (uint32_t*)(efl_lld_descriptor.address + + flashGetSectorOffset(getBaseFlash(devp), sector)); devp->state = FLASH_READ; osalDbgCheck((uint32_t)address % SAM_FLASH_SECTOR_SIZE == 0); /* Scanning the sector space.*/ - for (i = 0U; i < SAM_FLASH_SECTOR_SIZE / sizeof(uint32_t); i++) - { + for (i = 0U; i < SAM_FLASH_SECTOR_SIZE / sizeof(uint32_t); i++) { if (*address != 0xFFFFFFFFUL) { err = FLASH_ERROR_VERIFY; break; diff --git a/os/hal/ports/SAM/SAMD21A/hal_efl_lld.h b/os/hal/ports/SAM/SAMD21A/hal_efl_lld.h index 85594d6e2e..18483dc376 100644 --- a/os/hal/ports/SAM/SAMD21A/hal_efl_lld.h +++ b/os/hal/ports/SAM/SAMD21A/hal_efl_lld.h @@ -42,7 +42,7 @@ * @note The default is @p FALSE. */ #if !defined(SAM_EFL_USE_EFL1) || defined(__DOXYGEN__) -#define SAM_EFL_USE_EFL1 FALSE +#define SAM_EFL_USE_EFL1 FALSE #endif /** @} */ @@ -55,7 +55,7 @@ #endif #if !defined(SAM_FLASH_START_OFFSET) && !defined(__DOXYGEN__) -#define SAM_FLASH_START_OFFSET FLASH_SIZE/2 +#define SAM_FLASH_START_OFFSET FLASH_SIZE / 2 #endif #if SAM_FLASH_START_OFFSET > FLASH_SIZE @@ -73,16 +73,16 @@ /** * @brief Low level fields of the embedded flash driver structure. */ -#define efl_lld_driver_fields \ - /* Dummy field, it is not needed.*/ \ - nvmctrl_registers_t *flash +#define efl_lld_driver_fields \ + /* Dummy field, it is not needed.*/ \ + nvmctrl_registers_t* flash /** * @brief Low level fields of the embedded flash configuration structure. */ -#define efl_lld_config_fields \ - /* Dummy configuration, it is not needed.*/ \ - uint32_t dummy +#define efl_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy /*===========================================================================*/ /* External declarations. */ @@ -95,19 +95,18 @@ extern EFlashDriver EFLD1; #ifdef __cplusplus extern "C" { #endif - void efl_lld_init(void); - void efl_lld_start(EFlashDriver *eflp); - void efl_lld_stop(EFlashDriver *eflp); - const flash_descriptor_t *efl_lld_get_descriptor(void *instance); - flash_error_t efl_lld_read(void *instance, flash_offset_t offset, - size_t n, uint8_t *rp); - flash_error_t efl_lld_program(void *instance, flash_offset_t offset, - size_t n, const uint8_t *pp); - flash_error_t efl_lld_start_erase_all(void *instance); - flash_error_t efl_lld_start_erase_sector(void *instance, - flash_sector_t sector); - flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec); - flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector); +void efl_lld_init(void); +void efl_lld_start(EFlashDriver* eflp); +void efl_lld_stop(EFlashDriver* eflp); +const flash_descriptor_t* efl_lld_get_descriptor(void* instance); +flash_error_t efl_lld_read(void* instance, flash_offset_t offset, size_t n, + uint8_t* rp); +flash_error_t efl_lld_program(void* instance, flash_offset_t offset, size_t n, + const uint8_t* pp); +flash_error_t efl_lld_start_erase_all(void* instance); +flash_error_t efl_lld_start_erase_sector(void* instance, flash_sector_t sector); +flash_error_t efl_lld_query_erase(void* instance, uint32_t* msec); +flash_error_t efl_lld_verify_erase(void* instance, flash_sector_t sector); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/SAM/SAMD21A/hal_lld.c b/os/hal/ports/SAM/SAMD21A/hal_lld.c index a94b5ea425..080bcdacf2 100644 --- a/os/hal/ports/SAM/SAMD21A/hal_lld.c +++ b/os/hal/ports/SAM/SAMD21A/hal_lld.c @@ -61,125 +61,136 @@ static void sam_osculp32k_init(void); * * @notapi */ -void hal_lld_init(void) -{ - sam_clock_init(); +void hal_lld_init(void) { + sam_clock_init(); #if defined(SAM_DMAC_REQUIRED) - dmacInit(); + dmacInit(); #endif } -static void sam_clock_init(void) -{ - NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_RWS(SAM_NVM_DELAY); - sam_xosc32_init(); - sam_xosc_init(); - sam_gclk_init(1, SAM_GCLK1_SRC, SAM_GCLK1_GENDIV, SAM_GCLK1_ENABLE); - /* Init dfll48m when gclk1 is configured */ - sam_dfll48m_init(); - sam_gclk_init(2, SAM_GCLK2_SRC, SAM_GCLK2_GENDIV, SAM_GCLK2_ENABLE); - sam_gclk_init(3, SAM_GCLK3_SRC, SAM_GCLK3_GENDIV, SAM_GCLK3_ENABLE); - sam_gclk_init(4, SAM_GCLK4_SRC, SAM_GCLK4_GENDIV, SAM_GCLK4_ENABLE); - sam_gclk_init(5, SAM_GCLK5_SRC, SAM_GCLK5_GENDIV, SAM_GCLK5_ENABLE); - sam_gclk_init(6, SAM_GCLK6_SRC, SAM_GCLK6_GENDIV, SAM_GCLK6_ENABLE); - sam_gclk_init(7, SAM_GCLK7_SRC, SAM_GCLK7_GENDIV, SAM_GCLK7_ENABLE); - sam_gclk_init(8, SAM_GCLK8_SRC, SAM_GCLK8_GENDIV, SAM_GCLK8_ENABLE); - sam_gclk_init(0, SAM_GCLK0_SRC, SAM_GCLK0_GENDIV, TRUE); - sam_osc8m_init(); - sam_osc32k_init(); - sam_osculp32k_init(); - PM_REGS->PM_CPUSEL = PM_CPUSEL_CPUDIV(SAM_CPUDIV); - PM_REGS->PM_APBASEL = PM_APBASEL_APBADIV(SAM_APBADIV); - PM_REGS->PM_APBBSEL = PM_APBBSEL_APBBDIV(SAM_APBBDIV); - PM_REGS->PM_APBCSEL = PM_APBCSEL_APBCDIV(SAM_APBCDIV); +static void sam_clock_init(void) { + NVMCTRL_REGS->NVMCTRL_CTRLB = NVMCTRL_CTRLB_RWS(SAM_NVM_DELAY); + sam_xosc32_init(); + sam_xosc_init(); + sam_gclk_init(1, SAM_GCLK1_SRC, SAM_GCLK1_GENDIV, SAM_GCLK1_ENABLE); + /* Init dfll48m when gclk1 is configured */ + sam_dfll48m_init(); + sam_gclk_init(2, SAM_GCLK2_SRC, SAM_GCLK2_GENDIV, SAM_GCLK2_ENABLE); + sam_gclk_init(3, SAM_GCLK3_SRC, SAM_GCLK3_GENDIV, SAM_GCLK3_ENABLE); + sam_gclk_init(4, SAM_GCLK4_SRC, SAM_GCLK4_GENDIV, SAM_GCLK4_ENABLE); + sam_gclk_init(5, SAM_GCLK5_SRC, SAM_GCLK5_GENDIV, SAM_GCLK5_ENABLE); + sam_gclk_init(6, SAM_GCLK6_SRC, SAM_GCLK6_GENDIV, SAM_GCLK6_ENABLE); + sam_gclk_init(7, SAM_GCLK7_SRC, SAM_GCLK7_GENDIV, SAM_GCLK7_ENABLE); + sam_gclk_init(8, SAM_GCLK8_SRC, SAM_GCLK8_GENDIV, SAM_GCLK8_ENABLE); + sam_gclk_init(0, SAM_GCLK0_SRC, SAM_GCLK0_GENDIV, TRUE); + sam_osc8m_init(); + sam_osc32k_init(); + sam_osculp32k_init(); + PM_REGS->PM_CPUSEL = PM_CPUSEL_CPUDIV(SAM_CPUDIV); + PM_REGS->PM_APBASEL = PM_APBASEL_APBADIV(SAM_APBADIV); + PM_REGS->PM_APBBSEL = PM_APBBSEL_APBBDIV(SAM_APBBDIV); + PM_REGS->PM_APBCSEL = PM_APBCSEL_APBCDIV(SAM_APBCDIV); } -static void sam_xosc32_init(void) -{ +static void sam_xosc32_init(void) { #if SAM_XOSC32_ENABLED == 1 - SYSCTRL_REGS->SYSCTRL_XOSC32K = SYSCTRL_XOSC32K_STARTUP(5) | SYSCTRL_XOSC32K_EN32K_Msk | SYSCTRL_XOSC32K_XTALEN_Msk; - SYSCTRL_REGS->SYSCTRL_XOSC32K |= SYSCTRL_XOSC32K_ENABLE_Msk; - while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_XOSC32KRDY_Msk) != SYSCTRL_PCLKSR_XOSC32KRDY_Msk) - ; - GCLK_REGS->GCLK_GENCTRL = GCLK_GENCTRL_ID(1) | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_IDC(1) | GCLK_GENCTRL_GENEN_Msk; - while ((GCLK_REGS->GCLK_STATUS & GCLK_STATUS_SYNCBUSY_Msk) == GCLK_STATUS_SYNCBUSY_Msk) - ; + SYSCTRL_REGS->SYSCTRL_XOSC32K = SYSCTRL_XOSC32K_STARTUP(5) | + SYSCTRL_XOSC32K_EN32K_Msk | + SYSCTRL_XOSC32K_XTALEN_Msk; + SYSCTRL_REGS->SYSCTRL_XOSC32K |= SYSCTRL_XOSC32K_ENABLE_Msk; + while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_XOSC32KRDY_Msk) != + SYSCTRL_PCLKSR_XOSC32KRDY_Msk) + ; + GCLK_REGS->GCLK_GENCTRL = GCLK_GENCTRL_ID(1) | GCLK_GENCTRL_SRC_XOSC32K | + GCLK_GENCTRL_IDC(1) | GCLK_GENCTRL_GENEN_Msk; + while ((GCLK_REGS->GCLK_STATUS & GCLK_STATUS_SYNCBUSY_Msk) == + GCLK_STATUS_SYNCBUSY_Msk) + ; #else - SYSCTRL_REGS->SYSCTRL_XOSC32K = 0; + SYSCTRL_REGS->SYSCTRL_XOSC32K = 0; #endif } -static void sam_xosc_init(void) -{ +static void sam_xosc_init(void) { #if SAM_XOSC_ENABLED == 1 - SYSCTRL_REGS->SYSCTRL_XOSC = SYSCTRL_XOSC_STARTUP(5) | SYSCTRL_XOSC_XTALEN_Msk | SYSCTRL_XOSC_AMPGC_Msk; - SYSCTRL_REGS->SYSCTRL_XOSC |= SYSCTRL_XOSC_ENABLE_Msk; - while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_XOSCRDY_Msk) != SYSCTRL_PCLKSR_XOSCRDY_Msk) - ; - GCLK_REGS->GCLK_GENCTRL = GCLK_GENCTRL_ID(1) | GCLK_GENCTRL_SRC_XOSC | GCLK_GENCTRL_IDC(1) | GCLK_GENCTRL_GENEN_Msk; - while ((GCLK_REGS->GCLK_STATUS & GCLK_STATUS_SYNCBUSY_Msk) == GCLK_STATUS_SYNCBUSY_Msk) - ; + SYSCTRL_REGS->SYSCTRL_XOSC = SYSCTRL_XOSC_STARTUP(5) | + SYSCTRL_XOSC_XTALEN_Msk | SYSCTRL_XOSC_AMPGC_Msk; + SYSCTRL_REGS->SYSCTRL_XOSC |= SYSCTRL_XOSC_ENABLE_Msk; + while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_XOSCRDY_Msk) != + SYSCTRL_PCLKSR_XOSCRDY_Msk) + ; + GCLK_REGS->GCLK_GENCTRL = GCLK_GENCTRL_ID(1) | GCLK_GENCTRL_SRC_XOSC | + GCLK_GENCTRL_IDC(1) | GCLK_GENCTRL_GENEN_Msk; + while ((GCLK_REGS->GCLK_STATUS & GCLK_STATUS_SYNCBUSY_Msk) == + GCLK_STATUS_SYNCBUSY_Msk) + ; #else - SYSCTRL_REGS->SYSCTRL_XOSC = 0; + SYSCTRL_REGS->SYSCTRL_XOSC = 0; #endif } -static void sam_osc8m_init(void) -{ +static void sam_osc8m_init(void) { #if SAM_OSC8M_ENABLED == 1 // SYSCTRL_REGS->SYSCTRL_OSC8M = 0; // TODO: Init osc8m properly #else - SYSCTRL_REGS->SYSCTRL_OSC8M = 0; + SYSCTRL_REGS->SYSCTRL_OSC8M = 0; #endif } -static void sam_osc32k_init(void) -{ +static void sam_osc32k_init(void) { #if SAM_OSC32K_ENABLED == 1 // SYSCTRL_REGS->SYSCTRL_OSC32K = 0; // TODO: Init osc32k properly #else - SYSCTRL_REGS->SYSCTRL_OSCULP32K = 0; + SYSCTRL_REGS->SYSCTRL_OSCULP32K = 0; #endif } -static void sam_osculp32k_init(void) -{ - SYSCTRL_REGS->SYSCTRL_OSCULP32K = 0; +static void sam_osculp32k_init(void) { + SYSCTRL_REGS->SYSCTRL_OSCULP32K = 0; } -static void sam_dfll48m_init() -{ +static void sam_dfll48m_init() { #if SAM_DFLL48_ENABLED == 1 - /****************** DFLL Initialization *********************************/ - SYSCTRL_REGS->SYSCTRL_DFLLCTRL &= ~SYSCTRL_DFLLCTRL_ONDEMAND_Msk; - - while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLRDY_Msk) != SYSCTRL_PCLKSR_DFLLRDY_Msk) - ; - - /*Load Calibration Value*/ - uint8_t calibCoarse = (uint8_t)(((*(uint32_t *)0x806024) >> 26) & 0x3f); - calibCoarse = (((calibCoarse) == 0x3F) ? 0x1F : (calibCoarse)); - uint16_t calibFine = (uint16_t)(((*(uint32_t *)0x806028)) & 0x3ff); - - SYSCTRL_REGS->SYSCTRL_DFLLVAL = SYSCTRL_DFLLVAL_COARSE(calibCoarse) | SYSCTRL_DFLLVAL_FINE(calibFine); - GCLK_REGS->GCLK_CLKCTRL = GCLK_CLKCTRL_GEN_GCLK1 | GCLK_CLKCTRL_CLKEN_Msk | GCLK_CLKCTRL_ID_DFLL48; - while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLRDY_Msk) != SYSCTRL_PCLKSR_DFLLRDY_Msk) - ; - - SYSCTRL_REGS->SYSCTRL_DFLLMUL = SYSCTRL_DFLLMUL_MUL(1464) | SYSCTRL_DFLLMUL_FSTEP(511) | SYSCTRL_DFLLMUL_CSTEP(31); - - while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLRDY_Msk) != SYSCTRL_PCLKSR_DFLLRDY_Msk) - ; - - /* Configure DFLL */ - SYSCTRL_REGS->SYSCTRL_DFLLCTRL = SYSCTRL_DFLLCTRL_ENABLE_Msk | SYSCTRL_DFLLCTRL_MODE_Msk | SYSCTRL_DFLLCTRL_WAITLOCK(1); - - while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLLCKF_Msk) != SYSCTRL_PCLKSR_DFLLLCKF_Msk) - ; + /****************** DFLL Initialization *********************************/ + SYSCTRL_REGS->SYSCTRL_DFLLCTRL &= ~SYSCTRL_DFLLCTRL_ONDEMAND_Msk; + + while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLRDY_Msk) != + SYSCTRL_PCLKSR_DFLLRDY_Msk) + ; + + /*Load Calibration Value*/ + uint8_t calibCoarse = (uint8_t)(((*(uint32_t*)0x806024) >> 26) & 0x3f); + calibCoarse = (((calibCoarse) == 0x3F) ? 0x1F : (calibCoarse)); + uint16_t calibFine = (uint16_t)(((*(uint32_t*)0x806028)) & 0x3ff); + + SYSCTRL_REGS->SYSCTRL_DFLLVAL = + SYSCTRL_DFLLVAL_COARSE(calibCoarse) | SYSCTRL_DFLLVAL_FINE(calibFine); + GCLK_REGS->GCLK_CLKCTRL = + GCLK_CLKCTRL_GEN_GCLK1 | GCLK_CLKCTRL_CLKEN_Msk | GCLK_CLKCTRL_ID_DFLL48; + while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLRDY_Msk) != + SYSCTRL_PCLKSR_DFLLRDY_Msk) + ; + + SYSCTRL_REGS->SYSCTRL_DFLLMUL = SYSCTRL_DFLLMUL_MUL(1464) | + SYSCTRL_DFLLMUL_FSTEP(511) | + SYSCTRL_DFLLMUL_CSTEP(31); + + while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLRDY_Msk) != + SYSCTRL_PCLKSR_DFLLRDY_Msk) + ; + + /* Configure DFLL */ + SYSCTRL_REGS->SYSCTRL_DFLLCTRL = SYSCTRL_DFLLCTRL_ENABLE_Msk | + SYSCTRL_DFLLCTRL_MODE_Msk | + SYSCTRL_DFLLCTRL_WAITLOCK(1); + + while ((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLLCKF_Msk) != + SYSCTRL_PCLKSR_DFLLLCKF_Msk) + ; #else - SYSCTRL_REGS->SYSCTRL_DFLLCTRL = 0; + SYSCTRL_REGS->SYSCTRL_DFLLCTRL = 0; #endif } diff --git a/os/hal/ports/SAM/SAMD21A/hal_lld.h b/os/hal/ports/SAM/SAMD21A/hal_lld.h index e22e0d6d72..3f02059328 100644 --- a/os/hal/ports/SAM/SAMD21A/hal_lld.h +++ b/os/hal/ports/SAM/SAMD21A/hal_lld.h @@ -28,87 +28,86 @@ /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ -#define SAM_DMAC_CHAN_NUM 12 -#define SAM_EVSYS_CHAN_NUM 12 +#define SAM_DMAC_CHAN_NUM 12 +#define SAM_EVSYS_CHAN_NUM 12 /** * @brief Requires use of SPIv2 driver model. */ -#define HAL_LLD_SELECT_SPI_V2 TRUE +#define HAL_LLD_SELECT_SPI_V2 TRUE /** * @name Platform identification macros * @{ */ -#define PLATFORM_NAME "SAMD21" - -#define SAM_MAX_FREQ_SYSCLK 48000000UL - -#define SAM_MAX_FREQ_GCLK 48000000UL - -#define SAM_OSC8_VAL 1000000UL -#define SAM_OSC32K_VAL 32000UL - -#define SAM_XOSC_MAX_VAL 32000000UL -#define SAM_XOSC32K_VAL 32768UL -#define SAM_DFLL48_VAL 48000000UL - -#define RTC_HANDLER Vector4C -#define EIC_HANDLER Vector50 -#define DMAC_HANDLER Vector58 -#define SERCOM0_HANDLER Vector64 -#define SERCOM1_HANDLER Vector68 -#define SERCOM2_HANDLER Vector6C -#define SERCOM3_HANDLER Vector70 -#define SERCOM4_HANDLER Vector74 -#define SERCOM5_HANDLER Vector78 -#define TCC0_HANDLER Vector7C -#define TCC1_HANDLER Vector80 -#define TC2_HANDLER Vector84 -#define TC3_HANDLER Vector88 -#define TC4_HANDLER Vector8C -#define TC5_HANDLER Vector90 -#define TC6_HANDLER Vector94 -#define TC7_HANDLER Vector98 -#define ADC_HANDLER Vector9C -#define AC_HANDLER VectorA0 -#define DAC_HANDLER VectorA4 -#define PTC_HANDLER VectorA8 -#define I2S_HANDLER VectorAC +#define PLATFORM_NAME "SAMD21" + +#define SAM_MAX_FREQ_SYSCLK 48000000UL + +#define SAM_MAX_FREQ_GCLK 48000000UL + +#define SAM_OSC8_VAL 1000000UL +#define SAM_OSC32K_VAL 32000UL + +#define SAM_XOSC_MAX_VAL 32000000UL +#define SAM_XOSC32K_VAL 32768UL +#define SAM_DFLL48_VAL 48000000UL + +#define RTC_HANDLER Vector4C +#define EIC_HANDLER Vector50 +#define DMAC_HANDLER Vector58 +#define SERCOM0_HANDLER Vector64 +#define SERCOM1_HANDLER Vector68 +#define SERCOM2_HANDLER Vector6C +#define SERCOM3_HANDLER Vector70 +#define SERCOM4_HANDLER Vector74 +#define SERCOM5_HANDLER Vector78 +#define TCC0_HANDLER Vector7C +#define TCC1_HANDLER Vector80 +#define TC2_HANDLER Vector84 +#define TC3_HANDLER Vector88 +#define TC4_HANDLER Vector8C +#define TC5_HANDLER Vector90 +#define TC6_HANDLER Vector94 +#define TC7_HANDLER Vector98 +#define ADC_HANDLER Vector9C +#define AC_HANDLER VectorA0 +#define DAC_HANDLER VectorA4 +#define PTC_HANDLER VectorA8 +#define I2S_HANDLER VectorAC /** * @brief Enables or disables the HSI clock source. */ #if !defined(SAM_OSC8_ENABLED) || defined(__DOXYGEN__) -#define SAM_OSC8_ENABLED TRUE +#define SAM_OSC8_ENABLED TRUE #endif /** * @brief Enables or disables the LSI clock source. */ #if !defined(SAM_OSC32K_ENABLED) || defined(__DOXYGEN__) -#define SAM_OSC32K_ENABLED FALSE +#define SAM_OSC32K_ENABLED FALSE #endif /** * @brief Enables or disables the HSE clock source. */ #if !defined(SAM_XOSC_ENABLED) || defined(__DOXYGEN__) -#define SAM_XOSC_ENABLED FALSE +#define SAM_XOSC_ENABLED FALSE #endif /** * @brief Enables or disables the LSE clock source. */ #if !defined(SAM_XOSC32_ENABLED) || defined(__DOXYGEN__) -#define SAM_XOSC32_ENABLED TRUE +#define SAM_XOSC32_ENABLED TRUE #endif - /** * @brief Enables or disables the LSE clock source. */ #if !defined(SAM_DFLL48_ENABLED) || defined(__DOXYGEN__) -#define SAM_DFLL48_ENABLED TRUE +#define SAM_DFLL48_ENABLED TRUE #endif /** @} */ @@ -152,7 +151,7 @@ #ifdef __cplusplus extern "C" { #endif - void hal_lld_init(void); +void hal_lld_init(void); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/SAM/SAMD21A/sam_clk.c b/os/hal/ports/SAM/SAMD21A/sam_clk.c index da825ee5a8..c495cc6018 100644 --- a/os/hal/ports/SAM/SAMD21A/sam_clk.c +++ b/os/hal/ports/SAM/SAMD21A/sam_clk.c @@ -1,27 +1,32 @@ #include "hal.h" #include "sam_clk.h" -void sam_gclk_init(uint32_t id, uint32_t sysctrl_src, uint16_t gendiv, bool enable) -{ - if(enable) { - switch(id) { - case 2: - osalDbgAssert(gendiv < (1U << 5), "GENDIV exceeded"); - break; - case 1: - break; - default: - osalDbgAssert(gendiv < (1U << 8), "GENDIV exceeded"); - break; - } +void sam_gclk_init(uint32_t id, uint32_t sysctrl_src, uint16_t gendiv, + bool enable) { + if (enable) { + switch (id) { + case 2: + osalDbgAssert(gendiv < (1U << 5), "GENDIV exceeded"); + break; + case 1: + break; + default: + osalDbgAssert(gendiv < (1U << 8), "GENDIV exceeded"); + break; } - GCLK_REGS->GCLK_GENDIV = GCLK_GENDIV_ID(id) | GCLK_GENDIV_DIV(gendiv); - GCLK_REGS->GCLK_GENCTRL = GCLK_GENCTRL_ID(id) | sysctrl_src | GCLK_GENCTRL_IDC(1) | GCLK_GENCTRL_GENEN(enable); - while((GCLK_REGS->GCLK_STATUS & GCLK_STATUS_SYNCBUSY_Msk) == GCLK_STATUS_SYNCBUSY_Msk); + } + GCLK_REGS->GCLK_GENDIV = GCLK_GENDIV_ID(id) | GCLK_GENDIV_DIV(gendiv); + GCLK_REGS->GCLK_GENCTRL = GCLK_GENCTRL_ID(id) | sysctrl_src | + GCLK_GENCTRL_IDC(1) | GCLK_GENCTRL_GENEN(enable); + while ((GCLK_REGS->GCLK_STATUS & GCLK_STATUS_SYNCBUSY_Msk) == + GCLK_STATUS_SYNCBUSY_Msk) + ; } -void sam_gclk_mux(uint32_t id, uint32_t dest, bool enable) -{ - GCLK_REGS->GCLK_CLKCTRL = GCLK_CLKCTRL_GEN(id) | GCLK_CLKCTRL_ID(dest) | GCLK_CLKCTRL_CLKEN(enable); // Hook up the clock - while((GCLK_REGS->GCLK_STATUS & GCLK_STATUS_SYNCBUSY_Msk) == GCLK_STATUS_SYNCBUSY_Msk); +void sam_gclk_mux(uint32_t id, uint32_t dest, bool enable) { + GCLK_REGS->GCLK_CLKCTRL = GCLK_CLKCTRL_GEN(id) | GCLK_CLKCTRL_ID(dest) | + GCLK_CLKCTRL_CLKEN(enable); // Hook up the clock + while ((GCLK_REGS->GCLK_STATUS & GCLK_STATUS_SYNCBUSY_Msk) == + GCLK_STATUS_SYNCBUSY_Msk) + ; } \ No newline at end of file diff --git a/os/hal/ports/SAM/SAMD21A/sam_clk.h b/os/hal/ports/SAM/SAMD21A/sam_clk.h index ec1c386d51..2aec3299a6 100644 --- a/os/hal/ports/SAM/SAMD21A/sam_clk.h +++ b/os/hal/ports/SAM/SAMD21A/sam_clk.h @@ -2,13 +2,13 @@ #define SAM_CLK_H_ #if SAM_OSC8M_ENABLED == TRUE -#define SAM_OSC8M_FREQ SAM_OSC8_VAL +#define SAM_OSC8M_FREQ SAM_OSC8_VAL #else #define SAM_OSC8M_FREQ 0 #endif #if SAM_OSC32K_ENABLED == TRUE -#define SAM_OSC32K_FREQ SAM_OSC32K_VAL +#define SAM_OSC32K_FREQ SAM_OSC32K_VAL #else #define SAM_OSC32K_FREQ 0 #endif @@ -42,7 +42,7 @@ #elif SAM_GCLK0_SRC == GCLK_GENCTRL_SRC_XOSC32K #define SAM_GCLK0_SRC_FREQ SAM_XOSC32K_FREQ #endif -#define SAM_GCLK0_GENDIV SAM_GCLK0_SRC_FREQ/SAM_GCLK0_FREQ +#define SAM_GCLK0_GENDIV SAM_GCLK0_SRC_FREQ / SAM_GCLK0_FREQ #if SAM_GCLK0_GENDIV == 0 #error "GENDIV GCLK0 == 0" #endif @@ -63,7 +63,7 @@ #undef SAM_GCLK1_ENABLE #define SAM_GCLK1_ENABLE TRUE #endif -#define SAM_GCLK1_GENDIV SAM_GCLK1_SRC_FREQ/SAM_GCLK1_FREQ +#define SAM_GCLK1_GENDIV SAM_GCLK1_SRC_FREQ / SAM_GCLK1_FREQ #if SAM_GCLK1_GENDIV == 0 && SAM_GCLK1_ENABLE == TRUE #error "GENDIV GCLK1 == 0" #endif @@ -79,7 +79,7 @@ #define SAM_GCLK2_SRC_FREQ SAM_XOSC32K_FREQ #endif -#define SAM_GCLK2_GENDIV SAM_GCLK2_SRC_FREQ/SAM_GCLK2_FREQ +#define SAM_GCLK2_GENDIV SAM_GCLK2_SRC_FREQ / SAM_GCLK2_FREQ #if SAM_GCLK2_GENDIV == 0 && SAM_GCLK2_ENABLE == TRUE #error "GENDIV GCLK2 == 0" #endif @@ -95,7 +95,7 @@ #define SAM_GCLK3_SRC_FREQ SAM_XOSC32K_FREQ #endif -#define SAM_GCLK3_GENDIV SAM_GCLK3_SRC_FREQ/SAM_GCLK3_FREQ +#define SAM_GCLK3_GENDIV SAM_GCLK3_SRC_FREQ / SAM_GCLK3_FREQ #if SAM_GCLK3_GENDIV == 0 && SAM_GCLK3_ENABLE == TRUE #error "GENDIV GCLK3 == 0" #endif @@ -111,7 +111,7 @@ #define SAM_GCLK4_SRC_FREQ SAM_XOSC32K_FREQ #endif -#define SAM_GCLK4_GENDIV SAM_GCLK4_SRC_FREQ/SAM_GCLK4_FREQ +#define SAM_GCLK4_GENDIV SAM_GCLK4_SRC_FREQ / SAM_GCLK4_FREQ #if SAM_GCLK4_GENDIV == 0 && SAM_GCLK4_ENABLE == TRUE #error "GENDIV GCLK4 == 0" #endif @@ -127,7 +127,7 @@ #define SAM_GCLK5_SRC_FREQ SAM_XOSC32K_FREQ #endif -#define SAM_GCLK5_GENDIV SAM_GCLK5_SRC_FREQ/SAM_GCLK5_FREQ +#define SAM_GCLK5_GENDIV SAM_GCLK5_SRC_FREQ / SAM_GCLK5_FREQ #if SAM_GCLK5_GENDIV == 0 && SAM_GCLK5_ENABLE == TRUE #error "GENDIV GCLK5 == 0" #endif @@ -143,7 +143,7 @@ #define SAM_GCLK6_SRC_FREQ SAM_XOSC32K_FREQ #endif -#define SAM_GCLK6_GENDIV SAM_GCLK6_SRC_FREQ/SAM_GCLK6_FREQ +#define SAM_GCLK6_GENDIV SAM_GCLK6_SRC_FREQ / SAM_GCLK6_FREQ #if SAM_GCLK6_GENDIV == 0 && SAM_GCLK6_ENABLE == TRUE #error "GENDIV GCLK6 == 0" #endif @@ -159,7 +159,7 @@ #define SAM_GCLK7_SRC_FREQ SAM_XOSC32K_FREQ #endif -#define SAM_GCLK7_GENDIV SAM_GCLK7_SRC_FREQ/SAM_GCLK7_FREQ +#define SAM_GCLK7_GENDIV SAM_GCLK7_SRC_FREQ / SAM_GCLK7_FREQ #if SAM_GCLK7_GENDIV == 0 && SAM_GCLK7_ENABLE == TRUE #error "GENDIV GCLK7 == 0" #endif @@ -175,11 +175,29 @@ #define SAM_GCLK8_SRC_FREQ SAM_XOSC32K_FREQ #endif -#define SAM_GCLK8_GENDIV SAM_GCLK8_SRC_FREQ/SAM_GCLK8_FREQ +#define SAM_GCLK8_GENDIV SAM_GCLK8_SRC_FREQ / SAM_GCLK8_FREQ #if SAM_GCLK8_GENDIV == 0 && SAM_GCLK8_ENABLE == TRUE #error "GENDIV GCLK8 == 0" #endif +// GCLK9 +#if SAM_GCLK9_SRC == GCLK_GENCTRL_SRC_DFLL48M +#define SAM_GCLK9_SRC_FREQ SAM_DFLL48_FREQ +#elif SAM_GCLK9_SRC == GCLK_GENCTRL_SRC_OSC8M +#define SAM_GCLK9_SRC_FREQ SAM_OSC8_FREQ +#elif SAM_GCLK9_SRC == GCLK_GENCTRL_SRC_OSC32K +#define SAM_GCLK9_SRC_FREQ SAM_OSC32K_FREQ +#elif SAM_GCLK9_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define SAM_GCLK9_SRC_FREQ SAM_XOSC32K_FREQ +#endif + + + +#define SAM_GCLK9_GENDIV SAM_GCLK9_SRC_FREQ / SAM_GCLK9_FREQ +#if SAM_GCLK9_GENDIV == 0 && SAM_GCLK9_ENABLE == TRUE +#error "GENDIV GCLK9 == 0" +#endif + #define SAM_CPU_FREQ SAM_GCLK0_FREQ / (1UL << SAM_CPUDIV) #define SAM_APBA_FREQ SAM_GCLK0_FREQ / (1UL << SAM_APBADIV) #define SAM_APBB_FREQ SAM_GCLK0_FREQ / (1UL << SAM_APBADIV) @@ -187,26 +205,22 @@ #if SAM_CPU_FREQ > 1000000UL #define SAM_NVM_DELAY 3 -#else +#else #define SAM_NVM_DELAY 0 #endif #ifdef __cplusplus extern "C" { #endif - static inline uint32_t get_cpu_freq(void) { - return SAM_CPU_FREQ; - } - void sam_gclk_init(uint32_t id, - uint32_t sysctrl_src, - uint16_t gendiv, - bool enable); - void sam_gclk_mux(uint32_t id, - uint32_t dest, - bool enable); -#ifdef __cplusplus +static inline uint32_t get_cpu_freq(void) { + return SAM_CPU_FREQ; } -#endif +void sam_gclk_init(uint32_t id, uint32_t sysctrl_src, uint16_t gendiv, + bool enable); +void sam_gclk_mux(uint32_t id, uint32_t dest, bool enable); +#ifdef __cplusplus +} +#endif /*CPP*/ -#endif \ No newline at end of file +#endif /*SAM_CLK_H_*/ \ No newline at end of file diff --git a/os/hal/ports/SAM/SAMD21A/sam_extint.h b/os/hal/ports/SAM/SAMD21A/sam_extint.h index 8bede20ac2..b35505a0b9 100644 --- a/os/hal/ports/SAM/SAMD21A/sam_extint.h +++ b/os/hal/ports/SAM/SAMD21A/sam_extint.h @@ -8,48 +8,44 @@ * @param pad * @return int8_t extint */ -static inline int8_t _get_extint(ioportid_t port, iopadid_t pad) -{ - int8_t extint = 0; - if(port == GPIOA) { - switch(pad) { - case 8: - osalDbgAssert(0, "PA08 does not have EXTINT"); - extint = -1; - break; - case 24: - extint = 12; - break; - case 25: - extint = 13; - break; - case 27: - extint = 15; - break; - case 28: - extint = 8; - break; - case 30: - extint = 10; - break; - case 31: - extint = 11; - break; - default: - extint = pad % 16; - break; - } +static inline int8_t _get_extint(ioportid_t port, iopadid_t pad) { + int8_t extint = 0; + if (port == GPIOA) { + switch (pad) { + case 8: + osalDbgAssert(0, "PA08 does not have EXTINT"); + extint = -1; + break; + case 24: + extint = 12; + break; + case 25: + extint = 13; + break; + case 27: + extint = 15; + break; + case 28: + extint = 8; + break; + case 30: + extint = 10; + break; + case 31: + extint = 11; + break; + default: + extint = pad % 16; + break; } - else if(port == GPIOB) { - switch(pad) { - default: - extint = pad % 16; - break; - } + } else if (port == GPIOB) { + switch (pad) { + default: + extint = pad % 16; + break; } - return extint; - + } + return extint; } - #endif \ No newline at end of file diff --git a/os/hal/ports/SAM/SAME54/hal_lld.c b/os/hal/ports/SAM/SAME54/hal_lld.c new file mode 100644 index 0000000000..248594a002 --- /dev/null +++ b/os/hal/ports/SAM/SAME54/hal_lld.c @@ -0,0 +1,302 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.c + * @brief PLATFORM HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" +#include "sam_clk.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) && !defined(__DOXYGEN__) +/** + * @brief Post-reset configuration, must be implemented. + */ +const halclkcfg_t hal_clkcfg_reset = {.dummy = 0U}; + +/** + * @brief Configuration from mcuconf.h, must be implemented. + */ +const halclkcfg_t hal_clkcfg_default = {.dummy = 0U}; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +typedef enum ctrlb_refclk_t { + SAM_CTRLB_REFCLK_GCLK = 0, + SAM_CTRLB_REFCLK_XOSC32, + SAM_CTRLB_REFCLK_XOSC0, + SAM_CTRLB_REFCLK_XOSC1, +} ctrlb_refclk_t; + +typedef struct { + ctrlb_refclk_t refclk; + uint8_t div; + bool en; +} ctrlb_reg_t; + +typedef struct ratio_reg_t { + uint32_t ldfrac; + uint32_t ldr; +} ratio_reg_t; + +typedef struct gclk_cfg { + uint32_t src; + uint32_t gendiv; + uint8_t en; +} gclk_cfg_t; + +const static gclk_cfg_t gclk_cfg_arr[12] = { + {SAM_GCLK0_SRC, SAM_GCLK0_SRC_FREQ / SAM_GCLK0_FREQ, TRUE}, + {SAM_GCLK1_SRC, SAM_GCLK1_SRC_FREQ / SAM_GCLK1_FREQ, SAM_GCLK1_ENABLE}, + {SAM_GCLK2_SRC, SAM_GCLK2_SRC_FREQ / SAM_GCLK2_FREQ, SAM_GCLK2_ENABLE}, + {SAM_GCLK3_SRC, SAM_GCLK3_SRC_FREQ / SAM_GCLK3_FREQ, SAM_GCLK3_ENABLE}, + {SAM_GCLK4_SRC, SAM_GCLK4_SRC_FREQ / SAM_GCLK4_FREQ, SAM_GCLK4_ENABLE}, + {SAM_GCLK5_SRC, SAM_GCLK5_SRC_FREQ / SAM_GCLK5_FREQ, SAM_GCLK5_ENABLE}, + {SAM_GCLK6_SRC, SAM_GCLK6_SRC_FREQ / SAM_GCLK6_FREQ, SAM_GCLK6_ENABLE}, + {SAM_GCLK7_SRC, SAM_GCLK7_SRC_FREQ / SAM_GCLK7_FREQ, SAM_GCLK7_ENABLE}, + {SAM_GCLK8_SRC, SAM_GCLK8_SRC_FREQ / SAM_GCLK8_FREQ, SAM_GCLK8_ENABLE}, + {SAM_GCLK9_SRC, SAM_GCLK9_SRC_FREQ / SAM_GCLK9_FREQ, SAM_GCLK9_ENABLE}, + {SAM_GCLK10_SRC, SAM_GCLK10_SRC_FREQ / SAM_GCLK10_FREQ, SAM_GCLK10_ENABLE}, + {SAM_GCLK11_SRC, SAM_GCLK11_SRC_FREQ / SAM_GCLK11_FREQ, SAM_GCLK11_ENABLE}, +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Get the imult iptat values based on XOSC frequency (reference table 28-7) + * + * @param osc_freq Input oscillator frequency + * @param imult + * @param iptat + */ +static inline void get_imult_iptat(uint32_t osc_freq, uint8_t* imult, + uint8_t* iptat) { + if (osc_freq == 8000000ul) { + *imult = 3; + *iptat = 2; + } else if (osc_freq > 8000000ul && osc_freq <= 16000000ul) { + *imult = 4; + *iptat = 3; + } else if (osc_freq > 16000000ul && osc_freq <= 24000000ul) { + *imult = 5; + *iptat = 3; + } else if (osc_freq > 24000000ul && osc_freq <= 48000000ul) { + *imult = 6; + *iptat = 3; + } +} + +/** + * @brief Configure XOSCCTRL + * + * @param id id of the oscillator + * @param input_freq crystal frequency + * @param enable enable this or not + */ +static void sam_xosc_init(const uint32_t id, const uint32_t input_freq, + bool enable) { + osalDbgAssert(id < 2, "Invalid ID"); + uint8_t imult = 0, iptat = 0; + get_imult_iptat(input_freq, &imult, &iptat); + /* Configure External Oscillator */ + uint32_t en_mask = + OSCCTRL_XOSCCTRL_XTALEN_Msk | OSCCTRL_XOSCCTRL_ENABLE(enable); + if (!enable) { + en_mask = 0; + } + OSCCTRL_REGS->OSCCTRL_XOSCCTRL[id] = OSCCTRL_XOSCCTRL_STARTUP(0U) | + OSCCTRL_XOSCCTRL_IMULT(imult) | + OSCCTRL_XOSCCTRL_IPTAT(iptat) | en_mask; + if (enable) { + while ((OSCCTRL_REGS->OSCCTRL_STATUS & (1 << id)) != (1 << id)) { + /* Waiting for the XOSC Ready state */ + } + } +} + +/** + * @brief Configure FDPLL + * + * @param id FDPLL no + * @param ctrlb ctrlb values + * @param ratio ratio values + */ +static void sam_fdpll_init(const uint32_t id, const ctrlb_reg_t* ctrlb, + const ratio_reg_t* ratio) { + osalDbgAssert(((id < 2) && (ctrlb != NULL) && (ratio != NULL)), + "invalid parameters"); + if (!ctrlb->en) { + OSCCTRL_REGS->DPLL[id].OSCCTRL_DPLLCTRLA &= ~OSCCTRL_DPLLCTRLA_ENABLE_Msk; + return; + } + /* Configure DPLL */ + OSCCTRL_REGS->DPLL[id].OSCCTRL_DPLLCTRLB = + OSCCTRL_DPLLCTRLB_FILTER(0U) | OSCCTRL_DPLLCTRLB_LTIME(0x0U) | + OSCCTRL_DPLLCTRLB_REFCLK(ctrlb->refclk) | + OSCCTRL_DPLLCTRLB_DIV(ctrlb->div); + + OSCCTRL_REGS->DPLL[id].OSCCTRL_DPLLRATIO = + OSCCTRL_DPLLRATIO_LDRFRAC(ratio->ldfrac) | + OSCCTRL_DPLLRATIO_LDR(ratio->ldr); + + while ((OSCCTRL_REGS->DPLL[id].OSCCTRL_DPLLSYNCBUSY & + OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk) == + OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk) { + /* Waiting for the synchronization */ + } + + /* Enable DPLL */ + OSCCTRL_REGS->DPLL[id].OSCCTRL_DPLLCTRLA = OSCCTRL_DPLLCTRLA_ENABLE_Msk; + + while ((OSCCTRL_REGS->DPLL[id].OSCCTRL_DPLLSYNCBUSY & + OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk) == OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk) { + /* Waiting for the DPLL enable synchronization */ + } + + while ((OSCCTRL_REGS->DPLL[id].OSCCTRL_DPLLSTATUS & + (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk)) != + (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk)) { + /* Waiting for the Ready state */ + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + sam_xosc_init(0, SAM_XOSC0_FREQ, SAM_XOSC0_ENABLED); + sam_xosc_init(1, SAM_XOSC1_FREQ, SAM_XOSC1_ENABLED); + + sam_gclk_init(1, gclk_cfg_arr[1].src, gclk_cfg_arr[1].gendiv, + gclk_cfg_arr[1].en); + + /* Initialize FDPLL0 */ +#if SAM_FDPLL0_ENABLED == TRUE + ctrlb_reg_t ctrl = { + SAM_FDPLL0_INPUT_SRC, + SAM_FDPLL0_DIV, + SAM_FDPLL0_ENABLED, + }; + ratio_reg_t ratio_reg = {SAM_FDPLL0_LDFRAC, SAM_FDPLL0_LDR}; +#else + ctrlb_reg_t ctrl = { + 0, + 0, + SAM_FDPLL0_ENABLED, + }; + ratio_reg_t ratio_reg = {0, SAM_FDPLL0_LDR}; +#endif + + sam_fdpll_init(0, &ctrl, &ratio_reg); + + /* Initialize FDPLL 1 */ +#if SAM_FDPLL1_ENABLED == TRUE + ctrl = (ctrlb_reg_t){ + SAM_FDPLL1_INPUT_SRC, + SAM_FDPLL1_DIV, + SAM_FDPLL1_ENABLED, + }; + ratio_reg = (ratio_reg_t){SAM_FDPLL1_LDFRAC, SAM_FDPLL1_LDR}; +#else + ctrl = (ctrlb_reg_t){ + 0, + 0, + SAM_FDPLL1_ENABLED, + }; + ratio_reg = (ratio_reg_t){0, 0}; +#endif + sam_fdpll_init(1, &ctrl, &ratio_reg); + for (int i = 2; i < 11; i++) { + sam_gclk_init(i, gclk_cfg_arr[i].src, gclk_cfg_arr[i].gendiv, + gclk_cfg_arr[i].en); + } + sam_gclk_init(0, gclk_cfg_arr[0].src, gclk_cfg_arr[0].gendiv, + gclk_cfg_arr[0].en); + + MCLK_REGS->MCLK_CPUDIV = MCLK_CPUDIV_DIV(SAM_CPUDIV); + + while ((MCLK_REGS->MCLK_INTFLAG & MCLK_INTFLAG_CKRDY_Msk) != + MCLK_INTFLAG_CKRDY_Msk) { + /* Wait for the Main Clock to be Ready */ + } +#if defined(SAM_DMAC_REQUIRED) + dmacInit(); +#endif +} + +#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__) +/** + * @brief Switches to a different clock configuration + * + * @param[in] ccp pointer to clock a @p halclkcfg_t structure + * @return The clock switch result. + * @retval false if the clock switch succeeded + * @retval true if the clock switch failed + * + * @notapi + */ +bool hal_lld_clock_switch_mode(const halclkcfg_t* ccp) { + + (void)ccp; + + return false; +} + +/** + * @brief Returns the frequency of a clock point in Hz. + * + * @param[in] clkpt clock point to be returned + * @return The clock point frequency in Hz or zero if the + * frequency is unknown. + * + * @notapi + */ +halfreq_t hal_lld_get_clock_point(halclkpt_t clkpt) { + + (void)clkpt; + + return 0U; +} +#endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */ + +/** @} */ diff --git a/os/hal/ports/SAM/SAME54/hal_lld.h b/os/hal/ports/SAM/SAME54/hal_lld.h new file mode 100644 index 0000000000..a964a4c52b --- /dev/null +++ b/os/hal/ports/SAM/SAME54/hal_lld.h @@ -0,0 +1,178 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.h + * @brief PLATFORM HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef HAL_LLD_H +#define HAL_LLD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#ifndef SAM_XOSC32K_FREQ +#define SAM_XOSC32K_FREQ 0 +#endif + +#define SAM_DPLL_INPUT_SRC_GCLK 0 +#define SAM_DPLL_INPUT_SRC_XOSC32 1 +#define SAM_DPLL_INPUT_SRC_XOSC0 2 +#define SAM_DPLL_INPUT_SRC_XOSC1 3 +#define hal_lld_get_clock_point(clkpt) 0U +#define SAM_DMAC_CHAN_NUM 32 +/** + * @brief Requires use of SPIv2 driver model. + */ +#define HAL_LLD_SELECT_SPI_V2 TRUE + +/** + * @brief Specifies implementation of dynamic clock management. + */ +// #define HAL_LLD_USE_CLOCK_MANAGEMENT + +/** + * @name Platform identification macros + * @{ + */ +#define PLATFORM_NAME "SAME54" +/** @} */ + +/** + * @brief Macro for enabling XOSC0 + * + */ +#if !defined(SAM_XOSC0_ENABLED) || defined(__DOXYGEN__) +#define SAM_XOSC0_ENABLED FALSE +#undef SAM_XOSC0_FREQ +#define SAM_XOSC0_FREQ 0 +#endif + +/** + * @brief Macro for enabling XOSC1 + * + */ +#if !defined(SAM_XOSC1_ENABLED) || defined(__DOXYGEN__) +#define SAM_XOSC1_ENABLED FALSE +#undef SAM_XOSC0_FREQ +#define SAM_XOSC0_FREQ 0 +#endif + +/** + * @brief Macro for enabling XOSC32K + * + */ +#if !defined(SAM_XOSC32K_ENABLED) || defined(__DOXYGEN__) +#define SAM_XOSC32K_ENABLED FALSE +#endif + +/** + * @brief Macro for enabling FDPLL0 + * + */ +#if !defined(SAM_FDPLL0_ENABLED) || defined(__DOXYGEN__) +#define SAM_FDPLL0_ENABLED FALSE +#endif + +/** + * @brief Macro for enabling FDPLL1 + * + */ +#if !defined(SAM_FDPLL1_ENABLED) || defined(__DOXYGEN__) +#define SAM_FDPLL1_ENABLED FALSE +#endif + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name SAME54 configuration options + * @{ + */ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ +#include "nvic.h" +#include "sam_dmac.h" +#include "sam_clk.h" +#include "sam_irq.h" +#include "sam_gclk_add.h" +/* + * Configuration-related checks. + */ +#if !defined(SAME54_MCUCONF) +#error "Using a wrong mcuconf.h file, SAME54_MCUCONF not defined" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a clock point identifier. + */ +typedef unsigned halclkpt_t; + +#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__) +/** + * @brief Type of a clock point frequency in Hz. + */ +typedef uint32_t halfreq_t; + +/** + * @brief Type of a clock configuration structure. + */ +typedef struct { + uint32_t dummy; +} halclkcfg_t; +#endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) && !defined(__DOXYGEN__) +extern const halclkcfg_t hal_clkcfg_reset; +extern const halclkcfg_t hal_clkcfg_default; +#endif + +#ifdef __cplusplus +extern "C" { +#endif +void hal_lld_init(void); +#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__) +bool hal_lld_clock_switch_mode(const halclkcfg_t* ccp); +halfreq_t hal_lld_get_clock_point(halclkpt_t clkpt); +#endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SAM/SAME54/platform.mk b/os/hal/ports/SAM/SAME54/platform.mk new file mode 100644 index 0000000000..615717f800 --- /dev/null +++ b/os/hal/ports/SAM/SAME54/platform.mk @@ -0,0 +1,38 @@ +# Required platform files. +PLATFORMSRC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SAM/SAME54/sam_clk.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SAM/SAME54/hal_lld.c \ + +# Required include directories. +PLATFORMINC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SAM/SAME54 + +# Optional platform files. +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(HALCONFDIR),) + ifeq ($(CONFDIR),) + HALCONFDIR = . + else + HALCONFDIR := $(CONFDIR) + endif +endif + +HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) + +else +endif + +# Drivers compatible with the platform. +include $(CHIBIOS_CONTRIB)/os/hal/ports/SAM/LLD/DMACv2/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SAM/LLD/PORTv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SAM/LLD/SYSTICKv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SAM/LLD/SERCOMv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SAM/LLD/SPIv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/SAM/SAME54/sam_clk.c b/os/hal/ports/SAM/SAME54/sam_clk.c new file mode 100644 index 0000000000..cab8ace538 --- /dev/null +++ b/os/hal/ports/SAM/SAME54/sam_clk.c @@ -0,0 +1,36 @@ +#include "hal.h" +#include "sam_clk.h" + +uint32_t SystemCoreClock = SAM_CPU_FREQ; + +void sam_gclk_init(uint32_t id, uint32_t sysctrl_src, uint16_t gendiv, + bool enable) { + if (enable) { + switch (id) { + case 2: + osalDbgAssert(((uint32_t)gendiv) < (1U << 16), "GENDIV exceeded"); + break; + default: + osalDbgAssert(gendiv < (1U << 8), "GENDIV exceeded"); + break; + } + } + GCLK_REGS->GCLK_GENCTRL[id] = GCLK_GENCTRL_DIV(gendiv) | sysctrl_src | + GCLK_GENCTRL_IDC(1) | + GCLK_GENCTRL_GENEN(enable); + const uint32_t syncbusy_gen = 1 << (id + 2); + while ((GCLK_REGS->GCLK_SYNCBUSY & syncbusy_gen) == syncbusy_gen) { + /* Wait for synchronization */ + } +} + +void sam_gclk_mux(uint32_t id, uint32_t dest, bool enable) { + GCLK_REGS->GCLK_PCHCTRL[dest] = + GCLK_PCHCTRL_GEN(id) | GCLK_PCHCTRL_CHEN(enable); // Hook up the clock + if (enable) { + while ((GCLK_REGS->GCLK_PCHCTRL[dest] & GCLK_PCHCTRL_CHEN_Msk) != + GCLK_PCHCTRL_CHEN(enable)) { + /* Wait for synchronization */ + } + } +} \ No newline at end of file diff --git a/os/hal/ports/SAM/SAME54/sam_clk.h b/os/hal/ports/SAM/SAME54/sam_clk.h new file mode 100644 index 0000000000..fb2e5fad38 --- /dev/null +++ b/os/hal/ports/SAM/SAME54/sam_clk.h @@ -0,0 +1,336 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file sam_clk.h + * @brief Helper file to configure SAME54 + * + * @addtogroup HAL + * @{ + */ + +#ifndef SAM_CLK_H_ +#define SAM_CLK_H_ + +#if !defined(SAM_XOSC0_FREQ) && SAM_XOSC0_ENABLED == TRUE +#error "XOSC0 input freq is not defined" +#elif SAM_XOSC0_ENABLED == FALSE +#undef SAM_XOSC0_FREQ +#define SAM_XOSC0_FREQ 0 +#endif + +#if !defined(SAM_XOSC1_FREQ) && SAM_XOSC1_ENABLED == TRUE +#error "XOSC1 input freq is not defined" +#elif SAM_XOSC1_ENABLED == FALSE +#undef SAM_XOSC1_FREQ +#define SAM_XOSC1_FREQ 0 +#endif + +#if SAM_XOSC32K_ENABLED == FALSE +#undef SAM_XOSC32K_FREQ +#define SAM_XOSC32K_FREQ 0 +#endif + +// FDPLL0 Configuration +#if SAM_FDPLL0_ENABLED == TRUE + +#ifndef SAM_FDPLL0_INPUT_SRC +#error "no input source for FDPLL0" +#endif + +#if SAM_FDPLL0_INPUT_SRC == SAM_DPLL_INPUT_SRC_GCLK +#error "TODO this configuration is currently not supported" +#elif SAM_FDPLL0_INPUT_SRC == SAM_DPLL_INPUT_SRC_XOSC32 +#define SAM_FDPLL0_INPUT_FREQ SAM_XOSC32K_FREQ +#elif SAM_FDPLL0_INPUT_SRC == SAM_DPLL_INPUT_SRC_XOSC0 +#define SAM_FDPLL0_INPUT_FREQ SAM_XOSC0_FREQ +#elif SAM_FDPLL0_INPUT_SRC == SAM_DPLL_INPUT_SRC_XOSC1 +#define SAM_FDPLL0_INPUT_FREQ SAM_XOSC1_FREQ +#endif + +#if SAM_FDPLL0_INPUT_FREQ == 0 +#error input freq for FDPLL0 is 0 +#endif + +#define SAM_FDPLL0_OUTPUT_FREQ \ + (SAM_FDPLL0_INPUT_FREQ / (2 * (SAM_FDPLL0_DIV + 1))) * \ + (SAM_FDPLL0_LDR + 1 + SAM_FDPLL0_LDFRAC / 32) +#endif + +// FDPLL1 Configuration +#if SAM_FDPLL1_ENABLED == TRUE + +#ifndef SAM_FDPLL1_INPUT_SRC +#error "no input source for FDPLL1" +#endif + +#if SAM_FDPLL1_INPUT_SRC == SAM_DPLL_INPUT_SRC_GCLK +#error "TODO this configuration is currently not supported" +#elif SAM_FDPLL1_INPUT_SRC == SAM_DPLL_INPUT_SRC_XOSC32 +#define SAM_FDPLL1_INPUT_FREQ SAM_XOSC32K_FREQ +#elif SAM_FDPLL1_INPUT_SRC == SAM_DPLL_INPUT_SRC_XOSC0 +#define SAM_FDPLL1_INPUT_FREQ SAM_XOSC0_FREQ +#elif SAM_FDPLL1_INPUT_SRC == SAM_DPLL_INPUT_SRC_XOSC1 +#define SAM_FDPLL1_INPUT_FREQ SAM_XOSC1_FREQ +#endif + +#if SAM_FDPLL1_INPUT_FREQ == 0 +#error input freq for FDPLL0 is 0 +#endif + +#define SAM_FDPLL1_OUTPUT_FREQ \ + (SAM_FDPLL1_INPUT_FREQ / (2 * (SAM_FDPLL1_DIV + 1))) * \ + (SAM_FDPLL1_LDR + 1 + (SAM_FDPLL1_LDFRAC / 32)) + +#if (SAM_FDPLL1_OUTPUT_FREQ < 96000000ul) || \ + (SAM_FDPLL1_OUTPUT_FREQ > 200000000ul) +#error FDLL out of range +#endif + +#endif + +// GCLK0 +#if SAM_GCLK0_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK0_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK0_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK0_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK0_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK0_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK0_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK0_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif + +// GCLK1 +#if SAM_GCLK1_ENABLE == TRUE +#if SAM_GCLK1_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK1_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK1_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK1_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK1_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK1_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK1_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK1_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif +#else +#define SAM_GCLK1_SRC_FREQ 0 +#endif + +// GCLK2 +#if SAM_GCLK2_ENABLE == TRUE +#if SAM_GCLK2_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK2_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK2_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK2_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK2_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK2_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK2_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK2_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif +#else +#define SAM_GCLK2_SRC_FREQ 0 +#endif + +// GCLK3 +#if SAM_GCLK3_ENABLE == TRUE +#if SAM_GCLK3_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK3_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK3_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK3_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK3_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK3_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK3_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK3_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif +#else +#define SAM_GCLK3_SRC_FREQ 0 +#endif + +// GCLK4 +#if SAM_GCLK4_ENABLE == TRUE +#if SAM_GCLK4_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK4_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK4_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK4_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK4_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK4_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK4_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK4_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif +#else +#define SAM_GCLK4_SRC_FREQ 0 +#endif + +// GCLK5 +#if SAM_GCLK5_ENABLE == TRUE +#if SAM_GCLK5_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK5_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK5_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK5_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK5_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK5_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK5_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK5_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif +#else +#define SAM_GCLK5_SRC_FREQ 0 +#endif + +// GCLK6 +#if SAM_GCLK6_ENABLE == TRUE +#if SAM_GCLK6_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK6_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK6_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK6_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK6_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK6_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK6_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK6_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif +#else +#define SAM_GCLK6_SRC_FREQ 0 +#endif + +// GCLK7 +#if SAM_GCLK7_ENABLE == TRUE +#if SAM_GCLK7_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK7_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK7_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK7_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK7_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK7_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK7_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK7_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif +#else +#define SAM_GCLK7_SRC_FREQ 0 +#endif + +// GCLK8 +#if SAM_GCLK8_ENABLE == TRUE +#if SAM_GCLK8_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK8_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK8_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK8_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK8_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK8_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK8_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK8_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif +#else +#define SAM_GCLK8_SRC_FREQ 0 +#endif + +// GCLK9 +#if SAM_GCLK9_ENABLE == TRUE +#if SAM_GCLK9_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK9_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK9_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK9_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK9_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK9_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK9_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK9_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif +#else +#define SAM_GCLK9_SRC_FREQ 0 +#endif + +// GCLK10 +#if SAM_GCLK10_ENABLE == TRUE +#if SAM_GCLK10_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK10_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK10_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK10_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK10_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK10_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK10_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK8_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif +#else +#define SAM_GCLK10_SRC_FREQ 0 +#endif + +// GCLK11 +#if SAM_GCLK11_ENABLE == TRUE +#if SAM_GCLK11_SRC == GCLK_GENCTRL_SRC_XOSC0 +#define SAM_GCLK11_SRC_FREQ SAM_XOSC0_FREQ +#elif SAM_GCLK11_SRC == GCLK_GENCTRL_SRC_XOSC1 +#define SAM_GCLK11_SRC_FREQ SAM_XOSC1_FREQ +#elif SAM_GCLK11_SRC == GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK11_SRC_FREQ SAM_FDPLL0_OUTPUT_FREQ +#elif SAM_GCLK11_SRC == GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK11_SRC_FREQ SAM_FDPLL1_OUTPUT_FREQ +#else +#error not supported configuration +#endif +#else +#define SAM_GCLK11_SRC_FREQ 0 +#endif + +#if (SAM_CPUDIV % 2 != 0) && SAM_CPUDIV > 1 +#error invalid SAM_CPUDIV +#endif + +#define SAM_CPU_FREQ SAM_GCLK0_FREQ / (SAM_CPUDIV) +#if SAM_CPU_FREQ > 120000000UL +#error CPU Frequency is over 120MHz +#endif + +#define SAM_HS_FREQ SAM_GCLK0_FREQ + +#if SAM_CPU_FREQ > 1000000UL +#define SAM_NVM_DELAY 3 +#else +#define SAM_NVM_DELAY 0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif +static inline uint32_t get_cpu_freq(void) { + return SAM_CPU_FREQ; +} + +void sam_gclk_init(uint32_t id, uint32_t sysctrl_src, uint16_t gendiv, + bool enable); +void sam_gclk_mux(uint32_t id, uint32_t dest, bool enable); +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/os/hal/ports/SAM/SAME54/sam_extint.h b/os/hal/ports/SAM/SAME54/sam_extint.h new file mode 100644 index 0000000000..fb1a143902 --- /dev/null +++ b/os/hal/ports/SAM/SAME54/sam_extint.h @@ -0,0 +1,99 @@ +#ifndef SAMD21_EXTINT_H_ +#define SAMD21_EXTINT_H_ + +/** + * @brief get EXTINT number for certain PORT + * + * @param port + * @param pad + * @return int8_t extint + */ +static inline int8_t _get_extint(ioportid_t port, iopadid_t pad) { + int8_t extint = 0; + if (port == GPIOA) { + switch (pad) { + case 8: + case 26: + case 28: + case 29: + case 30: + case 31: + osalDbgAssert(0, "Pin does not support EIC"); + extint = -1; + break; + default: + extint = pad % 16; + break; + } + } else if (port == GPIOB) { + switch (pad) { + case 3: + osalDbgAssert(0, "Pin does not support EIC"); + extint = -1; + break; + case 26: + case 27: + case 28: + case 29: + extint = pad % 16 + 2; + break; + default: + extint = pad % 16; + break; + } + } else if (port == GPIOC) { + switch (pad) { + case 8: + case 9: + case 29: + osalDbgAssert(0, "Pin does not support EIC"); + extint = -1; + break; + case 7: + extint = pad % 16 + 2; + break; + default: + extint = pad % 16; + break; + } + } + + else if (port == GPIOD) { + if (pad >= 8 && pad <= 12) { + extint = pad % 16 - 5; + } else if (pad == 20 || pad == 21) { + extint = pad % 16 + 1; + } else { + osalDbgAssert(0, "Pin does not support EIC"); + extint = -1; + } + switch (pad) { + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + osalDbgAssert(0, "Pin does not support EIC"); + extint = -1; + break; + case 8: + case 9: + case 10: + case 11: + case 12: + extint = pad % 16 - 5; + break; + case 20: + case 21: + extint = pad % 16 + 1; + break; + default: + extint = pad % 16; + break; + } + } + return extint; +} + +#endif \ No newline at end of file diff --git a/os/hal/ports/SAM/SAME54/sam_gclk_add.h b/os/hal/ports/SAM/SAME54/sam_gclk_add.h new file mode 100644 index 0000000000..c09713a9b0 --- /dev/null +++ b/os/hal/ports/SAM/SAME54/sam_gclk_add.h @@ -0,0 +1,32 @@ +#ifndef SAM_GCLK_ADD_H_ +#define SAM_GCLK_ADD_H_ + +/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */ +/* Add more as needed, only defined what is needed for the drivers that have already been done/planned */ +/* If peripherial clock generation is required, use the generic clock generators in gclk.h for SAME*/ + +#define GCLK_PCHCTRL_ID_OSCCTRL_DFLL48 0 +#define GCLK_PCHCTRL_ID_EIC_Val 4 +#define GCLK_PCHCTRL_ID_SERCOM0_CORE_Val 7 +#define GCLK_PCHCTRL_ID_SERCOM1_CORE_Val 8 +#define GCLK_PCHCTRL_ID_USB_Val 10 +#define GCLK_PCHCTRL_ID_EVSYS_0_Val 11 +#define GCLK_PCHCTRL_ID_EVSYS_1_Val 12 +#define GCLK_PCHCTRL_ID_EVSYS_2_Val 13 +#define GCLK_PCHCTRL_ID_EVSYS_3_Val 14 +#define GCLK_PCHCTRL_ID_EVSYS_4_Val 15 +#define GCLK_PCHCTRL_ID_EVSYS_5_Val 16 +#define GCLK_PCHCTRL_ID_EVSYS_6_Val 17 +#define GCLK_PCHCTRL_ID_EVSYS_7_Val 18 +#define GCLK_PCHCTRL_ID_EVSYS_8_Val 19 +#define GCLK_PCHCTRL_ID_EVSYS_9_Val 20 +#define GCLK_PCHCTRL_ID_EVSYS_10_Val 21 +#define GCLK_PCHCTRL_ID_EVSYS_11_Val 22 +#define GCLK_PCHCTRL_ID_SERCOM2_CORE_Val 23 +#define GCLK_PCHCTRL_ID_SERCOM3_CORE_Val 24 +#define GCLK_PCHCTRL_ID_SERCOM4_CORE_Val 34 +#define GCLK_PCHCTRL_ID_SERCOM5_CORE_Val 35 +#define GCLK_PCHCTRL_ID_SERCOM6_CORE_Val 36 +#define GCLK_PCHCTRL_ID_SERCOM7_CORE_Val 37 + +#endif /* SAM_GCLK_ADD_H_*/ \ No newline at end of file diff --git a/os/hal/ports/SAM/SAME54/sam_irq.h b/os/hal/ports/SAM/SAME54/sam_irq.h new file mode 100644 index 0000000000..47f575d046 --- /dev/null +++ b/os/hal/ports/SAM/SAME54/sam_irq.h @@ -0,0 +1,82 @@ +#ifndef SAM_IRQ_H_ +#define SAM_IRQ_H_ + + +/* Vector offset calculation: Vector# = 0x40 + NVIC_line*4 */ +/* SAM EIC HANDLER*/ +#define SAM_EIC_EXTINT_0_HANDLER Vector70 +#define SAM_EIC_EXTINT_1_HANDLER Vector74 +#define SAM_EIC_EXTINT_2_HANDLER Vector78 +#define SAM_EIC_EXTINT_3_HANDLER Vector7C +#define SAM_EIC_EXTINT_4_HANDLER Vector80 +#define SAM_EIC_EXTINT_5_HANDLER Vector84 +#define SAM_EIC_EXTINT_6_HANDLER Vector88 +#define SAM_EIC_EXTINT_7_HANDLER Vector8C +#define SAM_EIC_EXTINT_8_HANDLER Vector90 +#define SAM_EIC_EXTINT_9_HANDLER Vector94 +#define SAM_EIC_EXTINT_10_HANDLER Vector98 +#define SAM_EIC_EXTINT_11_HANDLER Vector9C +#define SAM_EIC_EXTINT_12_HANDLER VectorA0 +#define SAM_EIC_EXTINT_13_HANDLER VectorA4 +#define SAM_EIC_EXTINT_14_HANDLER VectorA8 +#define SAM_EIC_EXTINT_15_HANDLER VectorAC + +/* DMAC HANDLER*/ +#define SAM_DMAC_0_HANDLER VectorBC +#define SAM_DMAC_1_HANDLER VectorC0 +#define SAM_DMAC_2_HANDLER VectorC4 +#define SAM_DMAC_3_HANDLER VectorC8 +#define SAM_DMAC_4_31_HANDLER VectorCC + +/* SERCOM HANDLER */ +#define SAM_SERCOM_0_0_HANDLER VectorF8 +#define SAM_SERCOM_0_1_HANDLER VectorFC +#define SAM_SERCOM_0_2_HANDLER Vector100 +#define SAM_SERCOM_0_3_HANDLER Vector104 + +#define SAM_SERCOM_1_0_HANDLER Vector108 +#define SAM_SERCOM_1_1_HANDLER Vector10C +#define SAM_SERCOM_1_2_HANDLER Vector110 +#define SAM_SERCOM_1_3_HANDLER Vector114 + +#define SAM_SERCOM_2_0_HANDLER Vector118 +#define SAM_SERCOM_2_1_HANDLER Vector11C +#define SAM_SERCOM_2_2_HANDLER Vector120 +#define SAM_SERCOM_2_3_HANDLER Vector124 + +#define SAM_SERCOM_3_0_HANDLER Vector128 +#define SAM_SERCOM_3_1_HANDLER Vector12C +#define SAM_SERCOM_3_2_HANDLER Vector130 +#define SAM_SERCOM_3_3_HANDLER Vector134 + +#define SAM_SERCOM_4_0_HANDLER Vector138 +#define SAM_SERCOM_4_1_HANDLER Vector13C +#define SAM_SERCOM_4_2_HANDLER Vector140 +#define SAM_SERCOM_4_3_HANDLER Vector144 + +#define SAM_SERCOM_5_0_HANDLER Vector148 +#define SAM_SERCOM_5_1_HANDLER Vector14C +#define SAM_SERCOM_5_2_HANDLER Vector150 +#define SAM_SERCOM_5_3_HANDLER Vector154 + +#define SAM_SERCOM_6_0_HANDLER Vector158 +#define SAM_SERCOM_6_1_HANDLER Vector15C +#define SAM_SERCOM_6_2_HANDLER Vector160 +#define SAM_SERCOM_6_3_HANDLER Vector164 + +#define SAM_SERCOM_7_0_HANDLER Vector168 +#define SAM_SERCOM_7_1_HANDLER Vector16C +#define SAM_SERCOM_7_2_HANDLER Vector170 +#define SAM_SERCOM_7_3_HANDLER Vector174 + +/* USB HANDLER*/ +#define SAM_USB_0_OTHER_HANDLER Vector180 +#define SAM_USB_1_SOF_HSOF_HANDLER Vector184 +#define SAM_USB_2_TRCPT0_HANDLER Vector188 +#define SAM_USB_3_TRCPT1_HANDLER Vector18C + +/* QSPI HANDLER*/ +#define SAM_QSPI_HANDLER Vector258 + +#endif + diff --git a/testhal/SAMD21A/Blinky/Makefile b/testhal/SAM/SAMD21A/Blinky/Makefile similarity index 100% rename from testhal/SAMD21A/Blinky/Makefile rename to testhal/SAM/SAMD21A/Blinky/Makefile diff --git a/testhal/SAMD21A/Blinky/cfg/chconf.h b/testhal/SAM/SAMD21A/Blinky/cfg/chconf.h similarity index 100% rename from testhal/SAMD21A/Blinky/cfg/chconf.h rename to testhal/SAM/SAMD21A/Blinky/cfg/chconf.h diff --git a/testhal/SAMD21A/Blinky/cfg/halconf.h b/testhal/SAM/SAMD21A/Blinky/cfg/halconf.h similarity index 100% rename from testhal/SAMD21A/Blinky/cfg/halconf.h rename to testhal/SAM/SAMD21A/Blinky/cfg/halconf.h diff --git a/testhal/SAMD21A/Blinky/cfg/mcuconf.h b/testhal/SAM/SAMD21A/Blinky/cfg/mcuconf.h similarity index 100% rename from testhal/SAMD21A/Blinky/cfg/mcuconf.h rename to testhal/SAM/SAMD21A/Blinky/cfg/mcuconf.h diff --git a/testhal/SAMD21A/Blinky/main.c b/testhal/SAM/SAMD21A/Blinky/main.c similarity index 100% rename from testhal/SAMD21A/Blinky/main.c rename to testhal/SAM/SAMD21A/Blinky/main.c diff --git a/testhal/SAMD21A/EFL-MFS/Makefile b/testhal/SAM/SAMD21A/EFL-MFS/Makefile similarity index 100% rename from testhal/SAMD21A/EFL-MFS/Makefile rename to testhal/SAM/SAMD21A/EFL-MFS/Makefile diff --git a/testhal/SAMD21A/EFL-MFS/cfg/chconf.h b/testhal/SAM/SAMD21A/EFL-MFS/cfg/chconf.h similarity index 100% rename from testhal/SAMD21A/EFL-MFS/cfg/chconf.h rename to testhal/SAM/SAMD21A/EFL-MFS/cfg/chconf.h diff --git a/testhal/SAMD21A/EFL-MFS/cfg/halconf.h b/testhal/SAM/SAMD21A/EFL-MFS/cfg/halconf.h similarity index 100% rename from testhal/SAMD21A/EFL-MFS/cfg/halconf.h rename to testhal/SAM/SAMD21A/EFL-MFS/cfg/halconf.h diff --git a/testhal/SAMD21A/EFL-MFS/cfg/mcuconf.h b/testhal/SAM/SAMD21A/EFL-MFS/cfg/mcuconf.h similarity index 100% rename from testhal/SAMD21A/EFL-MFS/cfg/mcuconf.h rename to testhal/SAM/SAMD21A/EFL-MFS/cfg/mcuconf.h diff --git a/testhal/SAMD21A/EFL-MFS/main.c b/testhal/SAM/SAMD21A/EFL-MFS/main.c similarity index 100% rename from testhal/SAMD21A/EFL-MFS/main.c rename to testhal/SAM/SAMD21A/EFL-MFS/main.c diff --git a/testhal/SAMD21A/SIO/Makefile b/testhal/SAM/SAMD21A/SIO/Makefile similarity index 100% rename from testhal/SAMD21A/SIO/Makefile rename to testhal/SAM/SAMD21A/SIO/Makefile diff --git a/testhal/SAMD21A/SIO/cfg/chconf.h b/testhal/SAM/SAMD21A/SIO/cfg/chconf.h similarity index 100% rename from testhal/SAMD21A/SIO/cfg/chconf.h rename to testhal/SAM/SAMD21A/SIO/cfg/chconf.h diff --git a/testhal/SAMD21A/SIO/cfg/halconf.h b/testhal/SAM/SAMD21A/SIO/cfg/halconf.h similarity index 100% rename from testhal/SAMD21A/SIO/cfg/halconf.h rename to testhal/SAM/SAMD21A/SIO/cfg/halconf.h diff --git a/testhal/SAMD21A/SIO/cfg/mcuconf.h b/testhal/SAM/SAMD21A/SIO/cfg/mcuconf.h similarity index 100% rename from testhal/SAMD21A/SIO/cfg/mcuconf.h rename to testhal/SAM/SAMD21A/SIO/cfg/mcuconf.h diff --git a/testhal/SAMD21A/SIO/main.c b/testhal/SAM/SAMD21A/SIO/main.c similarity index 98% rename from testhal/SAMD21A/SIO/main.c rename to testhal/SAM/SAMD21A/SIO/main.c index f3d3f765be..841b31ef0e 100644 --- a/testhal/SAMD21A/SIO/main.c +++ b/testhal/SAM/SAMD21A/SIO/main.c @@ -49,8 +49,8 @@ static const ShellConfig shell_cfg1 = { static const SIOConfig siocfg = { SIO_DEFAULT_BITRATE, - SERCOM_CTRLA_DEFAULT, - SERCOM_CTRLB_DEFAULT, + SERCOM_SIO_CTRLA_DEFAULT, + SERCOM_SIO_CTRLB_DEFAULT, 1, 3 }; diff --git a/testhal/SAM/SAMD51_SAME54/Main/Makefile b/testhal/SAM/SAMD51_SAME54/Main/Makefile new file mode 100644 index 0000000000..67061a5682 --- /dev/null +++ b/testhal/SAM/SAMD51_SAME54/Main/Makefile @@ -0,0 +1,216 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -Og -g -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_same54.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +# include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/SAM/SAME54/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/SAME54_XPlainedPro/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# include $(CHIBIOS)/os/hal/osal/os-less/ARMCMx/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS_CONTRIB)/os/hal/lib/complex/serial_nor/devices/SST26VF/sst26vf.mk +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/SAME54P20.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(ALLASMSRC) +ASMXSRC = $(ALLXASMSRC) + +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/rules.mk diff --git a/testhal/SAM/SAMD51_SAME54/Main/cfg/chconf.h b/testhal/SAM/SAMD51_SAME54/Main/cfg/chconf.h new file mode 100644 index 0000000000..27798f4858 --- /dev/null +++ b/testhal/SAM/SAMD51_SAME54/Main/cfg/chconf.h @@ -0,0 +1,849 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_8_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 1000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** + * @brief Safety checks hook. + * @details This hook is invoked when there is a safety violation and the + * system is going to stop. + */ +#define CH_CFG_SAFETY_CHECK_HOOK(l, f) do { \ + /* Safety handling code here.*/ \ + chSysHalt(f); \ +} while (false) +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ \ No newline at end of file diff --git a/testhal/SAM/SAMD51_SAME54/Main/cfg/halconf.h b/testhal/SAM/SAMD51_SAME54/Main/cfg/halconf.h new file mode 100644 index 0000000000..469312b2cb --- /dev/null +++ b/testhal/SAM/SAMD51_SAME54/Main/cfg/halconf.h @@ -0,0 +1,571 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_9_1_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate 100kHz for the i2c controller. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(I2C_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define I2C_DEFAULT_BITRATE 100000 +#endif + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_LINE +#endif + +/** + * @brief Serial Nor SPI slave driver settings + */ + +#if !defined(SNOR_BUS_DRIVER) || defined(__DOXYGEN__) +#define SNOR_BUS_DRIVER SNOR_BUS_DRIVER_SPI +#endif + +/** + * @brief Uses 4kB sub-sectors rather than 64kB sectors. + */ +#if !defined(SST26VF_USE_SUB_SECTORS) || defined(__DOXYGEN__) +#define SST26VF_USE_SUB_SECTORS TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ \ No newline at end of file diff --git a/testhal/SAM/SAMD51_SAME54/Main/cfg/mcuconf.h b/testhal/SAM/SAMD51_SAME54/Main/cfg/mcuconf.h new file mode 100644 index 0000000000..73aad24aec --- /dev/null +++ b/testhal/SAM/SAMD51_SAME54/Main/cfg/mcuconf.h @@ -0,0 +1,184 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define SAME54_MCUCONF + +#define SAM_CPUDIV 1 + +#define SAM_RTC_GCLK_SRC_ID 8 +#define SAM_RTC_DIV 6 + +#define SAM_ADC_GCLK_SRC_ID 0 +#define SAM_SERCOM0_GCLK_SRC_ID 0 +#define SAM_SERCOM1_GCLK_SRC_ID 0 +#define SAM_SERCOM2_GCLK_SRC_ID 7 +#define SAM_SERCOM3_GCLK_SRC_ID 0 +#define SAM_SERCOM4_GCLK_SRC_ID 0 +#define SAM_SERCOM5_GCLK_SRC_ID 0 +#define SAM_SERCOM6_GCLK_SRC_ID 9 +#define SAM_SERCOM7_GCLK_SRC_ID 7 +#define SAM_USB_GCLK_SRC_ID 9 +#define SAM_TCC0_TCC1_GCLK_SRC_ID 0 +#define SAM_TCC2_TC3_GCLK_SRC_ID 0 + +/********************* XOSC *******************/ + +#define SAM_XOSC1_FREQ 12000000UL +#define SAM_XOSC0_ENABLED FALSE +#define SAM_XOSC1_ENABLED TRUE +#define SAM_FDPLL0_INPUT_SRC SAM_DPLL_INPUT_SRC_XOSC1 +#define SAM_FDPLL1_INPUT_SRC SAM_DPLL_INPUT_SRC_XOSC1 + +#define SAM_FDPLL0_ENABLED TRUE +#define SAM_FDPLL1_ENABLED TRUE + +#define SAM_FDPLL0_DIV 5 +#define SAM_FDPLL0_LDR 119 +#define SAM_FDPLL0_LDFRAC 0 + +#define SAM_FDPLL1_DIV 5 +#define SAM_FDPLL1_LDR 95 +#define SAM_FDPLL1_LDFRAC 0 + +/******************** GENCLK *******************/ +#define SAM_GCLK0_SRC GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK0_FREQ 120000000UL + +#define SAM_GCLK1_SRC GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK1_FREQ 60000000UL +#define SAM_GCLK1_ENABLE FALSE + +#define SAM_GCLK2_SRC GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK2_FREQ 60000000UL +#define SAM_GCLK2_ENABLE FALSE + +#define SAM_GCLK3_SRC GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK3_FREQ 1000000UL +#define SAM_GCLK3_ENABLE FALSE + +#define SAM_GCLK4_SRC GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK4_FREQ 1000000UL +#define SAM_GCLK4_ENABLE FALSE + +#define SAM_GCLK5_SRC GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK5_FREQ 1000000UL +#define SAM_GCLK5_ENABLE FALSE + +#define SAM_GCLK6_SRC GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK6_FREQ 1000000UL +#define SAM_GCLK6_ENABLE FALSE + +#define SAM_GCLK7_SRC GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK7_FREQ 10000000UL +#define SAM_GCLK7_ENABLE TRUE + +#define SAM_GCLK8_SRC GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK8_FREQ 640000UL +#define SAM_GCLK8_ENABLE TRUE + +#define SAM_GCLK9_SRC GCLK_GENCTRL_SRC_DPLL1 +#define SAM_GCLK9_FREQ 48000000UL +#define SAM_GCLK9_ENABLE TRUE + +#define SAM_GCLK10_SRC GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK10_FREQ 1000000UL +#define SAM_GCLK10_ENABLE FALSE + +#define SAM_GCLK11_SRC GCLK_GENCTRL_SRC_DPLL0 +#define SAM_GCLK11_FREQ 1000000UL +#define SAM_GCLK11_ENABLE FALSE + +/***********************************************/ + +#define SAM_DMAC_IRQ_PRIORITY 4 +#define SAM_QSPI_IRQ_PRIORITY 5 +#define SAM_ADC_IRQ_PRIORITY 6 + +#define SAM_EIC_EXTI0_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI1_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI2_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI3_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI4_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI5_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI6_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI7_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI8_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI9_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI10_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI11_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI12_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI13_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI14_IRQ_PRIORITY 6 +#define SAM_EIC_EXTI15_IRQ_PRIORITY 6 + +#define SAM_RTC_IRQ_PRIORITY 6 + +#define SAM_SERCOM0_IRQ_PRIORITY 5 +#define SAM_SERCOM1_IRQ_PRIORITY 5 +#define SAM_SERCOM2_IRQ_PRIORITY 5 +#define SAM_SERCOM3_IRQ_PRIORITY 5 +#define SAM_SERCOM4_IRQ_PRIORITY 5 +#define SAM_SERCOM5_IRQ_PRIORITY 5 +#define SAM_SERCOM6_IRQ_PRIORITY 5 +#define SAM_SERCOM7_IRQ_PRIORITY 5 +#define SAM_TCC0_IRQ_PRIORITY 6 +#define SAM_TC3_IRQ_PRIORITY 6 + +#define SAM_ADC_USE_ADC1 FALSE + +#define SAM_SIO_USE_SERCOM0 FALSE +#define SAM_SPI_USE_SERCOM0 FALSE +#define SAM_I2C_USE_SERCOM0 FALSE + +#define SAM_SIO_USE_SERCOM1 FALSE +#define SAM_SPI_USE_SERCOM1 FALSE +#define SAM_I2C_USE_SERCOM1 FALSE + +#define SAM_SIO_USE_SERCOM2 TRUE +#define SAM_SPI_USE_SERCOM2 FALSE +#define SAM_I2C_USE_SERCOM2 FALSE + +#define SAM_SIO_USE_SERCOM3 FALSE +#define SAM_SPI_USE_SERCOM3 FALSE +#define SAM_I2C_USE_SERCOM3 FALSE + +#define SAM_SIO_USE_SERCOM4 FALSE +#define SAM_SPI_USE_SERCOM4 FALSE +#define SAM_I2C_USE_SERCOM4 FALSE + +#define SAM_SIO_USE_SERCOM5 FALSE +#define SAM_SPI_USE_SERCOM5 FALSE +#define SAM_I2C_USE_SERCOM5 FALSE + +#define SAM_SIO_USE_SERCOM6 FALSE +#define SAM_SPI_USE_SERCOM6 FALSE +#define SAM_I2C_USE_SERCOM6 FALSE + + +#define SAM_SIO_USE_SERCOM7 FALSE +#define SAM_SPI_USE_SERCOM7 FALSE +#define SAM_I2C_USE_SERCOM7 TRUE + +#define SAM_SPI_USE_QSPI1 TRUE +#define SAM_WSPI_USE_QSPI1 FALSE + +#define SAM_EFL_USE_EFL1 FALSE + +#endif /* MCUCONF_H */ + \ No newline at end of file diff --git a/testhal/SAM/SAMD51_SAME54/Main/cfg/osalconf.h b/testhal/SAM/SAMD51_SAME54/Main/cfg/osalconf.h new file mode 100644 index 0000000000..aa1d91f5e2 --- /dev/null +++ b/testhal/SAM/SAMD51_SAME54/Main/cfg/osalconf.h @@ -0,0 +1,67 @@ +/* + ChibiOS - Copyright (C) 2006-2026 Giovanni Di Sirio. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief Bare-metal OSAL configuration header. + * + * @addtogroup OSAL_CONF + * @{ + */ + +#ifndef OSALCONF_H +#define OSALCONF_H + +/** + * @brief Frequency in Hertz of the system tick. + */ +#if !defined(OSAL_ST_FREQUENCY) || defined(__DOXYGEN__) +#define OSAL_ST_FREQUENCY 1000 +#endif + +/** + * @brief Enables OSAL assertions. + */ +#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define OSAL_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Enables OSAL functions parameters checks. + */ +#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define OSAL_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief OSAL initialization hook. + */ +#if !defined(OSAL_INIT_HOOK) || defined(__DOXYGEN__) +#define OSAL_INIT_HOOK() { \ +} +#endif + +/** + * @brief Idle loop hook macro. + */ +#if !defined(OSAL_IDLE_HOOK) || defined(__DOXYGEN__) +#define OSAL_IDLE_HOOK() { \ +} +#endif + +#endif /* OSALCONF_H */ + +/** @} */ diff --git a/testhal/SAM/SAMD51_SAME54/Main/main.c b/testhal/SAM/SAMD51_SAME54/Main/main.c new file mode 100644 index 0000000000..2a2f43326e --- /dev/null +++ b/testhal/SAM/SAMD51_SAME54/Main/main.c @@ -0,0 +1,167 @@ +#include "ch.h" +#include "hal.h" +#include "chprintf.h" +#include "hal_serial_nor.h" +#include "hal_flash.h" + +#define XSPI_MOSI PAL_LINE(GPIOA, 8) +#define XSPI_MISO PAL_LINE(GPIOA, 9) +#define XSPI_WP PAL_LINE(GPIOA, 10) +#define XSPI_HOLD PAL_LINE(GPIOA, 11) +#define XSPI_SCK PAL_LINE(GPIOB, 10) +#define XSPI_CS PAL_LINE(GPIOB, 11) + +#define UART_TX PAL_LINE(GPIOB, 25) +#define UART_RX PAL_LINE(GPIOB, 24) + +#define BLINKY PAL_LINE(GPIOC, 18) + +#define I2C_SDA PAL_LINE(GPIOD, 8) +#define I2C_SCL PAL_LINE(GPIOD, 9) + +// i2c slave device on Xplained pro +#define AT24MAC402_ADDR 0x56 + +void pinsInit() +{ + // LED + palSetLineMode(BLINKY, PAL_MODE_OUTPUT_PUSHPULL); + // I2C + palSetLineMode(I2C_SDA, PAL_MODE_ALTERNATE(PAL_SAM_FUNC_C)); + palSetLineMode(I2C_SCL, PAL_MODE_ALTERNATE(PAL_SAM_FUNC_C)); + // UART + palSetLineMode(UART_TX, PAL_MODE_ALTERNATE(PAL_SAM_FUNC_D)); + palSetLineMode(UART_RX, PAL_MODE_ALTERNATE(PAL_SAM_FUNC_D)); + // XSPI (only testing single spi mode, therefore driving io 2/3 to high) + palSetLineMode(XSPI_MOSI, PAL_MODE_ALTERNATE(PAL_SAM_FUNC_H)); + palSetLineMode(XSPI_MISO, PAL_MODE_ALTERNATE(PAL_SAM_FUNC_H)); + palSetLineMode(XSPI_WP, PAL_MODE_OUTPUT_PUSHPULL); + palSetLineMode(XSPI_HOLD, PAL_MODE_OUTPUT_PUSHPULL); + palSetLineMode(XSPI_SCK, PAL_MODE_ALTERNATE(PAL_SAM_FUNC_H)); + // SW controlled CS for single SPI mode + palSetLineMode(XSPI_CS, PAL_MODE_OUTPUT_PUSHPULL); +} + +void sioInitTest() +{ +static const SIOConfig siocfg = { + SIO_DEFAULT_BITRATE, + SERCOM_SIO_CTRLA_DEFAULT, + SERCOM_SIO_CTRLB_DEFAULT, + 2, + 1 +}; + sioStart(&SIOD3, &siocfg); + static int sent_b = 0; + sent_b = chprintf((BaseSequentialStream *)&SIOD3, "SIO test passed\r\n"); +} + +void i2cInitTest() +{ + static const uint8_t tx_buf[] = {0x0, 0x1}; + uint8_t rx_buf[2] = {0x0, 0x0}; + static i2cflags_t errors = 0; + static const uint8_t dummy_tx_buf[] = {0x0}; + static const I2CConfig i2ccfg = {I2C_DEFAULT_BITRATE, SERCOM_I2C_CTRLA_DEFAULT}; + msg_t msg = 0xff; + msg = i2cStart(&I2CD8, &i2ccfg); + while (msg != MSG_OK) { + osalThreadSleepMilliseconds(1); + } + msg = i2cMasterTransmitTimeout(&I2CD8, AT24MAC402_ADDR, tx_buf, sizeof(tx_buf), NULL, 0, 100); + if (msg != MSG_OK) { + errors = i2cGetErrors(&I2CD8); + chprintf((BaseSequentialStream *)&SIOD3, "I2C test failed: %d\r\n", errors); + osalThreadSleepMilliseconds(100); + }; + osalThreadSleepMilliseconds(10); + msg = i2cMasterTransmitTimeout(&I2CD8, AT24MAC402_ADDR, dummy_tx_buf, sizeof(dummy_tx_buf), rx_buf, sizeof(rx_buf), 100); + if (tx_buf[1] != rx_buf[0]){ + chprintf((BaseSequentialStream *)&SIOD3, "I2C test failed: %d != %d\r\n", tx_buf[1], rx_buf[0]); + } + else { + chprintf((BaseSequentialStream *)&SIOD3, "I2C test passed\r\n"); + } + if (msg != MSG_OK) { + errors = i2cGetErrors(&I2CD8); + chprintf((BaseSequentialStream *)&SIOD3, "I2C test failed: %d\r\n", errors); + palSetLine(BLINKY); + osalThreadSleepMilliseconds(100); + }; +} + +void xspiFlashInitTest() +{ + palWriteLine(XSPI_WP, PAL_HIGH); + palWriteLine(XSPI_HOLD, PAL_HIGH); + palWriteLine(XSPI_CS, PAL_HIGH); + + static SPIConfig spi_cfg; + static SNORDriver snor_driver; + static snor_nocache_buffer_t spi_buf; + const static qspi_spi_config_t qspi_spi_cfg = { + 0, // ctrlb + 20000000, // Set frequency to 20Mhz + 0, // DLYBS to 0, CS valid transition is 1/2 of SCK period + 0, // CPOL: The inactive state value of SCK is logic level zero + 0 // CPHA: Data is captured on the leading edge of SCK and changed on the following edge of SCK. + }; + spi_cfg.qspi_cfg = qspi_spi_cfg; + spi_cfg.ssline = XSPI_CS; + static const SNORConfig snor_driver_config = { + .busp = &SPID9, + .buscfg = &spi_cfg, + }; + + snorObjectInit(&snor_driver, &spi_buf); + snorStart(&snor_driver, &snor_driver_config); + + static const uint8_t tx_data[4] = {0x11, 0x12, 0x13, 0x14}; + uint8_t rx_data[1000] = {0}; + BaseFlash* flash = getBaseFlash(&snor_driver); + flash_error_t ererr = flashStartEraseSector(flash, 0); + uint32_t msec = 1; + while (flashQueryErase(flash, &msec) == FLASH_BUSY_ERASING) { + osalThreadSleepMilliseconds(msec); + }; + flash_error_t rderr = flashRead(flash, 0U, 1000, rx_data); + flash_error_t wrerr = flashProgram(flash, 0U, 4, tx_data); + rderr = flashRead(flash, 0U, 5, rx_data); + bool passed = true; + for (int i = 0; i < (sizeof(tx_data) / sizeof(tx_data[0])); i++) { + if (tx_data[i] != rx_data[i]) { + chprintf((BaseSequentialStream *)&SIOD3, "XSPI flash test failed: %d != %d\r\n", tx_data[i], rx_data[i]); + passed = false; + break; + } + } + if (passed) { + chprintf((BaseSequentialStream *)&SIOD3, "XSPI flash test passed\r\n"); + } + osalThreadSleepMilliseconds(10); + +} + + +int main(void) +{ + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + */ + + halInit(); + chSysInit(); + + pinsInit(); + sioInitTest(); + osalThreadSleepMilliseconds(1); + i2cInitTest(); + xspiFlashInitTest(); + + while (true) { + palToggleLine(BLINKY); + osalThreadSleepMilliseconds(1000); + } +} \ No newline at end of file